Synaptic transistor for safety circuit, preparation method and use method
By using synaptic transistors in safety circuits, using the characteristics of the ferroelectric semiconductor layer and gate dielectric layer, combining light and electrical pulses to achieve logic locking and camouflage, the problems of high power consumption, large area and easy decoding in existing hardware security technologies are solved, and a low-power consumption and miniaturized hardware security solution is realized.
Patent Information
- Application Number
- CN202411989916.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-04-25
AI Technical Summary
Existing logic locking and camouflage technologies based on hardware security have problems such as high power consumption, large area and easy to decipher, making it difficult to effectively protect the security of integrated circuits.
A synaptic transistor for a security circuit is adopted, which includes an oxide layer on a silicon substrate, a ferroelectric semiconductor layer and a gate dielectric layer. Through light as a security key, different Boolean logic functions are realized in combination with electrical pulse conditions, and logic locking and camouflage technology are realized.
It realizes a hardware security solution with simple structure, miniaturization and easy integration, and low power consumption, which significantly reduces the circuit area of each logic function and is widely used in hardware security systems and post-Moore electronics fields.
Smart Images
Figure CN119894360A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of hardware security technology, and in particular to a synaptic transistor for a security circuit, and a preparation and use method thereof. Background Art
[0002] Hardware security and power consumption are key considerations in the current integrated circuit industry. Neuromorphic architectures that mimic biological neural networks have great potential in reducing power consumption and are expected to break through the von Neumann bottleneck. Reverse engineering is a common security threat in the integrated circuit industry. Reverse engineers can use certain techniques to obtain the layout of a chip and decipher the chip's functions. Logic locking and camouflage are hardware security technologies developed to address this threat. Logic locking means that the circuit will not produce the expected output unless activated with the correct key, and camouflage is defined as effectively hiding the true operation of the circuit by using cells that look the same but have different functions to mask the actual function of the circuit. Even if the reverse engineer manages to map out the entire chip layout, the chip's functions remain hidden without the correct key because the functions of the circuit cells remain unknown. The chip can only operate correctly when all the necessary keys are provided during operation to configure the logic gates to achieve their intended functions.
[0003] At present, logic locking and camouflage technology based on hardware security generally uses multiple transistors to build complex circuits to implement Boolean logic operations. This type of technology has the following disadvantages: 1. High power consumption. This type of technology relies on multiple transistors to build complex logic circuits, which produces high power consumption; 2. It occupies a large area and is difficult to integrate; 3. It is easy to decipher. The key of this type of technology is often an electrical programming parameter. Therefore, it is necessary to develop new transistors for hardware security to overcome the limitations of current traditional solutions. Summary of the invention
[0004] The purpose of the present invention is to address the shortcomings of existing hardware security solutions and provide a synaptic transistor for a security circuit, a preparation method and a use method. The synaptic transistor has the advantages of simple structure, miniaturization, easy integration, low power consumption and small circuit area for each logical function, and has broad application prospects in hardware security systems, post-Moore electronics and other fields.
[0005] The objective of the present invention is achieved through the following technical solutions:
[0006] In the first aspect, the present invention provides a synaptic transistor for a security circuit, the transistor comprising an oxide layer, a ferroelectric semiconductor layer, and a gate dielectric layer on a silicon substrate, the ferroelectric semiconductor layer material being a material having both ferroelectric and photoelectric response characteristics, the gate dielectric layer material being a light-transmitting material, a source and a drain being arranged on both sides of the ferroelectric semiconductor layer, the ferroelectric semiconductor layer between the source and the drain forming a channel region, two independent transparent gate electrodes being arranged on the gate dielectric layer as two input terminals, a voltage pulse being applied to the gate electrode, a constant voltage being applied to the drain, the source being grounded, a curve of the change of the drain current over time being measured, the post-synaptic current of the drain being read as an output, light being used as a security key, the security key being encoded as 0 / 1 and combined with the set electrical pulse conditions to realize different Boolean logic functions.
[0007] Furthermore, the oxide layer material is silicon oxide, aluminum oxide or hafnium oxide.
[0008] Furthermore, the ferroelectric semiconductor layer material is α-phase indium selenide (α-In2Se3).
[0009] Furthermore, the gate dielectric layer material is hexagonal boron nitride (hBN).
[0010] Furthermore, the source and drain materials are chromium or titanium.
[0011] Furthermore, a protective electrode is provided on the source and the drain, and the material of the protective electrode is gold or platinum.
[0012] Furthermore, the gate electrode material is indium tin oxide (ITO).
[0013] In a second aspect, the present invention provides a method for preparing a synaptic transistor for a safety circuit, the method comprising the following steps:
[0014] (1) Thermal oxidation on the surface of the silicon substrate to form an oxide layer;
[0015] (2) mechanically peeling off and transferring the oxide layer to form a ferroelectric semiconductor layer and a gate dielectric layer in sequence, and forming a source and a drain structure on both sides of the ferroelectric semiconductor layer by laser direct writing;
[0016] (3) depositing metal in the source-drain electrode pattern region to form source-drain contact electrodes and protective electrodes;
[0017] (4) forming two independent gate structures on the gate dielectric layer by laser direct writing;
[0018] (5) Depositing transparent metal in the gate electrode pattern area to form two independent gate electrodes, ultimately forming a synaptic transistor for a security circuit.
[0019] Furthermore, the method of thermal oxidation of the silicon substrate surface in step (1) is pure dry oxygen oxidation.
[0020] Furthermore, in the step (2), the transfer method of the ferroelectric semiconductor layer and the gate dielectric layer is a dry transfer method.
[0021] Furthermore, in the step (3), the method for depositing the metal electrode in the source-drain electrode pattern region is thermal evaporation or electron beam evaporation.
[0022] Furthermore, in step (5), the method for depositing the transparent metal electrode in the gate electrode pattern region is magnetron sputtering.
[0023] In a third aspect, the present invention provides a method for using a synaptic transistor for a safety circuit, the method comprising:
[0024] Apply a voltage pulse to the gate electrode, a constant voltage to the drain electrode, and ground the source electrode. Measure the curve of the drain current changing over time to simulate the behavior of electrical synapses.
[0025] Apply optical pulses to the channel region, apply a constant voltage to the drain, ground the source, and measure the curve of the drain current changing over time to simulate the behavior of the photoelectric synapse;
[0026] Using light as the security key, when the security key is coded as 0, it is a dark condition, and when the security key is coded as 1, it is a light condition;
[0027] The condition of applying an electric pulse to the gate electrode is set as input logic 1, and the condition of not applying an electric pulse is set as input logic 0. When the drain current reaches the set threshold, it is set as output logic 1, and when it is lower than the set threshold, it is set as output logic 0;
[0028] By encoding the security key into 0 / 1 and combining it with the set electrical pulse conditions to achieve different Boolean logic functions, logical locking technology and camouflage technology are realized.
[0029] Furthermore, the voltage pulse applied by the gate electrode is within a voltage range that enables the ferroelectric semiconductor layer to achieve polarization reversal, the constant voltage applied by the drain is a voltage that enables the transistor to operate in a linear region, and the optical pulse applied by the channel region is within a wavelength range that can be sensed by the ferroelectric semiconductor layer.
[0030] Furthermore, the synaptic transistor is used to implement logic "AND" and "OR", specifically:
[0031] When the security key is encoded as 0, a negative voltage pulse is input only at one of the input terminals, and the postsynaptic current is lower than the set threshold. Only when a negative voltage pulse is input at both input terminals at the same time, the postsynaptic current will exceed the set threshold. This is a logical "AND";
[0032] When the security key is encoded as 1, the synaptic current will exceed the preset threshold after a negative voltage pulse is input to either input terminal, which is a logical "OR".
[0033] Furthermore, the synaptic transistor is used to implement logic "NOR" and "NAND", specifically:
[0034] When the security key is encoded as 0, a positive voltage pulse is input to either input terminal, and the post-synaptic current will be lower than the preset threshold, which is a logical "NOR";
[0035] When the security key is encoded as 1, the post-synaptic current will be lower than the set threshold only when positive voltage pulses are input to both input terminals at the same time. This is a logical "NAND".
[0036] Compared with the prior art, the present invention has the following beneficial effects:
[0037] The present invention provides a synaptic transistor for a safety circuit, and a preparation and use method thereof. The synaptic transistor for a safety circuit has a single transistor structure with a simple structure. Secondly, based on the single transistor structure, a variety of Boolean logic operations can be realized. The miniaturization is easy to integrate and the circuit area of each logic function is significantly reduced. In addition, the transistor simulates synaptic behavior, has low power consumption, and has a wide range of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 A schematic diagram of the structure of a synaptic transistor used in a safety circuit;
[0039] Figure 2 (a) is an example of the electrical characteristics of the excitatory postsynaptic current over time after applying a negative voltage pulse; (b) is an example of the electrical characteristics of the inhibitory postsynaptic current over time after applying a positive voltage pulse;
[0040] Figure 3 An example of electrical characteristics after applying a light pulse;
[0041] Figure 4 Truth table for logic "AND", "OR", "NOR" and "NAND";
[0042] Figure 5 (a) is an example of the electrical characteristics of the synaptic transistor implementing the logic "AND" when the security key is encoded as 0 and under negative voltage pulse conditions; (b) is an example of the electrical characteristics of the synaptic transistor implementing the logic "OR" when the security key is encoded as 1 and under negative voltage pulse conditions; (c) is an example of the electrical characteristics of the synaptic transistor implementing the logic "NOR" when the security key is encoded as 0 and under positive voltage pulse conditions; (d) is an example of the electrical characteristics of the synaptic transistor implementing the logic "NAND" when the security key is encoded as 1 and under positive voltage pulse conditions;
[0043] Figure 6 Demonstration of logic locking and camouflage techniques implemented for synaptic transistors and applied to secure circuits;
[0044] In the figure, there is a silicon substrate 10 , an oxide layer 11 , a ferroelectric semiconductor layer 20 , a gate dielectric layer 21 , a source-drain contact electrode 30 , a protective electrode 31 , and a gate electrode 50 . DETAILED DESCRIPTION
[0045] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0046] The present invention provides a synaptic transistor for a safety circuit, comprising an oxide layer, a ferroelectric semiconductor layer, and a gate dielectric layer on a silicon substrate, a source electrode and a drain electrode are arranged on both sides of the ferroelectric semiconductor layer, a protective electrode is arranged on the source electrode and the drain electrode, the ferroelectric semiconductor layer between the source electrode and the drain electrode forms a channel region, and two independent transparent gate electrodes are arranged on the gate dielectric layer, such as Figure 1 As shown, it should be noted that the hardware security solution used for the specific implementation of the security circuit is logic locking technology and camouflage technology. The logic locking technology means that the circuit will not be able to produce the expected output unless activated with the correct key. The camouflage technology means that the actual function of the circuit is concealed by using units that look the same but have different functions, thereby effectively hiding the true operation of the circuit.
[0047] Specifically, the oxide layer material includes but is not limited to silicon oxide, aluminum oxide, and hafnium oxide. The ferroelectric semiconductor layer material is a material having both ferroelectric and photoelectric response properties, including but not limited to α-phase indium selenide (α-In2Se3). The gate dielectric layer material is a light-transmitting material, including but not limited to hexagonal boron nitride (hBN). The source and drain materials include but are not limited to chromium or titanium. The protective electrode material includes but is not limited to gold or platinum. The transparent gate electrode material includes but is not limited to indium tin oxide (ITO).
[0048] In the present invention, the transistor structure adopts a ferroelectric semiconductor channel, which has the characteristics of both ferroelectric and photoelectric response, has good light perception and storage capabilities, and is helpful to realize a variety of Boolean logic operations. In addition, two independent transparent gate electrodes are used. The transparent gate electrodes do not affect the photosensitivity of the channel area. Two input terminals are required to realize logical operations, and the read post-synaptic current is used as output.
[0049] The synaptic transistor for security circuit is a transistor based on ferroelectric semiconductor channel and dual-gate structure, two independent transparent gate electrodes are used as input terminals A and B respectively, voltage pulses are applied to the gate electrode, constant voltage is applied to the drain, the source is grounded, the curve of change of drain current over time is measured, and the peak current of synaptic current after the drain is read as output to realize Boolean logic operation. By utilizing the good light perception ability of the ferroelectric semiconductor channel, light is used as a security key. When the security key is encoded as 0, it is a dark condition, and when the security key is encoded as 1, it is a light condition. By encoding the security key as 0 / 1 and combining it with the set electrical pulse condition, the synaptic transistor can realize different Boolean logic functions, thereby realizing logic locking technology and camouflage technology, which can be applied to security circuits to protect the actual functions of the circuit from being deciphered.
[0050] The method for preparing a synaptic transistor for a safety circuit proposed by the present invention comprises the following steps:
[0051] (1) thermally oxidizing the surface of the silicon substrate 10 to form an oxide layer 11;
[0052] (2) mechanically peeling off and transferring the surface of the oxide layer 11 to form a ferroelectric semiconductor layer 20 and a gate dielectric layer 21 in sequence, and forming a source and a drain structure on both sides of the ferroelectric semiconductor layer by laser direct writing;
[0053] (3) depositing metal in the source-drain electrode pattern region to form source-drain contact electrodes 30 and protective electrodes 31;
[0054] (4) forming two independent gate structures on the gate dielectric layer 21 by laser direct writing;
[0055] (5) Depositing transparent metal in the gate electrode pattern region to form two independent gate electrodes 50, and finally forming a synaptic transistor for a safety circuit, the structure of which is as follows: Figure 1 shown.
[0056] Specifically, in step (1), the method of thermally oxidizing the surface of the silicon substrate 10 is pure dry oxygen oxidation, and the thickness of the oxide layer 11 is 200 to 300 nanometers.
[0057] In the step (2), the ferroelectric semiconductor layer 20 and the gate dielectric layer 21 are transferred by a dry transfer method, and the thickness of each layer is about tens of nanometers.
[0058] In the step (3), the method for depositing metal electrodes in the source-drain electrode pattern region is thermal evaporation or electron beam evaporation. The thickness of the source-drain contact electrode 30 is about 10 nanometers, and the thickness of the protective electrode 31 is about 30 nanometers.
[0059] In the step (5), the method for depositing transparent metal in the gate electrode pattern region to form the gate electrode 50 is magnetron sputtering, and the thickness is about 30 nanometers.
[0060] The method for using the synaptic transistor for a safety circuit proposed by the present invention is specifically as follows:
[0061] A voltage pulse is applied to the gate, a constant voltage is applied to the drain, the source is grounded, and the curve of the drain current changing over time is measured to simulate the behavior of electrical synapses.
[0062] An optical pulse is applied to the channel region, a constant voltage is applied to the drain, the source is grounded, and the curve of the drain current changing with time is measured to simulate the behavior of the photoelectric synapse.
[0063] The voltage pulse applied by the gate is a voltage range that enables the ferroelectric semiconductor layer to achieve polarization reversal, the constant voltage applied by the drain is a voltage that enables the transistor to operate in the linear region, and the optical pulse applied by the channel region is a wavelength range that the ferroelectric semiconductor layer can perceive. In this example, the amplitude of the voltage pulse applied by the gate is 3V / -3V, the constant voltage applied by the drain is 1V, and the wavelength of the optical pulse is 532nm. Figure 1 As shown, when the synaptic transistor is working, the source and drain contact electrodes 30 are grounded and the constant voltage signal V DS , the gate electrodes 50 at the A and B input terminals are connected to the voltage pulse signals V InA and V InB , measure the drain current I DS The time-varying curve, such as Figure 2 As shown in (a), W pulse is the voltage pulse width. After a negative voltage pulse is applied to the gate electrode 50, the postsynaptic current exhibits an excitatory behavior. EPSC is the excitatory postsynaptic current. Figure 2 As shown in (b), after a positive voltage pulse is applied to the gate electrode 50, the postsynaptic current exhibits an inhibitory behavior, and the IPSC is an inhibitory postsynaptic current, which well simulates the electrical synaptic behavior. Figure 3 As shown, an optical pulse is applied to the channel region with a light intensity P light Set to 0.18 mW cm -2 , the postsynaptic current exhibits excitatory behavior, which well simulates the behavior of optoelectronic synapses.
[0064] In a specific example of the present invention, the curves of the drain current changing with time under the same electric pulse conditions and the security key code being 0 / 1 are measured respectively, such as Figure 4 The truth table of the logic "AND", "OR", "NOR" and "NAND" is shown. The condition of applying the electric pulse is set to input logic 1, and the condition of not applying the electric pulse is set to input logic 0. When the drain current reaches the set threshold, it is set to output logic 1, and when it is lower than the set threshold, it is set to output logic 0. First, the implementation of the logic locking and camouflage technology is demonstrated by the logic "AND" and "OR". In this example, the set threshold is 8nA. Figure 5As shown in (a), PSC is the postsynaptic current. When the security key is encoded as 0, a negative voltage pulse (-3V, 500ms) is input to only one of the input terminals, and the postsynaptic current is lower than the set threshold. Only when a negative voltage pulse (-3V, 500ms) is input to both the A and B input terminals at the same time, the postsynaptic current will exceed the set threshold. This is the logical "AND". Figure 5 As shown in (b), when the security key is encoded as 1, a negative voltage pulse (-3V, 500ms) is input to any input terminal, and the postsynaptic current will exceed the preset threshold value, which is a logic "OR". When the electrical pulse condition is set to a positive voltage pulse (3V, 500ms), the security key can be encoded as 0 / 1 to achieve logic "NOR" and "NAND" respectively. In this example, the threshold value is set to 5nA. Figure 5 As shown in (c), when the security key is encoded as 0, a positive voltage pulse (3V, 500ms) is input to any input terminal, and the post-synaptic current will be lower than the preset threshold, which is the logic "NOR". Figure 5 As shown in (d), when the security key is encoded as 1, the post-synaptic current will be lower than the set threshold only when a positive voltage pulse (3V, 500ms) is input to both the A and B input terminals at the same time, which is a logical "NAND". Figure 6 As shown, the synaptic transistor in the present invention is used as a standard logic unit of the circuit, light is used as the key, the electric pulse condition is set to a negative voltage pulse, the key is encoded as 0, the transistor is used as a logic "AND", the key is encoded as 1, and the transistor is used as a logic "OR". Therefore, when the security key is encoded as 0 / 1 and the electric pulse condition is set, the synaptic transistor can realize different Boolean logic functions, realize the logic locking technology and camouflage technology, and can be applied to security circuits to protect the actual functions of the circuit from being deciphered.
[0065] The above description is merely a preferred embodiment of one or more embodiments of the present specification and is not intended to limit one or more embodiments of the present specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of the present specification shall be included in the scope of protection of one or more embodiments of the present specification.
Claims
1. A synaptic transistor for a safety circuit, characterized in that: It includes an oxide layer, a ferroelectric semiconductor layer, and a gate dielectric layer on a silicon substrate. The ferroelectric semiconductor layer material is a material with both ferroelectric and photoelectric response characteristics. The gate dielectric layer material is a light-transmitting material. A source and a drain are arranged on both sides of the ferroelectric semiconductor layer. The ferroelectric semiconductor layer between the source and the drain forms a channel region. Two independent transparent gate electrodes are arranged on the gate dielectric layer as two input terminals. A voltage pulse is applied to the gate electrode, a constant voltage is applied to the drain, the source is grounded, and a curve of the drain current changing with time is measured. The post-synaptic current of the drain is read as an output. Light is used as a security key, and the security key is encoded as 0 / 1 and combined with the set electrical pulse conditions to realize different Boolean logic functions.
2. The synaptic transistor for a safety circuit according to claim 1, characterized in that A protective electrode is arranged on the source electrode and the drain electrode. The source electrode and the drain electrode are made of chromium or titanium, and the protective electrode is made of gold or platinum.
3. The synaptic transistor for a safety circuit according to claim 1, characterized in that: The material of the ferroelectric semiconductor layer is α-phase indium selenide.
4. The synaptic transistor for a safety circuit according to claim 1, characterized in that: The gate dielectric layer material is hexagonal boron nitride.
5. The synaptic transistor for a safety circuit according to claim 1, characterized in that: The transparent gate electrode material is indium tin oxide.
6. A method for preparing a synaptic transistor for a safety circuit according to any one of claims 1 to 5, characterized in that: The steps include: (1) Thermal oxidation on the surface of the silicon substrate to form an oxide layer; (2) mechanically peeling off and transferring the oxide layer to form a ferroelectric semiconductor layer and a gate dielectric layer in sequence, and forming a source and a drain structure on both sides of the ferroelectric semiconductor layer by laser direct writing; (3) depositing metal in the source-drain electrode pattern region to form source-drain contact electrodes and protective electrodes; (4) forming two independent gate structures on the gate dielectric layer by laser direct writing; (5) Depositing transparent metal in the gate electrode pattern area to form two independent gate electrodes, ultimately forming a synaptic transistor for a security circuit.
7. A method for using a synaptic transistor for a safety circuit according to any one of claims 1 to 5, characterized in that: include: Apply a voltage pulse to the gate electrode, a constant voltage to the drain electrode, and ground the source electrode. Measure the curve of the drain current changing over time to simulate the behavior of electrical synapses. Apply optical pulses to the channel region, apply a constant voltage to the drain, ground the source, and measure the curve of the drain current changing over time to simulate the behavior of the photoelectric synapse; Using light as the security key, when the security key is coded as 0, it is a dark condition, and when the security key is coded as 1, it is a light condition; The condition of applying an electric pulse to the gate electrode is set as input logic 1, and the condition of not applying an electric pulse is set as input logic 0. When the drain current reaches the set threshold, it is set as output logic 1, and when it is lower than the set threshold, it is set as output logic 0; By encoding the security key into 0 / 1 and combining it with the set electrical pulse conditions to achieve different Boolean logic functions, logical locking technology and camouflage technology are realized.
8. The method of use according to claim 7, characterized in that: The voltage pulse applied by the gate electrode is within the voltage range that enables the ferroelectric semiconductor layer to achieve polarization reversal, the constant voltage applied by the drain is the voltage that enables the transistor to operate in the linear region, and the optical pulse applied by the channel region is within the wavelength range that the ferroelectric semiconductor layer can perceive.
9. The method of use according to claim 7, characterized in that: The synaptic transistor is used to implement logic "AND" and "OR", specifically: When the security key is encoded as 0, a negative voltage pulse is input only at one of the input terminals, and the postsynaptic current is lower than the set threshold. Only when a negative voltage pulse is input at both input terminals at the same time, the postsynaptic current will exceed the set threshold. This is a logical "AND"; When the security key is encoded as 1, the synaptic current will exceed the preset threshold after a negative voltage pulse is input to either input terminal, which is a logical "OR".
10. The method of use according to claim 7, characterized in that: The synaptic transistor is used to implement logic "NOR" and "NAND", specifically: When the security key is encoded as 0, a positive voltage pulse is input to either input terminal, and the post-synaptic current will be lower than the preset threshold, which is a logical "NOR"; When the security key is encoded as 1, the post-synaptic current will only be lower than the set threshold when a positive voltage pulse is input to both input terminals at the same time. This is a logical "NAND".