Storage system, operation method thereof and computer readable storage medium

Abstract

The embodiment of the invention discloses a storage system, an operation method of the storage system and a computer readable storage medium, the storage system comprises a nonvolatile memory, the nonvolatile memory comprises a plurality of storage areas, each storage area comprises a plurality of first storage groups located in a first area and a plurality of second storage groups located in a second area, the first area supports physical addressing, and the second area supports physical addressing; the second area does not support physical addressing; and a memory controller coupled to the non-volatile memory, configured to: perform a wear leveling process by swapping a first memory group having a first group of write counts with a second memory group having a second group of write counts; wherein the first group of write-in counts is the maximum group of write-in counts in the plurality of group of write-in counts corresponding to the plurality of first storage groups, and the second group of write-in counts is the minimum group of write-in counts in the plurality of group of write-in counts corresponding to the plurality of second storage groups.

Description

Storage system and operation method thereof, and computer-readable storage medium Technical Field

[0001] The present application relates to, but is not limited to, a storage system and an operating method thereof, and a computer-readable storage medium. Background Art

[0002] Non-volatile memory (NVM) is widely used in various fields, including embedded systems such as computers and network interconnection devices, as well as voice, image, and data storage products such as digital cameras and digital voice recorders. As the storage capacity requirements of these products continue to increase, the process size of non-volatile memory continues to shrink, resulting in increasingly severe challenges to the reliability of non-volatile memory. In particular, non-volatile memory is limited by its own physical properties, which makes non-volatile memory have limited write endurance during use. During use, if a specific storage location in the non-volatile memory is written too many times and exceeds the write endurance, the storage location cannot be reliably used for subsequent storage operations, thereby affecting the data storage performance of the entire memory. Therefore, how to use different storage locations in a balanced way to maximize the life of the non-volatile memory has become an urgent problem to be solved.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present application provides a storage system, comprising: a non-volatile memory, comprising a plurality of storage areas, each of the storage areas comprising a plurality of first storage groups located in a first area and a plurality of second storage groups located in a second area, the first area supporting physical addressing, and the second area not supporting physical addressing; and

[0005] A memory controller coupled to the non-volatile memory is configured to perform wear leveling by exchanging a first storage group having a first group write count with a second storage group having a second group write count; wherein the first group write count is a maximum group write count among a plurality of group write counts corresponding to the plurality of first storage groups, and the second group write count is a minimum group write count among a plurality of group write counts corresponding to the plurality of second storage groups.

[0006] In a second aspect, an embodiment of the present application provides an operating method for a storage system, the storage system comprising a non-volatile memory and a memory controller coupled to the non-volatile memory, the non-volatile memory comprising a plurality of storage areas, each storage area comprising a plurality of first storage groups located in a first area and a plurality of second storage groups located in a second area, the first area supporting physical addressing and the second area not supporting physical addressing; the operating method comprising:

[0007] Wear leveling is performed by exchanging a first storage group having a first group write count with a second storage group having a second group write count; the first group write count is the maximum group write count among the multiple group write counts corresponding to the multiple first storage groups, and the second group write count is the minimum group write count among the multiple group write counts corresponding to the multiple second storage groups.

[0008] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the operating method as described in any one of the second aspects is performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0010] FIG1 is a block diagram of a storage system provided by an embodiment of the present application;

[0011] FIG2 is a block diagram of a storage area provided in an embodiment of the present application;

[0012] FIG3 is a schematic diagram showing the distribution of group write counts corresponding to storage groups in different storage areas according to an embodiment of the present application;

[0013] FIG4 is a mapping table between logical addresses and physical addresses in FIG3 ;

[0014] FIG5 is a schematic diagram illustrating the distribution of group write counts corresponding to storage groups in different storage areas after wear leveling processing according to an embodiment of the present application;

[0015] FIG6 is a mapping table between logical addresses and physical addresses in FIG5 ;

[0016] FIG7 is a schematic diagram showing the distribution of group write counts corresponding to storage groups in different storage areas according to another embodiment of the present application;

[0017] FIG8 is a schematic diagram showing the distribution of group write counts corresponding to storage groups in different storage areas after wear leveling processing according to another embodiment of the present application;

[0018] FIG9 is a mapping table between logical addresses and physical addresses in FIG8 ;

[0019] FIG10 is a schematic diagram of the use process of a double Bloom filter according to an embodiment of the present application;

[0020] FIG11 is a flowchart of a method for operating a storage system according to an embodiment of the present application;

[0021] FIG12 is a block diagram of a computer-readable storage medium provided in one embodiment of the present application;

[0022] FIG13 is a block diagram of a system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0024] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0025] In addition, the accompanying drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0026] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to actual circumstances.

[0027] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0028] Since new non-volatile memories represented by Flash, Phase Change Memory (PCM), Resistive Random Access Memory (RRAM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM) and Nantero's CNT Random Access Memory (NRAM) have the advantages of fast access speed, low energy consumption and non-volatile storage, the application of non-volatile memories is becoming more and more extensive. However, most non-volatile memories (such as Flash, PCM, RRAM, FRAM) have the disadvantage of limited write times, and the upper limit of the write times of non-volatile memories decreases with the increase of storage capacity, which shortens the life of non-volatile memories. For example, Flash can usually write 10 4 times, PCM can usually write 10 8 RRAM can write 10 5 Second class.

[0029] Taking PCM as an example, the basic principle of PCM is as follows: a high-value, short-duration (i.e., high-narrow) electric pulse is applied to a phase-change memory cell. Due to Joule heating and other factors, a portion of the initially crystalline phase-change memory layer melts due to temperatures exceeding its melting point. After the electric pulse is interrupted, the melted portion rapidly cools, reverting to an amorphous state with low atomic order, completing the transition from low resistance to high resistance. This is the erase (reset) process. The melted portion during this process is called the programming volume. If a low-value, long-duration (i.e., low-narrow) electric pulse is applied, causing the temperature within the programming volume to rise above the crystallization temperature but below the melting temperature, and the duration is sufficient to crystallize the amorphous structure within the programming volume, a low-resistance state is achieved. This is the write (set) process. The PCM read process involves applying a low, narrow electric pulse to the phase-change memory cell, bringing the phase-change memory layer below its crystallization temperature, and then measuring the resistance of the phase-change memory cell.

[0030] Phase change memory materials are used as the storage medium of PCM, and their performance directly affects the quality of device characteristics. The wear of phase change memory materials is mainly related to the number of writes. When the number of writes is evenly distributed, the wear of the phase change memory material will also be relatively uniform. This can maintain the phase change characteristics and stability of the phase change memory material, prevent thermal drift and phase change failure caused by excessive writes, and the PCM can achieve a service life of more than 5 years. However, in actual applications, due to the unevenness of data access patterns and write operations, the number of writes in the PCM will be unevenly distributed among the storage cells. This may cause the phase change memory materials on some storage cells to wear severely and fail in a short period of time (such as weeks or months), resulting in the PCM not being able to work properly. Therefore, in order to avoid the failure of a certain storage cell causing the failure of the entire PCM, wear leveling is usually used to evenly distribute the number of writes to different storage cells.

[0031] Wear leveling is one of the main ways to extend the lifespan of non-volatile memory. It distributes write operations to non-volatile memory evenly to each target address so that the wear of each storage location in the non-volatile memory reaches a relatively balanced level. However, traditional wear leveling requires a very high exchange frequency, which will cause a large amount of storage space and performance overhead. At the same time, the data exchange granularity of wear leveling adopted in related technologies is single and fixed, and it is impossible to perform flexible and more refined wear leveling on non-volatile memory. In addition, traditional wear leveling cannot resist malicious attacks. For example, phase change memory can perform in-situ write operations, that is, there is no need to perform an erase operation before the write operation, and the newly written data is directly replaced with the previously written data in situ. Based on this, malicious attack programs can detect the changes in the mapping from logical address to physical address during wear leveling, infer the new location of the storage block to be exchanged, and then repeatedly perform in-situ write operations on a specific location, causing the phase change memory to fail quickly.

[0032] In view of this, embodiments of the present application provide a storage system, an operating method thereof, and a computer-readable storage medium.

[0033] FIG1 is a block diagram of a storage system according to an embodiment of the present application. As shown in FIG1 , according to a first aspect of an embodiment of the present application, a storage system 100 is provided. The storage system 100 includes a non-volatile memory 110 including a plurality of storage areas 111 .

[0034] FIG2 is a block diagram of a storage area provided in an embodiment of the present application. In conjunction with FIG1 and FIG2 , each storage area 111 includes a plurality of first storage groups 1111 located in a first region and a plurality of second storage groups 1112 located in a second region. The first region supports physical addressing, while the second region does not. The storage system 100 further includes a memory controller 120 coupled to the non-volatile memory 110 and configured to perform wear leveling by swapping a first storage group 1111 having a first group write count with a second storage group 1112 having a second group write count. The first group write count is the maximum group write count among the plurality of group write counts corresponding to the plurality of first storage groups 1111, and the second group write count is the minimum group write count among the plurality of group write counts corresponding to the plurality of second storage groups 1112.

[0035] Here, each first storage group in the first area has a logical address and a corresponding physical address. The first area supports physical addressing, which means that an external device (eg, a host) can directly access the first area through the mapping relationship between the logical address and the physical address.

[0036] Each second storage group in the second area has a logical address and a corresponding physical address. The fact that the second area does not support physical addressing means that the logical address of the second storage group is not visible to an external device (for example, a host). Therefore, the external device cannot directly access the second area through the mapping relationship between the logical address and the physical address of the second storage group, that is, the external device cannot perform read or write operations on the second storage group in the second area.

[0037] In some embodiments, the second storage group in the second region may be used to store dirty data.

[0038] It should be noted that the first group write count is the maximum group write count among all group write counts corresponding to all first storage groups in the first region, and the second group write count is the minimum group write count among all group write counts corresponding to all second storage groups in the second region.

[0039] In an embodiment of the present application, each storage area in a non-volatile memory is divided into a first area that supports physical addressing and a second area that does not support physical addressing. When performing wear leveling processing, a first storage group with a first group write count is exchanged with a second storage group with a second group write count to transfer the first storage group with the first group write count from the first area to the second area, thereby preventing the first storage group with the largest group write count among multiple first storage groups from remaining in the first area that supports physical access after wear leveling processing, thereby avoiding the risk of the first storage group with the largest group write count among multiple first storage groups still being physically accessed after wear leveling processing.

[0040] In some embodiments, storage system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, or any other suitable electronic device having non-volatile memory 110 therein.

[0041] In some embodiments, the memory controller 120 may control the overall operation of the memory system 100. The memory controller 120 may store data in the nonvolatile memory 110 or may read data stored in the nonvolatile memory 110.

[0042] In some embodiments, the nonvolatile memory 110 may include one of a phase change memory, a resistive random access memory, a magnetic random access memory, and a carbon nanotube random access memory.

[0043] In some embodiments, the memory controller 120 may also store various information required for the operation of the memory system 100 (eg, a mapping table) in the non-volatile memory 110 or in a volatile memory of the memory controller 120 .

[0044] The memory controller 120 may also be configured to manage various functions regarding data stored or to be stored in the non-volatile memory 110, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 120 may also be configured to process error correction codes (ECC) regarding data read from or written to the non-volatile memory 110.

[0045] The memory controller 120 may also perform any other suitable functions, such as formatting the non-volatile memory 110. The memory controller 120 may communicate with the external device according to a specific communication protocol. For example, the memory controller 120 may communicate with the external device through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer Small Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, etc.

[0046] In the embodiment of the present application, the first storage group and the second storage group both include a first number of storage units; or the first storage group and the second storage group both include a second number of storage units, wherein the first number is greater than the second number.

[0047] For example, the non-volatile memory 110 may be divided into a plurality of storage areas, and each storage area may be divided into a plurality of storage groups. The first storage group and the second storage group each include a second number of storage units.

[0048] In some embodiments, the size of the first storage group and the second storage group can be the same as the size of a codeword (CW), where a codeword includes user data, error correction code (ECC), and metadata. The size of a codeword is typically determined by the size of the user data, the size of the error correction code (ECC), and the size of the metadata. The size of the user data is typically determined by the actual amount of data to be stored or transmitted. User data can be bits, bytes, words, or other units, depending on the storage system and data transmission requirements. The error correction code (ECC) is redundant information added to the user data to detect and correct errors during data transmission or storage. The size of the error correction code (ECC) depends on the size of the user data and the required error correction capability. The metadata contains information about the codeword, such as the data format, checksum type, error detection and correction scheme, and a mapping table from logical addresses to physical addresses. The size of the metadata depends on the design and implementation of the storage system and the required management and control capabilities. In general, different storage systems may choose codewords of different sizes to meet their performance, reliability, and storage requirements. It is understood that a codeword can include multiple storage cells, and the number of storage cells included in a codeword can be adjusted based on actual conditions.

[0049] In a specific embodiment, the size of the error correction code ECC is 256B, and the size of the codeword is 4KB. It can be understood that the size of the first storage group and the second storage group is also 4KB. Taking the non-volatile memory 110 as a phase change memory as an example, the second number is 2 12 .

[0050] In some embodiments, the ratio of the first quantity to the second quantity is in the range of 2 4 to 2 12 For example, the ratio of the first quantity to the second quantity is in the range of 2 4 , 2 8 or 2 12 .

[0051] In some embodiments, the size of the first storage group and the second storage group can be the same as the size of a storage block. Typically, the size of a storage block is 512KB (4KB*2 7 ) or 1024KB(4KB*2 8 It is understandable that a storage block may include multiple storage units, and the number of storage units included in a storage block may be adjusted according to actual conditions.

[0052] In a specific embodiment, the size of the storage block is 1024KB. It is understandable that the sizes of the first storage group and the second storage group are also 1024KB. Taking the non-volatile memory 110 as a phase change memory as an example, the first number is 2 20 .

[0053] It should be noted that the first number and the second number in the above embodiment are only examples, and the storage area, the first storage group, and the second storage group may be divided into different sizes according to the actual size and type of the non-volatile memory.

[0054] In traditional wear leveling, smaller data exchange granularity may lead to frequent data movement and copying, increasing space overhead, while larger data exchange granularity may lead to wear imbalance problems. The present application flexibly divides the data exchange granularity of wear leveling into different levels, and can divide the size of the first storage group and the second storage group into a first number of storage units at the first granularity level, or divide the size of the first storage group and the second storage group into a second number of storage units at the second granularity level. In other words, the present application can reasonably divide the data exchange granularity of wear leveling according to the actual size of the non-volatile memory, thereby improving the flexibility and precision of the wear leveling processing of the non-volatile memory.

[0055] In the embodiment of the present application, wear leveling can be performed on the non-volatile memory at different granularity levels, which can greatly improve the flexibility and sophistication of wear leveling for the non-volatile memory. In the embodiment of the present application, the memory controller 120 is specifically configured to: compare the first set of write counts with the second set of write counts; when the first set of write counts is greater than the second set of write counts, perform wear leveling by swapping the first storage group having the first set of write counts with the second storage group having the second set of write counts.

[0056] In an embodiment of the present application, the memory controller 120 is specifically configured to: perform wear leveling by exchanging data stored in a first storage group having a first set of write counts and data stored in a second storage group having a second set of write counts; and exchanging the logical address of the first storage group having the first set of write counts and the logical address of the second storage group having the second set of write counts.

[0057] FIG3 is a schematic diagram showing the distribution of group write counts corresponding to storage groups in different storage areas provided by an embodiment of the present application, and FIG4 is a mapping table between logical addresses and physical addresses in FIG3 . As shown in FIG3 and FIG4 , the storage area includes a plurality of first storage groups located in a first area and a second storage group located in a second area. The logical addresses (Logical Address) and physical addresses (Physical Address) of the first storage group and the second storage group have a one-to-one mapping relationship. Each first storage group has a group write count (Write count), and each second storage group also has a group write count. The Write count shown in FIG3 is the current group write count of each storage group.

[0058] Referring to FIG3 , it can be seen that the group write count of the first storage group corresponding to physical address 2 mapped to logical address 2 is 6K, which is the maximum group write count of all first storage groups, that is, the first group write count is 6K. The group write count of the second storage group corresponding to physical address M mapped to logical address M is 5K, which is the minimum group write count of all second storage groups, that is, the second group write count is 5K. At this point, the first group write count is greater than the second group write count.

[0059] It should be noted that the number of second storage groups shown in FIG3 is only an example and is not intended to limit the number of second storage groups in the embodiments of the present application.

[0060] Figure 5 is a schematic diagram illustrating the distribution of group write counts corresponding to storage groups in different storage areas after wear leveling according to an embodiment of the present application, and Figure 6 is a mapping table between logical addresses and physical addresses in Figure 5. Referring to Figures 5 and 6, the memory controller 120 is configured to: swap data stored in the first storage group corresponding to physical address 2 mapped to logical address 2 with data stored in the second storage group corresponding to physical address M mapped to logical address M; and swap the logical address of the first storage group corresponding to physical address 2 with the logical address of the second storage group corresponding to physical address M to perform wear leveling.

[0061] As shown in Figures 5 and 6, after wear leveling, physical address 2 corresponds to logical address M, and physical address M corresponds to logical address 2. Since the first storage group with the first set of write counts is swapped to the second area that does not support physical access, the first storage group with the first set of write counts will not be physically accessed in subsequent write operations. Even if a malicious attack program can detect the change in the mapping from logical addresses to physical addresses during wear leveling and infer the new location to be swapped, it will not be able to launch a brute force attack on the second area that does not support physical access. In other words, the storage system in the embodiment of the present application can resist malicious attacks when performing wear leveling.

[0062] In some embodiments, when the first storage group and the second storage group both include a first number of storage cells, the memory controller 120 is configured to: update the mapping table between the logical address and the physical address of each storage group in the storage area after wear leveling processing, and store the mapping table in the volatile memory of the memory controller 120.

[0063] In some embodiments, when both the first storage group and the second storage group include a first number of storage units, the mapping tables shown in Figures 4 and 6 are stored in a volatile memory (e.g., a static random access memory (SRAM)) of the memory controller 120. Since the first storage group and the second storage group have a first number of storage units, the total number of the divided first storage group and the second storage group is relatively small for the entire non-volatile memory, and therefore the space occupied by the mapping table used to reflect the correspondence between the logical addresses of the first storage group and the second storage group and the physical addresses is also small. In this way, the above-mentioned mapping table is stored in the memory controller, which speeds up the access speed of the memory controller to the above-mentioned mapping table without occupying too much space in the memory controller and without increasing the burden on the memory controller. In a specific example, when the size of the first storage group and the second storage group is the same as the size of the storage block, the mapping table used to reflect the correspondence between the logical addresses of the first storage group and the second storage group and the physical addresses is stored in the volatile memory of the memory controller.

[0064] In other embodiments, when both the first storage group and the second storage group include a second number of memory cells, the memory controller is configured to update a mapping table between logical addresses and physical addresses for each storage group in the storage area after the wear leveling process, and store the mapping table in the non-volatile memory 110. For example, when both the first storage group and the second storage group include a second number of memory cells, the mapping tables shown in FIG. 4 and FIG. 6 are stored in metadata of the non-volatile memory 110 of the memory controller 120.

[0065] Since the first storage group and the second storage group have a second number of storage units, the total number of the divided first storage group and the second storage group is relatively large for the entire non-volatile memory. At this time, the mapping table used to reflect the correspondence between the logical addresses of the first storage group and the second storage group and the physical addresses occupies a large space. If the mapping table is stored in the volatile memory of the memory controller, the space utilization of the memory controller will be greatly reduced, the burden of the memory controller will be increased, and the system performance will be affected. Therefore, in order to balance space efficiency and system performance, the above-mentioned mapping table is stored in the metadata of the non-volatile memory. In a specific example, when the size of the first storage group and the second storage group is the same as the size of the codeword, the mapping table used to reflect the correspondence between the logical addresses of the first storage group and the second storage group and the physical addresses is stored in the metadata of the codeword. When the memory controller needs to access the above-mentioned mapping table, it is necessary to read the metadata to obtain the above-mentioned mapping table.

[0066] In an embodiment of the present application, the memory controller is further configured to: when the first group write count is less than or equal to the second group write count, perform wear leveling processing by exchanging the first storage group having the first group write count with the first storage group having the third group write count; wherein the third group write count is the smallest group write count among the multiple group write counts corresponding to the multiple first storage groups.

[0067] Wear leveling is performed by exchanging data stored in a first storage group having a first set of write counts and data stored in a first storage group having a third set of write counts; and exchanging logical addresses of the first storage group having the first set of write counts and logical addresses of the first storage group having the third set of write counts.

[0068] FIG7 is a schematic diagram of the distribution of group write counts corresponding to storage groups in different storage areas provided by another embodiment of the present application. The mapping table between logical addresses and physical addresses in FIG7 can refer to FIG4. As shown in FIG4 and FIG7, the group write count of the first storage group corresponding to physical address 2 mapped to logical address 2 is 4K, and the group write count of the first storage group is the maximum value among the group write counts of all first storage groups, that is, the first group write count is 4K. The group write count of the second storage group corresponding to physical address M mapped to logical address M is 5K, and the group write count of the second storage group is the minimum value among the group write counts of all second storage groups, that is, the second group write count is 5K. The first group write count is smaller than the second group write count.

[0069] The group write count of the first storage group corresponding to the physical address 7 mapped to the logical address 7 is 6. The group write count of the first storage group is the minimum value among the group write counts of all first storage groups, that is, the third group write count is 6.

[0070] FIG8 is a schematic diagram illustrating the distribution of group write counts corresponding to storage groups in different storage areas after wear leveling according to another embodiment of the present application, and FIG9 is a mapping table between logical addresses and physical addresses in FIG8. Referring to FIG8 and FIG9, the memory controller 120 is configured to: swap data stored in the first storage group corresponding to physical address 2 mapped to logical address 2 with data stored in the first storage group corresponding to physical address 7 mapped to logical address 7; and swap the logical address of the first storage group corresponding to physical address 2 with the logical address of the second storage group corresponding to physical address 7 to perform wear leveling.

[0071] As shown in Figures 8 and 9, after wear leveling, physical address 2 corresponds to logical address 7, and physical address 7 corresponds to logical address 2. Since the first group write count is less than the second group write count, this means that the first storage group with the first group write count can still withstand a certain number of write operations. Therefore, wear leveling is performed by swapping the first storage group with the largest group write count and the first storage group with the smallest group write count in the first region, thereby balancing the wear of multiple first storage groups.

[0072] In some embodiments, when both the first storage group and the second storage group include a first number of memory cells, the memory controller 120 is configured to update a mapping table between logical addresses and physical addresses of each storage group of the memory area after wear leveling, and store the mapping table in a volatile memory of the memory controller 120. For example, when both the first storage group and the second storage group include a first number of memory cells, the mapping table shown in FIG. 9 is stored in a volatile memory (e.g., static random access memory) of the memory controller 120.

[0073] In other embodiments, when both the first storage group and the second storage group include a second number of memory cells, the memory controller is configured to update a mapping table between logical addresses and physical addresses for each storage group in the storage area after the wear leveling process, and store the mapping table in the non-volatile memory 110. For example, when both the first storage group and the second storage group include a second number of memory cells, the mapping table shown in FIG9 is stored in metadata of the non-volatile memory 110 of the memory controller 120.

[0074] In the embodiment of the present application, the memory controller 120 is configured to: before comparing the first set of write counts with the second set of write counts, compare the first set of write counts with a first preset threshold;

[0075] When the first set of write counts is greater than a first preset threshold, the first set of write counts is compared with the second set of write counts.

[0076] Taking FIG. 7 as an example, the first preset threshold is illustratively set to 3500, and the group write count of the first storage group corresponding to physical address 2 mapped to logical address 2 is 4K. The group write count of this first storage group is the maximum value among the group write counts of all first storage groups, that is, the first group write count is 4K. That is, when the first group write count is greater than the first preset threshold, the memory controller begins wear leveling.

[0077] It can be understood that when the first group of write counts is greater than the first preset threshold and the second group of write counts, the memory controller 120 is configured to: exchange the first storage group with the first group of write counts in the first area and the second storage group with the second group of write counts in the second area to perform wear leveling processing.

[0078] When the first group write count is greater than the first preset threshold but less than the second group write count, the memory controller 120 is configured to swap the first storage group with the first group write count and the first storage group with the third group write count in the first region for wear leveling.

[0079] When the first set of write counts is less than or equal to the first preset threshold, the memory controller 120 is configured to not perform wear leveling.

[0080] In some embodiments, the memory controller is configured to compare the first set of write counts with a first preset threshold within a preset period, and the preset period may range from 1 s to 5 s.

[0081] In the embodiment of the present application, the first preset threshold increases as the electrical distance (ED) between the first storage group corresponding to the first group of write counts and the voltage source increases.

[0082] In some embodiments, the closer the first storage group corresponding to the first set of write counts is to the voltage source, the more susceptible it is to the voltage source. For example, surges or leakage in the voltage source may accelerate damage to the first storage group. It is understood that as the electrical distance between the first storage group corresponding to the first set of write counts and the voltage source decreases, the overall service life of the first storage group also decreases. Consequently, the upper limit of the number of writes to the first storage group, i.e., the first preset threshold, also decreases accordingly, thereby performing wear leveling on the first storage group before it reaches its upper limit of writes, thereby preventing the first storage group from reaching its service life prematurely.

[0083] The greater the electrical distance between the first storage group corresponding to the first group of write counts and the voltage source, the less the first storage group is affected by the voltage source, and the overall service life of the first storage group will not be reduced due to surges or leakage of the voltage source. Therefore, the upper limit of the number of writes of the first storage group, that is, the first preset threshold, will be larger.

[0084] Table 1 shows an example of the electrical distance between the first storage group and the voltage source corresponding to the first set of write counts and the first preset threshold. As shown in Table 1, "NN" indicates that the electrical distance between the first storage group and the voltage source corresponding to the first set of write counts is close (near), and the corresponding first preset threshold is 400. "MM" indicates that the electrical distance between the first storage group and the voltage source corresponding to the first set of write counts is middle (middle), and the corresponding first preset threshold is 800. "FF" indicates that the electrical distance between the first storage group and the voltage source corresponding to the first set of write counts is far (far), and the corresponding first preset threshold is 1600.

[0085] Table 1

[0086] It should be noted that the value of the first preset threshold shown in Table 1 is only an example and is not used to limit the range of the first preset threshold in the embodiments of the present application.

[0087] In the embodiment of the present application, the group write count is obtained by counting the double Bloom filter.

[0088] Figure 10 is a schematic diagram of the use process of the double Bloom filter provided in an embodiment of the present application. In the double Bloom filter, one Bloom filter is used to store forward data (such as inserted elements), and the other Bloom filter is used to store reverse data (such as deleted elements). When an element is inserted, it is inserted into the forward Bloom filter and the reverse Bloom filter. When it is necessary to check whether an element exists, it is necessary to check the forward Bloom filter and the reverse Bloom filter at the same time. Only when both are judged to exist can it be determined that the element may exist.

[0089] As shown in FIG10 , when the sizes of the first and second storage groups are the same as the size of the storage blocks, a mapping table reflecting the correspondence between the logical addresses of the first and second storage groups and their physical addresses is stored in the SRAM of the memory controller. The LBA IDs shown in FIG10 are the logical block addresses of different first storage groups in a storage area. When a new LBA is accessed, the corresponding LBA ID (e.g., LBA ID3 shown in FIG10 ) is inserted into the forward Bloom filter CBF1 and the reverse Bloom filter CBF2. Specifically, LBA ID3 is used as input and three hash values ​​(H1, H2, H3) are calculated using three hash functions. The corresponding bits in the bit array of the forward Bloom filter are set to 1, indicating that LBA ID3 exists in the forward Bloom filter CBF1. Similarly, LBA ID3 is used as input and three hash values ​​are calculated using three hash functions. The corresponding bits in the bit array of the reverse Bloom filter CBF2 are set to 1, indicating that LBA ID3 exists in the reverse Bloom filter CBF2.

[0090] Subsequently, the forward Bloom filter CBF1 and the reverse Bloom filter CBF2 are queried alternately. The same hash function may be used to calculate the hash value, and the corresponding bit may be checked to see whether it is 1, to determine whether the corresponding LBA ID3 exists in the forward Bloom filter CBF1 and the reverse Bloom filter CBF2.

[0091] Exemplarily, taking the element to be queried (e.g., LBA ID3) as input, multiple hash values ​​are calculated using the hash function of the forward Bloom filter CBF1 at the 0th second. In the bit array of the forward Bloom filter CBF1, it is checked whether the bits of the corresponding calculated hash values ​​are all 1. If any of the bits is 0, it can be determined that the element does not exist in the forward Bloom filter CBF1, and the group write count does not increase.

[0092] Taking the element to be queried (e.g., LBA ID3) as input, multiple hash values ​​are calculated using the hash function of the forward Bloom filter CBF1. In the bit array of the forward Bloom filter CBF1, the bits corresponding to the calculated hash values ​​are checked to see if they are all 1. If any of the bits is 0, it can be determined that the element does not exist in the forward Bloom filter CBF1, and the group write count does not increase. At the first second, taking the element to be queried (e.g., LBA ID3) as input, multiple hash values ​​are calculated using the hash function of the reverse Bloom filter CBF2. In the bit array of the reverse Bloom filter CBF2, the bits corresponding to the calculated hash values ​​are checked to see if they are all 1. If any of the bits is 0, it can be determined that the element does not exist in the reverse Bloom filter CBF2, and the group write count does not increase.

[0093] In this way, after alternating queries on the forward Bloom filter CBF1 and the reverse Bloom filter CBF2, if all corresponding hash value bits in the forward Bloom filter CBF1 and the reverse Bloom filter CBF2 are 1, indicating that the element may exist in the dual Bloom filter, then the group write count of the first storage group corresponding to LBA ID3 increases.

[0094] The dual Bloom filter can store a large number of group write counts for the first and second storage groups, avoiding wasting storage system resources. It also uses the relationship between the group write counts and a first preset threshold to help perform wear leveling, thereby improving the lifespan and performance of the non-volatile memory.

[0095] In some embodiments, during the process of alternately querying two Bloom filters, the previous Bloom filter may be cleared after each query so that the Bloom filter state is reset during the next query.

[0096] As shown in Figure 10, at second 0, forward Bloom filter CBF1 is queried. The element to be queried is used as input, and multiple hash values ​​are calculated using the hash function of forward Bloom filter CBF1. The corresponding bits in the bit array of forward Bloom filter CBF1 are checked to see if they are all 1. If any bit is 0, it can be determined that the element does not exist in forward Bloom filter CBF1. After the query at second 0 is completed, the bit array of forward Bloom filter CBF1 is cleared, and the state of forward Bloom filter CBF1 is reset for use in the next query.

[0097] At the first second, the reverse Bloom filter CBF2 is queried. Using the element to be queried as input, the reverse Bloom filter CBF2's hash function is used to calculate multiple hash values. The bits corresponding to the calculated hash values ​​in the reverse Bloom filter CBF2's bit array are checked to see if they are all 1. If any bit is 0, it can be determined that the element does not exist in the reverse Bloom filter CBF2. After the query is completed at the first second, the reverse Bloom filter CBF2's bit array is cleared, and the state of the forward and reverse Bloom filter CBF2 is reset for use in the next query.

[0098] At the next time point, the two Bloom filters are queried alternately and the previously queried Bloom filter is cleared to achieve periodic query operations. In this way, through the above-mentioned alternating query and clearing operations, the interference of the previous query information on the subsequent query can be avoided, and the memory usage of the Bloom filter can also be reduced.

[0099] In the embodiment of the present application, the storage system includes a storage class memory (SCM); the non-volatile memory includes a phase change memory.

[0100] In the existing storage hierarchy, there is a gap in storage speed and storage capacity between dynamic random access memory (DRAM) and non-volatile memory (e.g., NAND flash memory), which limits the further improvement of computer computing power. To this end, a storage-class memory is proposed, whose storage speed and storage capacity are between dynamic random access memory and non-volatile memory. For example, the storage density of DRAM, PCM, and NAND can be 1X, 1X to 4X, and 4X; the read latency of DRAM, PCM, and NAND can be 50 nanoseconds, 50 to 100 nanoseconds, and 10 to 25 microseconds. It can be seen that the storage speed (read latency and write latency) and storage capacity (storage density) of PCM enable it to be well positioned between dynamic random access memory and non-volatile memory, acting as an intermediate memory.

[0101] At present, there are many types of storage media for storage-class memory, the more mainstream ones include phase change memory, resistive random access memory, magnetic random access memory and carbon nanotube random access memory.

[0102] The storage system in the embodiment of the present application divides each storage area in the non-volatile memory into a first area that supports physical addressing and a second area that does not support physical addressing. When performing wear leveling processing, the first storage group with the first group write count is exchanged with the second storage group with the second group write count to transfer the first storage group with the first group write count from the first area to the second area, thereby preventing the first storage group with the largest group write count among multiple first storage groups from remaining in the first area that supports physical access after wear leveling processing, thereby avoiding the risk of the first storage group with the largest group write count among multiple first storage groups still being physically accessed after wear leveling processing. This can effectively improve the wear leveling effect of non-volatile memories such as phase change memories, resist malicious program attacks, and increase service life.

[0103] According to a second aspect of an embodiment of the present application, a method for operating a storage system is provided. The storage system includes: a non-volatile memory and a memory controller coupled to the non-volatile memory, wherein the non-volatile memory includes multiple storage areas, each storage area includes multiple first storage groups located in a first area and multiple second storage groups located in a second area, the first area supports physical addressing, and the second area does not support physical addressing. The method for operating the storage system includes:

[0104] Wear leveling is performed by exchanging a first storage group having a first group write count with a second storage group having a second group write count; the first group write count is the maximum group write count among multiple group write counts corresponding to multiple first storage groups, and the second group write count is the minimum group write count among multiple group write counts corresponding to multiple second storage groups.

[0105] For example, the non-volatile memory may be divided into a plurality of storage areas, and each storage area may then be divided into a plurality of storage groups. The first storage group and the second storage group each include a second number of storage cells. The sizes of the first storage group and the second storage group are the same as the size of a codeword, where the codeword includes user data, an error correction code (ECC), and metadata. A codeword may include a plurality of storage cells, and the number of storage cells included in a codeword may be adjusted based on actual conditions.

[0106] In a specific embodiment, the size of the error correction code ECC is 256B, and the size of the codeword is 4KB. It can be understood that the size of the first storage group and the second storage group is also 4KB. Taking the non-volatile memory 110 as a phase change memory as an example, the second number is 2 12 .

[0107] In some embodiments, the ratio of the first quantity to the second quantity is in the range of 2 4 to 2 12 For example, the ratio of the first quantity to the second quantity is in the range of 2 4 , 2 8 or 2 12 .

[0108] In some embodiments, the size of the first storage group and the second storage group can be the same as the size of a storage block. Typically, the size of a storage block is 512KB (4KB*2 7 ) or 1024KB(4KB*2 8 It is understandable that a storage block may include multiple storage units, and the number of storage units included in a storage block may be adjusted according to actual conditions.

[0109] In a specific embodiment, the size of the storage block is 1024KB. It is understandable that the sizes of the first storage group and the second storage group are also 1024KB. Taking the non-volatile memory 110 as a phase change memory as an example, the first number is 2 20 .

[0110] It should be noted that the first number and the second number in the above embodiment are only examples, and the storage area, the first storage group, and the second storage group may be divided into different sizes according to the actual size and type of the non-volatile memory.

[0111] It is understood that the first storage group and the second storage group including the first number of storage cells have a first level of granularity, and the first storage group and the second storage group including the second number of storage cells have a second level of granularity. In the embodiments of the present application, wear leveling processing can be performed on the non-volatile memory at different granularity levels, which can greatly improve the flexibility and sophistication of wear leveling processing on the non-volatile memory.

[0112] FIG11 is a flowchart of a method for operating a storage system according to an embodiment of the present application. The following describes in detail how to perform wear leveling processing in conjunction with FIG3 to FIG9 and FIG11.

[0113] As shown in FIG. 11 , in step S101 , the memory controller obtains a first preset threshold, a plurality of group write counts of a plurality of first memory groups, and a plurality of group write counts of a second memory group.

[0114] In step S102, the first group write count is compared with a first preset threshold to determine whether the first group write count is greater than the first preset threshold, wherein the first group write count is the maximum value among the group write counts of all first storage groups.

[0115] If the first set of write counts is less than or equal to the first preset threshold, step S104 is executed, ie, wear leveling is not performed.

[0116] If the first group write count is greater than the first preset threshold, step S103 is executed. In step S103, the first group write count is compared with the second group write count, and the first group write count is the minimum value among the group write counts of all second storage groups. Determine whether the first group write count is greater than the second group write count. Referring to Figures 3 and 4, the group write count of the first storage group corresponding to the physical address 2 mapped by the logical address 2 is 6K, and the group write count of the first storage group is the maximum value among the group write counts of all first storage groups, that is, the first group write count is 6K. The group write count of the second storage group corresponding to the physical address M mapped by the logical address M is 5K, and the group write count of the second storage group is the minimum value among the group write counts of all second storage groups, that is, the second group write count is 5K.

[0117] When the first group write count is greater than the second group write count, step S105 is executed to perform wear leveling by exchanging the data stored in the first storage group with the first group write count and the data stored in the second storage group with the second group write count; and exchanging the logical address of the first storage group with the first group write count and the logical address of the second storage group with the second group write count.

[0118] Referring to Figures 5 and 6, the data stored in the first storage group corresponding to the physical address 2 mapped by the logical address 2 and the data stored in the second storage group corresponding to the physical address M mapped by the logical address M are exchanged; and the logical address of the first storage group corresponding to the physical address 2 and the logical address of the second storage group corresponding to the physical address M are exchanged to perform wear leveling processing.

[0119] As shown in Figures 5 and 6, after wear leveling, physical address 2 corresponds to logical address M, and physical address M corresponds to logical address 2. Since the first storage group with the first set of write counts is swapped to the second area that does not support physical access, the first storage group with the first set of write counts will not be physically accessed in subsequent write operations. It can be understood that the storage system in the embodiment of the present application can resist malicious attacks when performing wear leveling.

[0120] When the first group write count is less than or equal to the second group write count, step S106 is executed. In step S106, data stored in the first storage group having the first group write count and data stored in the first storage group having the third group write count are swapped; and logical addresses of the first storage group having the first group write count and logical addresses of the first storage group having the third group write count are swapped to perform wear leveling processing.

[0121] Referring to Figures 4 and 7 , the group write count of the first storage group corresponding to physical address 2 mapped to logical address 2 is 4K. The group write count of this first storage group is the maximum value among all the group write counts of the first storage groups, that is, the first group write count is 4K. The group write count of the second storage group corresponding to physical address M mapped to logical address M is 5K. The group write count of this second storage group is the minimum value among all the group write counts of the second storage groups, that is, the second group write count is 5K. The first group write count is less than the second group write count.

[0122] The group write count of the first storage group corresponding to the physical address 7 mapped to the logical address 7 is 6. The group write count of the first storage group is the minimum value among the group write counts of all first storage groups, that is, the third group write count is 6.

[0123] Referring to Figures 8 and 9, the data stored in the first storage group corresponding to the physical address 2 mapped by the logical address 2 and the data stored in the first storage group corresponding to the physical address 7 mapped by the logical address 7 are exchanged; and the logical address of the first storage group corresponding to the physical address 2 and the logical address of the second storage group corresponding to the physical address 7 are exchanged to perform wear leveling processing.

[0124] As shown in Figures 8 and 9, after wear leveling, physical address 2 corresponds to logical address 7, and physical address 7 corresponds to logical address 2. Since the first group write count is less than the second group write count, this means that the first storage group with the first group write count can still withstand a certain number of write operations. Therefore, wear leveling is performed by swapping the first storage group with the largest group write count and the first storage group with the smallest group write count in the first region, thereby balancing the wear of multiple first storage groups.

[0125] After executing step S105 or step S106 , step S107 is executed, that is, the mapping table between the logical address and the physical address of each storage group in the storage area is updated after the wear leveling process.

[0126] In some embodiments, when both the first storage group and the second storage group include a first number of memory cells, a mapping table between logical addresses and physical addresses of each storage group of the storage area is updated after wear leveling processing, and the mapping table is stored in the volatile memory of the memory controller 120. For example, when both the first storage group and the second storage group include a first number of memory cells, the mapping tables shown in FIG. 4 and FIG. 6 are stored in the volatile memory of the memory controller 120.

[0127] In other embodiments, when both the first storage group and the second storage group include a second number of storage cells, a mapping table between logical addresses and physical addresses of each storage group in the storage area is updated after the wear leveling process, and the mapping table is stored in the non-volatile memory 110. For example, when both the first storage group and the second storage group include a second number of storage cells, the mapping tables shown in FIG4 and FIG6 are stored in metadata of the non-volatile memory 110 of the memory controller 120.

[0128] Refer to Figure 12, which is a block diagram of a computer-readable storage medium provided in an embodiment of the present application. As shown in Figure 12, an embodiment of the present application provides a readable storage medium, wherein the computer-readable storage medium 200 stores a computer program 210. When the computer program 210 is executed by a processor, it can implement the operating method of the storage system in the above technical solution. The operating method includes: performing wear leveling processing by exchanging a first storage group having a first group write count with a second storage group having a second group write count; the first group write count is the maximum group write count among the multiple group write counts corresponding to the multiple first storage groups, and the second group write count is the minimum group write count among the multiple group write counts corresponding to the multiple second storage groups.

[0129] Referring to Figure 13, which is a block diagram of a system according to an embodiment of the present application, system 300 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, or any other suitable electronic device having a non-volatile memory 310 (e.g., a PCM).

[0130] As shown in FIG13 , the system 300 may include a host 330 and a storage system. The storage system may include a memory controller 320 and at least one non-volatile memory 310. The host 330 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 330 may be configured to send data to or receive data from the non-volatile memory 310. FIG13 illustrates that the memory controller 320 is connected to four non-volatile memories 310. In fact, the embodiment of the present application does not impose any special limitation on the number of non-volatile memories 310 connected to the memory controller 320. The number of non-volatile memories 310 connected to the memory controller 320 may be less than four (e.g., one); or the number of non-volatile memories 310 connected to the memory controller 320 may be greater than four (e.g., five).

[0131] In some embodiments, the memory controller 320 may be separately connected to the host 330 and the nonvolatile memory 310 and configured to control the nonvolatile memory 310. The memory controller 320 may manage data stored in the nonvolatile memory 310 and communicate with the host 330.

[0132] In a specific example, the storage system may include at least one non-volatile memory 310 and a memory controller 320 coupled to the non-volatile memory 310; wherein the storage system may include storage-class memory; and the non-volatile memory 310 may include phase-change memory.

[0133] Still referring to FIG13 , the memory controller 320 includes a first communication interface 321, a second communication interface 322, a processing unit (Processing Unit) 323, a read-only memory (ROM) 324, a static random access memory (SRAM) 325, and a storage medium controller 326. The processing unit 323 and the host 330 are connected in communication via the first communication interface 321 and the second communication interface 322. The processing unit 323 can also be connected to the storage medium controller 326 to control the storage medium controller 326. The storage medium controller 326 is connected to the non-volatile memory 310 to control the non-volatile memory 310. The processing unit 323 can also be connected to the ROM 324 and the SRAM 325. The processing unit 323 can obtain data from the ROM 324 and can store some temporary data in the SRAM 325.

[0134] In some embodiments, the first communication interface 321 may be a Peripheral Component Interconnect Express (PCIE), that is, the first communication interface may be an interface set according to a high-speed serial computer expansion bus standard; the second communication interface 322 may be a Compute Express Link (CXL).

[0135] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0136] The above description is only a preferred embodiment of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made using the contents of the present application description and drawings under the inventive concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application. Industrial Applicability

[0137] In an embodiment of the present application, each storage area in a non-volatile memory is divided into a first area that supports physical addressing and a second area that does not support physical addressing. When performing wear leveling processing, a first storage group with a first group write count is exchanged with a second storage group with a second group write count to transfer the first storage group with the first group write count from the first area to the second area, thereby preventing the first storage group with the largest group write count among multiple first storage groups from remaining in the first area that supports physical access after wear leveling processing, thereby avoiding the risk of the first storage group with the largest group write count among multiple first storage groups still being physically accessed after wear leveling processing.

Claims

1. A storage system, comprising: A non-volatile memory, comprising a plurality of storage areas, each of the storage areas comprising a plurality of first storage groups located in a first area and a plurality of second storage groups located in a second area, the first area supporting physical addressing, and the second area not supporting physical addressing; as well as A memory controller coupled to the non-volatile memory is configured to perform wear leveling by exchanging a first storage group having a first group write count with a second storage group having a second group write count; wherein the first group write count is a maximum group write count among a plurality of group write counts corresponding to the plurality of first storage groups, and the second group write count is a minimum group write count among a plurality of group write counts corresponding to the plurality of second storage groups.

2. The storage system according to claim 1, wherein: The memory controller is specifically configured as follows: comparing the first set of write counts to the second set of write counts; When the first group write count is greater than the second group write count, wear leveling is performed by exchanging the first storage group having the first group write count with the second storage group having the second group write count.

3. The storage system according to claim 2, wherein: The memory controller is further configured to: When the first group of write counts is less than or equal to the second group of write counts, wear leveling is performed by exchanging the first storage group having the first group of write counts with the first storage group having the third group of write counts; wherein the third group of write counts is the smallest group of write counts among the multiple group write counts corresponding to the multiple first storage groups.

4. The storage system according to claim 3, wherein: The memory controller is specifically configured as follows: By exchanging the data stored in the first storage group having the first set of write counts and the data stored in the second storage group having the second set of write counts; and exchanging the logical address of the first storage group having the first set of write counts and the logical address of the second storage group having the second set of write counts Address for wear leveling; or, by swapping data stored in the first storage group having a first set of write counts and data stored in the first storage group having a third set of write counts; And the logical address of the first storage group having the first set of write counts and the logical address of the first storage group having the third set of write counts are exchanged to perform wear leveling processing.

5. The storage system according to claim 3, wherein: The memory controller is configured to: Before comparing the first set of write counts with the second set of write counts, comparing the first set of write counts with a first preset threshold; When the first group of write counts is greater than the first preset threshold, the first group of write counts is compared with the second group of write counts.

6. The storage system according to claim 5, wherein: The first preset threshold increases as the electrical distance between the first storage group corresponding to the first group of write counts and the voltage source increases.

7. The storage system according to claim 4, wherein: The first storage group and the second storage group each include a first number of storage units; the memory controller is configured to: update a mapping table between a logical address and a physical address of each storage group of the storage area after the wear leveling process, and store the mapping table in a volatile memory of the memory controller; or, The first storage group and the second storage group each include a second number of storage units; the memory controller is configured to: update a mapping table between a logical address and a physical address of each storage group of the storage area after the wear leveling process, and store the mapping table in the non-volatile memory; The first number is greater than the second number.

8. The storage system according to claim 7, wherein: The group write count is obtained by double Bloom filter counting.

9. The storage system according to claim 1, wherein: The storage system includes a storage-level storage system; The non-volatile memory includes a phase change memory.

10. A method for operating a memory system, the memory system comprising a nonvolatile memory and a memory controller coupled to the nonvolatile memory, the nonvolatile memory comprising a plurality of memory areas, each memory area comprising a plurality of first memory groups located in a first area and a plurality of second memory groups located in a second area, the first area supporting physical addressing, and the second area not supporting physical addressing; The operation method comprises: performing a wear leveling process by swapping a first storage group having a first set of write counts with a second storage group having a second set of write counts; The first group write count is a maximum group write count among a plurality of group write counts corresponding to the plurality of first storage groups, and the second group write count is a minimum group write count among a plurality of group write counts corresponding to the plurality of second storage groups.

11. The operating method according to claim 10, wherein: The operation method also includes: comparing the first set of write counts to the second set of write counts; When the first group write count is greater than the second group write count, wear leveling is performed by exchanging the first storage group having the first group write count with the second storage group having the second group write count.

12. The operating method according to claim 11, wherein: The operation method also includes: When the first group of write counts is less than or equal to the second group of write counts, wear leveling is performed by exchanging the first storage group having the first group of write counts with the first storage group having the third group of write counts; wherein the third group of write counts is the smallest group of write counts among the multiple group write counts corresponding to the multiple first storage groups.

13. The operating method according to claim 12, wherein: The operation method also includes: Performing wear leveling by swapping data stored in the first storage group having a first set of write counts and data stored in the second storage group having a second set of write counts; and swapping a logical address of the first storage group having the first set of write counts and a logical address of the second storage group having the second set of write counts; or, By exchanging the data stored in the first storage group having the first group write count and the data stored in the third storage group having the third group write count data stored in the first storage group having a first group write count; and exchanging a logical address of the first storage group having a first group write count and a logical address of the first storage group having a third group write count to perform wear leveling processing.

14. The operating method according to claim 12, wherein: The operation method also includes: Before comparing the first set of write counts with the second set of write counts, comparing the first set of write counts with a first preset threshold; When the first group of write counts is greater than the first preset threshold, the first group of write counts is compared with the second group of write counts.

15. The operating method according to claim 13, wherein: The first storage group and the second storage group each include a first number of storage units; the operation method further includes: updating a mapping table between a logical address and a physical address of each storage group of the storage area after the wear leveling process, and storing the mapping table in a volatile memory of the memory controller; or, The first storage group and the second storage group each include a second number of storage units; the operation method further includes: updating a mapping table between a logical address and a physical address of each storage group of the storage area after the wear leveling process, and storing the mapping table in the non-volatile memory; The first number is greater than the second number. 16 . A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the operating method according to claim 10 .

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