Resistance memory with resistance expansion layer

Abstract

To limit resistance variability across resistive random access memory (RRAM) cells, the present disclosure includes an RRAM cell in which a resistance extension layer within the RRAM cell is between a top electrode and a bottom electrode of the RRAM cell. The resistance extension layer is in series with the filament forming layer of the RRAM cell and has no impedance with the filament forming layer of the RRAM cell. The resistance spreading layer may be under the filament forming layer, or the resistance spreading layer may be over the filament forming layer. The resistance spreading layer may be further in series with the bottom electrode or the top electrode and has no impedance.

Description

Background Art

[0001] The present disclosure relates generally to the field of semiconductor device technology, and more particularly, to a resistive random access memory (RRAM) cell including a resistive spreading layer between a top electrode and a bottom electrode.

[0002] Metal-insulator-metal (MIM) devices can be used in integrated circuits. MIM devices include a MIM dielectric between metal plates, which form the electrodes of the MIM device. MIM devices are used in various applications, such as dynamic random access memory (DRAM) capacitors and decoupling capacitors, as well as in RRAM devices.

[0003] A typical RRAM device includes a typical RRAM cell in which a filament-forming layer is connected in series and presents no impedance to either electrode. The filament-forming layer, which is typically insulating, can conduct electricity through a filament or conductive path that forms after a sufficiently high voltage is applied. The conductive path can be generated by different mechanisms, including vacancy or metal defect migration. Once a filament is formed, it can be reset (disconnected, resulting in high resistance) or set (reformed, resulting in lower resistance) by another voltage. Therefore, in one operating state, there is at least one current path through the filament-forming layer.

[0004] For conventional RRAM cells to be utilized in conventional high voltage applications, this high voltage is typically reduced at the input electrodes of the RRAM cell. Figure 1A The prior art RRAM cell 100 and Figure 1B A solution to this problem is exemplarily described in a prior art circuit of , in which a voltage is stepped down or reduced at the RRAM cell 100 by a large compliance resistor (e.g., a transistor). The compliance resistor has typically been placed in series with the RRAM cell 100 and has relatively reduced the voltage seen by the RRAM cell 100. Traditionally, the compliance resistor has been placed external to the RRAM cell 100 (i.e., not between the top electrode 106 and the bottom electrode 110 therein). The RRAM cell 100 and circuit can result in the filament(s) 104 being relatively narrow (e.g., having relatively few oxygen vacancies in their formation, etc.), thereby resulting in relatively large resistance variability across the filament(s) 104 within the same or different RRAM cells 100, respectively. This resistance variation can render these known techniques and structures unsuitable or less suitable for high-voltage applications. Summary of the Invention

[0005] In some embodiments of the present invention, a resistive random access memory (RRAM) cell is provided. The RRAM cell includes a bottom electrode located below and in direct contact with a resistive spreading layer. The RRAM cell also includes a top electrode located above and in direct contact with a filament-forming layer. Current flows through the top electrode and generates a filament within the filament-forming layer, electrically connecting the bottom of the top electrode to the top of the resistive spreading layer. The resistive spreading layer radially propagates the current from the top of the resistive spreading layer to the bottom of the resistive spreading layer, where the current enters the bottom electrode.

[0006] In some implementations, there is no impedance between the entire top surface of the filament-forming layer and the entire bottom surface of the top electrode. Similarly, there may be no impedance between the entire bottom surface of the filament-forming layer and the entire top surface of the resistive spreading layer. Likewise, there may be no impedance between the entire bottom surface of the resistive spreading layer and the entire top surface of the bottom electrode.

[0007] The corresponding sidewalls of the bottom electrode, the resistive spreading layer, the filament-forming layer, and the top electrode may be coplanar. The resistive spreading layer may be between the top electrode and the bottom electrode. In some implementations, the top electrode may be a titanium nitride (TiN) top electrode, the bottom electrode may be a TiN bottom electrode, the filament-forming layer may be a transition metal oxide filament-forming layer, and the resistive spreading layer may be an aluminum carbide (AlC) resistive spreading layer.

[0008] In some embodiments of the present invention, another resistive random access memory (RRAM) cell is presented. The RRAM cell includes a top electrode located above and in direct contact with a resistive spreading layer. The RRAM cell also includes a bottom electrode located below and in direct contact with a filament-forming layer. Current flows through the bottom electrode and generates a filament within the filament-forming layer, electrically connecting the top of the bottom electrode to the bottom of the resistive spreading layer. The resistive spreading layer radially propagates the current from the bottom of the resistive spreading layer to the top of the resistive spreading layer, where the current enters the top electrode.

[0009] In some implementations, there is no impedance between the entire bottom surface of the filament-forming layer and the entire upper surface of the bottom electrode. Similarly, there is no impedance between the entire upper surface of the filament-forming layer and the entire bottom surface of the resistive spreading layer. Likewise, there is no impedance between the entire upper surface of the resistive spreading layer and the entire bottom surface of the top electrode.

[0010] In some implementations, the corresponding sidewalls of the bottom electrode, the resistive spreading layer, the filament-forming layer, and the top electrode are coplanar. The resistive spreading layer is between the top and bottom electrodes. In some implementations, the top electrode is a titanium nitride (TiN) top electrode, the bottom electrode is a TiN bottom electrode, the filament-forming layer is a transition metal oxide filament-forming layer, and the resistive spreading layer is an aluminum carbide (AlC) resistive spreading layer.

[0011] In other embodiments of the present disclosure, a method for fabricating a resistive random access memory (RRAM) cell is provided. The method includes forming a bottom electrode in a straight line above and perpendicular to a bottom conductive line. The method also includes forming a filament-forming layer directly on the bottom metal wire. The method also includes forming a resistive spreading layer directly on the filament-forming layer. The method also includes forming a top electrode directly on the filament-forming layer.

[0012] In some implementations, the method further includes forming a sacrificial cap directly on the top electrode and / or forming encapsulation spacers on sidewalls of the bottom electrode, on sidewalls of the resistive spreading layer, on sidewalls of the filament-forming layer, and on sidewalls of the top electrode.

[0013] In some implementations, the method further includes forming an interlayer dielectric (ILD) above the upper surface of the sacrificial cap and / or etching a top conductive line trench within the ILD. The etching removes the sacrificial cap and exposes at least a portion of the top electrode. The method further includes forming a top conductive line within the top conductive line trench and on the exposed portion of the top electrode.

[0014] These embodiments provide methods and structures for increasing the resistance between the top and bottom electrodes of an RRAM cell. Such RRAM cells with high resistance capabilities may be a contender for future random access memory implementations and in-logic memory applications such as artificial synapses. Arrays of artificial resistive synapses in the form of analog resistive processing units (RPUs) have shown great potential to accelerate the learning process in artificial neural networks compared to all digital solutions. The resistors at each intersection of the RPU array constitute neuromorphic weights and should be able to be programmed over a roughly linear range of conductance. The large RPU arrays required for high processing throughput require large resistance values ​​at the intersections on the order of megaohms.

[0015] Therefore, to limit resistance variability, embodiments of the present disclosure recognize that an RRAM cell may include a resistance spreading layer within the RRAM cell that is between the top and bottom electrodes of the series-connected RRAM cells and has no impedance relative to the filament-forming layer. In one embodiment, the resistance spreading layer may be located below the filament-forming layer such that the resistance spreading layer is closer to the bottom electrode relative to the filament-forming layer. In another embodiment, the resistance spreading layer may be located above the filament-forming layer such that the resistance spreading layer is closer to the top electrode relative to the filament-forming layer.

[0016] Thus, embodiments of the present disclosure result in the current passing through the filament(s) being forced to spread radially through the resistive spreading layer, rather than uniformly through the conductive electrode as in the RRAM cell 100. The result is a high spreading resistance in series with the filaments, where the resistance of the filaments is inversely proportional to the filament diameter. When the filament resistance is much smaller than the resistance through the resistive spreading layer, the total resistance between the top and bottom electrodes can be controlled by varying the geometry of the resistive spreading layer and controlling the radial distance of the filament groupings (e.g., by controlling the number of filaments within a particular filament group, etc.). Consequently, the variability of the total resistance between the top and bottom electrodes can be reduced.

[0017] Embodiments of the present disclosure also cause current to flow through the resistive spreading layer, thereby generating a localized potential drop across it, such that most of the potential drop occurs within a radial distance of several filament diameters. Thus, multiple filaments can be formed independently, separated by several filament diameters, without one path stealing voltage from its adjacent paths. This gives a multi-filament operating mode in which the total conductance between the top and bottom electrodes is proportional to the number of filaments. Here, the large number of filaments helps to reduce the variability of the total resistance between the top and bottom electrodes, which is still primarily controlled by the predetermined geometry of the resistive spreading layer.

[0018] The above and other aspects, features and advantages of various embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other aspects, features and advantages of various embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0020] Figure 1A Depicted is a cross-sectional view of a prior art RRAM cell.

[0021] Figure 1B Description includes Figure 1A Schematic diagram of a prior art circuit of an RRAM cell.

[0022] Figure 2Depicted is a cross-sectional view of an RRAM cell including a resistive spreading layer between a top electrode and a bottom electrode according to an embodiment of the present disclosure.

[0023] Figures 3 to 11 is a cross-sectional manufacturing view of a semiconductor device including an RRAM cell having a resistive spreading layer according to an embodiment of the present disclosure.

[0024] Figure 12 Depicted is a cross-sectional view of an RRAM cell including a resistive spreading layer between a top electrode and a bottom electrode according to an embodiment of the present disclosure.

[0025] Figure 13 A method of manufacturing a semiconductor device including a RRAM cell having a resistance spreading layer according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0026] Now refer to Figures 2 to 13 , wherein like components are labeled with like numerals, shows exemplary embodiments including semiconductor carriers, semiconductor devices such as wafers, chips, integrated circuits, micro devices, etc. according to embodiments of the present disclosure, and will now be described in more detail below. It should be noted that although this specification may refer to components in the singular tense, Figures 2 to 13 More than one component may be depicted in Figures 2 to 13 The specific number of components depicted in the drawings and the orientation of the applicable structural diagrams or cross-sectional views are chosen to best illustrate the various embodiments described herein.

[0027] Figure 2 Depicted is a cross-sectional view of an RRAM cell 200 including a resistive spreading layer 212 between a top electrode 206 and a bottom electrode 210 , in accordance with an embodiment of the present invention.

[0028] RRAM cell 200 is an exemplary non-volatile solid-state memory that utilizes the change in resistance across a filament-forming layer 202 under an applied electric field. RRAM cell 200 can be programmed into two or more different states or levels that exhibit different resistance characteristics. The programmable cell states can be used to represent different data values, thereby allowing the storage of information.

[0029] The RRAM cell 200 may include a MIM structure. This structure includes an insulating layer (I) sandwiched between two metal (M) electrodes. Applying a voltage pulse across the RRAM cell 200 enables the device to transition from an insulating state (HRS), or an off-state, commonly referred to as a logic value "0," to a low resistance state (LRS), or an on-state, commonly referred to as a logic value "1," and vice versa.

[0030] Typically, the prepared RRAM cell 200 is initially in the HRS. To switch the device from the HRS to the LRS, application of a voltage (e.g., a high voltage pulse, etc.) enables the formation of a conductive path in the filament-forming layer 202, which may be referred to as a filament 204, and the RRAM cell 200 is switched to the LRS. This process, which occurs due to the soft breakdown of the metal-insulator metal (MIM) structure, is generally referred to as "electroforming," and the voltage at which this process occurs is referred to as a forming voltage. To switch the RRAM cell 200 from the LRS to the HRS, a voltage pulse referred to as a RESET voltage may be applied.

[0031] To read data from the RRAM cell 200, a read voltage is applied that does not disturb the current state of the RRAM cell 200 to determine whether the cell is in a logic 0 (HRS) state or a logic 1 (LRS) state. Because the LRS and HRS retain their respective values ​​even after the applied voltage is removed, the RRAM cell 200 is a non-volatile memory.

[0032] The switching of the RRAM cell 200 is based on the growth of conductive filaments 204 within the filament-forming layer 202. The conductive filament(s) 204 may also be referred to as channels having a diameter on the order of nanometers, which connect the corresponding top electrode 206 or bottom electrode 210 of the RRAM cell 200 with the resistive spreading layer 212. When the conductive filament(s) 204 are formed across the thickness of the filament-forming layer 202 (as depicted), a low LRS with high conductivity is obtained, and when the conductive filament(s) 204 are disconnected from the gaps of the conductive filament(s) 204 across the filament-forming layer 202, a HRS is generated.

[0033] In some implementations, the RRAM cell 200 can have more than two programmable states, thereby permitting storage of more than one bit per RRAM cell 200. The different programmable states correspond to different relative proportions of the conductive filament(s) 204 across the filament-forming layer 202. In particular, the RRAM cell 200 can have intermediate states, wherein the RRAM cell 200 includes conductive filaments 204 of varying volumes or a varying number of conductive filaments 204. Because the LRS and HRS exhibit a large resistance contrast, varying the size of the conductive filaments 204 or increasing the number of conductive filaments 204 throughout the RRAM cell 200 produces a corresponding variation in the resistance of the RRAM cell 200.

[0034] The RRAM cell 200 includes a bottom electrode 210, a top electrode 206, and a dual RRAM layer located between the bottom electrode 210 and the top electrode 206. The dual RRAM layers are a resistive spreading layer 212 and a filament-forming layer 202. The resistive spreading layer 212 can be below the filament-forming layer 202, as shown. In this embodiment, the resistive spreading layer 212 is directly below the filament-forming layer 202, in series with it, and in direct contact with it. Thus, there is substantially no electrical impedance between the resistive spreading layer 212 and the filament-forming layer 202.

[0035] In the described implementation, the RRAM cell 200 can be a pillar, a pillar, or the like. One or more sidewalls of the RRAM cell 200 can be coplanar. For example, the filament-forming layer 202 can include a side surface 203, a side surface 205, a front surface 207, and a back surface 209. The resistive spreading layer 212 can include a side surface 213, a side surface 215, a front surface 217, and a back surface 219. The side surfaces 203 and 213 can be coplanar, the side surfaces 205 and 215 can be coplanar, the front surfaces 207 and 217 can be coplanar, and the back surfaces 209 and 219 can be coplanar. The top electrode 206 and the bottom electrode 210 can have similar side surfaces, front surfaces, and back surfaces, which can also be coplanar with the associated surfaces of the resistive spreading layer 212 and the filament-forming layer 202, respectively. Thus, the sidewalls of the pillar-shaped, cylindrical, or similarly shaped RRAM cell 200 can be coplanar.

[0036] To limit the resistance change across the RRAM cell 200, the resistive spreading layer 212 is located within the RRAM cell 200, between the top electrode 206 and the bottom electrode 210 in series, and has no impedance relative to the filament-forming layer 202. For example, there is no impedance between the entire top surface of the filament-forming layer and the entire bottom surface of the top electrode. Thus, in one example, the entire top surface of the filament-forming layer is in direct mechanical and electrical contact with the entire bottom surface of the top electrode.

[0037] Thus, embodiments of the present disclosure result in current 220 passing through the filament(s) 204 being forced to spread radially through the resistive spreading layer 212 rather than uniformly. Based on the conductive properties of the conductive electrodes 210 and 206, the current 220 will spread uniformly through the conductive electrodes 210 and 206, respectively. The result is a high spreading resistance in series with the filament 204, where the resistance of the filament 204 is inversely proportional to the diameter of the filament 204. When the resistance of the filament 204 is much smaller than the resistance through the resistive spreading layer 212, the total resistance between the top electrode 206 and the bottom electrode 210 can be controlled by varying the geometry or material (e.g., thickness, etc.) of the resistive spreading layer 212 and controlling the diameter of the filament 204. Consequently, the variability of the total resistance between the top electrode 206 and the bottom electrode 210 can be reduced.

[0038] Thus, embodiments of the present disclosure also cause current to flow through the resistive extension layer 212, thereby generating a localized potential drop across it, such that most of the potential drop occurs within a radial distance of several filament diameters. Thus, multiple filaments 204 can be independently formed within the filament-forming layer 202, separated by several filament diameters, with one path not stealing voltage from its adjacent path. This provides a multi-filament 204 operating mode in which the total conductance between the top electrode 206 and the bottom electrode 210 is proportional to the number of filaments 204. Here, the large number of filaments 204 helps to reduce the variability of the total resistance between the top electrode 206 and the bottom electrode 210, which is still primarily controlled by the predetermined geometry or material selection of the resistive extension layer 212.

[0039] Figures 3 to 7 Depicts the manufacturing stages of forming a semiconductor device 300. Specifically, refer to Figures 3 to 7 The method discussed involves being manufactured to include Figure 2 or Figure 12 A semiconductor device 300 of the RRAM cell 200 is shown.

[0040] For the purposes of the description below, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives refer to the structures and methods being described as oriented in the accompanying drawings. The terms "overlying", "on top", "positioned on" or "positioned on top" indicate that a first element, e.g., a first structure, is present on a second element, e.g., a second structure, wherein an intermediate element, e.g., an interface structure, may be present between the first element and the second element. The terms "direct contact" and the like refer to that a first element (e.g., a first structure) and a second element (e.g., a second structure) are connected at the interface of the two elements without any intermediate conductive, insulating or semiconducting layer. It should be noted that the term "selective to", e.g., "the first element is selective to the second element", means that the first element can be etched and the second element can act as an etch stop layer.

[0041] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measurements based on the equipment available at the time of filing this application. For example, substantial coplanarity between various materials may include appropriate manufacturing tolerances of ±8%, ±5%, or ±2% between coplanar materials.

[0042] For the sake of brevity, conventional techniques related to the fabrication of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. In addition, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. The various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps will be mentioned only briefly herein or will be omitted entirely without providing well-known process details.

[0043] Typically, the various processes for forming the microchips to be packaged into ICs are divided into four general categories, namely, film deposition, removal / etching, semiconductor doping, and patterning / photolithography. Deposition is any process by which material is grown, coated, or otherwise transferred onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD). Removal / etching is any process by which material is removed from a wafer. Examples include etching processes (wet or dry), chemical mechanical planarization (CMP), and the like. Semiconductor doping is the process of changing electrical properties, typically by diffusion and / or by ion implantation, by doping, for example, transistor source and drain electrodes. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing is used to activate the implanted dopants. Films of conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be changed as voltage is applied. By forming structures of these various components, millions of transistors can be constructed and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the process of forming a three-dimensional relief image, or pattern, on a semiconductor substrate so that the pattern can be subsequently transferred to the substrate. In semiconductor lithography, the pattern is formed from a photosensitive polymer called a photoresist. In order to build the complex structures that make up the transistors and the many wires that connect the millions of transistors in the circuit, the lithography and etching pattern transfer steps are repeated many times. Each pattern printed on the wafer is aligned with the previously formed pattern, and the conductors, insulators, and selectively doped regions are slowly built up to form the final device.

[0044] Figure 3 A cross-sectional manufacturing view of a semiconductor device 300 according to an embodiment of the present disclosure is depicted. At the current manufacturing stage, bottom conductive line(s) 350 may be formed on or within a substrate 310 .

[0045] Semiconductor device 300 can be an integrated circuit (IC) chip. The manufacturer can distribute the IC chip in raw wafer form (that is, as a single wafer with multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the IC chip can be installed in a single-chip package (such as a plastic carrier with a wire fixed to a motherboard or other more advanced carrier) or a multi-chip package (such as a ceramic carrier with any one or both of surface interconnection or buried interconnection). In any case, the IC chip can be integrated with other chips, discrete circuit elements, and / or other signal processing equipment as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product including an IC chip, ranging from toys and other low-end applications to advanced computer products with a display, keyboard, or other input device, and a central processing unit.

[0046] In one or more implementations, substrate 310 can be a semiconductor or insulator having an active surface semiconductor layer. Substrate 310 can be crystalline, semi-crystalline, microcrystalline, or amorphous. Substrate 310 can be substantially (i.e., excluding contaminants) a single element (e.g., silicon), predominantly (i.e., doped with) a single element, such as silicon (Si) or germanium (Ge), or can include a compound, such as GaAs, SiC, or SiGe. Substrate 310 can also have multiple material layers.

[0047] In some implementations, the substrate 310 may be an interlayer dielectric (ILD) layer, whereby additional layers and / or structures or components of the semiconductor device 300 have previously been fabricated below the interlayer dielectric (ILD) layer. The ILD may have a silicon-containing material selected from compounds such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH, silicon-containing materials in which some or all of the Si of the above is replaced by Ge, carbon-doped oxides, inorganic polymers, hybrid polymers, such as polyamide or SiLKH. TM organic polymers, other carbon-containing materials, organic-inorganic materials such as spin-on-glass and silsesquioxane-based materials, and diamond-like carbon (DLC) (also known as amorphous hydrogenated carbon, α-C:H).

[0048] The bottom conductive line 350 may be formed of one or more materials, material layers, etc. used as conductive lines of IC devices, such as copper, tungsten, platinum, titanium nitride, tantalum nitride, titanium aluminum nitride, etc.

[0049] The bottom conductive line 350 can be formed in the substrate 310 by conductive line manufacturing techniques. For example, trench(es) can be formed in the substrate 310 by known photolithography techniques and then filled with the conductive material of the bottom conductive line 350. Excess bottom conductive line 350 material can be removed from the upper surface of the substrate 310 using chemical mechanical planarization or other known methods so that the upper surface of the substrate 310 and the upper surface of the bottom conductive line 350 are coplanar.

[0050] The bottom conductive line 350 can be electrically connected to other components of the semiconductor device 300 through one or more electrical paths. For example, one or more electrical paths (e.g., VIAs, wires, etc.) can connect the bottom conductive line 350 to a memory controller, etc. In this way, components of the semiconductor device 300, or components connected to the semiconductor device 300, can be electrically connected to the RRAM cell 200 via the bottom conductive line 350 and / or the top conductive line 410, as shown in FIG. Figure 11 shown.

[0051] Figure 4 A cross-sectional manufacturing view of a semiconductor device 300 according to an embodiment of the present disclosure is depicted. At the current manufacturing stage, an encapsulation layer 320 may be formed on a substrate 310 and on bottom conductive line(s) 350 , and bottom electrode(s) 330 may be formed within the encapsulation layer 320 .

[0052] The encapsulation layer 320 may be, for example, a silicon layer or a silicon-based layer such as a silicon nitride layer, and may be formed on the substrate 310 by one or more deposition processes. The bottom electrode 330 is formed within the encapsulation layer 320 using a conductive material deposition technique. For example, a trench may be formed within the encapsulation layer 320 using known photolithography techniques to expose a portion below the associated bottom conductive line 350. The trench may be filled with a conductive bottom electrode 330 material. CMP or polishing may be used to remove excess bottom electrode 330 material from the upper surface of the encapsulation layer 320. The material of the bottom electrode 330 may be any common conductive material used as an electrode, such as tungsten, platinum, titanium nitride, tantalum nitride, titanium aluminum nitride, and the like.

[0053] In some implementations, a bottom electrode 330 trench is formed through the encapsulation layer 320, thereby exposing a portion of the upper surface of the bottom conductive line 350 previously formed in the substrate 310. In this way, the bottom electrode 330 can contact the bottom conductive line 350 such that there is substantially no or minimal electrical impedance between the bottom electrode 330 and the bottom conductive line 350.

[0054] Figure 5 A cross-sectional manufacturing view of a semiconductor device 300 according to an embodiment of the present disclosure is depicted. At the current manufacturing stage, the RRAM cell 200 build-up layers are fabricated.

[0055] For example, to manufacture the RRAM cell 200, Figure 2 As shown, a bottom electrode material layer 360 is formed on the encapsulation layer 320, a resistance extension layer 362 is formed on the bottom electrode material layer 360, a filament forming layer 364 is formed on the resistance extension layer 362, a top electrode material layer 366 is formed on the filament forming layer 364, and / or a covering layer 368 is formed on the top electrode material layer 366.

[0056] For example, to manufacture the RRAM cell 200, Figure 12 As shown, a bottom electrode material layer 360 is formed on the encapsulation layer 320, a filament forming layer 364 is formed on the bottom electrode material layer 360, a resistance expansion layer 362 is formed on the filament forming layer 364, a top electrode material layer 366 is formed on the resistance expansion layer 362, and / or a covering layer 368 is formed on the top electrode material layer 366.

[0057] The bottom electrode material layer 360 may be formed by depositing a conductive electrode material, such as titanium nitride, onto the encapsulation layer 320 and / or the electrode 330. The bottom electrode material layer 360 may be formed to a thickness between 5 and 75 nm. In certain embodiments, the bottom electrode material layer 360 may be formed to a thickness between 20 and 30 nm.

[0058] The resistive spreading layer 362 may be formed by depositing a dielectric material, such as aluminum carbide (AlC). The resistive spreading layer 362 may be formed to a thickness between 2 and 50 nm. In certain embodiments, the resistive spreading layer 362 may be formed to a thickness between 5 and 10 nm.

[0059] The resistive extension layer 362 should support high electric fields and high current densities. For example, a 1 megohm resistor with a 10 nm diameter filament 204, biased at 1 V, carries a current density of 1.3×106 A / cm2 and a maximum field of 2.6 MV / cm. An adventurous material that can undergo many programming cycles is one with a very short mean free path (MFP). A short MFP ensures that resistive behavior is maintained even over very short distances, but being longer than the MFP ensures that electrons do not obtain insufficiently high energy from the field. Suitable materials for the resistive extension layer 362 should be highly disordered, such as amorphous semiconductor materials.

[0060] The filament-forming layer 364 may be formed by depositing a metal oxide material, such as hafnium oxide (HfO x ), tantalum oxide (TaO x ) or titanium oxide (TiO x) is formed. The filament-forming layer 364 may also be referred to as an RRAM cell insulating layer. In other embodiments, the filament-forming layer 364 may also be referred to as an oxygen-deficient metal oxide layer, a transition metal oxide layer, etc. The filament-forming layer 364 may be formed to a thickness between 2 and 50 nm. In a specific embodiment, the filament-forming layer 364 may be formed to a thickness between 4 nm and 8 nm.

[0061] The top electrode material layer 366 can be formed by depositing a conductive electrode material (e.g., titanium nitride). The top electrode material layer 366 is typically, but not necessarily, formed of the same material as the bottom electrode material layer 360. The top electrode material layer 366 can be formed to a thickness between 5 and 75 nm. In certain embodiments, the top electrode material layer 366 can be formed to a thickness between 15 and 25 nm.

[0062] A capping layer 368 may be formed by depositing a dielectric material such as silicon nitride on the top electrode material layer 366. The capping layer 368 may be a mask layer and may be formed to a thickness between 10 and 80 nm. In a specific embodiment, the capping layer 368 may be formed to a thickness between 30 and 40 nm.

[0063] Figure 6 A cross-sectional manufacturing view of a semiconductor device 300 according to an embodiment of the present disclosure is depicted. At the current manufacturing stage, the RRAM cell 200 is formed by patterning the RRAM cell stacking layer. For example, etching techniques remove unwanted or exposed portions of the RRAM cell stacking layer and retain desired portions of the RRAM cell stacking layer to form one or more RRAM cells 200.

[0064] The capping layer 368 can be developed or patterned using photolithography techniques to leave portions of the capping layer 368 on the top layer of the cell stack, thereby defining and protecting the underlying RRAM cell 200 layer from the etchant of the chemical etch or the high-energy kinetic energy (ion, electron, or photon) beam of the dry etch. The protected underlying desired RRAM cell 200 layer is thereby retained and effectively forms the RRAM cell 200. The etching technique typically removes portions of the undesired RRAM cell 200 layer and typically exposes the encapsulation layer 320 in place, typically on the exterior of the formed RRAM cell 200.

[0065] The etching technique may be a physical or dry etching technique, or a chemical wet etching technique. In a preferred embodiment, the etching technique is a physical dry etching technique, and, as such, there is less risk of damage to the formed RRAM cell 200 material (e.g., limited lateral etching of the RRAM cell 200 layer material may be experienced due to the absence of a chemical etchant).

[0066] As depicted, the formed RRAM cell 200 includes a bottom electrode 210 formed from a remaining portion of the bottom electrode material layer 360, a resistive spreading layer 212 formed from a remaining portion of the resistive spreading layer 362, a filament-forming layer 202 formed from a remaining portion of the filament-forming layer 364, and a top electrode 206 formed from a remaining portion of the top electrode material layer 366. At this stage of fabrication, the RRAM cell 200 may also include a sacrificial cap 370 formed from a remaining portion of the capping layer 368.

[0067] Figure 7 A cross-sectional manufacturing view of a semiconductor device 300 according to an embodiment of the present disclosure is depicted. At the current stage of manufacturing, an encapsulation layer 380 is formed on the encapsulation layer 320 and on and around the one or more RRAM cells 200 .

[0068] The encapsulation layer 380 is a layer of dielectric material that helps prevent or limit short circuits between the various layers of the RRAM cell 200. For example, Figure 8 The spacer 383 formed by the encapsulation layer 380 described in prevents the bottom electrode 210 and the top electrode 206 from contacting via the side surfaces of the RRAM cell 200 .

[0069] The encapsulation layer 380 may be formed by depositing a dielectric conformal and insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, amorphous carbon, aluminum nitride, etc., on the exposed encapsulation layer 320 and on and around the RRAM cell 200. For example, the encapsulation layer 380 may be formed by depositing a blanket layer of dielectric material on the previously exposed encapsulation layer 320, on the sidewall(s) or side surface(s) of the RRAM cell(s) 200, and on the upper surface(s) of the RRAM cell(s) 200.

[0070] The thickness of the encapsulation layer 380 can be thick enough to protect the cell stack 380 during subsequent etching of undesired portions of the encapsulation isolation layer 380, such that the undesired encapsulation isolation layer 380 can be removed from the field while remaining on the sidewall(s) or side surface(s) of the RRAM cell(s) 200. For example, the encapsulation layer 380 can be formed to a thickness between 2 and 100 nm. In certain embodiments, the encapsulation layer 380 can be formed to a thickness between 10 and 20 nm.

[0071] Figure 8 A cross-sectional manufacturing view of a semiconductor device 300 according to an embodiment of the present disclosure is depicted. At the current manufacturing stage, encapsulation spacers 382 are formed from the encapsulation layer 380 around the RRAM cell 200.

[0072] The encapsulation spacers 382 may be formed by removing undesired portions of the encapsulation layer 380 and retaining desired portions of the encapsulation layer 380 on the sidewall(s) of the RRAM cell 200 .

[0073] Known directional etching techniques may be used to etch away or otherwise remove undesirable portions of the encapsulation layer 380. These undesirable portions of the encapsulation layer 380 may be generally horizontal (i.e., portions of the encapsulation layer 380 that are wider than they are tall). The directional etching process may retain desired portions of the encapsulation layer 380 that are located on the sidewalls of the encapsulation layer 380. These desired portions of the encapsulation layer 380 may be generally vertical, such as Figure 8 As shown in the cross-sectional view of (i.e., the portion of the layer(s) having a height greater than the width).

[0074] The etching technique may be a physical or dry etching technique, or a chemical wet etching technique. In a preferred embodiment, the etching technique is a chemical wet etching technique. Thus, the encapsulation layer 320 may be configured as an etch stop layer. For clarity, if an ILD 390 is required, e.g. Figure 9 As shown, to surround the sides and top of the RRAM cell 200, this manufacturing stage can be omitted.

[0075] Figure 9 A cross-sectional manufacturing view of a semiconductor device 300 according to an embodiment of the present disclosure is depicted. At the current manufacturing stage, an ILD 390 is formed on the encapsulation layer 320 and around the RRAM cell 200 .

[0076] As needed or desired, ILD 390 may be formed by depositing a blanket layer of a material such as a low-k dielectric material over encapsulation layer 320, encapsulation spacers 382, ​​and sacrificial cap 370. ILD 390 may be formed to a thickness generally greater than or generally above the upper surface of sacrificial cap 370.

[0077] Figure 10 A cross-sectional manufacturing view of the semiconductor device 300 is depicted in accordance with an embodiment of the present disclosure. At the current manufacturing stage, conductive trenches 404 and 406 are formed in the ILD 390 .

[0078] The conductive trench(es) 406 , 404 may be formed by known selective removal techniques to remove undesirable portions of the ILD 390 , generally above the bottom conductive line 350 and / or generally above the RRAM cell 200 .

[0079] The conductive trench(es) 404 generally expose at least a portion of an underlying conductive structure, such as a corresponding bottom conductive trace 350. The conductive trench(es) 406 generally expose at least a portion of an upper surface of the RRAM cell 200 (e.g., at least a portion of an upper surface of the top electrode 206) and planarize an upper surface of the encapsulation spacer 382 with an upper surface of the RRAM cell 200.

[0080] In a preferred embodiment, as depicted, conductive trench 406 exposes the entire upper surface of RRAM cell 200 (e.g., the upper surface of encapsulation spacer 382 and the upper surface of top electrode 206). Similarly, conductive trench 404 exposes at least a portion of the upper surface of the associated bottom conductive trace 350.

[0081] As described, etching techniques may be used to form the conductive trenches 404 , 406 with orthogonal sidewalls (ie, parallel to the sidewalls of the RRAM cell 200 ) or the conductive trenches 404 , 406 with sloped sidewalls.

[0082] According to an embodiment of the present disclosure, the upper surface of the top electrode 206 can serve as an etch stop layer, wherein an etch stop is formed for the conductive trench 406. In this manner, the conductive trench 406 is formed using an etch stop layer embedded or otherwise included in the RRAM cell 200.

[0083] The etching technique used to form the conductive trench 406 can be a physical or dry etching technique, or a chemical wet etching technique. In a preferred implementation, the etching technique used to form the conductive trench 406 is a chemical wet etching technique, and the top electrode 206 is configured as a wet etch stop.

[0084] Figure 11 A cross-sectional manufacturing view of a semiconductor device 300 according to an embodiment of the present disclosure is depicted. At the current manufacturing stage, a conductive line 408 is formed within the conductive line trench 404 , and a top conductive line 410 is formed within the conductive line trench 406 .

[0085] Conductive line 408 and top conductive line 410 may be formed by depositing conductive material within conductive line trench(es) 404 and 406 , respectively.

[0086] The top conductive line 410 can be directly connected to the top electrode 206 and the RRAM cell 200. For example, there can be no electrical impedance or the electrical impedance can be minimized between the top conductive line 410 and the top electrode 206. For example, the top conductive line 410 can contact a portion or the entire upper surface of the top electrode 206. In some implementations, the top conductive line 410 contacts the entire upper surface of the top electrode 206 and further contacts at least a portion of the upper surface(s) of the adjacent encapsulation spacer(s) 382.

[0087] Top conductors 410 and 408 can be electrically connected to other components of the IC device through one or more electrical pathways within the IC device. For example, one or more electrical pathways can connect top conductor 410 to a memory controller, etc. In this manner, components of semiconductor device 300 can be electrically connected to RRAM cell 200.

[0088] Figure 12 A cross-sectional view of an RRAM cell 200 including a resistive spreading layer 212 between a top electrode 206 and a bottom electrode 210 is depicted, according to an embodiment of the present disclosure. Figure 12 The RRAM cell 200 is Figure 2 The difference is that the relative orientations of the dual RRAM (ie, the resistance spreading layer 212 and the filament-forming layer 202) are reversed. Figure 12 The current direction of the RRAM cell 200 (eg, from the bottom electrode 210 to the top electrode 206) can be further related to Figure 2 The RRAM cell is reversed (eg, from the top electrode 206 to the bottom electrode 210 ). Figure 12 The RRAM cell 200 is described with Figure 2 The description of the RRAM cell 200 is similar and will not be repeated here.

[0089] Figure 13 A method 500 of fabricating a semiconductor device 300 including an RRAM cell 200 according to an embodiment of the present disclosure is shown. The method 500 may include forming one or more RRAM cells 200 (block 502). The RRAM cells 200 may be formed on an encapsulation layer 320 and / or on a bottom electrode 330 within the encapsulation layer 320. The RRAM cells 200 may be formed vertically in line with the bottom electrode 330. For example, associated in-line RRAM cells 200 and bottom electrodes 330 may share the same vertical bisector.

[0090] Forming the RRAM cell 200 may include forming a bottom electrode material layer 360 on the encapsulation layer 320 above the bottom electrode 330 (block 504). Forming the RRAM cell 200 may include forming a resistive spreading layer 362 and a filament-forming layer 364 on the bottom electrode material layer 360 (block 506). The relative orientation of the resistive spreading layer 362 and the filament-forming layer 364 may be selected as desired. Forming the RRAM cell 200 may also include forming a top electrode material layer 366 on the filament-forming layer 364 (block 508). In some implementations, a capping layer 368 may also be formed on the top electrode material layer 366. Forming the RRAM cell 200 may also include removing portions of the bottom electrode material layer 360, the resistive spreading layer 362, the filament-forming layer 364, and the top electrode material layer 366, while retaining other portions to form one or more RRAM cells 200 (block 510).

[0091] The method 500 may further include forming encapsulation spacer(s) 382 on the sidewall(s) of the RRAM cell 200 (block 512). The encapsulation spacer(s) 382 may be formed by forming an encapsulation layer on the substrate encapsulation layer 320 and on and around the RRAM cell 200 (block 514).

[0092] The encapsulation spacer(s) 382 may be further formed by removing the undesired portion(s) of the encapsulation layer (block 516). For example, the undesired portion(s) of the encapsulation layer may be etched away by chemical or physical etching. The desired or remaining portion(s) of the encapsulation layer effectively forms the encapsulation spacer(s) 382 and may be located on the sidewall(s) or side surface(s) of one or more RRAM cells 200 (block 518).

[0093] Method 500 may continue by forming a top conductive line in the RRAM cell 200 and / or on the encapsulation spacer 382 (block 520). For example, a top conductive line 410 is formed in the ILD 390 above the upper surface of the RRAM cell 200 and above the upper surface of the encapsulation spacer(s) 382. Using the upper surface top electrode 206 as an etch stop, a conductive line trench 406 may be formed in the ILD 390 (block 522), thereby exposing the upper surface of the upper surface top electrode 206. The etch may further expose at least a portion of the upper surface of the encapsulation spacer 382. The top conductive line 410 may be formed by depositing a conductive material in the conductive line trench 406 such that the conductive material contacts the upper surface of the top electrode 206 (block 524). The conductive material may further contact portions of the encapsulation spacer 382. CMP may be used to planarize the upper surface of the top conductive line 410 and the upper surface of the ILD 390.

[0094] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, practical applications, or improvements over existing technologies in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A resistance random access memory (RRAM) cell, comprising: a bottom electrode disposed below the resistance extension layer and in direct contact with the resistance extension layer; a top electrode located above and in direct contact with the filament-forming layer, wherein current flowing through the top electrode generates filaments within the filament-forming layer, the filaments electrically connecting a bottom of the top electrode with a top of the resistive spreading layer; as well as The resistance spreading layer spreads the current radially from the top of the resistance spreading layer to the bottom of the resistance spreading layer and enters the bottom electrode. 2 . The RRAM cell of claim 1 , wherein there is no resistance between the entire upper surface of the filament-forming layer and the entire bottom surface of the top electrode. 3 . The RRAM cell of claim 2 , wherein there is no impedance between the entire bottom surface of the filament-forming layer and the entire upper surface of the resistance spreading layer. 4 . The RRAM cell of claim 3 , wherein there is no impedance between the entire bottom surface of the resistance spreading layer and the entire upper surface of the bottom electrode. 5 . The RRAM cell of claim 4 , wherein respective sidewalls of the bottom electrode, the resistance spreading layer, the filament-forming layer, and the top electrode are coplanar. The RRAM cell of claim 1 , wherein the resistive spreading layer is located between the top electrode and the bottom electrode.

7. The RRAM cell of claim 1, wherein the top electrode is a titanium nitride (TiN) top electrode, wherein the bottom electrode is a TiN bottom electrode, wherein the filament-forming layer is a transition metal oxide filament-forming layer, and wherein the resistance spreading layer is an aluminum carbide (AlC) resistance spreading layer.

8. A resistance random access memory (RRAM) cell, comprising: a top electrode located above the resistance extension layer and in direct contact with the resistance extension layer; a bottom electrode disposed below and in direct contact with the filament-forming layer, wherein current flowing through the bottom electrode generates filaments within the filament-forming layer, the filaments electrically connecting a top portion of the bottom electrode with a bottom portion of the resistive spreading layer; as well as The resistance spreading layer spreads the current radially from the bottom of the resistance spreading layer to the top of the resistance spreading layer and enters the top electrode. 9 . The RRAM cell of claim 8 , wherein there is no resistance between the entire bottom surface of the filament-forming layer and the entire upper surface of the bottom electrode. 10 . The RRAM cell of claim 9 , wherein there is no impedance between the entire upper surface of the filament-forming layer and the entire bottom surface of the resistance spreading layer. 11 . The RRAM cell of claim 10 , wherein there is no impedance between the entire upper surface of the resistance spreading layer and the entire bottom surface of the top electrode. 12 . The RRAM cell of claim 11 , wherein respective sidewalls of the bottom electrode, the resistance spreading layer, the filament-forming layer, and the top electrode are coplanar.

13. The RRAM cell of claim 8, wherein the resistive spreading layer is located between the top electrode and the bottom electrode.

14. The RRAM cell of claim 8, wherein the top electrode is a titanium nitride (TiN) top electrode, wherein the bottom electrode is a TiN bottom electrode, wherein the filament-forming layer is a transition metal oxide filament-forming layer, and wherein the resistance spreading layer is an aluminum carbide (AlC) resistance spreading layer.

15. A method for manufacturing a resistance random access memory (RRAM) cell, comprising: forming a bottom electrode above the bottom conductive line and in a straight line perpendicular to the bottom conductive line; forming a filament-forming layer directly on the bottom electrode; forming a resistance spreading layer directly on the filament forming layer; as well as A top electrode is formed directly on the filament-forming layer.

16. The RRAM cell manufacturing method according to claim 15, further comprising: A sacrificial cap is formed directly on the top electrode.

17. The RRAM cell manufacturing method according to claim 16, further comprising: Encapsulation spacers are formed on sidewalls of the bottom electrode, on sidewalls of the resistance spreading layer, on sidewalls of the filament-forming layer, and on sidewalls of the top electrode.

18. The RRAM cell manufacturing method according to claim 17, further comprising: An interlayer dielectric ILD is formed over an upper surface of the sacrificial cap.

19. The RRAM cell manufacturing method according to claim 18, further comprising: A top conductive trench is etched in the ILD, the etching removing the sacrificial cap and exposing at least a portion of the top electrode.

20. The RRAM cell manufacturing method according to claim 19, further comprising: A top conductive line is formed within the top conductive line trench and on the exposed portion of the top electrode.

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