Capacitor

Abstract

The present disclosure improves electrical characteristics. A capacitor (1) includes a silicon substrate (2), a dielectric layer (4), and a conductor layer (5). The silicon substrate (2) has a doped layer (3). The doped layer (3) comprises a first doped layer (31) disposed along the second region (A2) of the first main surface (21) of the silicon substrate (2), a second doped layer (32) disposed at the bottom of the porous portion (23) of the silicon substrate (2), and a third doped layer (33) disposed at the side of the porous portion (23) of the silicon substrate (2). The doped layer (3) includes a first portion (35) connecting the first doped layer (31) to the third doped layer (33) and having a first curved portion (351) curved concavely in a cross-sectional view. The doped layer (3) includes a second portion (36) connecting the second doped layer (32) to the third doped layer (33) and having, in a cross-sectional view, a second curved portion (361) that is convexly curved.

Description

Technical Field

[0001] The present disclosure relates to capacitors, and more particularly to capacitors including silicon substrates. Background Art

[0002] Patent document 1 discloses a capacitor, including a silicon substrate, a conductor layer and a dielectric layer. The silicon substrate has a first main surface and a second main surface. The first main surface of the silicon substrate includes a capacitance performance region and a non-capacitance performance region. The silicon substrate includes a porous portion formed along a thickness direction in the capacitance performance region of the first main surface. The porous portion has a plurality of micropores.

[0003] For capacitors, improvements in electrical characteristics may be required.

[0004] Patent document 1: WO2020 / 184517A1 Summary of the invention

[0005] An object of the present disclosure is to provide a capacitor having improved electrical characteristics.

[0006] A capacitor of one aspect of the present disclosure includes a silicon substrate, a dielectric layer, and a conductor layer. The silicon substrate has a first main surface, a second main surface, and a porous portion, the first main surface including a first region and a second region surrounding the first region, the porous portion being formed in the first region and having a plurality of micropores along a thickness direction defined relative to the silicon substrate. The dielectric layer is disposed above the surface of the porous portion and the second region of the silicon substrate. The conductor layer is disposed on the dielectric layer. The intervals between adjacent micropores in the plurality of micropores are uneven in the thickness direction defined relative to the silicon substrate. The conductor layer overlaps the first region and the second region in the thickness direction defined relative to the silicon substrate in a top view. The silicon substrate has a doping layer containing a p-type dopant or an n-type dopant. The doping layer includes a first doping layer, a second doping layer, and a third doping layer. The first doping layer is disposed along the second region of the silicon substrate. The second doping layer is disposed at the bottom of the porous portion of the silicon substrate. The third doping layer is disposed at the side of the porous portion of the silicon substrate. The doping layer has a first portion connecting the first doping layer to the third doping layer. The first portion has a first curved portion that is concavely curved in a cross-sectional view in a second direction orthogonal to the first direction as the thickness direction. The doping layer includes a second portion connecting the second doping layer to the third doping layer. The second portion has a second curved portion that is convexly curved in a cross-sectional view.

[0007] The capacitor of another aspect of the present disclosure includes a silicon substrate, a dielectric layer and a conductor layer. The silicon substrate has a first main surface, a second main surface and a porous portion, the first main surface includes a first region and a second region surrounding the first region, the porous portion is formed in the first region and has a plurality of micropores along the thickness direction defined relative to the silicon substrate. The dielectric layer is arranged above the surface of the porous portion and the second region of the silicon substrate. The conductor layer is arranged on the dielectric layer. The intervals between adjacent micropores in the plurality of micropores are uneven in the thickness direction defined relative to the silicon substrate. The conductor layer overlaps the first region and the second region in the thickness direction defined relative to the silicon substrate in a top view. The silicon substrate has a doping layer containing a p-type dopant or an n-type dopant. The doping layer includes a first doping layer, a second doping layer and a third doping layer. The first doping layer is arranged along the second region of the silicon substrate. The second doping layer is arranged at the bottom of the porous portion of the silicon substrate. The third doping layer is arranged on the side of the porous portion of the silicon substrate. In the doping layer, a first doping layer is connected to a third doping layer, and in a cross-sectional view in a second direction orthogonal to a first direction as a thickness direction, a smaller angle of two angles formed between the first doping layer and the third doping layer is an obtuse angle. In the doping layer, a second doping layer is connected to a third doping layer, and in a cross-sectional view, a smaller angle of two angles formed between the second doping layer and the third doping layer is an obtuse angle. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic cross-sectional view of a capacitor according to a first embodiment;

[0009] Figure 2 This is an enlarged view of the main part of the capacitor cross section;

[0010] Figure 3 is a top view of the capacitor;

[0011] Figure 4A and 4B is a cross-sectional view for explaining a step in a method of manufacturing a capacitor;

[0012] Figure 5A and 5B is a cross-sectional view for explaining a step in a method of manufacturing a capacitor;

[0013] Fig. 6A is a surface SEM image of a silicon substrate in which a porous portion has been formed in the capacitor manufacturing method;

[0014] Figure 6B is a cross-sectional SEM image of a silicon substrate in which a porous portion has been formed in the capacitor manufacturing method;

[0015] Fig. 7A and 7Bis a cross-sectional view for explaining a step in a method of manufacturing a capacitor;

[0016] Figure 8 is a schematic cross-sectional view of a capacitor according to a second embodiment; and

[0017] Fig. 9 It is an enlarged view of a main part in a cross section of the capacitor of the second embodiment. DETAILED DESCRIPTION

[0018] The following first embodiment and second embodiment etc. described Figure 1-9 The drawings are schematic diagrams, and the size ratio and thickness ratio of each component in the drawings do not necessarily reflect the actual size ratio.

[0019] (First embodiment)

[0020] (1.1) Overview The following will refer to Figure 1-3 The capacitor 1 according to the first embodiment is described. Note that Figure 1 is along Figure 3 A cross-sectional view taken along line XX.

[0021] The capacitor 1 includes a silicon substrate 2, a dielectric layer 4, and a conductor layer 5. The silicon substrate 2 has a first main surface 21 and a second main surface 22. The silicon substrate 2 has a porous portion 23 having a plurality of micropores 24 formed in the first main surface 21. In addition, the silicon substrate 2 has a doping layer 3 containing a p-type dopant (e.g., boron or indium). The doping layer 3 is disposed along a surface 231 of the porous portion 23. The dielectric layer 4 has a shape that conforms to the shape of the surface 231 of the porous portion 23 and is disposed on the doping layer 3. The conductor layer 5 is disposed on the dielectric layer 4.

[0022] In the capacitor 1, the doped layer 3 constitutes a first electrode of the capacitor 1, and the conductive layer 5 constitutes a second electrode of the capacitor 1. Thus, in the capacitor 1, the dielectric layer 4 is located between the first electrode and the second electrode.

[0023] Furthermore, the capacitor 1 further comprises a first external connection electrode 7 and a second external connection electrode 8. The first external connection electrode 7 is connected to the doped layer 3. The second external connection electrode 8 is connected to the conductor layer 5.

[0024] (1.2) Components of capacitors

[0025] The components of capacitor 1 will be described in further detail below.

[0026] (1.2.1) Silicon substrate

[0027] like Figure 1 and 2As shown, the silicon substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. The silicon substrate 2 has an outer edge of a rectangular shape in a top view in a thickness direction D1 defined relative to the silicon substrate 2. The silicon substrate 2 has a thickness of, for example, greater than or equal to 300 μm and less than or equal to 1 mm.

[0028] The silicon substrate 2 includes a first region A1 and a second region A2 on the first main surface 21, the first region A1 including a porous portion 23 formed therein, and the second region A2 surrounding the first region A1 (see Figure 1 and 3 ). In a top view in the thickness direction D1 defined relative to the silicon substrate 2, the first area A1 is a rectangular area and is surrounded by the second area A2. When viewed in the thickness direction D1 defined relative to the silicon substrate 2, the first area A1 is not limited to a rectangular area, but the first area A1 may be, for example, a circular area, a polygonal area other than a rectangle, or an area of ​​a polygonal shape other than a convex polygon.

[0029] The porous portion 23 has a plurality of micropores 24 along the thickness direction D1 defined relative to the silicon substrate 2. The plurality of micropores 24 are arranged in the first main surface 21 of the silicon substrate 2. Each of the plurality of micropores 24 is a hole whose depth from the first main surface 21 of the silicon substrate 2 in the thickness direction D1 defined relative to the silicon substrate 2 is greater than its opening width at the first main surface 21 of the silicon substrate 2. The plurality of micropores 24 are arranged along the thickness direction of the silicon substrate 2 from the first main surface 21 of the silicon substrate 2 and do not reach the second main surface 22. In other words, the plurality of micropores 24 do not penetrate the silicon substrate 2 in the thickness direction D1 defined relative to the silicon substrate 2. That is, the plurality of micropores 24 are separated from the second main surface 22 of the silicon substrate 2. Each of the plurality of micropores 24 has an opening width, for example, greater than or equal to 0.1 μm and less than or equal to 10 μm at the first main surface 21 of the silicon substrate 2. In addition, each of the plurality of micropores 24 has a depth less than the thickness of the silicon substrate 2. The depth of the plurality of micropores 24 in the thickness direction D1 defined relative to the silicon substrate 2 is, for example, greater than or equal to 20 μm and less than or equal to 300 μm, more preferably greater than or equal to 30 μm and less than or equal to 100 μm. Note that the upper limit value of the depth of the plurality of micropores 24 can be determined accordingly based on, for example, the opening width of the plurality of micropores 24 and the formation method of each of the doping layer 3, the dielectric layer 4, and the conductor layer 5. The opening width and depth of each micropore 24 in the porous portion 23 of the silicon substrate 2 are values ​​determined by, for example, a cross-sectional scanning electron microscope (SEM) image of the capacitor 1.

[0030] The surface 231 of the porous portion 23 includes: an inner side surface 241 and an inner bottom surface 242 of each of the plurality of micropores 24 formed in the first main surface 21 of the silicon substrate 2 ; and a portion of the first main surface 21 of the silicon substrate 2 .

[0031] The greater the depth of the plurality of micropores 24 in the porous portion 23 of the capacitor 1, the greater the surface area of ​​the surface 231 of the porous portion 23, and thus the greater the capacitance of the capacitor 1. In addition, the greater the number of micropores 24 in the porous portion 23 of the capacitor 1, the greater the surface area of ​​the surface 231 of the porous portion 23, and thus the greater the capacitance of the capacitor 1.

[0032] The silicon substrate 2 having the porous portion 23 and the doped layer 3 is formed by anodizing, for example, a p-type silicon wafer 20 (see Figure 4A ), and then the dopant diffusion step is performed. That is, the plurality of micropores 24 in the porous portion 23 are formed by anodizing a region that is a portion of the p-type silicon wafer 20 and corresponds to the first region A1 of the silicon substrate 2.

[0033] In the capacitor 1, the interval L1 between two adjacent micropores 24 among the plurality of micropores 24 is not uniform in the thickness direction D1 defined with respect to the silicon substrate 2, as shown in FIG. Figure 2 As shown. In the capacitor 1, the surface area of ​​the surface 231 of the porous portion 23 is large compared to the case where the interval L1 between two adjacent micropores 24 among the plurality of micropores 24 is uniform in the thickness direction D1 defined relative to the silicon substrate 2. Note that when the plurality of micropores 24 are formed by, for example, dry etching, the interval L1 between two adjacent micropores 24 among the plurality of micropores 24 is uniform in the thickness direction D1 defined relative to the silicon substrate 2. In addition, in the capacitor 1, each of the plurality of micropores 24 has a non-uniform opening width in the thickness direction D1 defined relative to the silicon substrate 2.

[0034] In a second direction D2 (see FIG. 1 ) orthogonal to a thickness direction D1 (hereinafter also referred to as the first direction D1) defined relative to the silicon substrate 2 Figure 3 ), the inner side surface 241 of one micropore 24 of two adjacent micropores 24 and the inner side surface 241 of the other micropore 24 of the two adjacent micropores 24 are not in the form of straight lines, but in the form of lines having concave portions and convex portions. The height difference between the respective troughs and crests of the concave portions and the convex portions is smaller than the opening width of the micropore 24. The height difference between the respective troughs and crests of the concave portions and the convex portions is a value determined by, for example, a cross-sectional scanning electron microscope (SEM) image of the capacitor 1. The height difference between the respective troughs and crests of the concave portions and the convex portions can be changed depending on the impurity concentration of the p-type silicon wafer 20 from which the silicon substrate 2 will be formed and the conditions of anodization (see Figure 4A ).

[0035] The inner bottom surface 242 of each of the plurality of micropores 24 in the porous portion 23 has a concave shape (see Figure 2 ). The radius of curvature of the inner bottom surface 242 of each of the plurality of micropores 24 is greater than or equal to 1.25 nm.

[0036] The capacitor 1 has a body region 26, which is located between the doping layer 3 and the second main surface 22 of the silicon substrate 2 and has an impurity concentration equal to the impurity concentration of the p-type silicon wafer 20. In addition, the body region 26 of the silicon substrate 2 has a carrier concentration equal to the carrier concentration of the p-type silicon wafer 20 (see Figure 4A ). When the silicon substrate 2 is formed of a p-type silicon wafer 20, the main body region 26 of the silicon substrate 2 includes, for example, boron (B) as a dopant, but this should not be construed as limiting. The main body region 26 may include indium (In) as a dopant. The impurity concentration of the main body region 26 of the silicon substrate 2 is, for example, greater than or equal to 1×10 13 cm -3 and less than or equal to 1×10 17 cm -3 , more preferably greater than or equal to 5×10 13 cm -3 and less than or equal to 5×10 16 cm -3 The impurity concentration of the bulk region 26 of the silicon substrate 2 is a value determined by, for example, secondary ion mass spectrometry (SIMS) analysis.

[0037] The doping layer 3 possessed by the silicon substrate 2 is a diffusion layer. The conductivity type of the doping layer 3 is the same as the conductivity type of the main region 26 of the silicon substrate 2. In addition, the impurity concentration of the doping layer 3 is higher than the impurity concentration of the main region 26 of the silicon substrate 2. Therefore, when the conductivity type of the main region 26 of the silicon substrate 2 is p-type, the doping layer 3 is a p-type silicon region (p+ silicon region) having a higher concentration than the main region 26 of the silicon substrate 2. The doping type of the doping layer 3 is, for example, the same as the doping type of the main region 26 of the silicon substrate 2. More specifically, when the dopant of the main region 26 is boron, the dopant of the doping layer 3 is boron. The impurity concentration of the doping layer 3 is greater than or equal to 1×10 18 cm -3 and less than or equal to 1×10 21 cm -3 , more preferably greater than or equal to 5×10 18 cm -3 and less than or equal to 1×10 20 cm -3 The impurity concentration of the doping layer 3 is a value obtained by, for example, SIMS analysis.

[0038] Furthermore, the carrier concentration of doped layer 3 is higher than that of body region 26. The carrier concentration of doped layer 3 and the carrier concentration of body region 26 are values ​​determined by, for example, carrier concentration profile observation using a scanning microwave impedance microscope (sMIM).

[0039] In order to discuss the relative magnitude relationship between the carrier concentration of the doped layer 3 and the carrier concentration of the main region 26, the carrier concentration is not limited to the value determined by the carrier concentration distribution observation using sMIM. The carrier concentration of the doped layer 3 and the carrier concentration of the main region 26 may be values ​​determined by, for example, the carrier concentration distribution observation by a scanning capacitance microscope (SCM). The carrier concentration of the doped layer 3 and the carrier concentration of the main region 26 may be values ​​determined by, for example, the carrier concentration distribution observation by a scanning nonlinear dielectric microscope (SNDM).

[0040] The thickness of the doping layer 3 is greater than or equal to 10 nm and less than or equal to 10000 nm, more preferably greater than or equal to 50 nm and less than or equal to 5000 nm. The thickness of the doping layer 3 is a value determined, for example, by observing a cross section of the capacitor 1 using a scanning microwave impedance microscope (sMIM). The thickness of the doping layer 3 is the thickness of the doping layer 3 in the normal direction of any point on the inner surface (inner side surface 241 and inner bottom surface 242) of the micropore 24.

[0041] The silicon substrate 2 has a doping layer 3 disposed over first and second regions A1 and A2 of the first main surface 21 of the silicon substrate 2. The doping layer 3 is disposed in the first region A1 along the surface 231 of the porous portion 23 and in the second region A2 along the surface 231 of the porous portion 23.

[0042] The doping layer 3 includes a first doping layer 31 , a second doping layer 32 and a third doping layer 33 .

[0043] The first doping layer 31 is disposed along the second area A2 of the silicon substrate 2. The second doping layer 32 is disposed at the bottom of the porous portion 23 of the silicon substrate 2. The third doping layer 33 is disposed at the side of the porous portion 23 of the silicon substrate 2. The thickness T1 of the first doping layer 31, the thickness T2 of the second doping layer 32, and the thickness T3 of the third doping layer 33 are equal to each other.

[0044] The doping layer 3 has a first portion 35 connecting the first doping layer 31 and the third doping layer 33. The first portion 35 has a first curved portion 351 that is concavely curved (arc-shaped) in a cross-sectional view along the second direction D2. The doping layer 3 has a second portion 36 that connects the second doping layer 32 to the third doping layer 33. The second portion 36 has a second curved portion 361 that is convexly curved (arc-shaped) in a cross-sectional view.

[0045] In the doping layer 3 , the first curved portion 351 has a curvature radius of greater than or equal to 10 nm and less than or equal to 10 μm. In addition, the second curved portion 361 has a curvature radius of greater than or equal to 10 nm and less than or equal to 10 μm.

[0046] In addition, the doping layer 3 further includes a fourth doping layer 34. The fourth doping layer 34 is disposed at a portion between two adjacent micropores 24 in the plurality of micropores 24 in the porous portion 23 of the silicon substrate 2. The width of the portion between two adjacent micropores 24 is preferably less than or equal to twice the thickness T3 of the third doping layer 33.

[0047] (1.2.2) Dielectric layer

[0048] The dielectric layer 4 is provided on the doping layer 3 and has a shape that conforms to the shape of the surface 231 of the porous portion 23 in the first region A1 and the shape of the second region A2 of the first main surface 21 of the silicon substrate 2. The dielectric layer 4 has: a portion between the doping layer 3 and the conductor layer 5 in the thickness direction D1 defined relative to the silicon substrate 2; and a portion between the doping layer 3 and the conductor layer 5 in the plurality of micropores 24 in the porous portion 23.

[0049] The dielectric layer 4 has a thickness of, for example, greater than or equal to 10 nm and less than or equal to 500 nm. The upper limit of the thickness of the dielectric layer 4 is limited by, for example, the opening width of the micropores 24 in the porous portion 23 in one direction along the first main surface 21 of the silicon substrate 2 and the thickness of the conductor layer 5 in the micropores 24 in the porous portion 23 in one direction.

[0050] The dielectric layer 4 has a multilayer film structure including a plurality of dielectric films stacked one on top of another, but this should not be construed as limiting. The dielectric layer 4 may include a single dielectric film. When the dielectric layer 4 has a multilayer film structure, the dielectric layer 4 includes, for example: a first dielectric film (for example, a first silicon oxide film) on the doping layer 3; a second dielectric film (for example, a silicon nitride film) on the first dielectric film; and a third dielectric film (for example, a second silicon oxide film) on the second dielectric film. The material of the first silicon oxide film and the second silicon oxide film is, for example, silicon dioxide (SiO2). The composition of each of the first silicon oxide film and the second silicon oxide film does not necessarily have to be SiO2 in the strict sense. In addition, the composition of the first silicon oxide film may be different from the composition of the second silicon oxide film. When the dielectric layer 4 includes a single dielectric film, the material of the dielectric film is, for example, silicon oxide. The material of the dielectric film is not limited to silicon oxide, but may be, for example, titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, tungsten oxide, niobium oxide, tantalum oxide, or aluminum oxide.

[0051] (1.2.3) Conductor layer

[0052] The conductor layer 5 is provided on the dielectric layer 4. The conductor layer 5 overlaps with the first area A1 and the second area A2 of the first main surface 21 of the silicon substrate 2 in a plan view in the thickness direction D1 defined relative to the silicon substrate 2. Therefore, in a plan view in the thickness direction D1 defined relative to the silicon substrate 2, the conductor layer 5 overlaps with the first doping layer 31, the second doping layer 32, and the third doping layer 33 of the doping layer 3.

[0053] The conductor layer 5 is, for example, a conductive polysilicon layer. The impurity concentration of the conductive polysilicon layer is, for example, greater than or equal to 1×10 18 cm -3 and less than or equal to 1×10 21 cm -3 , more preferably greater than or equal to 5×10 18 cm -3 and less than or equal to 1×10 20 cm -3 . The dopant of the conductive polysilicon layer includes one selected from the group consisting of, for example, boron, indium, phosphorus, arsenic and antimony. The conductor layer 5 is not limited to the conductive polysilicon layer, but may be, for example, a metal electrode layer. The material of the metal electrode layer includes at least one selected from the group consisting of, for example, ruthenium (Ru), titanium (Ti), tantalum (Ta), tungsten (W) and aluminum (Al). More specifically, the material of the metal electrode layer is, for example, ruthenium, titanium, tantalum, tungsten, aluminum or an alloy including one of these metals as a main component.

[0054] The conductor layer 5 has a first portion 51 overlapping the first area A1 and a second portion 52 overlapping the second area A2 in the thickness direction D1 defined relative to the silicon substrate 2. The first portion 51 of the conductor layer 5 includes: a plurality of columnar portions 512 located in the plurality of micropores 24 in the porous portion 23 of the silicon substrate 2; and a portion 511 connected to the upper ends of the plurality of columnar portions 512.

[0055] (1.2.4) First external connection electrode and second external connection electrode

[0056] The first external connection electrode 7 is connected to the doped layer 3 of the silicon substrate 2. More specifically, the first external connection electrode 7 is connected to the first main surface 21 of the silicon substrate 2 and the doped layer 3 through a contact hole 47 formed in a portion 42 of the dielectric layer 4. The portion 42 is provided on a second area A2 of the first main surface 21 of the silicon substrate 2. In the capacitor 1, the first external connection electrode 7 is electrically connected to the doped layer 3 of the silicon substrate 2. That is, “the first external connection electrode 7 is electrically connected to the doped layer 3 of the silicon substrate 2” means that the first external connection electrode 7 is in ohmic contact with the doped layer 3 (the first doped layer 31) of the silicon substrate 2.

[0057] The first external connection electrode 7 has, for example, a quadrilateral outer edge in a top view in a thickness direction D1 defined with respect to the silicon substrate 2 (see FIG. 1 ). Figure 3 ), but this should not be construed as limiting. The outer edge may have, for example, a circular shape. The first external connection electrode 7 is disposed above a portion of the first main surface 21 of the silicon substrate 2, the inner peripheral surface of the contact hole 47 in the insulating layer 6, and a portion of the first doped layer 31. In a top view in the thickness direction D1 defined relative to the silicon substrate 2, the first external connection electrode 7 overlaps with the second area A2 but does not overlap with the first area A1 of the first main surface 21 of the silicon substrate 2.

[0058] The second external connection electrode 8 is connected to the conductor layer 5. In the capacitor 1, the second external connection electrode 8 is electrically connected to the conductor layer 5. That is, "the second external connection electrode 8 is electrically connected to the conductor layer 5" means that the second external connection electrode 8 is in ohmic contact with the conductor layer 5. In a top view in the thickness direction D1 defined relative to the silicon substrate 2, the first external connection electrode 8 overlaps with the second area A2 but does not overlap with the first area A1 of the first main surface 21 of the silicon substrate 2.

[0059] The materials of the first external connection electrode 7 and the second external connection electrode 8 include, for example, but not limited to aluminum, and may include, for example, gold, platinum, and ruthenium. The material of the second external connection electrode 8 is the same as the material of the first external connection electrode 7, but it should not be understood as limiting. The material of the second external connection electrode 8 may be a material different from the material of the first external connection electrode 7.

[0060] The thickness of each of the first external connection electrode 7 and the second external connection electrode 8 is, for example, greater than or equal to 1 μm and less than or equal to 3 μm. The thickness of the second external connection electrode 8 is equal to the thickness of the first external connection electrode 7, but this should not be interpreted as restrictive. The thickness of the second external connection electrode 8 may be different from the thickness of the first external connection electrode 7.

[0061] (2) Method for manufacturing capacitor

[0062] The method for manufacturing the capacitor 1 includes, for example, a first step, a second step, a third step, a fourth step, a fifth step, a sixth step, a seventh step, and an eighth step. Figure 4A , 4B , 5A, 5B, 6A, 6B, 7A and 7B describe a method for manufacturing capacitor 1.

[0063] The first step includes preparing a p-type silicon wafer 20 (see Figure 4A). The p-type silicon wafer 20 has a first main surface 201 and a second main surface 202 opposite to the first main surface 201. The first main surface 201 of the p-type silicon wafer 20 is, for example, a (100) plane, but this should not be construed as limiting. The first main surface 201 may be, for example, a (110) plane or a (111) plane. In addition, the first main surface 201 of the p-type silicon wafer 20 may be, for example, a crystal surface having an angle of deviation from the (100) plane greater than 0° and less than or equal to 5°. In this embodiment, the "deviation angle" is the tilt angle of the first main surface 201 relative to the (100) plane. Therefore, when the deviation angle is 0°, the first main surface 201 is a (100) plane.

[0064] The second step includes forming an insulating layer 6 having a prescribed pattern on the first main surface 201 of the p-type silicon wafer 20 (see Figure 4B ). In order to form the insulating layer 6 having a prescribed pattern, for example, a first process and a second process are performed. The first process includes: forming a silicon oxide layer on the entire surface of the first main surface 201 of the p-type silicon wafer 20 by, for example, thermal oxidation; and forming a silicon nitride layer on the silicon oxide layer by, for example, chemical vapor deposition (CVD). The second process includes patterning the layered structure of the silicon oxide layer and the silicon nitride layer into a prescribed pattern by using a photolithography technique and an etching technique, thereby forming the insulating layer 6. Here, the first main surface 201 of the p-type silicon wafer 20 corresponds to the first main surface 21 of the silicon substrate 2. The insulating layer 6 having a prescribed pattern covers an area of ​​the first main surface 201 of the p-type silicon wafer 20 corresponding to the second area A2 of the first main surface 21 of the silicon substrate 2, but does not cover an area of ​​the first main surface 201 of the p-type silicon wafer 20 corresponding to the first area A1 of the first main surface 21 of the silicon substrate 2.

[0065] The third step includes anodizing the p-type silicon wafer 20 by using the p-type silicon wafer 20 as an anode, thereby forming the p-type silicon wafer 20 having the porous portion 23 (see Figure 5A , 6A and 6B), and then remove the insulating layer 6. Fig. 6A is an example of a surface SEM image of a p-type silicon wafer 20 having a porous portion 23 . Figure 6B23 is an example of a cross-sectional SEM image of a p-type silicon wafer 20 having a porous portion 23. In anodization, a platinum electrode is arranged to face the first main surface 201 of the p-type silicon wafer 20 in an electrolyte, and a current having a specified current density is allowed to flow for a predetermined period of time while the p-type silicon wafer 20 is used as an anode and the platinum electrode is used as a cathode. Therefore, in anodization, the p-type silicon wafer 20 is made porous in a region that is a part of the first main surface 201 of the p-type silicon wafer 20 and is not covered by the insulating layer 6. The electrolyte is, for example, a mixed solution of hydrofluoric acid and ethanol. Note that before anodization, an electrode to be used in anodization is formed on the second main surface 202 of the p-type silicon wafer 20. The electrode is removed after anodization. The electrode is, for example, a metal film.

[0066] In the third step, changing at least one of the hydrogen fluoride concentration in the electrolyte, the prescribed current density, or the predetermined time period enables control of the shape and depth of the plurality of micropores 24. The concentration of hydrogen fluoride in the electrolyte is, for example, greater than or equal to 1 wt% and less than or equal to 80 wt%, more preferably greater than or equal to 20 wt% and less than or equal to 40 wt%. In addition, in the method for manufacturing the capacitor 1, the shapes of the plurality of micropores 24 can be changed by changing the specific resistance of the p-type silicon wafer 20, which is determined by the impurity concentration of the p-type silicon wafer 20 that will form the silicon substrate 2.

[0067] The fourth step includes forming a doped layer 3 from a diffusion layer in a p-type silicon wafer 20, such as Figure 5B That is, the fourth step includes a diffusion step. The diffusion step includes thermally diffusing a p-type dopant (for example, boron) into the p-type silicon wafer 20, thereby forming a doped layer 3. Thus, a silicon substrate 2 having a porous portion 23 and a doped layer 3 is formed.

[0068] The fifth step includes forming a dielectric layer 4 on the doped layer 3, such as Fig. 7A In the fifth step, a first silicon oxide film of the dielectric layer 4 is formed by, for example, CVD, a silicon nitride film of the dielectric layer 4 is formed by, for example, CVD, and a second silicon oxide film of the dielectric layer 4 is formed by, for example, CVD. Note that the first silicon oxide film may be formed by thermal oxidation.

[0069] The sixth step includes forming a conductor layer 5 on the dielectric layer 4, such as Figure 7BMore specifically, the sixth step includes first forming a conductor material layer on the dielectric layer 4, from which the conductor layer 5 will be formed. In the sixth step, the conductor material layer is formed by, for example, CVD, and thereafter, the conductor material layer is patterned by, for example, using photolithography and etching techniques, thereby forming the conductor layer 5 from a portion of the conductor material layer. The conductor layer 5 has a first portion 51 overlapping the first area A1 in the thickness direction D1 defined relative to the silicon substrate 2 and a second portion 52 overlapping the second area A2.

[0070] The seventh step includes forming a first external connection electrode 7 and a second external connection electrode 8 (see Figure 1 ). More specifically, the seventh step includes first forming a contact hole 47 in the dielectric layer 4 (see Figure 7B ), thereby exposing a portion of the first main surface 21 of the silicon substrate 2. In the seventh step, a contact hole 47 is formed by using, for example, a photolithography technique and an etching technique. Then, for example, a thin film forming method, a photolithography technique and an etching technique are used to form a first external connection electrode 7 and a second external connection electrode 8. The thin film forming method is, for example, evaporation, sputtering or CVD. The seventh step may include heat treatment to achieve ohmic contact between the first external connection electrode 7 and the doped layer 3.

[0071] In the method for manufacturing the capacitor 1, a first wafer (e.g., a silicon wafer) may be prepared as a p-type silicon wafer 20 in the first step, and then the first step to the seventh step may be performed to obtain a second wafer including a plurality of capacitors 1. In the method for manufacturing the capacitor 1, a plurality of capacitors 1 may be obtained by cutting the second wafer in the eighth step by using, for example, a dicing saw or a laser cutting device.

[0072] (3) Advantages

[0073] In the capacitor 1 according to the first embodiment, the dielectric layer 4 is disposed over the surface 231 of the porous portion 23 and the second region A2 of the silicon substrate 2. Furthermore, in a top view in the thickness direction D1 defined relative to the silicon substrate 2, the conductor layer 5 disposed on the dielectric layer 4 overlaps a portion of the first region A1 and the second region A2. Furthermore, the silicon substrate 2 has a doping layer 3, and the doping layer 3 includes a first doping layer 31 formed along the second region A2 of the silicon substrate 2, a second doping layer 32 formed at the bottom of the porous portion 23 of the silicon substrate 2, and a third doping layer 33 formed at the side of the porous portion 23 of the silicon substrate 2. This allows the capacitor 1 according to the first embodiment to have improved electrical characteristics. More specifically, the capacitor 1 according to the first embodiment is allowed to have a further increased capacitance.

[0074] In addition, in the doping layer 3, the capacitor 1 according to the first embodiment includes: a first portion 35, the first portion 35 connects the first doping layer 31 to the third doping layer 33, and has a first bent portion 351 that is concavely bent in the second direction D2 orthogonal to the first direction D1 as the thickness direction D1 in the cross-sectional view; and a second portion 36, the second portion 36 connects the second doping layer 32 to the third doping layer 33, and has a second bent portion 361 that is concavely bent in the cross-sectional view. Therefore, the capacitor 1 according to the first embodiment has suppressed electric field concentration at each of the first portion 35 and the second portion 36, and thus has a reduced equivalent series resistance (ESR). In addition, the capacitor 1 according to the first embodiment allows the reflection of the current at the second portion 36 to be reduced, thereby reducing the transmission loss.

[0075] Furthermore, in the capacitor 1 according to the first embodiment, the silicon substrate 2 has the doping layer 3, and therefore, the surface 231 where the porous portion 23 is present easily has the advantage of increased surface area. More specifically, the porous portion 23 is formed by anodizing the p-type silicon wafer 20 having a lower impurity concentration than the doping layer 3 before forming the doping layer 3, thereby increasing the surface area of ​​the surface 231 of the porous portion 23.

[0076] (4) Modification of the First Embodiment

[0077] The conductivity type of the main region 26 and the doping layer 3 of the silicon substrate 2 is not limited to the p-type, but can be an n-type. When the conductivity type of the main region 26 and the doping layer 3 of the silicon substrate 2 is n-type, the main region 26 and the doping layer 3 contain, for example, phosphorus (P) as an n-type dopant, but this should not be interpreted as limiting. The main region 26 and the doping layer 3 may contain arsenic (As) or antimony (Sb) as a dopant. In addition, when the conductivity type of the main region 26 and the doping layer 3 of the silicon substrate 2 is n-type, the impurity concentration of the doping layer 3 is higher than the impurity concentration of the main region 26. In addition, the carrier concentration of the doping layer 3 is higher than the carrier concentration of the main region 26.

[0078] When the conductivity type of the doped layer 3 and the body region 26 is n-type, the method for manufacturing the capacitor 1 is substantially the same as the method for manufacturing the capacitor 1 according to the first embodiment. Note that in the first step, an n-type silicon substrate is prepared as a substitute for the p-type silicon wafer 20. Furthermore, in order to form the porous portion 23 by anodization, the n-type silicon substrate from which the silicon substrate 2 is to be formed is irradiated with light to increase the number of pores in the n-type silicon substrate.

[0079] (Second embodiment)

[0080] refer to Figure 8 and 9, a capacitor 1A according to a second embodiment will be described below. In the capacitor 1A according to the second embodiment, components similar to those in the capacitor 1 according to the first embodiment (see Figures 1 to 3 ) are denoted by the same figure numerals as those in the first embodiment, and thus their description is omitted.

[0081] (1) Configuration

[0082] The capacitor 1A according to the second embodiment includes a silicon substrate 2, a dielectric layer 4, and a conductor layer 5. The silicon substrate 2 has a first main surface 21 and a second main surface 22. The silicon substrate 2 has a porous portion 23 having a plurality of micropores 24 formed in the first main surface 21. In addition, the silicon substrate 2 has a doping layer 3 containing a p-type dopant (for example, boron or indium). The doping layer 3 is provided along a surface 231 of the porous portion 23. The dielectric layer 4 has a shape that conforms to the shape of the surface 231 of the porous portion 23 and is provided on the doping layer 3. The conductor layer 5 is provided on the dielectric layer 4.

[0083] In capacitor 1A, doped layer 3 constitutes a first electrode of capacitor 1A, and conductor layer 5 constitutes a second electrode of capacitor 1A. Therefore, in capacitor 1A, dielectric layer 4 is located between the first electrode and the second electrode.

[0084] Furthermore, the capacitor 1A further includes a first external connection electrode 7 and a second external connection electrode 8. The first external connection electrode 7 is connected to the doped layer 3. The second external connection electrode 8 is connected to the conductor layer 5.

[0085] The doping layer 3 includes a first doping layer 31, a second doping layer 32 and a third doping layer 33. The first doping layer 31 is arranged along the second area A2 of the silicon substrate 2. The second doping layer 32 is arranged at the bottom of the porous portion 23 of the silicon substrate 2. The third doping layer 33 is arranged at the side of the porous portion 23 of the silicon substrate 2. In the doping layer 3, the first doping layer 31 is connected to the third doping layer 33. In addition, in the doping layer 3, the second doping layer 32 is connected to the third doping layer 33.

[0086] In the capacitor 1A according to the second embodiment, in the second direction D2 (see Figure 3 ) are different in shape from the porous portion 23 and the doping layer 3 in the cross-sectional view in FIG. 1 , respectively, from the porous portion 23 and the doping layer 3 of the capacitor 1 according to the first embodiment.

[0087] In the capacitor 1A, the porous portion 23 has an inverted trapezoidal shape in a cross-sectional view along the second direction D2, and the porous portion 23 has a width that decreases away from the first main surface 21. The porous portion 23 in the capacitor 1A includes: a first porous region having a first group of micropores 24, the first group of micropores 24 being included in the plurality of micropores 24 and formed by the first main surface 21 of the silicon substrate 2 in the thickness direction D1; and a second porous region having a second group of micropores 24, the second group of micropores 24 being included in the plurality of micropores 24 and formed by the first main surface 21 of the silicon substrate 2 in an inclined direction.

[0088] In the doping layer 3 of the capacitor 1A, the first doping layer 31 is connected to the third doping layer 33, and in a cross-sectional view in a second direction D2 orthogonal to the first direction D1 as the thickness direction D1, the smaller angle θ1 of the two angles formed between the first doping layer 31 and the third doping layer 33 is an obtuse angle. In the doping layer 3, the second doping layer 32 is connected to the third doping layer 33, and in a cross-sectional view, the smaller angle θ2 of the two angles formed between the second doping layer 32 and the third doping layer 33 is an obtuse angle.

[0089] The doping layer 3 has a first portion 35 connecting the first doping layer 31 and the third doping layer 33. The first portion 35 has a first curved portion 351 that is concavely curved (arc-shaped) in a cross-sectional view along the second direction D2. The doping layer 3 has a second portion 36 that connects the second doping layer 32 to the third doping layer 33. The second portion 36 has a second curved portion 361 that is convexly curved (arc-shaped) in a cross-sectional view.

[0090] In the doping layer 3 , the first curved portion 351 has a curvature radius of greater than or equal to 10 nm and less than or equal to 10 μm. In addition, the second curved portion 361 has a curvature radius of greater than or equal to 10 nm and less than or equal to 10 μm.

[0091] Furthermore, the doping layer 3 further includes a fourth doping layer 34. The fourth doping layer 34 is provided at a portion between two adjacent micropores 24 among the plurality of micropores 24 in the porous portion 23 of the silicon substrate 2.

[0092] (2) Manufacturing method

[0093] The manufacturing method of the capacitor 1A according to the second embodiment is substantially the same as the manufacturing method of the capacitor 1 according to the first embodiment. Therefore, descriptions of steps in the manufacturing method of the capacitor 1A according to the second embodiment similar to the manufacturing method of the capacitor 1 according to the first embodiment will be omitted.

[0094] The manufacturing method of the capacitor 1A according to the second embodiment includes a first step, a second step, a third step, a fourth step, a fifth step, a sixth step, a seventh step, and an eighth step in a manner similar to the manufacturing method of the capacitor 1 according to the first embodiment.

[0095] In the method for manufacturing the capacitor 1A according to the second embodiment, the shape of the porous portion 23 formed in the third step is different from that in the first embodiment. The shape of the porous portion 23 can be controlled by changing at least one of the conditions of anodization and the impurity concentration of the p-type silicon wafer 20 from which the silicon substrate 2 is to be formed (see Figure 4A ).

[0096] (3) Advantages

[0097] In the capacitor 1A according to the second embodiment, the dielectric layer 4 is disposed above the surface 231 of the porous portion 23 and the second region A2 of the silicon substrate 2. Furthermore, in a top view in the thickness direction D1 defined relative to the silicon substrate 2, the conductor layer 5 formed on the dielectric layer 4 overlaps a portion of the first region A1 and the second region A2. Furthermore, the silicon substrate 2 has a doping layer 3, and the doping layer 3 includes a first doping layer 31 formed along the second region A2 of the silicon substrate 2, a second doping layer 32 formed at the bottom of the porous portion 23 of the silicon substrate 2, and a third doping layer 33 formed at the side of the porous portion 23 of the silicon substrate 2. This allows the capacitor 1A according to the second embodiment to have improved electrical characteristics. More specifically, the capacitor 1A according to the second embodiment is allowed to have a further increased capacitance.

[0098] Furthermore, in the doping layer 3 of the capacitor 1A according to the second embodiment, the first doping layer 31 is connected to the third doping layer 33, and in a cross-sectional view in the second direction D2 orthogonal to the first direction D1 as the thickness direction D1, the smaller angle θ1 of the two angles formed between the first doping layer 31 and the third doping layer 33 is an obtuse angle. In the doping layer 3, the second doping layer 32 is connected to the third doping layer 33, and in a cross-sectional view, the smaller angle θ2 of the two angles formed between the second doping layer 32 and the third doping layer 33 is an obtuse angle. Therefore, the capacitor 1A according to the second embodiment has a reduced ESR and a reduced transmission loss compared to the case where the angle θ1 and the angle θ2 are each 90 degrees.

[0099] Furthermore, the capacitor 1A according to the second embodiment includes, in the doping layer 3, a first portion 35 connecting the first doping layer 31 to the third doping layer 33 and having a first bent portion 351 that is concavely bent in a cross-sectional view along the second direction D2, and a second portion 36 connecting the second doping layer 32 to the third doping layer 33 and having a second bent portion 361 that is concavely bent in a cross-sectional view. Therefore, the capacitor 1A according to the second embodiment has suppressed electric field concentration at each of the first portion 35 and the second portion 36, and thus has reduced ESR.

[0100] (Variation of the Second Embodiment)

[0101] The conductivity type of the main region 26 and the doping layer 3 of the silicon substrate 2 is not limited to the p-type, but can be an n-type. When the conductivity type of the main region 26 and the doping layer 3 of the silicon substrate 2 is n-type, the main region 26 and the doping layer 3 contain, for example, phosphorus (P) as an n-type dopant, but this should not be interpreted as limiting. The main region 26 and the doping layer 3 may contain arsenic or antimony as an n-type dopant. In addition, when the conductivity type of the main region 26 and the doping layer 3 of the silicon substrate 2 is n-type, the impurity concentration of the doping layer 3 is higher than the impurity concentration of the main region 26. In addition, the carrier concentration of the doping layer 3 is higher than the carrier concentration of the main region 26.

[0102] When the conductivity type of the doped layer 3 and the body region 26 is n-type, the manufacturing method of the capacitor 1A is substantially the same as the manufacturing method of the capacitor 1A according to the second embodiment. Note that in the first step, an n-type silicon substrate is prepared as a substitute for the p-type silicon wafer 20. In addition, in order to form the porous portion 23 by anodization, the n-type silicon substrate from which the silicon substrate 2 is to be formed is irradiated with light to increase the number of pores in the n-type silicon substrate.

[0103] (Other variants)

[0104] The first and second embodiments and the like are merely examples of various embodiments of the present disclosure. As long as the purpose of the present disclosure is achieved, various modifications may be made to the first and second embodiments and the like according to design and the like.

[0105] For example, the silicon substrate 2 may be provided with a plurality of circuit elements (eg, MOSFETs) in addition to the capacitors 1, 1A. That is, the capacitors 1, 1A according to the present disclosure may be applied to semiconductor devices including the capacitors 1, 1A, such as integrated circuit (IC) chips including the capacitors 1, 1A.

[0106] (All aspects)

[0107] This specification discloses the following aspects from the first and second examples and the like.

[0108] A capacitor (1; 1A) of the first aspect comprises a silicon substrate (2), a dielectric layer (4) and a conductor layer (5). The silicon substrate (2) has a first main surface (21), a second main surface (22) and a porous portion (23), the first main surface (21) comprising a first region (A1) and a second region (A2) surrounding the first region (A1), the porous portion (23) being formed in the first region (A1) and having a plurality of micropores (24) along a thickness direction (D1) defined relative to the silicon substrate (2). The dielectric layer (4) is disposed above a surface (231) of the porous portion (23) and the second region (A2) of the silicon substrate (2). The conductor layer (5) is disposed on the dielectric layer (4). The interval (L1) between two adjacent micropores (24) among the plurality of micropores (24) is non-uniform in the thickness direction (D1) defined relative to the silicon substrate (2). The conductor layer (5) overlaps with the first region (A1) and the second region (A2) in a thickness direction (D1) defined relative to the silicon substrate (2) in a top view. The silicon substrate (2) has a doping layer (3). The doping layer (3) includes a first doping layer (31), a second doping layer (32) and a third doping layer (33). The first doping layer (31) is arranged along the second region (A2) of the silicon substrate (2). The second doping layer (32) is arranged at the bottom of the porous portion (23) of the silicon substrate (2). The third doping layer (33) is arranged on the side of the porous portion (23) of the silicon substrate (2). The doping layer (3) has a first portion (35) connecting the first doping layer (31) to the third doping layer (33). The first portion (35) has a first bent portion (351) that is concavely bent in a cross-sectional view in a second direction (D2) orthogonal to the first direction (D1) as the thickness direction (D1). The doping layer (3) includes a second portion (36) connecting the second doping layer (32) to the third doping layer (33). The second portion (36) has a second curved portion (361) that is convexly curved in a cross-sectional view.

[0109] This aspect allows improvement in electrical characteristics.

[0110] In the capacitor (1; 1A) of the second aspect with reference to the first aspect, in a cross-sectional view, the smaller angle (θ1) of the two angles formed between the first doping layer (31) and the third doping layer (33) is an obtuse angle, and the smaller angle (θ2) of the two angles formed between the second doping layer (32) and the third doping layer (33) is an obtuse angle.

[0111] This aspect enables ESR and transmission losses to be reduced.

[0112] The capacitor (1A) of the third aspect comprises a silicon substrate (2), a dielectric layer (4) and a conductor layer (5). The silicon substrate (2) has a first main surface (21), a second main surface (22) and a porous portion (23), the first main surface (21) comprising a first region (A1) and a second region (A2) surrounding the first region (A1), the porous portion (23) being formed in the first region (A1) and having a plurality of micropores (24) along a thickness direction (D1) defined relative to the silicon substrate (2). The dielectric layer (4) is disposed above a surface (231) of the porous portion (23) and the second region (A2) of the silicon substrate (2). The conductor layer (5) is disposed on the dielectric layer (4). The interval (L1) between two adjacent micropores (24) among the plurality of micropores (24) is non-uniform in the thickness direction (D1) defined relative to the silicon substrate (2). The conductor layer (5) overlaps with the first region (A1) and the second region (A2) in a thickness direction (D1) defined relative to the silicon substrate (2) in a top view. The silicon substrate (2) has a doping layer (3). The doping layer (3) includes a first doping layer (31), a second doping layer (32) and a third doping layer (33). The first doping layer (31) is arranged along the second region (A2) of the silicon substrate (2). The second doping layer (32) is arranged at the bottom of the porous portion (23) of the silicon substrate (2). The third doping layer (33) is arranged on the side of the porous portion (23) of the silicon substrate (2). In the doping layer (3), the first doping layer (31) is connected to the third doping layer (33), and in a second direction (D2) orthogonal to the first direction (D1) as the thickness direction (D1), the smaller angle (θ1) of the two angles formed between the first doping layer (31) and the third doping layer (33) is an obtuse angle. In the doping layer (3), the second doping layer (32) is connected to the third doping layer (33), and in a cross-sectional view, the smaller angle (θ2) of two angles formed between the second doping layer (32) and the third doping layer (33) is an obtuse angle.

[0113] This aspect allows improvement in electrical characteristics.

[0114] In the capacitor (1; 1A) of the fourth aspect referring to the first aspect or the second aspect, the first curved portion (351) has a radius of curvature greater than or equal to 10 nm and less than or equal to 10 μm, and the second curved portion (361) has a radius of curvature greater than or equal to 10 nm and less than or equal to 10 μm.

[0115] This aspect allows suppressing electric field concentration at each of the first portion (35) and the second portion (36) of the doped layer (3).

[0116] In the capacitor (1; 1A) of the fifth aspect referring to any one of the first to fourth aspects, each of the plurality of micropores (24) in the porous portion (23) has a concavely curved inner bottom surface (242).

[0117] This aspect allows suppressing the electric field concentration at the doped layer (3).

[0118] In the capacitor (1; 1A) of the sixth aspect referring to the fifth aspect, the inner bottom surface (242) of each of the plurality of micropores (24) has a radius of curvature greater than or equal to 1.25 nm.

[0119] In the capacitor (1; 1A) of the seventh aspect referring to any one of the first to sixth aspects, the doped layer (3) further includes a fourth doped layer (34) between two adjacent micropores (24) among the plurality of micropores (24) in the porous portion (23) of the silicon substrate (2).

[0120] This aspect enables the ESR to be reduced.

[0121] In the capacitor (1; 1A) of the eighth aspect with reference to any one of the first to seventh aspects, when the doping layer (3) contains a p-type dopant, the p-type dopant is boron or indium, and when the doping layer (3) contains an n-type dopant, the n-type dopant is phosphorus, arsenic or antimony.

[0122] Reference numerals list

[0123] 1. 1A: Capacitor

[0124] 2: Silicon substrate

[0125] 21: First main surface

[0126] 22: Second main surface

[0127] 23: Porous part

[0128] 231: Surface

[0129] 24: Micropores

[0130] 241: Inner surface

[0131] 242: Inner bottom surface

[0132] 3: Doping layer

[0133] 31: First doping layer

[0134] 32: Second doping layer

[0135] 33: The third doping layer

[0136] 34: Fourth doping layer

[0137] 35: Part 1

[0138] 351: First bending part

[0139] 36: Part 2

[0140] 361: Second curved part

[0141] 4: Dielectric layer

[0142] 5: Conductor layer

[0143] 7: First external connection electrode

[0144] 8: Second external connection electrode

[0145] A1: First Area

[0146] A2: Second Area

[0147] D1: Thickness direction (first direction)

[0148] D2: Second direction

[0149] T1: Thickness

[0150] T2: Thickness

[0151] T3: Thickness

[0152] L1: Interval

[0153] θ1: Angle

[0154] θ2: Angle

Claims

1. A capacitor, comprising: A silicon substrate, the silicon substrate comprising: a first major surface, the first major surface comprising a first region and a second region surrounding the first region, a second major surface, and a porous portion formed in the first region and having a plurality of micropores along a thickness direction defined with respect to the silicon substrate; a dielectric layer disposed over a surface of the porous portion and the second region of the silicon substrate; as well as a conductor layer, the conductor layer being disposed on the dielectric layer, The intervals between adjacent micro-holes in the plurality of micro-holes are non-uniform in the thickness direction defined relative to the silicon substrate, and the conductor layer overlaps the first region and the second region in the thickness direction defined relative to the silicon substrate in a top view. The silicon substrate has a doping layer including a p-type dopant or an n-type dopant, The doping layer comprises: a first doped layer, wherein the first doped layer is arranged along the second region of the silicon substrate, a second doped layer, the second doped layer being disposed at the bottom of the porous portion of the silicon substrate, and a third doping layer, the third doping layer being disposed on a side of the porous portion of the silicon substrate, The doped layer has: a first portion connecting the first doping layer to the third doping layer, the first portion having a first curved portion that is concavely curved in a second direction orthogonal to the first direction that is the thickness direction in a cross-sectional view; as well as The second portion connects the second doping layer to the third doping layer, and the second portion has a convexly curved second curved portion in the cross-sectional view.

2. The capacitor according to claim 1, wherein: In the cross-sectional view, in the second direction, the smaller angle of the two angles formed between the first doping layer and the third doping layer is an obtuse angle, and In the cross-sectional view, the smaller angle of the two angles formed between the second doping layer and the third doping layer is an obtuse angle.

3. A capacitor, comprising: A silicon substrate, the silicon substrate comprising: a first major surface, the first major surface comprising a first region and a second region surrounding the first region, a second major surface, and a porous portion formed in the first region and having a plurality of micropores along a thickness direction defined with respect to the silicon substrate; a dielectric layer disposed over a surface of the porous portion and the second region of the silicon substrate; a conductor layer disposed on the dielectric layer, and Intervals between adjacent micropores among the plurality of micropores are non-uniform in the thickness direction defined with respect to the silicon substrate. The conductor layer overlaps the first region and the second region in the thickness direction defined relative to the silicon substrate in a top view, The silicon substrate has a doping layer including a p-type dopant or an n-type dopant, The doping layer comprises: a first doped layer, wherein the first doped layer is arranged along the second region of the silicon substrate, a second doped layer, the second doped layer being disposed at the bottom of the porous portion of the silicon substrate, and a third doping layer, the third doping layer being disposed on a side of the porous portion of the silicon substrate, In the doped layer, The first doping layer is connected to the third doping layer, and in a cross-sectional view, in a second direction orthogonal to the first direction as the thickness direction, the smaller angle of two angles formed between the first doping layer and the third doping layer is an obtuse angle; and The second doping layer is connected to the third doping layer, and in the cross-sectional view, the smaller angle of the two angles formed between the second doping layer and the third doping layer is an obtuse angle.

4. The capacitor according to claim 1 or 2, wherein: The first curved portion has a radius of curvature greater than or equal to 10 nm and less than or equal to 10 μm; and A curvature radius of the second curved portion is greater than or equal to 10 nm and less than or equal to 10 μm.

5. The capacitor according to claim 1 or 2, wherein: Each of the plurality of micropores in the porous portion has a concavely curved inner bottom surface.

6. The capacitor according to claim 5, wherein: The radius of curvature of the inner bottom surface of each of the plurality of micropores is greater than or equal to 1.25 nm.

7. The capacitor according to any one of claims 1 to 3, wherein: The doping layer further includes a fourth doping layer located between two adjacent micropores among the plurality of micropores in the porous portion of the silicon substrate.

8. The capacitor according to any one of claims 1 to 3, wherein: When the doping layer includes the p-type dopant, the p-type dopant is boron or indium, and When the doping layer includes the n-type dopant, the n-type dopant is phosphorus, arsenic or antimony.

Images