Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises: a plurality of pixel circuits (100); an insulating material layer (ISL) on the plurality of pixel circuits and including a plurality of organic insulating layers, each organic insulating layer including an organic material; a plurality of pixel electrodes (E1) located on the plurality of organic insulating layers and connected to a pixel circuit; a light-emitting functional layer (EML) including a common layer (CL); and an isolation structure (600) having a protruding portion (PR) protruding from the organic insulating layer therebelow or itself having a protruding portion (PR), the isolation structure (600) being configured to block the common layer (CL) at the protruding portion (PR); the isolation structures (600) are located between the adjacent pixel electrodes (E1) and comprise inorganic materials, the isolation structures (600) are located on at least part of the organic insulating layer, and the isolation structures (600) and the pixel electrodes (E1) are at least separated by part of the organic insulating layer, so that the display effect is improved, and crosstalk is avoided.

Description

Display panel and display device Technical Field

[0001] Embodiments of the present disclosure relate to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, organic light-emitting diode (OLED) display devices have become a research hotspot and technology development direction for major manufacturers due to their advantages such as wide color gamut, high contrast, thin and light design, self-luminescence, and wide viewing angle.

[0003] Currently, organic light-emitting diode (OLED) displays are widely used in a variety of electronic products, ranging from small devices like smart bracelets, smart watches, smartphones, and tablets to large devices like laptops, desktop computers, and televisions. Consequently, market demand for active-matrix OLED displays is also growing rapidly.

[0004] Summary of the Invention

[0005] Embodiments of the present disclosure provide a display panel and a display device.

[0006] An embodiment of the present disclosure provides a display panel, comprising: a base substrate; a plurality of pixel circuits located on the base substrate; an insulating material layer located on a side of the plurality of pixel circuits facing away from the base substrate and comprising a plurality of organic insulating layers, each of the plurality of organic insulating layers comprising an organic material; a plurality of pixel electrodes located on a side of the plurality of organic insulating layers facing away from the base substrate and connected to one of the plurality of pixel circuits; a light-emitting functional layer comprising a common layer, an orthographic projection of the common layer on the base substrate overlapping with an orthographic projection of the plurality of pixel electrodes on the base substrate, at least a portion of the common layer being located on a side of the plurality of pixel electrodes facing away from the base substrate; and an isolation structure having a protruding portion protruding from the organic insulating layer thereunder or the isolation structure itself having a protruding portion, the isolation structure being configured to isolate the common layer at the protruding portion; the isolation structure being located between adjacent pixel electrodes and comprising an inorganic material, the isolation structure being located above at least a portion of the organic insulating layer, and the isolation structure being separated from the plurality of pixel electrodes by at least a portion of the organic insulating layer.

[0007] For example, the organic insulating layer located below the isolation structure has a groove or a first through hole at the protrusion.

[0008] For example, the organic insulating layer located above the isolation structure has a second through hole at the protrusion, and the first through hole and the second through hole are connected.

[0009] For example, the display panel further includes a pixel defining layer having a plurality of first openings, each of the plurality of first openings being configured to expose one of the plurality of pixel electrodes, and the pixel defining layer further having a second opening connected to the second through hole.

[0010] For example, an orthographic projection of the second opening on the base substrate overlaps with an orthographic projection of the isolation structure on the base substrate.

[0011] For example, the isolation structure has a protrusion at the groove or the first through hole.

[0012] For example, the groove or the first through hole is in the shape of an elongated strip, and the isolation structure includes two isolation parts at the groove or the first through hole, and the two isolation parts respectively form two protrusions, and the two protrusions are located in the groove or the first through hole and on opposite sides of the elongated groove or the first through hole.

[0013] For example, the display panel further includes a common electrode, at least part of which is located on a side of the light-emitting functional layer away from the base substrate, and the multiple pixel electrodes, the light-emitting functional layer, and the common electrode constitute multiple light-emitting elements.

[0014] For example, an isolation structure surrounding a light emitting element includes a plurality of isolation substructures.

[0015] For example, the plurality of spacer structures include at least two spacer structures located on two opposite sides of the light emitting region of the light emitting element.

[0016] For example, the distances between at least one of the plurality of isolation substructures and two adjacent light emitting elements are not equal.

[0017] For example, the light-emitting element includes a first light-emitting element, a second light-emitting element, and a third light-emitting element, the light-emitting area of ​​the first light-emitting element is smaller than the light-emitting area of ​​the second light-emitting element, the light-emitting area of ​​the second light-emitting element is smaller than the light-emitting area of ​​the third light-emitting element, and the isolation structure includes a first isolation structure and a second isolation structure, the first isolation structure is located at the periphery of the light-emitting area of ​​the first light-emitting element, and the second isolation structure is located at the periphery of the light-emitting area of ​​the second light-emitting element.

[0018] For example, the first isolation structure includes two first isolation substructures located on opposite sides of the light-emitting area of ​​the first light-emitting element, and the second isolation structure includes four second isolation substructures. The four second isolation substructures are arranged around the light-emitting area of ​​the second light-emitting element, two of the four second isolation substructures are located on opposite sides of the light-emitting area of ​​the second light-emitting element, and the other two second isolation substructures of the four second isolation substructures are located on opposite sides of the light-emitting area of ​​the second light-emitting element.

[0019] For example, the light-emitting region of the first light-emitting element is surrounded by two first spacer structures and two second spacer structures located at the gaps of the first spacer structures.

[0020] For example, the light emitting region of the third light emitting element is surrounded by four first spacer structures and two second spacer structures.

[0021] For example, the common electrode is not disconnected at the isolation structure.

[0022] For example, the first light emitting element is configured to emit green light, the second light emitting element is configured to emit red light, and the third light emitting element is configured to emit blue light.

[0023] For example, the isolation structure does not contact the plurality of pixel electrodes.

[0024] For example, the isolation structure includes a passivation layer, the passivation layer is configured to form the protrusion, the inorganic material includes an inorganic non-metallic material, and the inorganic material is an insulating material.

[0025] For example, the inorganic material includes a metal material, and the isolation structure includes a first sublayer, a second sublayer, and a third sublayer that are stacked and arranged in sequence, the first sublayer is closer to the base substrate than the third sublayer, and the third sublayer protrudes outward relative to the second sublayer to form the protrusion.

[0026] For example, the multiple organic insulating layers include a first organic insulating layer, a second organic insulating layer, and a third organic insulating layer arranged in sequence, the first organic insulating layer is closer to the base substrate than the third organic insulating layer, and in a direction perpendicular to the base substrate, the isolation structure is located above at least a portion of the first organic insulating layer and below at least a portion of the third organic insulating layer.

[0027] For example, the display panel also includes a first connecting electrode and a second connecting electrode, wherein the pixel circuit includes a transistor, the first connecting electrode is located on the first organic insulating layer, and is connected to the transistor through a via hole passing through the first organic insulating layer, the second connecting electrode is located on the second organic insulating layer, and is connected to the first connecting electrode through a via hole passing through the second organic insulating layer, and the pixel electrode is located on the third organic insulating layer, and is connected to the second connecting electrode through a via hole passing through the third organic insulating layer.

[0028] For example, the insulating material layer further includes an inorganic insulating material layer, the inorganic insulating material layer is located between the transistor and the first organic insulating layer, and the first connecting electrode also passes through the inorganic insulating material layer.

[0029] For example, the display panel has a bending area.

[0030] For example, the display panel has a hole area, and a plurality of isolation structures are provided, and at least some of the plurality of isolation structures are located in a frame area close to the hole area.

[0031] An embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0033] FIG1 is a schematic diagram of a light-emitting element.

[0034] FIG2 is a cross-sectional view of a display panel.

[0035] FIG3 is a cross-sectional view of a display panel.

[0036] FIG4 is a plan view of a display panel.

[0037] FIG5 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure.

[0038] FIG6 is a partially enlarged view of FIG5.

[0039] FIG7 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure.

[0040] FIG8 is a partially enlarged view of FIG7 .

[0041] FIG9 is a plan view of a display panel provided by an embodiment of the present disclosure.

[0042] 10 to 14 are cross-sectional views of several display panels provided by embodiments of the present disclosure.

[0043] FIG15A is a plan view of a display panel provided by an embodiment of the present disclosure.

[0044] FIG15B is a plan view of a display panel provided by an embodiment of the present disclosure.

[0045] FIG16A is a schematic diagram of area division of a display panel provided by an embodiment of the present disclosure.

[0046] FIG16B is a schematic diagram of another area division of a display panel provided by an embodiment of the present disclosure.

[0047] FIG17 is a schematic diagram of another area division of a display panel provided by an embodiment of the present disclosure.

[0048] 18 to 21 are cross-sectional views of several display panels provided by embodiments of the present disclosure. DETAILED DESCRIPTION

[0049] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0050] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0051] With the continuous development of display technology, people's pursuit of display quality is getting higher and higher. In order to further reduce power consumption, extend service life and achieve high brightness, one of the light-emitting layers in the light-emitting element of the OLED display panel can be replaced with two light-emitting layers, and a charge generation layer (CGL) is added between the two light-emitting layers. The N-type doped charge generation layer and the P-type doped charge generation layer (N / P-CGL) are used as heterojunctions, and the two light-emitting device structures are connected in series to form a double-stacked design to form a Tandem structure. The display panel with the Tandem structure realizes the series connection of dual light-emitting devices. Under the same luminous intensity, the luminous current of the light-emitting element is greatly reduced, and the life of the light-emitting element is improved, which is conducive to the development and mass production of new technologies with high lifespan, such as automotive. The display device with the Tandem structure has the advantages of long life, low power consumption and high brightness.

[0052] Figure 1 is a schematic diagram of a light-emitting element. Figure 1(a) is a schematic diagram of a conventional light-emitting element. Figure 1(b) is a schematic diagram of a light-emitting element with a tandem structure. As shown in Figure 1(b), the charge generation layers (CGLs) of different light-emitting elements in the tandem structure are connected.

[0053] Figure 1 shows a pixel electrode E1, a common electrode E2, a hole transport layer HTL, an electron transport layer ETL, a light coupling layer CPL, an antireflection layer ARL, a P-type doped charge generation layer P-CGL, an N-type doped charge generation layer N-CGL, a light-emitting layer R, a light-emitting layer G, and a light-emitting layer B. As shown in Figure 1 , the hole transport layer HTL includes a hole transport layer HTL-1 and a hole transport layer HTL-2. As shown in Figure 1 , the electron transport layer ETL includes an electron transport layer ETL-1 and an electron transport layer ETL-2.

[0054] As shown in Figure 1, the light-emitting layer R includes two sublayers containing light-emitting materials R1 and R2, respectively; the light-emitting layer G includes two sublayers containing light-emitting materials G1 and G2, respectively; and the light-emitting layer B includes light-emitting materials B1 and B2. Light-emitting materials R1 and R2 are two different materials that emit red light, light-emitting materials G1 and G2 are two different materials that emit green light, and light-emitting materials B1 and B2 are two different materials that emit blue light.

[0055] Figure 1 shows the light-emitting functional layer (EML) located between the pixel electrode E1 and the common electrode E2. The light-emitting functional layer (EML) includes a common layer CL and a local layer LL. The local layer LL includes a light-emitting layer R, a light-emitting layer G, and a light-emitting layer B. The common layer CL includes a first common layer CL1, a second common layer CL2, and a third common layer CL3. As shown in Figure 1, the first common layer CL1 includes a hole transport layer HTL-1, the second common layer CL2 includes an electron transport layer ETL-1, a charge generation layer N-CGL, a charge generation layer P-CGL, and a hole transport layer HTL-2. The third common layer CL3 includes an electron transport layer ETL-2.

[0056] For example, the common layer CL may be manufactured using an open mask, and the local layer LL may be manufactured using a fine metal mask, but the present invention is not limited thereto.

[0057] FIG2 is a cross-sectional view of a display panel. As shown in FIG2 , the display panel includes a plurality of sub-pixels SP. FIG2 shows a sub-pixel SP1 and a pixel SP2. FIG2 also includes a plurality of pixel circuits 100 and a plurality of light-emitting elements 200. As shown in FIG2 , a pixel circuit 100 includes a transistor T1 and a transistor T2. FIG2 also shows a light-emitting element EM1 and a light-emitting element EM2. For example, the light-emitting element 200 includes an organic light-emitting diode, but is not limited thereto.

[0058] The inventors noticed that for high-resolution products, the common layer CL, such as the charge generation layer, is shared by multiple sub-pixels. Since the charge generation layer has a high doping concentration and strong conductivity, and the charge generation layers in the light-emitting functional layers of adjacent sub-pixels are connected, the layers with high conductivity in the common layer CL, such as the charge generation layer, are prone to cause crosstalk between adjacent sub-pixels, affecting the product image quality, thereby seriously affecting the display quality.

[0059] For example, crosstalk between adjacent sub-pixels occurs when a light-emitting element that should not emit light actually emits light. As shown in Figure 2, if the desired behavior is for light-emitting element EM1 to emit light while light-emitting element EM2 does not, the conductivity of the charge generation layer causes light-emitting element EM2 to also emit light, resulting in lateral light leakage and crosstalk.

[0060] In order to avoid lateral light leakage, structures such as isolation columns can be provided to alleviate or avoid lateral light leakage and improve image quality, especially low grayscale image quality.

[0061] Figure 3 is a cross-sectional view of a display panel. Figure 4 is a plan view of a display panel.

[0062] As shown in FIG3 , an isolation structure 06 is provided (at the dotted box F1). By providing a passivation layer PVX2 on the planarization layer PLN3, the planarization layer PLN3 is provided with a groove or through hole at the location where the passivation layer PVX2 is provided, thereby forming an isolation structure 06 that can be used to isolate the common layer in the light-emitting functional layer, thereby alleviating or avoiding lateral light leakage and improving image quality.

[0063] Figure 4 shows sub-pixel SP1, sub-pixel SP2, and sub-pixel SP3. For example, two sub-pixels SP1, one sub-pixel SP2, and one sub-pixel SP3 constitute a repeating unit PX. Sub-pixel SP1 includes a light-emitting element 201, sub-pixel SP2 includes a light-emitting element 202, and sub-pixel SP3 includes a light-emitting element 203. The sub-pixel is shown with respect to the light-emitting area of ​​the light-emitting element of the sub-pixel. As shown in Figure 4, position P2 is the outer edge of the light-emitting area of ​​the light-emitting element of the sub-pixel. Position P3 is the outer edge of the passivation layer PVX2 used to form the isolation structure 06. Position P1 is the location of the isolation structure 06. The outermost arc-shaped portion of the light-emitting element shown in Figure 4 is the opening in the pixel defining layer PDL that exposes the isolation structure 06.

[0064] For example, as shown in Figure 3, the passivation layer PVX2 is approximately 3μm larger than the pixel electrode. For example, if the passivation layer PVX2 is larger than 20μm, the gap between adjacent passivation layers PVX2 is approximately 5μm, resulting in a severe lack of space for graphic design. As shown in Figure 3, in order to expose the isolation structure 06, the outer boundary of the pixel definition layer PDL must be smaller than the outer boundary of the passivation layer PVX2.

[0065] However, the display panel shown in Figure 3 has at least one of the following problems. First, the passivation layer PVX2 is arranged between the pixel electrode E1 and the planarization layer PLN3 (such as in the dotted box F3). The flatness of the passivation layer PVX2 is lower than that of the planarization layer, which makes the pixel electrode E1 uneven, resulting in reduced light efficiency, which is not conducive to improving the display effect. Second, the pixel defining layer PDL is in contact with the passivation layer PVX2 used to form the isolation structure 06 (in the dotted box F2), and it is easy for the pixel defining layer PDL to peel off from the passivation layer PVX2. Third, the area of ​​the passivation layer PVX2 used to form the isolation structure 06 is large, which is not conducive to the exhaust of the planarization layer below it. Fourth, due to the spacing limitation between the pixel electrodes, only a single-sided isolation structure can be set. Fifth, the passivation layer PVX2 seriously affects the bending performance of the display panel.

[0066] Other structures in Figures 2 and 3 can be found in the description of other cross-sectional views and will not be described here.

[0067] The embodiments of the present disclosure provide a display panel and a display device including the display panel, wherein the pixel electrode E1 and the isolation structure are separated by at least a portion of a planarization layer, which facilitates planarization of the pixel electrode E1 and improves the display effect.

[0068] Figure 5 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure. Figure 6 is a partial enlarged view of Figure 5. Figure 7 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure. Figure 8 is a partial enlarged view of Figure 7. Figure 9 is a plan view of a display panel provided by an embodiment of the present disclosure. Figures 10 to 14 are cross-sectional views of several display panels provided by an embodiment of the present disclosure. Figure 15A is a plan view of a display panel provided by an embodiment of the present disclosure. Figure 15B is a plan view of a display panel provided by an embodiment of the present disclosure. Figure 16A is a schematic diagram of the area division of a display panel provided by an embodiment of the present disclosure. Figure 16B is a schematic diagram of the area division of another display panel provided by an embodiment of the present disclosure. Figure 17 is a schematic diagram of the area division of another display panel provided by an embodiment of the present disclosure. Figures 18 to 21 are cross-sectional views of several display panels provided by an embodiment of the present disclosure.

[0069] As shown in Figures 5 to 8, 10 to 14, and 18 to 21, embodiments of the present disclosure provide a display panel comprising: a base substrate BS, a plurality of pixel circuits 100, an insulating layer ISL, a plurality of pixel electrodes E1, a light-emitting functional layer EML, and an isolation structure 600. The plurality of pixel circuits 100 are located on the base substrate BS. The insulating layer ISL is located on a side of the plurality of pixel circuits 100 facing away from the base substrate BS and includes a plurality of planarization layers, each of which comprises an organic material. The pixel electrode E1 is located on a side of the plurality of planarization layers facing away from the base substrate BS and is connected to one of the plurality of pixel circuits 100. The light-emitting functional layer EML includes a common layer CL. The orthographic projection of the common layer CL on the base substrate BS overlaps with the orthographic projections of the plurality of pixel electrodes E1 on the base substrate BS, and at least a portion of the common layer CL is located on a side of the plurality of pixel electrodes E1 facing away from the base substrate BS. As shown in Figures 5 to 8, 10 to 14, 18 to 19, and 21, the isolation structure 600 has a protrusion PR that protrudes from the underlying planarization layer, or, as shown in Figure 20, the isolation structure 600 itself has the protrusion PR. As shown in Figures 7 and 8, the isolation structure 600 is configured to isolate the common layer CL at the protrusion PR. As shown in Figures 5 to 8, 10 to 14, and 18 to 21, the isolation structure 600 is located between adjacent pixel electrodes E1 and comprises an inorganic material. The isolation structure 600 is located above at least a portion of the planarization layer, and the isolation structure 600 is separated from the plurality of pixel electrodes E1 by at least a portion of the planarization layer. For example, "separating the isolation structure 600 from the plurality of pixel electrodes E1 by at least a portion of the planarization layer" may mean that at least a portion of a planarization layer is disposed between the isolation structure 600 and the plurality of pixel electrodes E1. The cross-sectional views of the present disclosure illustrate a planarization structure layer PLN composed of multiple planarization layers.

[0070] The display panel provided by the embodiments of the present disclosure has at least one of the following effects. First, the isolation structure 600 has a protrusion PR protruding from the planarization layer below it, or the isolation structure 600 itself has a protrusion PR. The pixel electrode E1 and the isolation structure 600 are separated by at least part of the planarization layer, which ensures flatness, facilitates flattening the pixel electrode E1, improves light efficiency, and facilitates improving display effects. Second, the pixel electrode E1 and the isolation structure 600 are separated by at least part of the planarization layer. The isolation structure 600 is located below the pixel electrode E1. Even if there is a limitation of a small spacing between pixel electrodes, bilateral isolation (two-side isolation) can still be performed to improve the isolation effect. Third, the pixel defining layer is not in direct contact with the structure forming the isolation structure 600, avoiding the risk of pixel defining layer peeling. Fourth, the structure forming the isolation structure 600 can be set smaller, which is conducive to the exhaust of the planarization layer during the annealing process and reduces the risk of outgassing caused by subsequent high-temperature processes. Fifth, the impact on the bending performance of the display panel can be reduced. Sixth, lateral crosstalk between adjacent sub-pixels is avoided. For example, the structure forming the isolation structure 600 includes the passivation layer PVX2 mentioned later.

[0071] For example, the common layer CL includes at least a charge generation layer, but is not limited thereto.

[0072] 5 to 8, 10 to 14, 18 to 19, and 21, the isolation structure 600 includes a passivation layer PVX2, which is provided to form the protrusion PR. Figure 20 shows a case where the isolation structure 600 itself includes the protrusion PR.

[0073] For example, as shown in Figures 5 to 8, Figures 10 to 14, and Figures 18 to 21, the multiple planarization layers include a planarization layer PLN1, a planarization layer PLN2, and a planarization layer PLN3 arranged in sequence, the planarization layer PLN1 is closer to the substrate BS than the planarization layer PLN3, and in the direction perpendicular to the substrate BS, the isolation structure 600 is located above at least part of the planarization layer and below at least part of the planarization layer.

[0074] For example, the planarization layer PLN1 may be referred to as a first planarization layer, the planarization layer PLN2 may be referred to as a second planarization layer, and the planarization layer PLN3 may be referred to as a third planarization layer, but is not limited thereto.

[0075] It should be noted that in the embodiments of the present disclosure, the number of planarization layers is not limited to that shown in the figure, and the number of planarization layers can be at least two. For example, the number of planarization layers can also be three or more, depending on the layer structure of the display panel.

[0076] For example, as shown in Figures 5 to 8, 10 to 12, 14, 19, and 21, the planarization layer below the isolation structure 600 has a groove GRV or a first through hole H1 at the protrusion PR. For example, the passivation layer PVX2 protrudes from the planarization layer below it at the groove GRV or the first through hole H1 to form the protrusion PR.

[0077] For example, in an embodiment of the present disclosure, in order to better play a partitioning role, the distance between the protrusion PR and the bottom surface of the groove GRV or the first through hole H1 is greater than or equal to 0.4 μm.

[0078] For example, in an embodiment of the present disclosure, in order to better play a partitioning role, the distance between the protrusion PR and the bottom surface of the groove GRV or the first through hole H1 is greater than or equal to 0.4 μm and less than or equal to 2 μm.

[0079] For example, in the embodiment of the present disclosure, in order to better play a partitioning role, the protruding size of the protrusion PR in the lateral direction is greater than or equal to 0.1 μm.

[0080] As shown in Figures 5 to 8, 10 to 12, 14, 19, and 21, the planarization layer below the isolation structure 600 has a groove GRV at the protrusion PR. As shown in Figures 13 and 18, the planarization layer below the isolation structure 600 has a first through-hole H1 at the protrusion PR. In the embodiment of the present disclosure, the groove GRV does not penetrate the planarization layer below the isolation structure 600, and the first through-hole H1 penetrates the planarization layer below the isolation structure 600. As shown in Figure 8, the groove GRV or the first through-hole H1 is provided to facilitate the subsequent formation of the common layer CL, so that a portion of the common layer CL falls into the groove GRV or the first through-hole H1, thereby disconnecting the common layer CL at the protrusion PR of the isolation structure 600. Figure 8 shows the separation portion CL11 formed by the disconnection of the first common layer CL1 at the isolation structure 600, and the separation portion CL21 formed by the disconnection of the second common layer CL2 at the isolation structure 600.

[0081] It should be noted that the form of at least one of the separation portion CL11 or the separation portion CL21 may be different from that shown in Figure 8. For example, in some embodiments, at least one of the separation portion CL11 or the separation portion CL21 may also cover the sidewall of the groove GRV or the first through hole H1.

[0082] Figures 7 and 8 illustrate the example of the electron transport layer ETL-2 and the common electrode E2 being continuous at the isolation structure 600. The embodiments of the present disclosure are not limited thereto. In other embodiments, the electron transport layer ETL-2 and the common electrode E2 may also be disconnected at the isolation structure 600. Whether the common electrode E2 is disconnected at the isolation structure 600 may be related to the protruding size of the protrusion PR and / or the depth of the groove GRV or the first through hole H1 below the protrusion PR. Of course, in other embodiments, the display panel may not be provided with the electron transport layer ETL-2.

[0083] For example, as shown in FIG5 to FIG8, FIG10 to FIG12, FIG14, FIG19 and FIG21, the planarization layer located above the isolation structure 600 has a second through hole H2 at the protrusion PR, and the first through hole H1 and the second through hole H2 are connected.

[0084] For example, as shown in FIG. 5 to FIG. 8 , FIG. 10 to FIG. 12 , FIG. 14 , FIG. 19 , and FIG. 21 , the maximum dimension of the first through hole H1 is smaller than the maximum dimension of the second through hole H2 .

[0085] For example, as shown in Figures 9, 15A, and 15B, the passivation layer PVX2 extends around the light-emitting area of ​​the light-emitting element, and the maximum dimension of the first through hole H1 in a direction perpendicular to the extension direction of the passivation layer PVX2 is smaller than the maximum dimension of the second through hole H2 in a direction perpendicular to the extension direction of the passivation layer PVX2. In other words, the maximum width of the first through hole H1 is smaller than the maximum width of the second through hole H2.

[0086] For example, as shown in Figures 5 to 6, 10 to 12, 14, 19, and 21, the display panel further includes a pixel defining layer (PDL), the pixel defining layer (PDL) having a plurality of first openings PN1, each of the plurality of first openings PN1 being configured to expose one of the plurality of pixel electrodes E1, and the pixel defining layer (PDL) further having a second opening PN2 connected to the second through hole H2. The second opening PN2 is configured to expose the isolation structure 600 to facilitate disconnection of the common layer CL at the isolation structure 600.

[0087] For example, as shown in Figures 5 to 6, 10 to 12, 14, 19 and 21, the orthographic projection of the second opening PN2 on the base substrate BS overlaps with the orthographic projection of the isolation structure 600 on the base substrate BS, so that the second opening PN2 exposes the isolation structure 600.

[0088] As shown in Figures 5 to 8, 10 to 12, 14, 19, and 21, the main portion of the pixel defining layer (PDL) does not contact the passivation layer (PVX) forming the isolation structure 600, thereby preventing the pixel defining layer (PDL) from being easily peeled off. The main portion of the pixel defining layer (PDL) is a structure comprising the material of the pixel defining layer.

[0089] For example, as shown in FIG10 , the isolation structure 600 has a protrusion PR at the recess GRV or the first through hole H1. That is, the isolation structure 600 forms a single-sided structure, isolating the common layer CL at a single edge. Single-sided isolation (single-sided isolation) can reduce the occupied area of ​​the passivation layer PVX2 and the isolation structure 600.

[0090] For example, as shown in FIG. 10 , the thickness of the passivation layer PVX2 is about 0.07 μm, and the width of the passivation layer PVX2 can be designed to be about 3 μm.

[0091] For example, in other embodiments of the present disclosure, the thickness of the passivation layer PVX2 may also be set to about 0.07 μm. Of course, the thickness of the passivation layer PVX2 is not limited to the above description.

[0092] For example, as shown in Figures 5-6, 11-12, 14, 19, and 21, to enhance the isolation effect, the isolation structure 600 includes two isolation portions, namely, isolation portion PT1 and isolation portion PT2, at the groove GRV or first through hole H1. The two isolation portions each form two protrusions PR, namely, protrusion PR1 and protrusion PR2. Protrusion PR1 is formed at isolation portion PT1, and protrusion PR2 is formed at isolation portion PT2. This creates a double-sided structure between two adjacent sub-pixels (two adjacent light-emitting elements), isolating the common layer CL on both sides, further facilitating isolation of the common layer CL. As shown in Figures 9, 15A, and 15B, the groove GRV or first through hole H1 is elongated. Combining the partial cross-sectional view and the plan view shown in Figure 9, the two protrusions PR are located within the groove GRV or first through hole H1 and on opposite sides of the elongated groove GRV or first through hole H1. The shape of the second opening PN2 in plan view is similar to that of the groove GRV or the first through hole H1, except that the size of the groove GRV or the first through hole H1 may be slightly smaller than that of the second opening PN2.

[0093] Whether to form a single-sided isolation structure or a double-sided isolation structure can be determined according to the distance between two adjacent light-emitting elements.

[0094] For example, as shown in Figures 7 and 8, the display panel further includes a common electrode E2, at least a portion of which is located on a side of the light-emitting functional layer EML facing away from the base substrate BS. The plurality of pixel electrodes E1, the light-emitting functional layer EML, and the common electrode E2 constitute a plurality of light-emitting elements 200. Figures 7 and 8 illustrate a light-emitting element EM1 and a light-emitting element EM2. Figures 9, 15A, and 15B also illustrate the plurality of light-emitting elements 200.

[0095] 7 and 8 show the light emitting functional layer EML and the common electrode E2 . The display panel in other cross-sectional views not showing the light emitting functional layer EML and the common electrode E2 may refer to FIG. 7 .

[0096] For example, as shown in Figures 5 to 8, 10 to 12, 14, 19, and 21, the passivation layer PVX2 used to form the isolation structure 600 protrudes laterally from the planarization layer below it and laterally from the planarization layer above it. For example, the laterally direction refers to a direction parallel to the main surface of the substrate.

[0097] For example, as shown in Figures 5 to 8, Figures 10 to 12, Figure 14, Figure 19 and Figure 21, in order to facilitate the formation of the isolation structure 600, a portion of the lower surface of the passivation layer PVX2 contacts the upper surface of the planarization layer located below the passivation layer PVX2, and a portion of the lower surface of the passivation layer PVX2 does not contact the upper surface of the planarization layer located below the passivation layer PVX2.

[0098] For example, as shown in Figures 5 to 8, Figures 10 to 12, Figure 14, Figure 19 and Figure 21, in order to facilitate the formation of the isolation structure 600, a portion of the lower surface of the passivation layer PVX2 contacts the upper surface of the planarization layer located above the passivation layer PVX2, and a portion of the lower surface of the passivation layer PVX2 does not contact the upper surface of the planarization layer located above the passivation layer PVX2.

[0099] For example, in some embodiments, at least part of the side surface of the protrusion PR of the passivation layer PVX2 is covered with the material of the light-emitting functional layer EML. For example, at least part of the side surface of the protrusion PR of the passivation layer PVX2 is covered with the material of at least one of the common layer CL and the local layer LL. For example, at least part of the side surface of the protrusion PR of the passivation layer PVX2 is covered with the common layer CL. In an embodiment of the present disclosure, the protrusion PR has a lower surface, an upper surface, and a side surface located between the lower surface and the lower surface. The lower surface of the protrusion PR is closer to the base substrate than the upper surface.

[0100] In the case that at least part of the side surface of the protrusion PR of the passivation layer PVX2 is covered with the material of the light-emitting functional layer EML, the protrusion PR can also play a role in disconnecting at least one film layer in the common layer CL.

[0101] It should be noted that, for clarity of illustration, FIG7 and FIG8 do not show the material of the light-emitting functional layer EML on the side surface of the protrusion PR of the passivation layer PVX2.

[0102] For example, as shown in Figures 9, 15A, and 15B, the light-emitting element 200 includes a first light-emitting element 201, a second light-emitting element 202, and a third light-emitting element 203. Subpixel SP1 includes the first light-emitting element 201 and a pixel circuit connected to the first light-emitting element 201 (not shown in Figures 9, 15A, and 15B). Subpixel SP2 includes the second light-emitting element 202 and a pixel circuit connected to the second light-emitting element 202 (not shown in Figures 9, 15A, and 15B). Subpixel SP3 includes the third light-emitting element 203 and a pixel circuit connected to the third light-emitting element 203 (not shown in Figures 9, 15A, and 15B).

[0103] For example, as shown in Figures 9, 15A, and 15B, the isolation structure 600 surrounding one light-emitting element 200 includes a plurality of isolation substructures 660. As shown in Figures 9, 15A, and 15B, the isolation structure 600 surrounding the light-emitting element 201 includes two isolation substructures 660. As shown in Figures 9, 15A, and 15B, the isolation structure 600 surrounding the light-emitting element 202 includes four isolation substructures 660.

[0104] For example, as shown in Figures 9, 15A and 15B, the plurality of isolation substructures 660 include at least two isolation substructures 660 located on opposite sides of the light-emitting area of ​​the light-emitting element 200 (position P2 is the outer edge of the light-emitting area, corresponding to the first opening PN1). Such an arrangement facilitates the formation of a gap G0 between adjacent isolation substructures 660. Providing the gap G0 facilitates the continuity of the common electrode E2 and the application of the signal on the common electrode E2. That is, it facilitates the formation of the common electrodes E2 corresponding to adjacent light-emitting elements into an integrated structure to facilitate the application of the signal. That is, the common electrode E2 can be isolated at the isolation structure 600 and connected at the gap G0, thereby ensuring the continuity of the common electrodes E2 of different light-emitting elements. Of course, a full circle of isolation structures can also be provided, that is, the isolation structure surrounds the light-emitting area in a full circle. In this case, the connection of the common electrodes E2 corresponding to different sub-pixels can be achieved through other film layers.

[0105] For example, as shown in Figures 7 and 8, the common electrode E2 is not disconnected at the isolation structure 600. Of course, the embodiments of the present disclosure are not limited thereto. The common electrode E2 may also be disconnected at the isolation structure 600. The common electrode E2 may be continuous at the gap G0 between the isolation substructures 660 mentioned later. Of course, if the common electrodes E2 of different sub-pixels are not an integrated structure, the common electrodes E2 corresponding to different sub-pixels may also be connected through other film layers.

[0106] For example, as shown in Figures 9, 15A, and 15B, the spacing between at least one of the plurality of isolation substructures 660 and two adjacent light-emitting elements 200 is unequal. As shown in Figures 9, 15A, and 15B, for light-emitting element 201 and its adjacent light-emitting element 203, spacing D1 is smaller than spacing D2. As shown in Figures 9, 15A, and 15B, for light-emitting element 201 and its adjacent light-emitting element 202, spacing D3 is smaller than spacing D4. The isolation structure 600 (isolation substructure 660) between adjacent light-emitting elements is disposed near one of the light-emitting elements. When two protrusions PR are disposed within a second opening PN2, the center line between the two protrusions PR can be used as one end of the spacing calculation.

[0107] As shown in Figure 9 , position P1 is the location of one protrusion of the isolation structure 600 , position P4 is the location of another protrusion of the isolation structure 600 , and position P2 is the outer edge of the light-emitting area of ​​the sub-pixel's light-emitting element, corresponding to the edge of the first opening PN1 . The plan view shown in Figure 9 corresponds to a case where an isolation structure 600 has two protrusions PR and is partitioned on both sides. For example, Figure 9 may be a plan view of the display panel shown in Figures 5 , 7 , 11 to 13 , 18 , 19 , or 21 .

[0108] The display panel shown in FIG15A adopts single-side partitioning, which may be a plan view of the display panel shown in FIG10 .

[0109] The display panel shown in Figure 15B adopts double-sided partition, and the two ends of the passivation layer PVX2 or the metal structure MT perpendicular to its extension direction can be located in the groove GRV (the groove can also be replaced by a through hole). Figure 15B can be a plan view of the display panel shown in Figure 14 or Figure 20.

[0110] As shown in FIG. 5 , FIG. 7 , FIG. 11 to FIG. 14 , and FIG. 18 to FIG. 20 , the two protrusions PR are both located in the same second opening PN2 .

[0111] 9 , 15A and 15B , the first opening PN1 and the second opening PN2 are shown. In the plan views, the pixel defining layer PDL is shown as an opening. In the pixel defining layer PDL, the portion other than the first opening PN1 and the second opening PN2 is a body portion.

[0112] As shown in FIG15A and FIG15B , position P2 is the outer edge of the light emitting area of ​​the light emitting element of the sub-pixel, corresponding to the edge of the first opening PN1 , and position P1 is where the isolation structure 600 (the protruding portion of the isolation structure 600 ) is located.

[0113] For example, as shown in Figures 9, 15A and 15B, the light-emitting area of ​​the first light-emitting element 201 is smaller than the light-emitting area of ​​the second light-emitting element 202, and the light-emitting area of ​​the second light-emitting element 202 is smaller than the light-emitting area of ​​the third light-emitting element 203. The isolation structure 600 includes a first isolation structure 601 and a second isolation structure 602. The first isolation structure 601 is located at the periphery of the light-emitting area of ​​the first light-emitting element 201, and the second isolation structure 602 is located at the periphery of the light-emitting area of ​​the second light-emitting element 202.

[0114] For example, as shown in Figures 9, 15A, and 15B, the first isolation structure 601 includes two first isolation substructures 6601 located on opposite sides of the light-emitting region of the first light-emitting element 201. The second isolation structure 602 includes four second isolation substructures 6602. The four second isolation substructures 6602 are arranged around the light-emitting region of the second light-emitting element 202. Two of the four second isolation substructures 6602 are located on opposite sides of the light-emitting region of the second light-emitting element 202, and the other two of the four second isolation substructures 6602 are located on opposite sides of the light-emitting region of the second light-emitting element 202. As shown in Figure 9, the four second isolation substructures 6602 are arranged sequentially around the light-emitting region of the second light-emitting element 202. As shown in Figure 9, a gap G01 is defined between two first isolation substructures 6601. As shown in Figures 9, 15A, and 15B, a gap G02 is defined between two adjacent second isolation substructures 6602. The size of the gap G01 is larger than the size of the gap G02.

[0115] For example, as shown in Figures 9, 15A, and 15B, the light-emitting region of the first light-emitting element 201 is surrounded by two first isolation substructures 6601 and two second isolation substructures 6602 located at the gaps in the first isolation substructures 6601. Thus, the isolation structures 600 / isolation substructures 660 are disposed in the regions between the first light-emitting element 201 and its two adjacent second light-emitting elements 202, as well as between the first light-emitting element 201 and its two adjacent third light-emitting elements 203, thereby mitigating or avoiding crosstalk between adjacent sub-pixels.

[0116] For example, as shown in Figures 9, 15A, and 15B, the light-emitting region of the third light-emitting element 203 is surrounded by four first isolation substructures 6601 and two second isolation substructures 6602. Thus, isolation structures 600 / isolation substructures 660 are provided in the regions between the third light-emitting element 203 and its two adjacent second light-emitting elements 202, and between the third light-emitting element 203 and its four adjacent first light-emitting elements 201, thereby reducing or avoiding crosstalk between adjacent sub-pixels.

[0117] For example, as shown in Figures 9, 15A, and 15B, the first light-emitting element 201 is configured to emit green light, the second light-emitting element 202 is configured to emit red light, and the third light-emitting element 203 is configured to emit blue light. Figure 9 illustrates an example in which the first light-emitting element 201 is configured to emit green light, the second light-emitting element 202 is configured to emit red light, and the third light-emitting element 203 is configured to emit blue light. However, the light-emitting colors of the light-emitting elements provided in the embodiments of the present disclosure are not limited thereto and can be determined as needed.

[0118] For example, as shown in Figures 9, 15A, and 15B, a repeating unit PX includes two first sub-pixels SP1, one second sub-pixel SP2, and one third sub-pixel SP3. For example, as shown in Figure 9, in a repeating unit PX, the second sub-pixel SP2 and the third sub-pixel SP3 are located on either side of a line connecting the centers of the two first sub-pixels SP1. Of course, the pixel arrangement of the display panel is not limited to that shown in Figure 9, and the pixel arrangement can be set as needed.

[0119] As shown in Figures 9, 15A, and 15B, the distance between the spacer structure 660 surrounding the light-emitting region of one light-emitting element and the light-emitting region of that light-emitting element is greater than the distance between the spacer structure 660 and the light-emitting region of the adjacent light-emitting element. In other words, the closer the spacer structure 660 is to the light-emitting region of the light-emitting element around which it is located, the closer it is to the light-emitting region of the light-emitting element.

[0120] FIG9 , FIG15A and FIG15B take the example of forming the isolation structure 600 and the passivation layer PVX2 set around the light-emitting area of ​​the light-emitting element as a plurality of examples, however, it is not limited to this. The passivation layer PVX2 set around the light-emitting area of ​​the light-emitting element can also be set to a full circle structure, as long as a plurality of discrete second openings PN2 are set around the light-emitting area of ​​the same light-emitting element. For multiple isolation substructures set in the light-emitting area of ​​the same light-emitting element, the position between adjacent second openings PN2 is the gap G0. That is, in the embodiment of the present disclosure, in order to facilitate the continuity of the common electrode E2, a plurality of second openings PN2 are provided around the light-emitting area of ​​the same light-emitting element, and the area between adjacent second openings PN2 is the gap G0.

[0121] 9, 15A, and 15B illustrate arc-shaped isolation structures 600 and isolation substructures 660, but are not limited thereto and may be configured as needed. For example, isolation structures 600 and isolation substructures 660 may be configured according to the shape of the outer edge of the light-emitting region of the light-emitting element.

[0122] 9, 15A, and 15B illustrate a circular light-emitting region of a sub-pixel / light-emitting element, but the present invention is not limited thereto. The light-emitting region of a sub-pixel / light-emitting element may be configured in other shapes as needed, such as a pentagon, hexagon, rectangle, or the like.

[0123] For example, as shown in Figures 5 to 8, 10 to 14, and 18 to 21, the isolation structure 600 does not contact the plurality of pixel electrodes E1, thereby preventing the isolation structure 600 from affecting the flatness of the pixel electrodes E1 and the display effect.

[0124] For example, as shown in Figures 5 to 8, 10 to 14, 18 to 19, and 21, the inorganic material included in the isolation structure 600 includes an inorganic non-metallic material, and the inorganic material is an insulating material. The isolation structure 600 includes a passivation layer PVX2, which protrudes from the planarization layer below it, thereby forming a protrusion PR. The passivation layer PVX2 includes an inorganic non-metallic material, and the inorganic material is an insulating material. For example, the material of the passivation layer PVX2 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0125] For example, as shown in FIG20 , isolation structure 600 includes a metal structure MT. The inorganic material included in isolation structure 600 includes a metal material, or the metal structure MT includes a metal material. Isolation structure 600 / metal structure MT includes a first sublayer 610, a second sublayer 620, and a third sublayer 630 that are stacked and sequentially arranged. The first sublayer 610 is closer to the substrate BS than the third sublayer 630, and the third sublayer 630 protrudes outward from the second sublayer 620 to form a protrusion PR. For example, the materials of the first sublayer 610, the second sublayer 620, and the third sublayer 630 each include a metal. For example, the materials of the first sublayer 610 and the third sublayer 630 are the same and different from the material of the second sublayer 620. For example, the materials of the first sublayer 610 and the third sublayer 630 include titanium. For example, the material of the second sublayer 620 includes aluminum. For example, the first sublayer 610, the second sublayer 620, and the third sublayer 630 form a stacked structure of three sublayers: Ti / AlTi. For example, as shown in FIG. 20 , the second sub-layer 620 is retracted relative to the first sub-layer 610 and the third sub-layer 630 .

[0126] For example, as shown in Figures 5 to 8, Figures 10 to 14, and Figures 18 to 21, the display panel also includes a first connection electrode CE1 and a second connection electrode CE2, the pixel circuit 100 includes a transistor T1, the first connection electrode CE1 is located on the planarization layer PLN1, and is connected to the transistor T1 through a via hole passing through the planarization layer PLN1, the second connection electrode CE2 is located on the planarization layer PLN2, and is connected to the first connection electrode CE1 through a via hole passing through the planarization layer PLN2, the pixel electrode E1 is located on the planarization layer PLN3, and is connected to the second connection electrode CE2 through a via hole passing through the planarization layer PLN3.

[0127] For example, as shown in Figures 5 to 8, 10 to 14, and 18 to 21, transistor T1 includes a gate electrode GT1, a gate insulating layer GI1, an active layer AT1, a first electrode Ea, and a second electrode Eb. The first electrode Ea and the second electrode Eb are respectively connected to two ends of the active layer AT1. A first connection electrode CE1 is connected to the second electrode Eb. For example, the active layer AT1 of transistor T1 is made of low-temperature polycrystalline silicon (LTPS), but is not limited thereto.

[0128] For example, as shown in Figures 5 to 8, 10 to 14, and 18 to 21, the pixel circuit 100 further includes a transistor T2, which includes a gate GT2, a gate GT3, a gate insulating layer GI2, a gate insulating layer GI3, an active layer AT2, a first electrode Ec, and a second electrode Ed, wherein the first electrode Ec and the second electrode Ed are respectively connected to the two ends of the active layer AT2. For example, the gate GT2 and the gate GT3 of the transistor T2 form a dual-gate structure to improve the performance of the transistor T2. For example, the active layer AT2 of the transistor T2 uses an oxide semiconductor, such as indium gallium zinc oxide (IGZO), but is not limited thereto.

[0129] For example, as shown in Figures 5 to 8, Figures 10 to 14, and Figures 18 to 21, the insulating layer ISL also includes an inorganic insulating layer PVX1, which is located between the pixel circuit 100 (including transistor T1 and transistor T2) and the planarization layer PLN1, and the first connecting electrode CE1 also passes through the inorganic insulating layer PVX1.

[0130] For example, as shown in FIG. 5 to FIG. 8 , FIG. 10 to FIG. 14 , and FIG. 18 to FIG. 21 , the inorganic insulating layer PVX1 is provided on a side of the planarization layer close to the base substrate BS.

[0131] For example, as shown in Figures 5 to 8, 10 to 14, and 18 to 21, the pixel electrode E1 is connected to one of the plurality of pixel circuits 100 via a via hole penetrating at least a portion of the insulating layer ISL. In the case where a connection electrode is provided, the pixel electrode E1 is connected to the connection electrode via a via hole penetrating at least a portion of the insulating layer ISL, and the connection electrode is further connected to the pixel circuit 100. In the case where no connection electrode is provided, the pixel electrode E1 is connected to the pixel circuit 100 via a via hole penetrating the insulating layer ISL.

[0132] For example, as shown in Figures 5 to 8, 10 to 14, and 18 to 21, the base substrate BS includes a first base substrate PI1, a barrier layer BR1, and a second base substrate PI2. Of course, the structure of the base substrate BS is not limited to the above description. For example, the base substrate BS may also have a single-layer structure.

[0133] For example, the base substrate BS may be a flexible base substrate, but is not limited thereto. A flexible base substrate can be bent to reduce a frame or form a foldable display panel.

[0134] As shown in Figures 5 to 8, 10 to 14, and 18 to 21, a barrier layer BR2 is located on a base substrate BS. A light-shielding layer LS is provided on the barrier layer BR2. A buffer layer BF1 is provided on the light-shielding layer LS. A buffer layer BF2 is provided on the buffer layer BF1. An active layer AT2 is provided on the buffer layer BF2. A gate insulating layer GI1 is provided on the active layer AT2. A gate electrode GT1 is located on the gate insulating layer GI1. A buffer layer BF3 is provided on the gate electrode GT1. A gate electrode GT2 is provided on the buffer layer BF3. A gate insulating layer GI2 is provided on the gate electrode GT2. An active layer AT2 is provided on the gate insulating layer GI2. A gate insulating layer GI3 is provided on the active layer AT2. An interlayer insulating layer ILD is provided on the gate insulating layer GI3. A first electrode Ea, a second electrode Eb, a first electrode Ec, and a second electrode Ed are provided on the interlayer insulating layer ILD. The light-shielding layer LS blocks light, thereby improving the performance of the transistor T1.

[0135] For example, the barrier layer BR2 and the barrier layer BR1 may be made of the same material, but are not limited thereto.

[0136] As shown in Figures 5 to 8, 10 to 14, and 18 to 21, the display panel further includes a connecting electrode Ee, which may be connected to the light shielding layer LS. The connecting electrode Ee may be connected to other signal lines, such as a power line providing a constant voltage, to reduce the resistance of the power line. For example, the power line may be a signal line providing a power supply voltage VDD. The connecting electrode Ee is located on the interlayer insulating layer ILD and may be provided on the same layer as the first electrode Ea, the second electrode Eb, the first electrode Ec, and the second electrode Ed.

[0137] As shown in Figures 5 to 8, 10 to 14, and 18 to 21, the display panel further includes a connecting electrode CEa and a connecting electrode CEb. The connecting electrode CEa and the connecting electrode CEb are connected to each other. The connecting electrode CEa is located on the planarization layer PLN1, and the connecting electrode CEb is located on the planarization layer PLN2. The connecting electrode CEb is connected to the connecting electrode CEa via a via hole penetrating the planarization layer PLN2. The connecting electrode CEa and the connecting electrode CE1 are located on the same layer, and the connecting electrode CEb and the connecting electrode CE2 are located on the same layer.

[0138] As shown in Figures 5 to 8, 10 to 14, and 18 to 21, the display panel further includes a storage capacitor Cst, which includes a first plate Ca and a second plate Cb. For example, the first plate Ca and the gate electrode GT1 are located on the same layer, and the second plate Cb and the gate electrode GT2 are located on the same layer.

[0139] As shown in FIG5 to FIG8, FIG10 to FIG14, and FIG18 to FIG21, the display panel further includes a spacer PS configured to support the fine metal mask during the process of evaporating the local layer LL in the light emitting functional layer EML.

[0140] For example, the spacer PS can be integrated with the pixel defining layer PDL and can be manufactured using a dual-tone mask.

[0141] For example, as shown in Figures 5 to 8, 10 to 14, and 18 to 21, to facilitate the planarization of the pixel electrode E1, the planarization layer PLN3 includes a planarization sublayer PLN3-1 and a planarization sublayer PLN3-2. The planarization sublayer PLN3-1 is closer to the base substrate BS than the planarization sublayer PLN3-2. Of course, in other embodiments, the planarization layer PLN3 may also adopt a single-layer structure.

[0142] As shown in Figures 5, 7, 10, 19 and 21, the passivation layer PVX2 is disposed on the planarization sublayer PLN3-1 (a portion of the planarization layer PLN3), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization sublayer PLN3-2 (a portion of the planarization layer PLN3). In Figure 5, a groove GRV is formed in the planarization sublayer PLN3-1.

[0143] As shown in Figure 11 , the passivation layer PVX2 is disposed on the planarization layer PLN2 (part of the planarization layer), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization layer PLN3 (part of the planarization layer).

[0144] As shown in Figure 12, the passivation layer PVX2 is disposed on the planarization layer PLN1 (part of the planarization layer), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization layer PLN2 and the planarization layer PLN3 (part of the planarization layer). In Figure 12, a groove GRV is formed in the planarization layer PLN1.

[0145] 10 to 12 show the situation where the isolation structure 600 is moved downward to form display panels of different structures. It should be noted that the isolation structure 600 can be disposed above the planarization layer PLN1 and can be located at any film layer position separated from the pixel electrode E1 by at least part of the planarization layer.

[0146] As shown in Figures 13 and 18, the passivation layer PVX2 is disposed on the planarization sublayer PLN3-1 (a portion of the planarization layer PLN3), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization sublayer PLN3-2 (a portion of the planarization layer PLN3). In Figure 13, a first through hole H1 is formed in the planarization sublayer PLN3-1.

[0147] As shown in Figure 14, the passivation layer PVX2 is arranged on the planarization sublayer PLN3-1 (a portion of the planarization layer PLN3), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization sublayer PLN3-2 (a portion of the planarization layer PLN3). In Figure 14, a groove GRV is formed in the planarization sublayer PLN3-1. Of course, the groove GRV shown in Figure 14 may also be a through hole, and the through hole may at least pass through the planarization sublayer PLN3-1. For example, the through hole may pass through the planarization sublayer PLN3-1 and the planarization layer PLN2, or may not pass through the planarization layer PLN2, but may be in the form of a groove in the planarization layer PLN2. In the embodiment of the present disclosure, as long as it passes through one layer, it can be called a through hole.

[0148] For example, as shown in Figure 14, the passivation layer PVX2 is located between two adjacent sub-pixels. For example, the passivation layer PVX2 is located in the middle of the two adjacent sub-pixels, and the width of the passivation layer PVX2 can be designed to be about 5 μm, forming a partition on both sides to enhance the partition effect.

[0149] As shown in Figure 20 , the passivation layer PVX2 is disposed on the planarization layer PLN2 (part of the planarization layer), and the passivation layer PVX2 and the pixel electrode E1 are separated by the planarization layer PLN3 (part of the planarization layer).

[0150] As shown in FIG16A , the display panel includes a display area R1 and a peripheral area R2. The peripheral area R2 surrounds the display area R1 and has a bending area R21, so that a portion of the display panel can be bent backward to reduce the frame of the display panel.

[0151] For example, as shown in FIG5 and FIG16A , the display panel has a bending region R21 , and a via hole V0 may be provided in the bending region R21 so that the planarization layer can be filled into the via hole V0 , thereby enhancing the bendability of the display panel.

[0152] As shown in Figures 5 to 8 and Figures 10 to 14, the via hole V0 penetrates the passivation layer PVX1, the interlayer insulating layer ILD, the gate insulating layer GI3, the gate insulating layer GI2, the buffer layer BF3, the gate insulating layer GI1, the buffer layer BF2, the buffer layer BF1, and the barrier layer BR2.

[0153] As shown in Figures 5 to 8 and Figures 10 to 14, the connecting electrode CEc is located in the bending region R21. The connecting electrode CEc overlaps with the via V0. For example, the connecting electrode CEc can be connected to a signal line located in the display area, such as a data line or a power line that provides a constant voltage. For example, the power line that provides a constant voltage includes a power line that provides a constant voltage VDD and a power line that provides a constant voltage VSS. Of course, the connecting electrode CEc can also be connected to other signal lines. The embodiments of the present disclosure do not limit the signal line to which the connecting electrode CEc is connected.

[0154] As shown in Figure 16B , the display panel includes a display area R1 and a peripheral area R2. Peripheral area R2 surrounds display area R1. Peripheral area R2 includes a wiring area R22. For example, wiring area R22 can be used to connect to an integrated circuit or a flexible printed circuit board, but is not limited thereto. If the display panel does not require bending, a bending area is not provided.

[0155] As shown in FIG. 17 , the display panel includes a display region R1 and a peripheral region R2 , and the peripheral region R2 may surround the display region R1 .

[0156] For example, as shown in FIG17 , a display panel has an aperture region R3 and is provided with multiple isolation structures 600. At least some of the isolation structures 600 are located in a border region R0 adjacent to the aperture region R3. Border region R0 is used for routing. At least a portion of the display panel located in the aperture region R3 is removed to form a receiving cavity, within which a sensor may be located. For example, the sensor includes, but is not limited to, a camera.

[0157] At the border region R0 shown in FIG. 18 and FIG. 19 , at the isolation structure 600 , the passivation layer PVX2 is located on the planarization layer PLN1 . However, the planarization layer here is not limited to the planarization layer PLN1 , and other planarization layers may also be used.

[0158] As shown in FIG. 18 and FIG. 19 , the isolation structure 600 located in the display region R1 and the isolation structure 600 located in the border region R0 may be manufactured using the same patterning process.

[0159] As shown in FIG. 18 and FIG. 19 , the isolation structure 600 located in the display region R1 and the isolation structure 600 located in the frame region R0 have the same structure.

[0160] 18 to 21 show the display area R1, the frame area R0, and the hole area R3. In the display panels shown in FIG18 to 21, the structure in the hole area R3 is completely removed.

[0161] Figure 21 shows an isolation structure 600 provided between adjacent sub-pixels in a display area. The display panels shown in Figures 5, 7, 10 to 14 may also be provided without a bending region, thereby forming a structure similar to that shown in Figure 21 .

[0162] For example, in some embodiments, the passivation layer PXV2 used to form the isolation structure 600 is located only in the display region R1. Of course, in a display panel having a frame region R0, the passivation layer PXV2 used to form the isolation structure 600 may be located in both the display region R1 and the frame region R0.

[0163] In some embodiments, the display panel may have a bending region R21 and a hole region R3 .

[0164] For example, in the embodiments of the present disclosure, components located on the same layer can be formed from the same film layer through the same patterning process. In the embodiments of the present disclosure, the composition or patterning process can include only a photolithography process, or a photolithography process and an etching step, or can include other processes such as printing and inkjet for forming a predetermined pattern. The photolithography process refers to a process including film formation, exposure, and development, using photoresist, a mask, an exposure machine, etc. to form a pattern. The corresponding patterning process can be selected according to the structure formed in the embodiments of the present disclosure.

[0165] For example, in an embodiment of the present disclosure, when the planarization layer PLN3 includes a planarization sublayer PLN3-1 and a planarization sublayer PLN3-2, the thickness of the planarization sublayer PLN3-1 may be 1-2 μm, and the thickness of the planarization sublayer PLN3-2 may be 1-2 μm. For example, in this case, the thickness of the planarization layer PLN3 may be 2-4 μm.

[0166] For example, in the embodiment of the present disclosure, when the planarization layer PLN3 is a single-layer structure, the thickness of the planarization layer PLN3 may be 1-2 μm.

[0167] For example, in an embodiment of the present disclosure, the thickness of the planarization layer PLN1 may be 1-2 μm.

[0168] For example, in an embodiment of the present disclosure, the thickness of the planarization layer PLN2 may be 1-2 μm.

[0169] For example, in an embodiment of the present disclosure, the thickness of the passivation layer PVX1 may be 0.1-0.25 μm.

[0170] For example, in an embodiment of the present disclosure, the base substrate BS, buffer layer BF1, buffer layer BF2, buffer layer BF3, gate insulation layer GI1, gate insulation layer GI2, gate insulation layer GI3, interlayer insulation layer ILD, passivation layer PVX1, passivation layer PVX2, planarization layer PLN1, planarization layer PLN2, planarization layer PLN3, and pixel defining layer PDL are all made of insulating materials.

[0171] For example, the material of the base substrate BS includes polyimide, but is not limited thereto. For example, the material of the base substrate PI1 includes polyimide, but is not limited thereto. For example, the material of the base substrate PI2 includes polyimide, but is not limited thereto. For example, the base substrate BS can be a flexible base substrate to form a flexible display panel.

[0172] For example, at least one of the buffer layers BF1, BF2, BF3, the gate insulating layers GI1, GI2, GI3, the interlayer insulating layer ILD, the passivation layer PVX1, and the passivation layer PVX2 may be made of an inorganic insulating material. For example, the inorganic insulating material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0173] For example, the pixel defining layer (PDL) and the planarization layer materials include organic insulating materials. For example, the planarization layers PLN1, PLN2, and PLN3 include organic insulating materials. For example, the organic insulating materials include one or a combination of acrylic, polyethylene terephthalate, polyimide, polyamide, polycarbonate, epoxy resin, and the like.

[0174] For example, in embodiments of the present disclosure, both the pixel defining layer (PDL) and the planarization layer may be referred to as an organic layer or an organic insulating layer. For example, each of the planarization layers PLN1, PLN2, and PLN3 may be referred to as an organic layer. The pixel defining layer (PDL) may be referred to as an organic layer. The planarization sublayer PLN3-1 may be referred to as an organic sublayer or an organic insulating sublayer, and the planarization sublayer PLN3-2 may be referred to as an organic sublayer or an organic insulating sublayer.

[0175] For example, in the embodiment of the present disclosure, the insulating layer ISL may also be referred to as an insulating material layer.

[0176] For example, in an embodiment of the present disclosure, at least one of the gate GT1, gate GT2, gate GT3, first electrode Ca, second electrode Cb, first electrode Ea, second electrode Eb, first electrode Ec, second electrode Ed, connecting electrode CE1, connecting electrode CE2, connecting electrode CEa, connecting electrode CEb, and connecting electrode CEc is made of metal or alloy.

[0177] For example, in the embodiment of the present disclosure, the active layer AT1 and the active layer AT2 are semiconductor layers, and can be made of polysilicon or metal oxide semiconductor materials.

[0178] For example, in the embodiment of the present disclosure, one of the pixel electrode E1 and the common electrode E2 is the anode of the light-emitting element, and the other of the pixel electrode E1 and the common electrode E2 is the cathode of the light-emitting element. The embodiment of the present disclosure is described by taking the pixel electrode E1 as the anode and the common electrode E2 as the cathode as an example.

[0179] For example, the pixel electrode E1 is made of a conductive material. For example, the material of the pixel electrode E1 includes metal and conductive metal oxide. For example, the pixel electrode E1 has a structure in which indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) are stacked. The material and structure of the pixel electrode E1 can be set as needed.

[0180] For example, the common electrode E2 is made of a conductive material. For example, the material of the common electrode E2 includes a metal or an alloy. For example, the material of the common electrode E2 includes a Mg / Ag alloy. The material and structure of the common electrode E2 can be set as needed.

[0181] It should be noted that the embodiments of the present disclosure are described using an example in which the common layer CL includes a first common layer CL1, a second common layer CL2, and a third common layer CL3, but the present invention is not limited thereto. The common layer CL may have a single-layer structure or a stacked-layer structure including multiple film layers. For example, in some embodiments, the common layer CL includes at least a charge generation layer.

[0182] For example, in an embodiment of the present disclosure, at least one film layer in the light-emitting functional layer EML may be manufactured by an evaporation process.

[0183] It should be noted that the embodiments of the present disclosure are described by taking the light emitting element having a Tandem structure as an example, but are not limited thereto. The light emitting element may also adopt other suitable structures.

[0184] For example, the display panel may further include an encapsulation layer configured to encapsulate the plurality of light emitting elements to prevent water and oxygen from invading.

[0185] For example, the pixel defining layer PDL can be a black pixel defining layer. Usually, the color filter on encapsulation (COE) structure can be matched with the black pixel defining layer.

[0186] For example, the display panel may further include a touch layer, and the touch layer may be disposed between the encapsulation layer and the COE structure.

[0187] In the embodiments of the present disclosure, the cross-sectional view of the display panel with the bending region shows the structure before the bending. For example, the bending region on the right side of the figure can be bent downward so that part of the display panel is arranged behind another part of the display panel, thereby reducing the bezel of the display panel.

[0188] It should be noted that, in the embodiment of the present disclosure, the pixel circuit 100 includes a transistor T1, a transistor T2 and a storage capacitor. For example, the transistor T1 can be a light-emitting control transistor, and the transistor T2 can be a threshold compensation transistor or a reset control transistor, but are not limited thereto. The embodiment of the present disclosure does not limit the structure of the pixel circuit 100, and a conventional pixel circuit can be used. For example, the pixel circuit 100 can adopt a 7T1C pixel circuit, a 7T2C pixel circuit, an 8T1C pixel circuit or a 9T1C pixel circuit. Of course, the number of transistors and the number of capacitors included in the pixel circuit 100 are not limited to the above description, and can be determined as needed. The connection relationship between transistors or between transistors and capacitors is not shown in the cross-sectional view, and this is a conventional structure.

[0189] In the drawings provided in the embodiments of the present disclosure, the plan views illustrate directions X and Y, and the cross-sectional views illustrate direction Z. Direction X intersects direction Y. For example, direction X is perpendicular to direction Y. Both direction X and direction Y are parallel to the main surface of the substrate. For example, direction Z is perpendicular to direction X and perpendicular to direction Y.

[0190] For example, in an embodiment of the present disclosure, when the isolation structure 600 includes an inorganic non-metallic material (passivation layer PVX2), after forming the pattern of the pixel defining layer PDL and the second through hole H2 in the planarization layer above the isolation structure 600, the first through hole H1 or the groove GRV in the planarization layer below the isolation structure 600 is formed. Of course, the method for manufacturing the display panel is not limited to the above description. For example, in other embodiments, the first through hole H1 or the groove GRV in the planarization layer below the isolation structure 600 is first formed, and then subsequent patterns are produced until a display panel with the described structure is formed. The embodiment of the present disclosure does not limit the method for manufacturing the display panel, and a suitable manufacturing method can be set as needed.

[0191] An embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned display panels.

[0192] For example, the display device can be a display device such as an organic light-emitting diode display device, as well as any product or component with a display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, navigator, etc. that includes the display device. The embodiments of the present disclosure include but are not limited to the above.

[0193] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: substrate substrate; A plurality of pixel circuits are located on the substrate; an insulating material layer, located on a side of the plurality of pixel circuits away from the base substrate, and comprising a plurality of organic insulating layers, each of the plurality of organic insulating layers comprising an organic material; a plurality of pixel electrodes, the pixel electrodes being located on a side of the plurality of organic insulating layers away from the base substrate and connected to one of the plurality of pixel circuits; The light-emitting functional layer comprises a common layer, the orthographic projection of the common layer on the base substrate overlaps with the orthographic projection of the plurality of pixel electrodes on the base substrate, and at least a portion of the common layer is located on a side of the plurality of pixel electrodes away from the base substrate; as well as an isolation structure having a protruding portion protruding from the organic insulating layer therebelow or having a protruding portion itself, wherein the isolation structure is configured to isolate the common layer at the protruding portion, The isolation structure is located between adjacent pixel electrodes and comprises an inorganic material. The isolation structure is located on at least a portion of the organic insulating layer, and the isolation structure is separated from the plurality of pixel electrodes by at least a portion of the organic insulating layer.

2. The display panel according to claim 1, wherein: The organic insulating layer located below the isolation structure has a groove or a first through hole at the protrusion.

3. The display panel according to claim 2, wherein: The organic insulating layer located above the isolation structure has a second through hole at the protruding portion, and the first through hole is connected to the second through hole.

4. The display panel according to claim 3, further comprising a pixel defining layer, wherein: The pixel defining layer has a plurality of first openings, each of the plurality of first openings is configured to expose one of the plurality of pixel electrodes, and the pixel defining layer further has a second opening, the second opening being in communication with the second through hole.

5. The display panel according to claim 4, wherein: An orthographic projection of the second opening on the base substrate overlaps with an orthographic projection of the isolation structure on the base substrate.

6. The display panel according to any one of claims 2 to 5, wherein: The isolation structure has a protrusion at the groove or the first through hole.

7. The display panel according to any one of claims 2 to 5, wherein: The groove or the first through hole is in the shape of an elongated strip, and the isolation structure includes two isolation parts at the groove or the first through hole, and the two isolation parts respectively form two protrusions, and the two protrusions are located in the groove or the first through hole and on opposite sides of the elongated groove or the first through hole.

8. The display panel according to any one of claims 1 to 7, further comprising a common electrode, wherein: At least a portion of the common electrode is located on a side of the light-emitting functional layer away from the base substrate, and the plurality of pixel electrodes, the light-emitting functional layer, and the common electrode constitute a plurality of light-emitting elements.

9. The display panel according to claim 8, wherein: The isolation structure surrounding a light emitting element includes a plurality of isolation substructures.

10. The display panel according to claim 9, wherein: The plurality of spacer structures include at least two spacer structures located on two opposite sides of the light emitting region of the light emitting element.

11. The display panel according to any one of claims 9 to 10, wherein: The distances between at least one of the plurality of isolation substructures and two adjacent light emitting elements are not equal.

12. The display panel according to claim 8, wherein: The light-emitting elements include a first light-emitting element, a second light-emitting element, and a third light-emitting element. The light-emitting area of ​​the first light-emitting element is smaller than the light-emitting area of ​​the second light-emitting element, and the light-emitting area of ​​the second light-emitting element is smaller than the light-emitting area of ​​the third light-emitting element. The isolation structure includes a first isolation structure and a second isolation structure. The first isolation structure is located at the periphery of the light-emitting area of ​​the first light-emitting element, and the second isolation structure is located at the periphery of the light-emitting area of ​​the second light-emitting element.

13. The display panel according to claim 12, wherein: The first isolation structure includes two first isolation substructures located on opposite sides of the light emitting area of ​​the first light emitting element, and the second isolation structure includes four second isolation substructures. The four second isolation substructures are arranged around the light emitting area of ​​the second light emitting element, two of the four second isolation substructures are located on opposite sides of the light emitting area of ​​the second light emitting element, and the other two second isolation substructures of the four second isolation substructures are located on opposite sides of the light emitting area of ​​the second light emitting element.

14. The display panel according to claim 13, wherein: The light emitting area of ​​the first light emitting element is surrounded by two first isolating substructures and two second isolating substructures located at the gaps of the first isolating substructures.

15. The display panel according to claim 13 or 14, wherein: The light emitting region of the third light emitting element is surrounded by four first spacer structures and two second spacer structures.

16. The display panel according to any one of claims 8 to 15, wherein: The common electrode is not disconnected at the isolation structure.

17. The display panel according to any one of claims 12 to 16, wherein: The first light emitting element is configured to emit green light, the second light emitting element is configured to emit red light, and the third light emitting element is configured to emit blue light.

18. The display panel according to any one of claims 1 to 17, wherein: The isolation structure does not contact the plurality of pixel electrodes.

19. The display panel according to any one of claims 1 to 18, wherein: The isolation structure includes a passivation layer, the passivation layer is configured to form the protrusion, the inorganic material includes an inorganic non-metallic material, and the inorganic material is an insulating material.

20. The display panel according to any one of claims 1 to 19, wherein: The inorganic material includes a metal material, and the isolation structure includes a first sublayer, a second sublayer, and a third sublayer that are stacked and arranged in sequence, the first sublayer is closer to the substrate than the third sublayer, and the third sublayer protrudes outward relative to the second sublayer to form the protrusion.

21. The display panel according to any one of claims 1 to 20, wherein: The multiple organic insulating layers include a first organic insulating layer, a second organic insulating layer, and a third organic insulating layer arranged in sequence, the first organic insulating layer is closer to the base substrate than the third organic insulating layer, and in a direction perpendicular to the base substrate, the isolation structure is located above at least a portion of the first organic insulating layer and below at least a portion of the third organic insulating layer.

22. The display panel according to claim 21, further comprising a first connection electrode and a second connection electrode, wherein: The pixel circuit includes a transistor, the first connecting electrode is located on the first organic insulating layer and is connected to the transistor through a via hole penetrating the first organic insulating layer, the second connecting electrode is located on the second organic insulating layer and is connected to the first connecting electrode through a via hole penetrating the second organic insulating layer, and the pixel electrode is located on the third organic insulating layer and is connected to the second connecting electrode through a via hole penetrating the third organic insulating layer.

23. The display panel according to claim 22, wherein: The insulating material layer further includes an inorganic insulating layer, the inorganic insulating layer is located between the transistor and the first organic insulating layer, and the first connecting electrode also passes through the inorganic insulating layer.

24. The display panel according to any one of claims 1 to 23, wherein: The display panel has a bending area.

25. The display panel according to any one of claims 1 to 24, wherein: The display panel has a hole area, and a plurality of isolation structures are arranged, and at least part of the plurality of isolation structures are located in a frame area close to the hole area.

26. A display device comprising the display panel according to any one of claims 1-25.

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