Array substrate and display device

Abstract

The application provides an array substrate and a display device. The array substrate comprises a driving module, the driving circuit comprises an input module, an output module and a noise reduction module, the input module transmits a first input signal to a first node under the control of an input signal, the output module transmits a second input signal to an output end of the driving circuit under the control of the potential of the first node, and the noise reduction module transmits a first voltage signal to the first node and / or the output end under the control of the potential of a second node; the driving circuit comprises a plurality of transistors; at least one transistor in the plurality of transistors is electrically connected to the first node through a first via, at least one transistor in the plurality of transistors is electrically connected to the second node through a second via; and at least one transistor is arranged between the first via and the second via. The application improves the reliability corrosion defect phenomenon of the narrow frame display product.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] In related technologies, with the development of LCD technology, narrow bezels have become the primary requirement for consumer display products. Narrow bezel display products reduce the amount of sealant covering internal wiring and vias, making them more susceptible to corrosion defects. Summary of the Invention

[0003] The main objective of this invention is to provide an array substrate and a display device that solves the problem of reliability corrosion that is common in existing narrow-bezel display products.

[0004] In one aspect, embodiments of the present invention provide an array substrate, including a substrate and a driving module disposed on the substrate. The driving module includes a multi-stage driving circuit. The driving circuit includes an input module, an output module, and a noise reduction module. The input module is electrically connected to a first node and is used to transmit a first input signal to the first node under the control of an input signal provided at an input signal terminal. The output module is used to transmit a second input signal to the output terminal of the driving circuit under the control of the potential of the first node. The noise reduction module is used to transmit a first voltage signal transmitted by a first voltage line to the first node and / or the output terminal under the control of the potential of the second node.

[0005] The driving circuit includes multiple transistors;

[0006] At least one of the plurality of transistors is electrically connected to the first node through a first via, and at least one of the plurality of transistors is electrically connected to the second node through a second via;

[0007] At least one transistor is spaced between the first via and the second via.

[0008] Optionally, the distance between the orthographic projection of the first via on the substrate and the orthographic projection of the second via on the substrate is greater than or equal to a first distance threshold.

[0009] The first distance threshold is greater than or equal to 100 μm.

[0010] Optionally, the first voltage line is disposed on the side of some transistors included in the driving circuit closer to the display area;

[0011] At least one of the plurality of transistors is electrically connected to the first voltage line via a third via.

[0012] Optionally, the noise reduction module includes a first transistor;

[0013] The first transistor is used to reset the potential of the first node under the control of the potential of the second node;

[0014] The first electrode of the first transistor is electrically connected to the first node through the first via.

[0015] Optionally, the driving circuit further includes a second transistor;

[0016] The second transistor is used to reset the potential of the first node under the control of the frame reset signal provided by the frame reset line;

[0017] The first electrode of the second transistor is electrically connected to the first node through the first via.

[0018] Optionally, the first via is disposed on the side of the first transistor closer to the display area.

[0019] Optionally, the driving circuit further includes a third transistor and a fourth transistor;

[0020] The third transistor is used to write the second voltage signal provided by the second voltage line into the second node under the control of the potential of the pull-down control node;

[0021] The fourth transistor is used to reset the potential of the second node under the control of the potential of the first node;

[0022] The second terminal of the third transistor and the first terminal of the fourth transistor are both electrically connected to the second node through the second via.

[0023] Optionally, the second via is disposed on the side of the fourth transistor away from the display area.

[0024] Optionally, the driving circuit includes a first transistor;

[0025] The fourth transistor is located on the side of the first transistor away from the display area.

[0026] Optionally, the output module includes a driving transistor for providing a driving signal through its output terminal under the control of the potential of the first node; the array substrate also includes a first voltage line.

[0027] The orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the second via on the substrate are arranged along a first direction;

[0028] The first direction is approximately the same as the extension direction of the first voltage line.

[0029] Optionally, the driving transistor and the third transistor are arranged along a first direction;

[0030] The driving transistor and the fourth transistor are arranged along a first direction;

[0031] Optionally, the driving circuit further includes a storage capacitor and a fifth transistor;

[0032] The fifth transistor is used to control the connection between the output terminal and the first voltage line under the control of the frame reset signal provided by the frame reset line; the fifth transistor is electrically connected to the first voltage line through the third via.

[0033] The storage capacitor has a notch on the side closest to the first voltage line, and the orthographic projection of the gate of the fifth transistor on the substrate at least partially overlaps with the orthographic projection of the notch on the substrate.

[0034] Optionally, the drive module includes N-stage drive circuits, the first voltage line includes N first voltage line sections, and the nth stage drive circuit corresponds to the nth first voltage line section; N is an integer greater than 1, and n is a positive integer less than or equal to N;

[0035] The fifth transistor in the nth stage drive circuit is electrically connected to the (n-1)th first voltage line.

[0036] Optionally, the storage capacitor is located adjacent to the first voltage line, and the fifth transistor is located adjacent to the first voltage line.

[0037] Optionally, the input module includes a sixth transistor; the gate of the sixth transistor is electrically connected to the input signal terminal, the first terminal of the sixth transistor is electrically connected to the first input signal terminal, and the second terminal of the sixth transistor is electrically connected to the first node;

[0038] The first voltage line is positioned between the storage capacitor and the sixth transistor.

[0039] Optionally, the output module includes a driving transistor;

[0040] The driving transistor is used to provide a driving signal through its output terminal under the control of the potential of the first node;

[0041] The storage capacitor is located on the side of the driving transistor closer to the display area.

[0042] Optionally, the array substrate further includes a first voltage line; the storage capacitor includes a first electrode and a second electrode.

[0043] The orthographic projection of the first plate of the storage capacitor onto the substrate at least partially overlaps with the orthographic projection of the second plate of the storage capacitor onto the substrate;

[0044] The orthographic projection of the first electrode plate of the storage capacitor on the substrate and the orthographic projection of the first via on the substrate are arranged along a first direction;

[0045] The first direction is approximately the same as the extension direction of the first voltage line.

[0046] Optionally, the driving circuit includes a first transistor and a second transistor;

[0047] The storage capacitor and the first transistor are arranged along a first direction;

[0048] The storage capacitor and the second transistor are arranged along a first direction.

[0049] In a second aspect, embodiments of the present invention provide a display device including the array substrate described above.

[0050] By setting the first via and the second via to be spaced apart by at least one transistor, this embodiment of the invention can avoid severe corrosion of the first via during the reliability process, thus improving the reliability corrosion problem that is prone to occur in narrow bezel display products. Attached Figure Description

[0051] Figure 1 This is a structural diagram of the relevant display panel;

[0052] Figure 2 This is a structural diagram of at least one embodiment of a pixel circuit;

[0053] Figure 3 This is a circuit diagram of at least one embodiment of the pixel circuit;

[0054] Figure 4 yes Figure 3 The layout diagram shows at least one embodiment of the driving circuit.

[0055] Figure 5 yes Figure 4 Layout diagram of the gate metal layer in the middle;

[0056] Figure 6 yes Figure 4 Layout diagram of the source and drain metal layers in the image;

[0057] Figure 7 yes Figure 4 Layout diagram of the ITO layer in the image;

[0058] Figure 8 yes Figure 4Layout diagram of the semiconductor layer in the diagram;

[0059] Figure 9 yes Figure 3 A schematic diagram showing the positional relationship between at least one embodiment of the driving circuit and the display area A0;

[0060] Figure 10 This is a layout diagram of at least one embodiment of a two-stage drive circuit. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal, and the other as the second terminal.

[0063] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0064] The array substrate described in this embodiment of the invention includes a substrate and a driving module disposed on the substrate. The driving module includes a multi-stage driving circuit. The driving circuit includes an input module, an output module, and a noise reduction module. The input module is electrically connected to a first node and is used to transmit a first input signal to the first node under the control of an input signal provided at an input signal terminal. The output module is used to transmit a second input signal to the output terminal of the driving circuit under the control of the potential of the first node. The noise reduction module is used to transmit a first voltage signal transmitted by a first voltage line to the first node and / or the output terminal under the control of the potential of the second node.

[0065] The driving circuit includes multiple transistors;

[0066] At least one of the plurality of transistors is electrically connected to the first node through a first via, and at least one of the plurality of transistors is electrically connected to the second node through a second via;

[0067] At least one transistor is spaced between the first via and the second via.

[0068] In this embodiment of the invention, the first via is a via between the first node and at least one transistor included in the driving circuit, and the second via is a via between the second node and at least one transistor included in the driving circuit. By setting the first via and the second via to be spaced apart by at least one transistor, the first via can be prevented from being severely corroded during the reliability process.

[0069] In related technologies, the first via and the second via are adjacent. During reliability testing, the first via often suffers severe corrosion. Increasing the device spacing without changing the layout offers only limited increase in distance between the first and second vias, while simultaneously increasing the bezel size, making it unsuitable for narrow-bezel display products. Therefore, in the array substrate described in this embodiment of the invention, by spacing the first and second vias by at least one transistor, a narrow bezel can be achieved while increasing the distance between them.

[0070] In related technologies, with the development of LCD technology, narrow bezels have become a primary requirement for consumer display products. Narrow bezel displays reduce the amount of sealant covering internal traces and vias, making them more susceptible to reliability corrosion. High temperature and high humidity operation testing is the most demanding environmental test and also the most prone to reliability issues. Under high temperature and high humidity conditions, such as… Figure 1 As shown, water vapor penetrates the display screen through the sealant and is absorbed by the PI (polyimide) layer, entering the ITO (indium tin oxide) layer and forming a solution at the PI interface. When the high-voltage and low-voltage signals are too close (i.e., when the high-voltage via and the low-voltage via are too close), an electrolytic cell reaction occurs between them. During this process, the low-voltage via is easily corroded. When a large amount of water is absorbed, water vapor enters the gap between the ITO layer and the source / drain metal layer, causing a galvanic cell reaction. At this time, the high-voltage via will also be corroded. Based on this, in the array substrate described in this embodiment of the invention, by spacing the first via and the second via with at least one transistor, the distance between the high-voltage and low-voltage vias is increased, avoiding the corrosion of the vias caused by the close proximity of the high-voltage and low-voltage vias.

[0071] exist Figure 1 In the diagram, 10 is the substrate, 11 is the gate metal layer, 12 is the gate insulating layer, 13 is the source / drain metal layer, 14 is the passivation layer, 15 is the ITO layer, 16 is the PI layer, 17 is the sealant, and 18 is the electrolyte (water vapor).

[0072] In at least one embodiment of the present invention, the specific value of the distance is related to PPI (pixel density). The larger the PPI, the greater the distance between the first via and the second via.

[0073] like Figure 2 As shown, the driving circuit may include an input module 21, an output module 22, and a noise reduction module 23;

[0074] The input module 21 is electrically connected to the first node PU, the input signal terminal I0 and the first input terminal I1 respectively, and is used to transmit the first input signal provided by the first input terminal I1 to the first node PU under the control of the input signal provided by the input signal terminal I0.

[0075] The output module 22 is electrically connected to the first node PU, the second input terminal I2 and the output terminal O1 of the driving circuit, respectively, and is used to transmit the second input signal provided by the second input terminal I2 to the output terminal O1 of the driving circuit under the control of the potential of the first node PU.

[0076] The noise reduction module 23 is electrically connected to the second node PD, the first voltage line VL1, the first node PU and the output terminal O1 respectively, and is used to transmit the first voltage signal transmitted by the first voltage line VL1 to the first node PU and / or the output terminal O1 under the control of the potential of the second node PD.

[0077] Optionally, the first input terminal I1 can be a first control voltage line VDS, the second input terminal I2 can be a clock signal line, and the first voltage line VL1 can be a low voltage line, but is not limited thereto.

[0078] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown,

[0079] The noise reduction module includes a first transistor M1, and the driving circuit further includes a second transistor M2, a third transistor M3, and a fourth transistor M4; the output module includes a driving transistor M0; the driving circuit further includes a storage capacitor C1 and a fifth transistor M5; the input module includes a sixth transistor M6; the driving circuit further includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10;

[0080] The gate of M1 is electrically connected to the second node PD, the first terminal of M1 is electrically connected to the first node PU, and the second terminal of M1 is electrically connected to the low voltage line VGL.

[0081] The gate of M2 is electrically connected to the frame reset line STV0, the first terminal of M2 is electrically connected to the first node PU, and the second terminal of M2 is electrically connected to the low voltage line VGL.

[0082] The gate of M3 is electrically connected to the pull-down control node PD_CN, the first terminal of M3 is electrically connected to the high voltage line GCH, and the second terminal of M3 is electrically connected to the second node PD.

[0083] The gate of M4 is electrically connected to the first node PU, the first terminal of M4 is electrically connected to the second node PD, and the second terminal of M4 is electrically connected to the low voltage line VGL.

[0084] The gate of M0 is electrically connected to the first node PU, the first terminal of M0 is electrically connected to the clock signal line CLK, and the second terminal of M0 is electrically connected to the output terminal O1.

[0085] The first electrode plate of C1 is electrically connected to the first node PU, and the second electrode plate of C1 is electrically connected to the output terminal O1.

[0086] The gate of M5 is electrically connected to the frame reset line STV0, the first terminal of M5 is electrically connected to the output terminal O1, and the second terminal of M5 is electrically connected to the low voltage line VGL.

[0087] The gate of M6 is electrically connected to the input signal terminal I0, the first terminal of M6 is electrically connected to the first control voltage line VDS, and the second terminal of M6 is electrically connected to the first node PU.

[0088] The gate and first terminal of M7 are electrically connected to the high voltage line GCH, and the second terminal of M7 is electrically connected to the pull-down control node PD_CN.

[0089] The gate of M8 is electrically connected to the first node PU, the first terminal of M8 is electrically connected to the pull-down control node PD_CN, and the second terminal of M8 is electrically connected to the low voltage line VGL.

[0090] The gate of M9 is electrically connected to the reset terminal R1, the first terminal of M9 is electrically connected to the first node PU, and the second terminal of M9 is electrically connected to the second control voltage line VSD.

[0091] The gate of M10 is electrically connected to the second node PD, the first terminal of M10 is electrically connected to the output terminal O1, and the second terminal of M10 is electrically connected to the low voltage line VGL.

[0092] exist Figure 3 In at least one embodiment shown, all transistors are n-type transistors, but this is not a limitation.

[0093] exist Figure 3 In at least one embodiment shown, when the driving circuit is in a forward scanning state, VDS provides a high voltage signal and VSD provides a low voltage signal; when the driving circuit is in a reverse scanning state, VDS provides a low voltage signal and VSD provides a high voltage signal.

[0094] In at least one embodiment of the present invention, the potential of the first node PU can be regarded as a low-voltage signal, the potential of the second node PD is controlled by the potential of the first node PU, and the potential of the second node PD can be regarded as a high-voltage signal. The first via can be a low-voltage via, and the second via can be a high-voltage via. The potential of the first node PU is high between the output signal and the reset signal of this stage, and low at other times. The potential of the first node PU can be regarded as a low-voltage signal. The potential of the second node PD is controlled by the PU voltage. When the potential of the first node PU is low, the potential of the second node PD is high. The potential of the second node PD can be regarded as a high-voltage signal.

[0095] In at least one embodiment of the present invention, the distance between the orthographic projection of the first via on the substrate and the orthographic projection of the second via on the substrate is greater than or equal to a first distance threshold.

[0096] The first distance threshold is greater than or equal to 100 μm.

[0097] In a specific implementation, the distance between the orthographic projection of the first via on the substrate and the orthographic projection of the second via on the substrate can be greater than or equal to 100 μm. For example, the distance between the orthographic projection of the first via on the substrate and the orthographic projection of the second via on the substrate can be set to be greater than or equal to 150 μm, but is not limited thereto.

[0098] In at least one embodiment of the present invention, the first distance threshold may be greater than or equal to 100 μm and less than or equal to 200 μm. For example, the first distance threshold may be 110 μm, 120 μm, 130 μm, 150 μm, 160 μm, 180 μm, 190 μm or 200 μm, but is not limited thereto.

[0099] In practical implementation, the first via can be the outermost low-pressure via. Compared with related technical solutions, the low-pressure via can be moved inward by 230μm.

[0100] In at least one embodiment of the present invention, the first voltage line is disposed on the side of a portion of the transistors included in the driving circuit near the display area;

[0101] At least one of the plurality of transistors is electrically connected to the first voltage line via a third via.

[0102] In related technologies, the first voltage line can be a low-voltage line, which is located on the side of the driving circuit away from the display area. The low-voltage line is close to the edge of the sealant, and the connection via between the transistor in the driving circuit and the low-voltage line is also close to the edge of the sealant, making it easy for moisture to enter the connection via. Therefore, at least one embodiment of the present invention places the first voltage line on the side of some transistors in the driving circuit closer to the display area, increasing the distance between the third via and the edge of the sealant to prevent moisture from entering the third via.

[0103] In at least one embodiment of the present invention, by setting the first voltage line on the side of the partial transistors included in the driving circuit closer to the display area, the third via can be moved to the inside, and the first via becomes the outermost low-voltage via. Compared with related schemes, the low-voltage via is moved inward by 230μm.

[0104] Optionally, the noise reduction module includes a first transistor;

[0105] The first transistor is used to reset the potential of the first node under the control of the potential of the second node;

[0106] The first electrode of the first transistor is electrically connected to the first node through the first via.

[0107] Figure 4 yes Figure 3 The layout diagram of at least one embodiment of the driving circuit shown is provided. Figure 5 yes Figure 4 Layout diagram of the gate metal layer in the middle. Figure 6 yes Figure 4 Layout diagram of the source and drain metal layers in the middle. Figure 7 yes Figure 4 Layout diagram of the ITO layer in the middle. Figure 8 yes Figure 4 The layout diagram of the semiconductor layer.

[0108] In at least one embodiment of the present invention, the gate metal layer, semiconductor layer, source / drain metal layer and ITO layer may be arranged sequentially along a direction away from the substrate, but are not limited thereto.

[0109] exist Figure 9 In the diagram, area A0 is the display area. For example... Figure 9 As shown, the display area A0 is located on the right side of the drive circuit.

[0110] Figure 10 This is a layout diagram of at least one embodiment of a two-stage drive circuit.

[0111] In at least one embodiment of the present invention, the gate of the first transistor is electrically connected to the second node, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the low voltage line.

[0112] like Figures 4-9 As shown, the first electrode S1 of the first transistor M1 is electrically connected to the first node through the first via H1, and the first node is electrically connected to the first plate C1a of the storage capacitor C1.

[0113] like Figures 4-9 As shown, the first via H1 includes a first connection portion H11 formed on the gate metal layer, a second connection portion H12 formed on the source / drain metal layer, and a third connection portion H13 formed on the ITO layer; optionally, the ITO layer can be the same layer and material as the pixel electrode layer of the display area or the same layer and material as the common electrode of the display area; through the first via H1, the third connection portion H13 formed on the ITO layer realizes the electrical connection between the connection pattern formed on the gate metal layer and the connection pattern formed on the source / drain metal layer.

[0114] In at least one embodiment of the present invention, the driving circuit further includes a second transistor;

[0115] The second transistor is used to reset the potential of the first node under the control of the frame reset signal provided by the frame reset line;

[0116] The first electrode of the second transistor is electrically connected to the first node through the first via.

[0117] In a specific implementation, the driving circuit may further include a second transistor, the first electrode of which is electrically connected to the first node through a first via.

[0118] like Figures 4-9 As shown, the first electrode S2 of the second transistor is electrically connected to the first node through the first via H1, and the first node is electrically connected to the first plate of the storage capacitor C1.

[0119] like Figures 4-9 As shown, the first electrode S1 of the first transistor is electrically connected to the first electrode S2 of the second transistor. The first transistor M1 and the second transistor M2 are arranged adjacent to each other. The first electrode S1 of the first transistor M1 and the first electrode S2 of the second transistor M2 are electrically connected to the first node through the same via. Compared with related technologies, one via is reduced, and the overall width of the driving circuit is reduced by about 30μm.

[0120] In at least one embodiment of the present invention, the first via is disposed on the side of the first transistor near the display area.

[0121] like Figure 4 and Figure 9 As shown, the first via H1 is disposed on the side of the first transistor M1 near the display area A0, the display area A0 is disposed on the right side of the driving circuit, and the edge of the sealing adhesive is disposed on the left side of the driving circuit.

[0122] Optionally, the driving circuit further includes a third transistor and a fourth transistor;

[0123] The third transistor is used to write the second voltage signal provided by the second voltage line into the second node under the control of the potential of the pull-down control node;

[0124] The fourth transistor is used to reset the potential of the second node under the control of the potential of the first node;

[0125] The second terminal of the third transistor and the first terminal of the fourth transistor are both electrically connected to the second node through the second via.

[0126] like Figures 4-9 As shown, the second terminal D3 of the third transistor M3 is electrically connected to the second node through the second via H2, and the first terminal S4 of the fourth transistor M4 is electrically connected to the second node through the second via H2.

[0127] like Figures 4-9 As shown, the second via H2 includes a fourth connection portion H21 formed on the gate metal layer, a fifth connection portion H22 formed on the source / drain metal layer, and a sixth connection portion H23 formed on the ITO layer; through the second via H2, the sixth connection portion H23 formed on the ITO layer enables an electrical connection between the connection pattern formed on the gate metal layer and the connection pattern formed on the source / drain metal layer.

[0128] like Figures 4-9 As shown, the second via H2 is the outermost via, and the outermost via is moved inward by 32μm.

[0129] In at least one embodiment of the present invention, the second via is disposed on the side of the fourth transistor away from the display area.

[0130] exist Figures 4-9 In the diagram, CLK1 is the first clock signal line, CLK2 is the second clock signal line, CLK3 is the third clock signal line, and CLK4 is the fourth clock signal line. It should be noted that the specific number of clock signal lines is not limited.

[0131] The second via H2 is located between each clock signal line and the fourth transistor M4.

[0132] like Figure 4 and Figure 9As shown, the second via H2 is disposed on the side of the fourth transistor M4 away from the display area A0.

[0133] like Figure 4 As shown, there are three transistors between the second via H2 and the first via H1.

[0134] Optionally, the driving circuit includes a first transistor;

[0135] The fourth transistor is located on the side of the first transistor away from the display area.

[0136] like Figures 4-9 As shown, the driving circuit includes a first transistor M1;

[0137] The fourth transistor M4 is disposed on the side of the first transistor M1 away from the display area A0. In this embodiment, the extension directions of the source and drain of the fourth transistor M4 are different from those of the first transistor M1. Optionally, their extension directions intersect, or alternatively, they are perpendicular. The extension direction of the source and drain of the fourth transistor M4 is in the row direction, and the extension direction of the source and drain of the first transistor M1 is in the column direction. The purpose of this arrangement is to further utilize the non-display area and further reduce the narrow bezel by rationally arranging the transistors. Optionally, the GOA circuit may include multiple transistors with different extension directions, see reference. Figure 4 For example, transistors with source and drain extending in the row direction include M0, M7, M8, M3, and M4, while the source and drain of other transistors extend in the row direction.

[0138] In at least one embodiment of the present invention, the output module includes a driving transistor; the driving transistor is used to provide a driving signal through an output terminal under the control of the potential of the first node; the array substrate further includes a first voltage line;

[0139] The orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the second via on the substrate are arranged along a first direction;

[0140] The first direction is approximately the same as the extension direction of the first voltage line.

[0141] Optionally, the first voltage line can be a low voltage line, and the first direction can be a vertical direction.

[0142] like Figures 4-9 As shown, the output module includes a driving transistor M0; the array substrate also includes a low-voltage line VGL;

[0143] The orthographic projection of the gate G0 of the driving transistor M0 on the substrate and the orthographic projection of the second via H2 on the substrate are arranged in a vertical direction. The space below the gate of the driving transistor M0 can be used to set the second via H2, which is beneficial to achieve a narrow bezel.

[0144] Optionally, the driving transistor and the third transistor are arranged along a first direction;

[0145] The driving transistor and the fourth transistor are arranged along a first direction;

[0146] like Figures 4-9 As shown, the driving transistor M0 and the third transistor M3 are arranged vertically, and the driving transistor M0 and the fourth transistor M4 are arranged vertically.

[0147] In at least one embodiment of the present invention, M3 and M4 are positioned below M0, which facilitates the achievement of a narrow bezel.

[0148] In at least one embodiment of the present invention, the driving circuit further includes a storage capacitor and a fifth transistor;

[0149] The fifth transistor is used to control the connection between the output terminal and the first voltage line under the control of the frame reset signal provided by the frame reset line; the fifth transistor is electrically connected to the first voltage line through the third via.

[0150] The storage capacitor has a notch on the side closest to the first voltage line, and the orthographic projection of the gate of the fifth transistor on the substrate at least partially overlaps with the orthographic projection of the notch on the substrate.

[0151] like Figures 4-10 As shown, the driving circuit also includes a storage capacitor C1 and a fifth transistor M5;

[0152] The fifth transistor M5 is electrically connected to the low voltage line VGL through the third via H3.

[0153] The storage capacitor C1 has a notch on the side near the low voltage line VGL;

[0154] The orthographic projection of the gate G5 of the fifth transistor M5 on the substrate at least partially overlaps with the orthographic projection of the notch on the substrate, so as to set the fifth transistor M5 in the notch of the storage capacitor C1 and to place the fifth transistor M5 between the storage capacitor C1 and the low voltage line VGL, so as to facilitate the fifth transistor M5 between the third via H3 and the low voltage line VGL.

[0155] like Figures 4-10As shown, the third via H3 includes a seventh connection portion H31 formed on the gate metal layer, an eighth connection portion H32 formed on the source / drain metal layer, and a ninth connection portion H33 formed on the ITO layer; through the third via H3, the ninth connection portion H33 formed on the ITO layer enables an electrical connection between the connection pattern formed on the gate metal layer and the connection pattern formed on the source / drain metal layer.

[0156] In at least one embodiment of the present invention, the driving module includes N-stage driving circuits, the first voltage line includes N first voltage line portions, and the nth-stage driving circuit corresponds to the nth first voltage line portion; N is an integer greater than 1, and n is a positive integer less than or equal to N;

[0157] The fifth transistor in the nth stage drive circuit is electrically connected to the (n-1)th first voltage line.

[0158] exist Figure 10 In the diagram, the circuit labeled GAn-1 is the (n-1)th stage drive circuit, and the circuit labeled GAn is the nth stage drive circuit.

[0159] The part labeled VGLn-1 is the (n-1)th low voltage line section. The (n-1)th low voltage line section VGLn-1 corresponds to the low voltage line section of the (n-1)th stage drive circuit GAn-1. The part labeled VGLn is the nth low voltage line section. The nth low voltage line section VGLn corresponds to the low voltage line section of the nth stage drive circuit GAn.

[0160] The fifth transistor M5 in the nth stage drive circuit is electrically connected to the (n-1)th low-voltage line VGLn through the third via H3.

[0161] Optionally, the storage capacitor is located adjacent to the first voltage line, and the fifth transistor is located adjacent to the first voltage line.

[0162] like Figures 4-9 As shown, the storage capacitor C1 is adjacent to the low voltage line VGL, and the fifth transistor M5 is adjacent to the low voltage line VGL to facilitate electrical connection between M5 and VGL. This wiring design can further reduce the bezel size.

[0163] In at least one embodiment of the present invention, the input module includes a sixth transistor; the gate of the sixth transistor is electrically connected to the input signal terminal, the first terminal of the sixth transistor is electrically connected to the first input signal terminal, and the second terminal of the sixth transistor is electrically connected to the first node;

[0164] The first voltage line is positioned between the storage capacitor and the sixth transistor.

[0165] like Figures 4-9 As shown, the input module includes a sixth transistor M6;

[0166] The low-voltage line VGL is positioned between the storage capacitor C1 and the sixth transistor M6.

[0167] Optionally, the output module includes a driving transistor;

[0168] The driving transistor is used to provide a driving signal through its output terminal under the control of the potential of the first node;

[0169] The storage capacitor is located on the side of the driving transistor closer to the display area.

[0170] like Figures 4-9 As shown, the output module includes a driving transistor M0;

[0171] The storage capacitor C1 is disposed on the side of the driving transistor M0 near the display area A0;

[0172] The storage capacitor C1 and the driving transistor M0 can be arranged in a horizontal direction.

[0173] In at least one embodiment of the present invention, the array substrate further includes a first voltage line; the storage capacitor includes a first electrode and a second electrode.

[0174] The orthographic projection of the first plate of the storage capacitor onto the substrate at least partially overlaps with the orthographic projection of the second plate of the storage capacitor onto the substrate;

[0175] The orthographic projection of the first electrode plate of the storage capacitor on the substrate and the orthographic projection of the first via on the substrate are arranged along a first direction;

[0176] The first direction is approximately the same as the extension direction of the first voltage line.

[0177] like Figures 4-9 As shown, the array substrate also includes a low-voltage line VGL; the storage capacitor C1 includes a first plate C1a and a second plate C1b.

[0178] The orthographic projection of the first plate C1a of the storage capacitor C1 onto the substrate at least partially overlaps with the orthographic projection of the second plate C1b of the storage capacitor C1 onto the substrate;

[0179] The orthographic projection of the first plate C1a of the storage capacitor C1 onto the substrate and the orthographic projection of the first via H1 onto the substrate are arranged vertically, so that the first via H1 is set through the space below the storage capacitor C1, which is beneficial to achieve a narrow bezel.

[0180] Optionally, the driving circuit includes a first transistor and a second transistor;

[0181] The storage capacitor and the first transistor are arranged along a first direction;

[0182] The storage capacitor and the second transistor are arranged along a first direction.

[0183] like Figures 4-9 As shown, the storage capacitor C1 and the first transistor M1 are arranged vertically, and the storage capacitor C1 and the second transistor M2 are also arranged vertically, so that the space below the storage capacitor C1 can be used to set up the first transistor M1 and the second transistor M2, which is beneficial to achieve a narrow bezel.

[0184] exist Figure 8 In the diagram, the active graphic labeled A0 is M0, the active graphic labeled A1 is M1, the active graphic labeled A2 is M2, the active graphic labeled A3 is M3, the active graphic labeled A4 is M4, the active graphic labeled A5 is M5, the active graphic labeled A6 is M6, the active graphic labeled A7 is M7, the active graphic labeled A8 is M8, the active graphic labeled A9 is M9, and the active graphic labeled A10 is M10.

[0185] exist Figure 4 and Figure 5 middle,

[0186] The line labeled GCH is the high voltage line, the line labeled VDS is the first control voltage line, and the line labeled VSD is the second control voltage line; the line labeled CLK1 is the first clock signal line, the line labeled CLK2 is the second clock signal line, the line labeled CLK3 is the third clock signal line, and the line labeled CLK4 is the fourth clock signal line.

[0187] The line labeled STV0 is the frame reset line, the line labeled VGL is the low voltage line, the line labeled VCOM1 is the first common electrode voltage line, the line labeled VCOM2 is the second common electrode voltage line, the line labeled GND is the ground line, the line labeled STV1 is the first start voltage line, and the line labeled STV2 is the second start voltage line.

[0188] The display device described in this embodiment of the invention includes the array substrate described above.

[0189] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that, The system includes a substrate and a driving module disposed on the substrate. The driving module includes a multi-stage driving circuit. The driving circuit includes an input module, an output module, and a noise reduction module. The input module is electrically connected to a first node and is used to transmit a first input signal to the first node under the control of an input signal provided at an input signal terminal. The output module is used to transmit a second input signal to the output terminal of the driving circuit under the control of the potential of the first node. The noise reduction module is used to transmit a first voltage signal transmitted by a first voltage line to the first node and / or the output terminal under the control of the potential of the second node. The driving circuit includes multiple transistors; At least one of the plurality of transistors is electrically connected to the first node through a first via, and at least one of the plurality of transistors is electrically connected to the second node through a second via; At least one transistor is spaced between the first via and the second via; The noise reduction module includes a first transistor; The first transistor is used to reset the potential of the first node under the control of the potential of the second node; The first electrode of the first transistor is electrically connected to the first node through the first via.

2. The array substrate as described in claim 1, characterized in that, The distance between the orthographic projection of the first via on the substrate and the orthographic projection of the second via on the substrate is greater than or equal to a first distance threshold. The first distance threshold is greater than or equal to 100 μm.

3. The array substrate as described in claim 1, characterized in that, The first voltage line is disposed on the side of some transistors in the driving circuit closer to the display area; At least one of the plurality of transistors is electrically connected to the first voltage line via a third via.

4. The array substrate as described in claim 1, characterized in that, The driving circuit also includes a second transistor; The second transistor is used to reset the potential of the first node under the control of the frame reset signal provided by the frame reset line; The first electrode of the second transistor is electrically connected to the first node through the first via.

5. The array substrate as described in claim 1, characterized in that, The first via is disposed on the side of the first transistor closer to the display area.

6. The array substrate according to any one of claims 1 to 5, characterized in that, The driving circuit also includes a third transistor and a fourth transistor; The third transistor is used to write the second voltage signal provided by the second voltage line into the second node under the control of the potential of the pull-down control node; The fourth transistor is used to reset the potential of the second node under the control of the potential of the first node; The second terminal of the third transistor and the first terminal of the fourth transistor are both electrically connected to the second node through the second via.

7. The array substrate as described in claim 6, characterized in that, The second via is located on the side of the fourth transistor away from the display area.

8. The array substrate as claimed in claim 7, characterized in that, The driving circuit includes a first transistor; The fourth transistor is located on the side of the first transistor away from the display area.

9. The array substrate as described in claim 6, characterized in that, The output module includes a driving transistor that provides a driving signal through its output terminal under the control of the potential of the first node; the array substrate also includes a first voltage line. The orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the second via on the substrate are arranged along a first direction; The first direction is approximately the same as the extension direction of the first voltage line.

10. The array substrate as claimed in claim 9, characterized in that, The driving transistor and the third transistor are arranged along a first direction; The driving transistor and the fourth transistor are arranged along a first direction.

11. The array substrate as claimed in claim 3, characterized in that, The driving circuit also includes a storage capacitor and a fifth transistor; The fifth transistor is used to control the connection between the output terminal and the first voltage line under the control of the frame reset signal provided by the frame reset line; the fifth transistor is electrically connected to the first voltage line through the third via. The storage capacitor has a notch on the side closest to the first voltage line, and the orthographic projection of the gate of the fifth transistor on the substrate at least partially overlaps with the orthographic projection of the notch on the substrate.

12. The array substrate as claimed in claim 11, characterized in that, The drive module includes N levels of drive circuits, and the first voltage line includes N first voltage line sections, with the nth drive circuit corresponding to the nth first voltage line section; N is an integer greater than 1, and n is a positive integer less than or equal to N; The fifth transistor in the nth stage drive circuit is electrically connected to the (n-1)th first voltage line.

13. The array substrate as claimed in claim 11, characterized in that, The storage capacitor is adjacent to the first voltage line, and the fifth transistor is adjacent to the first voltage line.

14. The array substrate as claimed in claim 11, characterized in that, The input module includes a sixth transistor; the gate of the sixth transistor is electrically connected to the input signal terminal, the first terminal of the sixth transistor is electrically connected to the first input signal terminal, and the second terminal of the sixth transistor is electrically connected to the first node; The first voltage line is positioned between the storage capacitor and the sixth transistor.

15. The array substrate as claimed in claim 11, characterized in that, The output module includes a driving transistor; The driving transistor is used to provide a driving signal through its output terminal under the control of the potential of the first node; The storage capacitor is located on the side of the driving transistor closer to the display area.

16. The array substrate as claimed in claim 15, characterized in that, The array substrate further includes a first voltage line; the storage capacitor includes a first electrode and a second electrode. The orthographic projection of the first plate of the storage capacitor onto the substrate at least partially overlaps with the orthographic projection of the second plate of the storage capacitor onto the substrate; The orthographic projection of the first electrode plate of the storage capacitor on the substrate and the orthographic projection of the first via on the substrate are arranged along a first direction; The first direction is approximately the same as the extension direction of the first voltage line.

17. The array substrate as claimed in claim 16, characterized in that, The driving circuit includes a first transistor and a second transistor; The storage capacitor and the first transistor are arranged along a first direction; The storage capacitor and the second transistor are arranged along a first direction.

18. A display device, characterized in that, Includes the array substrate as described in any one of claims 1 to 17.

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