A constant transconductance input stage circuit for an operational amplifier

Abstract

The application belongs to the technical field of integrated circuits, and discloses a constant transconductance input stage circuit for an operational amplifier, comprising a segmented tail current compensation circuit and complementary NMOS differential input pair and PMOS differential input pair; wherein the segmented tail current compensation circuit comprises two parts of an NMOS tail current compensation circuit and a PMOS tail current compensation circuit; wherein the NMOS tail current compensation circuit is used for providing different compensation currents when the PMOS differential input pair is in a sub-threshold region and an off region, and the PMOS tail current compensation circuit is used for providing different compensation currents when the NMOS differential input pair is in the sub-threshold region and the off region. The application adopts a segmented tail current compensation mode to provide different compensation currents when the input pair tube works in the sub-threshold region and the off region, so that the transconductances in the sub-threshold region and the off region can be effectively and properly compensated, the problem of poor transconductance stability in the sub-threshold region of the triple current mirror method is overcome, and better transconductance stability can be realized in the full input range.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a constant transconductance input stage circuit for an operational amplifier. Background Technology

[0002] In single-ended to differential applications, fully differential operational amplifiers need to have constant transconductance over a wide input range to meet linearity requirements in wide input scenarios.

[0003] Currently, existing traditional rail-to-rail input stage structures without constant transconductance, such as Figure 1 As shown, it mainly consists of two complementary NMOS (N-channel metal oxide semiconductor FET) and PMOS (P-channel metal oxide semiconductor FET) differential pairs; specifically, when the input common-mode voltage V CM Located at power supply voltage V DD When the voltage is around / 2, both differential pairs operate simultaneously, and the input transconductance is the sum of the transconductances of the NMOS and PMOS input transistors; when the input common-mode voltage V CM When near power or ground, only one type of differential pair operates, and only one type of input transistor provides transconductance; the input transconductance variation curve is shown below. Figure 2 As shown, the total input transconductance exhibits an intermediate V0. DD The transconductance near / 2 is twice that near the power supply or ground on both sides, and the input transconductance varies greatly across the entire input range.

[0004] To ensure that the input transconductance remains constant across the entire input range, the traditional triple current mirror method constant transconductance input stage structure, such as... Figure 3 As shown; where M7 and M8 are compensation current control transistors, V s1 and V s2 To control the voltage, M9~M 12 To compensate for the current mirror; when the input common-mode voltage V CM When close to the power supply or ground, the input transconductance is increased to twice its original value through the effect of the triple compensation current mirror, so as to achieve constant input transconductance in the entire input common mode range; Figure 4 The input transconductance variation curve obtained using the triple current mirror method is shown. Figure 4 As can be seen, the transconductance varies significantly within the subthreshold region; within the subthreshold region, both tail current sources M5 and M6 are in the linear region. Taking M6 as an example, the current I... p for:

[0005]

[0006] In the formula, K p =μ p C ox W p / L p μ p C represents hole mobility. ox For gate oxide capacitor, W p L p V represents the width and length of the PMOS conductive channel. GS6 and V DS6 These are the gate-source voltage and drain-source voltage of PMOS transistor M6, respectively. THP This is the threshold voltage of the PMOS transistor;

[0007] As can be seen from the above formula, I p It is a drain-source voltage V of M6 DS6 It is a quadratic function of the variable;

[0008] The current I of the current control transistor M8 s1 for:

[0009]

[0010] In the formula, V GS8 and V s1 These are the gate-source voltage and control voltage of PMOS transistor M8, respectively.

[0011] From the above formula, it can be seen that I s1 Also a V DS6 It is a quadratic function of the variable I, but the polarity of the coefficients of the function is the same as that of I. p on the contrary;

[0012] When the PMOS input pair is operating in the subthreshold region, the total transconductance of the input stage is:

[0013]

[0014] In the formula, I n V is the total current flowing through input transistors M1 and M2. dsatn Its saturation drain-source voltage; ζ>1, is a non-ideal factor; thermal voltage V T = kT / q, where k is Boltzmann's constant, q is the electron charge, and T represents the absolute temperature.

[0015] In summary, the total transconductance in the subthreshold region consists of the NMOS saturation region transconductance, the compensation transconductance, and the PMOS subthreshold region transconductance. The saturation region transconductance remains constant, while the compensation transconductance and subthreshold transconductance are respectively composed of I0... s1 and I pThe two factors determine each other and their trends are opposite; however, the triple current mirror method, in order to compensate for the total transconductance in the cutoff region, ensures that the current I in the subthreshold region... s1 Excessive changes lead to excessive changes in the compensated transconductance, resulting in overcompensation of the total transconductance in the subthreshold region. Summary of the Invention

[0016] The purpose of this invention is to provide a constant transconductance input stage circuit for operational amplifiers to solve one or more of the aforementioned technical problems. The technical solution provided by this invention employs a segmented tail current compensation method, providing different compensation currents in the subthreshold and cutoff regions of the input pair, thus effectively and appropriately compensating for the transconductance in both the subthreshold and cutoff regions. This invention overcomes the technical problem of poor transconductance stability in the subthreshold region of existing triple current mirror methods, achieving better transconductance stability across the entire input range.

[0017] To achieve the above objectives, the present invention adopts the following technical solution:

[0018] This invention provides a constant transconductance input stage circuit for an operational amplifier, comprising: a segmented tail current compensation circuit and complementary NMOS differential input pairs and PMOS differential input pairs; wherein,

[0019] The segmented tail current compensation circuit includes two parts: an NMOS tail current compensation circuit and a PMOS tail current compensation circuit. The NMOS tail current compensation circuit provides different compensation currents when the PMOS differential input pair is in the subthreshold region and the cutoff region, and the PMOS tail current compensation circuit provides different compensation currents when the NMOS differential input pair is in the subthreshold region and the cutoff region.

[0020] A further improvement of the present invention is that,

[0021] The NMOS differential input pair includes: NMOS transistor M1 and NMOS transistor M2;

[0022] The PMOS differential input pair includes: PMOS transistor M3 and PMOS transistor M4;

[0023] The NMOS tail current compensation circuit includes: NMOS transistor M5, NMOS transistor M... 11 NMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14 PMOS transistor M8 and PMOS transistor M 10 ;

[0024] The PMOS tail current compensation circuit includes: PMOS transistor M6 and PMOS transistor M. 15 PMOS transistor M16 PMOS transistor M 17 PMOS transistor M 18 NMOS transistors M7 and M9;

[0025] in,

[0026] PMOS transistor M6, PMOS transistor M 15 PMOS transistor M 16 PMOS transistor M 17 PMOS transistor M 18 The source is connected to the power supply, NMOS transistor M5, NMOS transistor M 11 NMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14 The source is grounded;

[0027] PMOS transistor M 18 The gate, drain and PMOS transistor M 17 The gates of the PMOS transistor M are connected to form a current mirror. 16 The gate, drain and PMOS transistor M 15 The gates of the PMOS transistor are connected to form a current mirror; 18 The drain of the PMOS transistor is connected to the drain of the NMOS transistor M9. 16 The drain of the transistor is connected to the drain of NMOS transistor M7, and the gate of NMOS transistor M7 is connected to the bias voltage V. s2 The gate of NMOS transistor M9 is connected to a bias voltage V. s4 The gate of PMOS transistor M6 is connected to a bias voltage V. b2 ;

[0028] PMOS transistor M6, PMOS transistor M 15 PMOS transistor M 17 The drain of PMOS transistors M3, M4, M8, and M1 is connected. 10 The source of the NMOS transistor M1 and the gate of the PMOS transistor M3 are connected to the positive input V. in The gates of NMOS transistor M2 and PMOS transistor M4 are connected to the negative input V. ip The drains of NMOS transistors M1, M2, M3, and M4 are output nodes.

[0029] The sources of NMOS transistors M1, M2, M7, and M9 are connected to NMOS transistors M5 and M6. 11 NMOS transistor M 13 The drain of the NMOS transistor M5 is connected to the gate of the NMOS transistor with a bias voltage V. b1The gate of PMOS transistor M8 is connected to a bias voltage V. s1 PMOS transistor M 10 Gate bias voltage V s3 The drain of PMOS transistor M8 is connected to NMOS transistor M. 12 The drain of the PMOS transistor M 10 The drain of the NMOS transistor M 14 The drain of the NMOS transistor M 12 The gate, drain and NMOS transistor M 11 The gates of the NMOS transistors are connected to form a current mirror. 14 The gate, drain and NMOS transistor M 13 The gates are connected to form a current mirror.

[0030] A further improvement of the present invention is that,

[0031] NMOS transistor M 11 The current of NMOS transistor M 12 k1 times, NMOS transistor M 13 The current of NMOS transistor M 14 k3 times;

[0032] Among them, through NMOS transistor M 11 Copy k1 times NMOS transistor M 12 The current provides compensation current for PMOS transistors M3 and M4 to operate in the subthreshold region; through NMOS transistor M... 13 Copy k3 times NMOS transistor M 14 The current provides compensation current for PMOS transistors M3 and M4 to operate in the cutoff region.

[0033] A further improvement of the present invention is that,

[0034] PMOS transistor M 15 The current of PMOS transistor M 16 k2 times, PMOS transistor M 17 The current of PMOS transistor M 18 4 times that of k;

[0035] Among them, through PMOS transistor M 15 Copy k2 times PMOS transistor M 16 The current provides compensation current for NMOS transistors M1 and M2 to operate in the subthreshold region; through PMOS transistor M... 17 Copy k4 times PMOS transistor M 18 The current provides compensation current for NMOS transistors M1 and M2 to operate in the cutoff region.

[0036] A further improvement of the present invention is that,

[0037] NMOS transistor M 11 The width of the NMOS transistor M 12 k1 times, NMOS transistor M 13 The width of the NMOS transistor M 14 k3 times, NMOS transistor, M5, NMOS transistor M 11 NMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14 They are the same length.

[0038] A further improvement of the present invention is that,

[0039] PMOS transistor M 15 The width of the PMOS transistor M 16 k2 times, PMOS transistor M 17 The width of the PMOS transistor M 18 k4 times, PMOS transistor M6, PMOS transistor M 15 PMOS transistor M 16 PMOS transistor M 17 PMOS transistor M 18 They are the same length.

[0040] A further improvement of the present invention is that,

[0041] Dimensions and bias voltage V of PMOS transistor M8 s1 It enables PMOS transistor M8 to conduct when the PMOS differential input pair is in the subthreshold region.

[0042] A further improvement of the present invention is that,

[0043] PMOS transistor M 10 Size and bias voltage V s3 Enables PMOS transistor M to operate in the cutoff region when the PMOS differential input pair is in the cutoff region. 10 Conduction.

[0044] A further improvement of the present invention is that,

[0045] The dimensions and bias voltage V of NMOS transistor M7 s2 It enables NMOS transistor M7 to conduct when the NMOS differential input pair is in the subthreshold region.

[0046] A further improvement of the present invention is that,

[0047] Dimensions and bias voltage V of NMOS transistor M9 s4 It enables NMOS transistor M9 to conduct when the NMOS differential input pair is in the cutoff region.

[0048] Compared with the prior art, the present invention has the following beneficial effects:

[0049] To address the poor transconductance stability of existing triple current mirror methods in the subthreshold region, this invention discloses a constant transconductance input stage circuit for operational amplifiers. This circuit employs a segmented tail current compensation method, providing different compensation currents in the subthreshold and cutoff regions of the input transistor pair. When the input transistor pair operates in the subthreshold region, the transconductance generated by the compensation current varies with the drain-source voltage of the tail current source transistor, and its trend is opposite to that of the input transconductance in the subthreshold region, thus achieving effective compensation. In the cutoff region, since the tail current source current is constant, the compensation transconductance remains unchanged, and its value is equal to the decrease in input transconductance from the saturation region to the cutoff region, thus achieving effective compensation. In summary, the improved technical solution of this invention can provide adaptive compensation transconductance when the input transistor pair operates in different regions, ensuring effective and appropriate compensation of transconductance in both the subthreshold and cutoff regions, thereby achieving better transconductance stability across the entire input range. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of an input stage structure without constant transconductance in the prior art;

[0052] Figure 2 This is a schematic diagram of the input transconductance variation curve without a constant transconductance structure in the existing technology;

[0053] Figure 3 This is a schematic diagram of a constant transconductance input stage structure using the triple current mirror method in the prior art;

[0054] Figure 4 This is a schematic diagram of the input transconductance variation curve using the triple current mirror method in the existing technology;

[0055] Figure 5 This is a schematic diagram of a constant transconductance input stage circuit for an operational amplifier in an embodiment of the present invention;

[0056] Figure 6 This is a schematic diagram of the input transconductance variation curve for segmented tail current compensation in an embodiment of the present invention;

[0057] Figure 7 This is a schematic diagram comparing the simulation results of the circuit disclosed in the embodiments of the present invention with those of the prior art with no constant transconductance structure and a triple current mirror. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention; obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0059] Based on the technical solutions disclosed in the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this invention. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0060] Please see Figure 5 This invention discloses a constant transconductance input stage circuit for an operational amplifier, specifically a segmented tail current compensation constant transconductance input stage structure, comprising: complementary NMOS differential input pairs (NMOS transistors M1 and M2) and PMOS differential input pairs (PMOS transistors M3 and M4), and a segmented tail current compensation circuit; wherein,

[0061] The segmented tail current compensation circuit includes two parts: an NMOS tail current compensation circuit and a PMOS tail current compensation circuit. The NMOS tail current compensation circuit provides different compensation currents when the PMOS differential input pair is in the subthreshold region and the cutoff region, and the PMOS tail current compensation circuit provides different compensation currents when the NMOS differential input pair is in the subthreshold region and the cutoff region.

[0062] Explained, in the technical solution of the embodiments of the present invention, the NMOS differential input pair (M1, M2) and the PMOS differential input pair (M3, M4) serve as basic complementary differential input pair circuits for receiving input signals; based on the segmented tail current compensation circuit, the input transconductance can be kept constant across the entire input common-mode range through the segmented compensation mechanism.

[0063] In a specific technical solution of this invention embodiment, an NMOS tail current compensation circuit is used to compensate for the tail current of the NMOS differential input pair, including PMOS current control transistors (PMOS transistors M8 and M...). 10 ) and NMOS current compensation mirror (NMOS transistor M) 11 ~M 14The PMOS tail current compensation circuit is used to compensate for the tail current of the PMOS differential input pair, including NMOS current control transistors (NMOS transistors M7 and M9) and a PMOS compensation current mirror (PMOS transistor M...). 15 ~M 18 );in,

[0064] PMOS transistors M6 and M 15 ~M 18 The source is connected to the power supply, NMOS transistors M5 and M6. 11 ~M 14 The source of the PMOS transistor is grounded; 18 The gate and drain of the PMOS transistor M 17 The gates of the PMOS transistor M are connected to form a current mirror. 16 The gate and drain of the PMOS transistor M 15 The gates of the PMOS transistor are connected to form a current mirror; 18 The drain of the PMOS transistor is connected to the drain of the NMOS transistor M9. 16 The drain of the transistor is connected to the drain of NMOS transistor M7, and the gate of NMOS transistor M7 is connected to the bias voltage V. s2 The gate of NMOS transistor M9 is connected to a bias voltage V. s4 The gate of PMOS transistor M6 is connected to a bias voltage V. b2 PMOS transistors M6 and M 15 M 17 The drain of the PMOS transistors M3, M4, M8, and M1 is connected. 10 The source of the NMOS transistor M1 and the gate of the PMOS transistor M3 are connected to the positive input V. in The gates of NMOS transistor M2 and PMOS transistor M4 are connected to the negative input V. ip The drains of NMOS transistors M1 and M2 and PMOS transistors M3 and M4 are the output nodes; the sources of NMOS transistors M1, M2, M7, and M9 are connected to NMOS transistors M5 and M6. 11 M 13 The drain of the NMOS transistor M5 is connected to the gate of the NMOS transistor with a bias voltage V. b1 The gate of PMOS transistor M8 is connected to a bias voltage V. s1 PMOS transistor M 10 Gate bias voltage V s3 The drain of PMOS transistor M8 is connected to NMOS transistor M. 12 The drain of the PMOS transistor M 10 The drain of the NMOS transistor M 14 The drain of the NMOS transistor M 12 The gate and drain of the NMOS transistor M 11 The gates of the NMOS transistors are connected to form a current mirror. 14The gate and drain of the NMOS transistor M 13 The gates are connected to form a current mirror.

[0065] In a preferred embodiment of the present invention, the NMOS transistor M 11 The current of NMOS transistor M 12 k1 times, NMOS transistor M 13 The current of NMOS transistor M 14 k3 times. PMOS transistor M 15 The current of PMOS transistor M 16 k2 times, PMOS transistor M 17 The current of PMOS transistor M 18 k4 times. NMOS transistor M 11 The width W is for NMOS transistor M 12 k1 times, NMOS transistor M 13 The width W is for NMOS transistor M 14 k3 times, NMOS transistors M5 and M 11 ~M 14 The length L is the same; PMOS transistor M 15 The width W is for PMOS transistor M 16 k2 times, PMOS transistor M 17 The width W is for PMOS transistor M 18 k4 times, PMOS transistors M6 and M 15 ~M 18 The length L is the same.

[0066] In this embodiment of the invention, the size of the PMOS transistor M8 and the bias voltage V are adjusted. s1 When the PMOS differential input pair is in the subthreshold region, PMOS transistor M8 is turned on. By adjusting PMOS transistor M... 10 Size and bias voltage V s3 When the PMOS differential input pair is in the cutoff region, the PMOS transistor M... 10 Turn on; by adjusting the size of NMOS transistor M7 and the bias voltage V s2 When the NMOS differential input pair is in the subthreshold region, NMOS transistor M7 is turned on. This is achieved by adjusting the size of NMOS transistor M9 and the bias voltage V. s4 This allows NMOS transistor M9 to conduct when the NMOS differential input pair is in the cutoff region.

[0067] Please see Figures 5 to 7 The principle explanation of the technical solution of the present invention embodiment is as follows: the constant transconductance input stage circuit disclosed in the present invention embodiment includes a basic complementary differential input pair circuit, an NMOS tail current compensation circuit, and a PMOS current source compensation circuit.

[0068] In a basic complementary differential input pair, the gates of the input NMOS transistor M1 and the PMOS transistor M3 are connected to the positive input V. in The gates of NMOS transistor M2 and PMOS transistor M4 are connected to the negative input V. ip The drains of the input NMOS transistors M1 and M2 and the PMOS transistors M3 and M4 are the output nodes; the drain of the PMOS tail current source transistor M6 is connected to the source of the input PMOS transistors M3 and M4, and its gate is connected to the bias voltage V. b2 The drain of NMOS tail current source transistor M5 is connected to the source of input NMOS transistors M1 and M2, and its gate is connected to the bias voltage V. b1 .

[0069] In the NMOS tail current compensation circuit, the gate of the PMOS current control transistor M8 is connected to a bias voltage V. s1 Its drain is connected to NMOS transistor M. 12 The drain of the PMOS current control transistor M 10 Gate bias voltage V s3 Its drain is connected to NMOS transistor M. 14 The drain of the two transistors is connected to the drain of the PMOS tail current source transistor M6 and the source of the input PMOS transistors M3 and M4, respectively, to control the current drawn from the PMOS tail current source transistor M6; the NMOS transistor M... 12 The gate and drain of the NMOS transistor M 11 The gates of the transistors M3 and M4 are connected to form a current mirror with a current replication ratio of 1:k1, used to provide compensation current when the input PMOS transistors M3 and M4 are in the subthreshold region; NMOS transistor M... 14 The gate and drain of the NMOS transistor M 13 The gates of the two transistors are connected to form a current mirror with a current replication ratio of 1:k3, which is used to provide compensation current when the input PMOS transistors M3 and M4 are in the cutoff region.

[0070] In the PMOS tail current compensation circuit, the gate of the NMOS current control transistor M7 is connected to a bias voltage V. s2 Its drain is connected to PMOS transistor M. 16 The drain of the NMOS current control transistor M9 is connected to the gate of the bias voltage V. s4 Its drain is connected to PMOS transistor M. 18 The drain of the two transistors is connected to the drain of the NMOS tail current source transistor M5 and the source of the input NMOS transistors M1 and M2, respectively, to control the current drawn from the NMOS tail current source transistor M5; the PMOS transistor M... 16 The gate and drain of the PMOS transistor M 15 The gates of the two transistors are connected to form a current mirror with a current replication ratio of 1:k2, which is used to provide compensation current when the input NMOS transistors M1 and M2 are in the subthreshold region; the PMOS transistor M... 18 The gate and drain of the PMOS transistor M17 The gates of the two transistors are connected to form a current mirror with a current replication ratio of 1:k4, which is used to provide compensation current when the input NMOS transistors M1 and M2 are in the cutoff region.

[0071] The specific analysis is as follows: if the input common-mode voltage is at V DD / 2~V DD area:

[0072] When all input transistors M1 to M4 are operating in the saturation region, the current control transistor is not working, and the total transconductance of the input stage is:

[0073]

[0074] In the formula, I n V is the total current flowing through input transistors M1 and M2. dsatn Its saturation drain-source voltage; I p V is the total current flowing through input transistors M3 and M4. dsatp Its saturation drain-source voltage.

[0075] When input transistors M1 and M2 are operating in the saturation region, and M3 and M4 are operating in the subthreshold region, M8 is turned on and begins to draw current from M6, which is operating in the linear region. At this time, the total transconductance of the input stage is:

[0076]

[0077] In the formula, k1 is M 11 and M 12 Current replication ratio; I s1 The current flowing through the current-controlled transistor M8; ζ>1, which is a non-ideal factor; thermal voltage V T = kT / q, where k is Boltzmann's constant, q is the electron charge, and T represents the absolute temperature.

[0078] Will I s1 and I p Substitute, set 2 (V) s1 –V THP ) = V GS6 –V THP To determine the current mirror replication ratio k1 and the dimensions of the current control tube and the current mirror, so that the sum of the compensated transconductance and the subthreshold transconductance remains constant;

[0079] When input transistors M1 and M2 are operating in the saturation region, and M3 and M4 are operating in the cutoff region, the current in M6 remains constant. 10 When the circuit is turned on, both sets of compensation current mirrors work simultaneously. At this time, the total transconductance of the input stage is:

[0080]

[0081] In the formula, k3 is M 13 and M 14 Current replication ratio; I s3 For current control transistor M 10 The current flowing through it.

[0082] Figure 6 The input transconductance variation curve of the segmented tail current compensation structure is shown in the figure. mtot1 This is a set of total transconductance variation curves compensated by a current mirror, mainly for compensating transconductance in the subthreshold region, where the transconductance in the cutoff region is lower than the total transconductance; g mtot2 The curves show the total transconductance variation after compensation by both sets of compensating current mirrors. It can be seen that the transconductance in both the subthreshold and cutoff regions is effectively compensated, solving the problem of poor transconductance stability in the subthreshold region using the triple current mirror method.

[0083] Specifically, based on a 0.18μm CMOS process, the total input transconductance was simulated at a power supply voltage of 1.8V. The circuit disclosed in this embodiment of the invention is compared with the total input transconductance variation curves of a structure without constant transconductance and a triple current mirror. Figure 7 As shown, from Figure 7 As can be seen, the circuit disclosed in this embodiment of the invention does not have a constant transconductance structure compared with the triple current mirror, and achieves the effect of constant transconductance in the range of input common mode voltage from 0V to 1.8V; however, in the range of input common mode voltage from 0.2V to 0.7V and from 1.1V to 1.6V, the circuit disclosed in this embodiment of the invention achieves better transconductance stability than the triple current mirror.

[0084] In summary, this invention provides a constant transconductance input stage circuit for an operational amplifier, comprising complementary NMOS and PMOS differential input pairs and a segmented tail current compensation circuit. When the NMOS differential input pair is in the subthreshold and cutoff regions, the NMOS current control transistor extracts the NMOS tail current source operating in the linear region and injects compensation current into the PMOS differential input pair through the PMOS compensation current mirror. When the PMOS differential input pair is in the subthreshold and cutoff regions, the PMOS current control transistor extracts the PMOS tail current source operating in the linear region and injects compensation current into the NMOS differential input pair through the NMOS compensation current mirror. When both the NMOS differential input pair and the PMOS differential input pair are in the saturation region, the segmented tail current compensation circuit does not operate. Compared to traditional constant transconductance input stage circuits, this invention effectively improves transconductance stability across the entire input common-mode range, thereby improving the linearity of the operational amplifier.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A constant transconductance input stage circuit for an operational amplifier, characterized in that, include: The segmented tail current compensation circuit and complementary NMOS differential input pairs and PMOS differential input pairs; among them, The segmented tail current compensation circuit includes two parts: an NMOS tail current compensation circuit and a PMOS tail current compensation circuit. The NMOS tail current compensation circuit provides different compensation currents when the PMOS differential input pair is in the subthreshold region and the cutoff region, and the PMOS tail current compensation circuit provides different compensation currents when the NMOS differential input pair is in the subthreshold region and the cutoff region. The NMOS differential input pair includes NMOS transistors M1 and M2; the PMOS differential input pair includes PMOS transistors M3 and M4; the NMOS tail current compensation circuit includes NMOS transistors M5 and M6. 11 NMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14 PMOS transistor M8 and PMOS transistor M 10 The PMOS tail current compensation circuit includes: PMOS transistor M6 and PMOS transistor M... 15 PMOS transistor M 16 PMOS transistor M 17 PMOS transistor M 18 NMOS transistors M7 and M9; among them, PMOS transistors M6 and M7 are also present. 15 PMOS transistor M 16 PMOS transistor M 17 PMOS transistor M 18 The source is connected to the power supply, NMOS transistor M5, NMOS transistor M 11 NMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14 The source of the PMOS transistor is grounded; 18 The gate, drain and PMOS transistor M 17 The gates of the PMOS transistor M are connected to form a current mirror. 16 The gate, drain and PMOS transistor M 15 The gates of the PMOS transistor are connected to form a current mirror; 18 The drain of the PMOS transistor is connected to the drain of the NMOS transistor M9. 16 The drain of the transistor is connected to the drain of NMOS transistor M7, and the gate of NMOS transistor M7 is connected to the bias voltage. V s2 The gate of NMOS transistor M9 is connected to a bias voltage. V s4 The gate of PMOS transistor M6 is connected to a bias voltage. V b2 PMOS transistor M6, PMOS transistor M 15 PMOS transistor M 17 The drain of PMOS transistors M3, M4, M8, and M1 is connected. 10 The source, gate of NMOS transistor M1, and gate of PMOS transistor M3 are connected to the positive input. V in The gates of NMOS transistor M2 and PMOS transistor M4 are connected to the negative input. V ip The drains of NMOS transistors M1, M2, M3, and M4 are the output nodes; the sources of NMOS transistors M1, M2, M7, and M9 are connected to NMOS transistors M5 and M6. 11 NMOS transistor M 13 The drain of NMOS transistor M5 is biased by the gate voltage. V b1 The gate of PMOS transistor M8 is connected to a bias voltage. V s1 PMOS transistor M 10 Gate bias voltage V s3 The drain of PMOS transistor M8 is connected to NMOS transistor M. 12 The drain of the PMOS transistor M 10 The drain of the NMOS transistor M 14 The drain of the NMOS transistor M 12 The gate, drain and NMOS transistor M 11 The gates of the NMOS transistors are connected to form a current mirror. 14 The gate, drain and NMOS transistor M 13 The gates of the transistors are connected to form a current mirror; the dimensions and bias voltage of the PMOS transistor M8. V s1 This enables PMOS transistor M8 to conduct when the PMOS differential input pair is in the subthreshold region; PMOS transistor M 10 Size and bias voltage V s3 Enables PMOS transistor M to operate in the cutoff region when the PMOS differential input pair is in the cutoff region. 10 On; Dimensions and bias voltage of NMOS transistor M7 V s2 Enables NMOS transistor M7 to conduct when the NMOS differential input pair is in the subthreshold region; the dimensions and bias voltage of NMOS transistor M9. V s4 It enables NMOS transistor M9 to conduct when the NMOS differential input pair is in the cutoff region; NMOS transistor M 11 The current of NMOS transistor M 12 of k 1x, NMOS transistor M 13 The current of NMOS transistor M 14 of k 3 times; of which, through NMOS transistor M 11 copy k 1x NMOS transistor M 12 The current provides compensation current for PMOS transistors M3 and M4 to operate in the subthreshold region; through NMOS transistor M... 13 copy k 3 times NMOS transistor M 14 The current provides compensation current for PMOS transistors M3 and M4 to operate in the cutoff region; PMOS transistor M 15 The current of PMOS transistor M 16 of k 2 times, PMOS transistor M 17 The current of PMOS transistor M 18 of k 4 times; of which, through PMOS transistor M 15 copy k 2x PMOS transistor M 16 The current provides compensation current for NMOS transistors M1 and M2 to operate in the subthreshold region; through PMOS transistor M... 17 copy k 4x PMOS transistor M 18 The current provides compensation current for NMOS transistors M1 and M2 to operate in the cutoff region; NMOS transistor M 11 The width of the NMOS transistor M 12 of k 1x, NMOS transistor M 13 The width of the NMOS transistor M 14 of k 3 times, NMOS transistor, M5, NMOS transistor M 11 NMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14 They have the same length; PMOS transistor M 15 The width of the PMOS transistor M 16 of k 2 times, PMOS transistor M 17 The width of the PMOS transistor M 18 of k 4 times, PMOS transistor M6, PMOS transistor M 15 PMOS transistor M 16 PMOS transistor M 17 PMOS transistor M 18 They are the same length.

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