Light emitting diode and method of manufacturing light emitting diode

Abstract

The present disclosure provides a light emitting diode and a light emitting diode preparation method. The light emitting diode comprises an epitaxial structure, a first electrode, a second electrode, a reflective layer, a first electrode pad and a second electrode pad; the epitaxial structure comprises a first semiconductor layer, an active layer and a second semiconductor layer which are stacked in sequence, the first semiconductor layer, the active layer and the second semiconductor layer form a step structure, the first electrode is located on a step surface of the step structure, the second electrode is located on a surface of the second semiconductor layer, and the reflective layer covers the step structure and the first electrode and the second electrode; the reflective layer has a first through hole and a second through hole, the first electrode pad is connected with the first electrode through the first through hole, and the second electrode pad is connected with the second electrode through the second through hole; a projection of the first through hole on a bottom surface of the first semiconductor layer is located at an edge of a projection of the first electrode pad on the bottom surface of the first semiconductor layer, and the bottom surface of the first semiconductor layer is a surface away from the active layer.

Description

Technical Field

[0001] This disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a method for fabricating a light-emitting diode. Background Technology

[0002] Light-emitting diodes (LEDs) can cover a wavelength range from ultraviolet to infrared. Currently, the low-resolution display market is still dominated by liquid crystal displays (LCDs), but micro light-emitting diodes (Micro LEDs) are gradually gaining attention in the low-resolution display market due to their inherent advantages.

[0003] The miniature light-emitting diodes provided by related technologies typically include epitaxial structures, electrodes, reflective layers, and pads.

[0004] However, the small size of the pads in the miniature light-emitting diodes provided by the related technologies, and the inability to guarantee the flatness of the pads, easily leads to low yield in subsequent soldering processes. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) and a method for manufacturing the LED, which can improve the soldering yield of pads. The technical solution is as follows:

[0006] On one hand, a light-emitting diode is provided, the light-emitting diode comprising: an epitaxial structure, a first electrode, a second electrode, a reflective layer, a first electrode pad, and a second electrode pad;

[0007] The epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially. The first semiconductor layer, the active layer, and the second semiconductor layer form a stepped structure. The first electrode is located on the step surface of the stepped structure, and the second electrode is located on the surface of the second semiconductor layer. The reflective layer covers the stepped structure, the first electrode, and the second electrode.

[0008] The reflective layer has a first through hole and a second through hole, the first electrode pad is connected to the first electrode through the first through hole, and the second electrode pad is connected to the second electrode through the second through hole;

[0009] The projection of the first via on the bottom surface of the first semiconductor layer is located at the edge of the projection of the first electrode pad on the bottom surface of the first semiconductor layer, and the bottom surface of the first semiconductor layer is the side away from the active layer.

[0010] Optionally, the projection of the first electrode pad onto the bottom surface of the first semiconductor layer is a first rectangle, and the projection of the first via onto the bottom surface of the first semiconductor layer is located at one corner of the first rectangle.

[0011] Optionally, the bottom surface of the first semiconductor layer is a second rectangle, and the projection of the stepped surface of the stepped structure onto the bottom surface of the first semiconductor layer is located at one corner of the second rectangle.

[0012] Optionally, the light-emitting diode further includes: a first barrier structure and a second barrier structure, wherein the first barrier structure is located on the surface of the first electrode pad and arranged along the edge of the first electrode pad, and the second barrier structure is located on the surface of the second electrode pad and arranged along the edge of the second electrode pad.

[0013] Optionally, the first barrier structure and the second barrier structure are silicon oxide structures.

[0014] Optionally, both the first retaining wall structure and the second retaining wall structure are annular stepped retaining wall structures, and the stepped surfaces of the stepped retaining wall structures face the center of the annulus.

[0015] Optionally, both the first retaining wall structure and the second retaining wall structure are three-stage stepped retaining wall structures, and the height of each step in the three-stage stepped retaining wall structure is 0.2 to 0.4 micrometers.

[0016] On the other hand, a method for fabricating a light-emitting diode is provided, the method comprising:

[0017] A first semiconductor layer, an active layer, and a second semiconductor layer are formed in sequence, and the second semiconductor layer, the active layer, and the first semiconductor layer constitute an epitaxial structure.

[0018] The extensional structure is graphically processed to form a stepped structure;

[0019] A first electrode and a second electrode are fabricated, wherein the first electrode is located on the step surface of the stepped structure and the second electrode is located on the surface of the second semiconductor layer.

[0020] A reflective layer is fabricated, which covers the stepped structure, the first electrode, and the second electrode, and the reflective layer has a first through hole and a second through hole;

[0021] A first electrode pad and a second electrode pad are fabricated. The first electrode pad is connected to the first electrode through the first via, and the second electrode pad is connected to the second electrode through the second via. The projection of the first via onto the bottom surface of the first semiconductor layer is located at the edge of the projection of the first electrode pad onto the bottom surface of the first semiconductor layer. The bottom surface of the first semiconductor layer is the side away from the active layer.

[0022] Optionally, the method further includes:

[0023] An insulating film layer is formed on the first electrode pad and the second electrode pad;

[0024] The insulating film layer is patterned to obtain a first barrier structure and a second barrier structure. The first barrier structure is located on the surface of the first electrode pad and arranged along the edge of the first electrode pad, and the second barrier structure is located on the surface of the second electrode pad and arranged along the edge of the second electrode pad.

[0025] Optionally, the patterning process of the insulating film layer includes:

[0026] The insulating film layer is subjected to multiple patterning processes to form the first retaining wall structure and the second retaining wall structure with a stepped structure.

[0027] The beneficial effects of the technical solutions provided in this disclosure are:

[0028] In this embodiment, the first through-hole connecting the first electrode pad and the first electrode is moved from the center of the first electrode pad to the edge of the first electrode pad. This way, during welding, even if some of the welding material (conductive particles) falls into the depression of the first electrode pad caused by the first through-hole, the welding of the first electrode pad will not be affected because the depression is located at the edge. Furthermore, this arrangement makes the center of the surface of the first electrode pad flatter, and the large flat surface at the center of the solder joint improves the welding yield, improves the conductivity after welding, and optimizes the light-emitting effect of the light-emitting diode. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided by related technologies;

[0031] Figure 2 This is a top view of a portion of the structure of a light-emitting diode provided by related technologies;

[0032] Figure 3 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure;

[0033] Figure 4 This is a top view of a portion of the structure of a light-emitting diode provided in an embodiment of this disclosure;

[0034] Figure 5 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure;

[0035] Figure 6 This is a top view of a portion of the structure of a light-emitting diode provided in an embodiment of this disclosure;

[0036] Figure 7 This is a top view of a portion of the structure of a light-emitting diode provided in an embodiment of this disclosure;

[0037] Figure 8 This is a flowchart of a method for fabricating a light-emitting diode provided in an embodiment of this disclosure;

[0038] Figure 9 This is a flowchart of another method for fabricating a light-emitting diode provided in this embodiment.

[0039] The attached figures are labeled as follows:

[0040] 10: Electrode structure; 100: Substrate; 101: First semiconductor layer; 102: Active layer; 103: Second semiconductor layer; 104: Bonding layer; 105: First electrode; 106: Second electrode; 107: Reflective layer; 108: First electrode pad; 109: Second electrode pad; 110: Passivation layer; 111: First via; 112: Second via; 120: Stepped surface of stepped structure; 1000: Epitaxial structure; 201: First barrier structure; 202: Second barrier structure. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0042] Figure 1 A schematic diagram of a light-emitting diode (LED) provided for related technologies. See also... Figure 1 The light-emitting diode includes: a substrate 100, an epitaxial structure 1000, a bonding layer 104, a reflective layer 107, a passivation layer 110, and an electrode structure 10.

[0043] The epitaxial structure 1000 includes a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103, and the electrode structure 10 includes a first electrode 105, a second electrode 106, a first electrode pad 108, and a second electrode pad 109.

[0044] The substrate 100 is bonded to the epitaxial structure 1000 through the bonding layer 104, the reflective layer 107 covers the surface of the epitaxial structure 1000, the electrode structure 10 penetrates the reflective layer 107 and is connected to the epitaxial structure 1000, and the passivation layer 110 covers the surface of the reflective layer 107.

[0045] The reflective layer 107 has a first through hole 111 and a second through hole 112. The first electrode pad 108 is connected to the first electrode 105 through the first through hole 111, and the second electrode pad 109 is connected to the second electrode 106 through the second through hole 112.

[0046] Figure 2 This is a top view of a portion of the structure of a light-emitting diode provided by related technologies. See also: Figure 2 Because the first through hole 111 is deep, a depression A appears in the middle of the surface of the first electrode pad 108. Since the depression A is located in the center of the pad surface, during subsequent soldering, the soldering material (conductive particles) is easily trapped in the depression A, which reduces the soldering yield of the subsequent pad and results in poor conductivity after soldering, thus affecting the light emission of the light-emitting diode.

[0047] This disclosure provides a light-emitting diode, which includes: an epitaxial structure, a first electrode, a second electrode, a reflective layer, a first electrode pad, and a second electrode pad.

[0048] The epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially. The first semiconductor layer, the active layer, and the second semiconductor layer form a stepped structure. The first electrode is located on the step surface of the stepped structure, and the second electrode is located on the surface of the second semiconductor layer. The reflective layer covers the stepped structure, the first electrode, and the second electrode.

[0049] The reflective layer 107 has a first through hole 111 and a second through hole 112. The first electrode pad 108 is connected to the first electrode 105 through the first through hole 111, and the second electrode pad 109 is connected to the second electrode 106 through the second through hole 112.

[0050] The projection of the first via 111 onto the bottom surface of the first semiconductor layer 101 is located at the edge of the projection of the first electrode pad 108 onto the bottom surface of the first semiconductor layer 101, and the bottom surface of the first semiconductor layer 101 is the side away from the active layer 102.

[0051] Wherein, the side of the first semiconductor layer 101 away from the active layer 102 refers to the side opposite to the side of the first semiconductor layer 101 that is close to the active layer 102.

[0052] In this embodiment, the first through-hole connecting the first electrode pad and the first electrode is moved from the center of the first electrode pad to the edge of the first electrode pad. This way, during welding, even if some of the welding material (conductive particles) falls into the depression of the first electrode pad caused by the first through-hole, the welding of the first electrode pad will not be affected because the depression is located at the edge. Furthermore, this arrangement makes the center of the surface of the first electrode pad flatter, and the large flat surface at the center of the solder joint improves the welding yield, improves the conductivity after welding, and optimizes the light-emitting effect of the light-emitting diode.

[0053] The welding material is in a fluid state during the welding process, making it prone to sinking into the dent.

[0054] Optionally, the second via connecting the second electrode pad and the second electrode can also be moved from the center of the second electrode pad to the edge of the second electrode pad. That is, the projection of the second via on the bottom surface of the first semiconductor layer is located at the edge of the projection of the second electrode pad on the bottom surface of the first semiconductor layer.

[0055] Although the smaller depth of the second via has a lower impact on the surface flatness of the second electrode pad, this improvement can still optimize the welding yield of the second electrode pad to some extent.

[0056] Furthermore, the subsequent improvements to the design of the first through hole position also apply to the second through hole, so they will not be elaborated further.

[0057] Figure 3 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. See also... Figure 3 The light-emitting diode includes: a substrate 100, an epitaxial structure 1000, a bonding layer 104, a reflective layer 107, and an electrode structure 10.

[0058] The substrate 100 is bonded to the epitaxial structure 1000 through the bonding layer 104, and the electrode structure 10 is connected to the epitaxial structure 1000 through the reflective layer 107.

[0059] In this embodiment of the disclosure, the epitaxial structure 1000 includes a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 stacked sequentially, forming a stepped structure; the first electrode 105 is located on the step surface 120 of the stepped structure, the second electrode 106 is located on the surface of the second semiconductor layer 103, and the reflective layer 107 covers the stepped structure and the first electrode 105 and the second electrode 106.

[0060] The reflective layer 107 has a first through hole 111 and a second through hole 112. The first electrode pad 108 is connected to the first electrode 105 through the first through hole 111, and the second electrode pad 109 is connected to the second electrode 106 through the second through hole 112.

[0061] It should be noted that the depression on the surface of the first electrode pad caused by the first through-hole is a microstructure, which is not shown in the attached figure, but it has been verified by experiments that it does affect the soldering effect.

[0062] Figure 4 This is a top view of a portion of the structure of a light-emitting diode provided in an embodiment of this disclosure. See also... Figure 3 and Figure 4 It can be seen that the projection of the first electrode pad 108 onto the bottom surface of the first semiconductor layer 101 is a first rectangle, and the projection of the first via 111 onto the bottom surface of the first semiconductor layer 101 is located at one corner of the first rectangle.

[0063] In this embodiment of the present disclosure, the first through hole 111 is disposed on one corner of the first electrode pad 108, which can minimize the impact of the depression on the surface of the first electrode pad caused by the first through hole on the welding yield.

[0064] exist Figure 4 In the implementation shown, the projection of the first via 111 onto the bottom surface of the first semiconductor layer 101 is located at a corner of the first rectangle away from the second electrode pad 109.

[0065] In other implementations, the projection of the first via 111 onto the bottom surface of the first semiconductor layer 101 may also be located at the center of one side of the first rectangle.

[0066] In other embodiments, the projection of the first electrode pad 108 onto the bottom surface of the first semiconductor layer 101 can also be other shapes, such as circles, other polygons, etc.

[0067] like Figure 4As shown, the bottom surface of the first semiconductor layer 101 is a second rectangle, and the projection of the step surface 120 of the stepped structure onto the bottom surface of the first semiconductor layer 101 is located at one corner of the second rectangle.

[0068] In this implementation, the stepped structure is formed at one corner of the first semiconductor layer 101. The stepped structure occupies a small area, which makes the overall light-emitting area of ​​the light-emitting diode larger.

[0069] exist Figure 4 In the structure shown, the step structure is a notch, and the sidewalls of the step structure are arc-shaped.

[0070] exist Figure 4 In the structure shown, the projection of the first through hole 111 is circular, and the circular through hole and the arc are concentrically arranged.

[0071] In other implementations, the stepped structure sidewalls and / or the first through hole 111 can also be of other shapes.

[0072] In other embodiments, the stepped structure may have a larger area, which is not limited in this disclosure.

[0073] Figure 5 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. See also... Figure 5 The light-emitting diode and Figure 3 The difference of the light-emitting diode shown is that the light-emitting diode further includes: a first barrier structure 201 and a second barrier structure 202, wherein the first barrier structure 201 is located on the surface of the first electrode pad 108, and the second barrier structure 202 is located on the surface of the second electrode pad 109.

[0074] Figure 6 This is a top view of a portion of the structure of a light-emitting diode provided in an embodiment of this disclosure. See also... Figure 6 It can be seen that the first barrier structure 201 is arranged along the edge of the first electrode pad 108, and the second barrier structure 202 is arranged along the edge of the second electrode pad 109.

[0075] In this implementation, by arranging a retaining wall structure at the edge of the pad surface, the easily flowing welding material can be confined to the middle of the pad surface during the welding process, preventing it from flowing outside the pad, thereby ensuring welding quality and avoiding the adverse effects caused by welding material overflow.

[0076] In one possible implementation of this disclosure, the first barrier structure 201 and the second barrier structure 202 are silicon oxide structures.

[0077] For example, the first retaining wall structure 201 and the second retaining wall structure 202 are silicon dioxide structures.

[0078] In this implementation, silicon oxide is used to make the barrier structure, which is convenient to manufacture and can be attached to the surface of the pads, and can also block the welding material.

[0079] In other implementations, the first retaining wall structure 201 and the second retaining wall structure 202 may also be structures made of other materials, and there are no restrictions on this.

[0080] See you again Figure 5 Both the first retaining wall structure 201 and the second retaining wall structure 202 are annular stepped retaining wall structures, and the stepped surfaces of the stepped retaining wall structures face the center of the annulus.

[0081] In this implementation, the stepped structure can better block the welding material and ensure that the welding material is in the center of the welding surface.

[0082] See you again Figure 5 Both the first retaining wall structure 201 and the second retaining wall structure 202 are three-stage stepped retaining wall structures, and the height of each step in the three-stage stepped retaining wall structure is 0.2 to 0.4 micrometers.

[0083] In this implementation, the height mentioned above can meet the requirements for the amount of welding material, while not being too high and affecting the overall thickness of the light-emitting diode.

[0084] For example, the height of each step in the three-step retaining wall structure is 0.3 micrometers.

[0085] In this embodiment of the disclosure, the width of the first retaining wall structure 201 and the second retaining wall structure 202 can be 4 to 6 micrometers, for example 5 micrometers.

[0086] In other implementations, the first retaining wall structure 201 and the second retaining wall structure 202 may also be non-step structures, and there are no restrictions on this.

[0087] Figure 7 This is a top view of a portion of the structure of a light-emitting diode provided in an embodiment of this disclosure. See also... Figure 7 It can be seen that, with Figure 6 In contrast, the first retaining wall structure 201 is arranged along the edge of the first electrode pad 108, but excludes the area corresponding to the first through hole 111, thereby further ensuring the flatness of the welding area.

[0088] That is, in Figure 6In the structure shown, the projection of the first through hole 111 on the bottom surface of the first semiconductor layer 101 is located within the projection of the first barrier structure 201 on the bottom surface of the first semiconductor layer 101.

[0089] And in Figure 7 In the structure shown, the projection of the first through-hole 111 on the bottom surface of the first semiconductor layer 101 is outside the projection of the first barrier structure 201 on the bottom surface of the first semiconductor layer 101. This method can exclude the recess A from the first barrier structure 201, further preventing the soldering material from sinking into the recess A.

[0090] like Figure 6 As shown, the first retaining wall structure 201 is a rectangular ring; as Figure 7 As shown, the first retaining wall structure 201 is a rectangular ring with an arc-shaped notch at one corner, and the arc-shaped notch is opposite to the first through hole 111.

[0091] In the embodiments of this disclosure, the substrate 100 can be any one of sapphire substrate, Si substrate, SiC substrate, etc., and this disclosure does not limit the material of the substrate.

[0092] For example, substrate 100 is a sapphire substrate.

[0093] In this embodiment of the disclosure, the first semiconductor layer 101 can be an N-type semiconductor layer, and the second semiconductor layer 103 can be a P-type semiconductor layer.

[0094] For example, the first semiconductor layer 101 may include a stacked N-type AlGaInP current spreading layer and an N-type AlInP carrier confinement layer, and the second semiconductor layer 103 may include a stacked P-type AlInP carrier confinement layer and a P-type GaP window layer.

[0095] The thickness of the P-type GaP window layer is 2.8–3.2 μm, for example, 3 μm.

[0096] In another example, the first semiconductor layer 101 can be a P-type semiconductor layer, and the second semiconductor layer 103 can be an N-type semiconductor layer.

[0097] In this embodiment of the disclosure, the active layer 102 can be a multi-quantum well layer, for example, the multi-quantum well layer can include multiple AlGaInP quantum well layers and AlGaInP quantum barrier layers stacked alternately in a periodic manner.

[0098] Optionally, an etching stop layer may be provided between the bonding layer 104 and the first semiconductor layer 101. The etching stop layer may be a cured phosphoric acid mixture.

[0099] In this embodiment, the bonding layer 104 can be made of any one of photoresist, benzocyclobutene, or silicone.

[0100] For example, the bonding layer 104 is made of silicone.

[0101] In this embodiment of the present disclosure, a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 are stacked sequentially to form a stepped structure, and a reflective layer 107 covers the stepped structure.

[0102] In this embodiment of the disclosure, the reflective layer 107 is a distributed Bragg reflector (DBR) layer.

[0103] In this embodiment of the disclosure, both the first electrode 105 and the second electrode 106 may include AuGe or AuBe electrodes.

[0104] In this embodiment of the disclosure, both the first electrode pad 108 and the second electrode pad 109 may include a Cr layer, an Al layer, a Ti layer, a Ni layer and an Au alloy layer stacked sequentially.

[0105] In one example, the thickness of the Cr layer is 80–120 nm, the thickness of the Al layer is 2500–3500 nm, the thickness of the Ti layer is 450–550 nm, the thickness of the Ni layer is 1800–2200 nm, and the thickness of the Au alloy layer is 18000–22000 nm.

[0106] For example, the thickness of the Cr layer is 100 nm, the thickness of the Al layer is 3000 nm, the thickness of the Ti layer is 500 nm, the thickness of the Ni layer is 2000 nm, and the thickness of the Au alloy layer is 20000 nm.

[0107] In one example, the first electrode 105 is an N-electrode, and the first electrode pad 108 is an N-electrode pad; the second electrode 106 is a P-electrode, and the second electrode pad 109 is a P-electrode pad.

[0108] In another example, the first electrode 105 is a P electrode, the first electrode pad 108 is a P electrode pad; the second electrode 106 is an N electrode, and the second electrode pad 109 is an N electrode pad.

[0109] Optionally, the light-emitting diode may further include a passivation layer 110, which covers the sidewalls of the epitaxial structure 1000 and the reflective layer 107.

[0110] like Figure 3 As shown, in one example, the passivation layer thickness can be less than the pad thickness. A lower passivation layer thickness results in a thinner passivation layer on the sides, thus enabling miniaturization of the light-emitting diode. In other examples, the passivation layer thickness is the same as the pad thickness.

[0111] In this embodiment, the passivation layer 110 can be a film layer formed of materials such as SiO2 layer and Al2O3 layer.

[0112] For example, passivation layer 110 is a SiO2 layer.

[0113] It is worth noting that, in the embodiments of this disclosure, the structure can be selectively added or reduced based on the structure of the light-emitting diode described above, and this disclosure does not limit this.

[0114] Figure 8 This disclosure provides a flowchart of a method for fabricating a light-emitting diode (LED). See also... Figure 8 The method includes the following steps:

[0115] S11. A first semiconductor layer, an active layer, and a second semiconductor layer are formed in sequence, wherein the second semiconductor layer, the active layer, and the first semiconductor layer constitute an epitaxial structure.

[0116] S12. The extensional structure is graphically processed to form a stepped structure.

[0117] S13. Fabricate a first electrode and a second electrode, wherein the first electrode is located on the step surface of the stepped structure and the second electrode is located on the surface of the second semiconductor layer.

[0118] S14. Fabricate a reflective layer, the reflective layer covering the stepped structure and the first electrode and the second electrode, the reflective layer having a first through hole and a second through hole.

[0119] S15. Fabricate a first electrode pad and a second electrode pad. The first electrode pad is connected to the first electrode through the first through-hole, and the second electrode pad is connected to the second electrode through the second through-hole. The projection of the first through-hole on the bottom surface of the first semiconductor layer is located at the edge of the projection of the first electrode pad on the bottom surface of the first semiconductor layer. The bottom surface of the first semiconductor layer is the side away from the active layer.

[0120] In this embodiment, the first through-hole connecting the first electrode pad and the first electrode is moved from the center of the first electrode pad to the edge of the first electrode pad. This way, during welding, even if some of the welding material (conductive particles) falls into the depression of the first electrode pad caused by the first through-hole, the welding of the first electrode pad will not be affected because the depression is located at the edge. Furthermore, this arrangement makes the center of the surface of the first electrode pad flatter, and the large flat surface at the center of the solder joint improves the welding yield, improves the conductivity after welding, and optimizes the light-emitting effect of the light-emitting diode.

[0121] Figure 9A flowchart illustrating another method for fabricating a light-emitting diode (LED) according to an embodiment of this disclosure. See also... Figure 9 The method includes the following steps:

[0122] S21. The epitaxial structure is bonded to the substrate through a bonding layer.

[0123] In one example, step S21 includes:

[0124] Step 1: Fabricate a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the surface of a first temporary substrate, i.e., fabricate an epitaxial structure.

[0125] The first temporary substrate is a gallium arsenide substrate.

[0126] In one example, step 1 includes:

[0127] The first step is to fabricate the first semiconductor layer.

[0128] In this embodiment of the disclosure, the first semiconductor layer includes an N-type AlGaInP current spreading layer and an N-type AlInP carrier confinement layer stacked sequentially.

[0129] For example, an N-type AlGaInP current spreading layer and an N-type AlInP carrier confinement layer are sequentially fabricated on the surface of a first temporary substrate using a metal-organic chemical vapor deposition (MOCVD) apparatus.

[0130] In the embodiments disclosed herein, the above-mentioned semiconductor layer can be grown using a Veeco K465i or C4 or RB MOCVD equipment or an AIXTRON metal-organic chemical vapor deposition equipment. High-purity H2 (hydrogen), high-purity N2 (nitrogen), or a mixture of high-purity H2 and high-purity N2 is used as the carrier gas; high-purity NH3 is used as the N source; trimethylgallium (TMGa) and triethylgallium (TEGa) are used as gallium sources; trimethylindium (TMIn) is used as the indium source; silane (SiH4) is used as the N-type dopant; trimethylaluminum (TMAl) is used as the aluminum source; and magnesium pyrocene (CP2Mg) is used as the P-type dopant.

[0131] Optionally, an etching stop layer may be formed between the first temporary substrate and the first semiconductor layer, and the etching medium layer is a cured phosphoric acid mixture.

[0132] The second step is to create the active layer.

[0133] In this embodiment of the disclosure, the active layer is a multi-quantum-well layer, comprising multiple alternating AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0134] For example, multiple AlGaInP quantum well layers and AlGaInP quantum barrier layers are alternately grown on the surface of the first semiconductor layer using an MOCVD device.

[0135] The third step is to fabricate the second semiconductor layer.

[0136] In this embodiment of the disclosure, the second semiconductor layer includes a P-type AlInP carrier confinement layer and a P-type GaP window layer.

[0137] For example, a P-type AlInP carrier confinement layer and a P-type GaP window layer are sequentially fabricated on the surface of the active layer using an MOCVD device.

[0138] Step 2: Bond a second temporary substrate to the surface of the second semiconductor layer.

[0139] The second temporary substrate can be any of the following: sapphire substrate, Si substrate, etc.

[0140] In this embodiment of the disclosure, the second temporary substrate and the second semiconductor layer can be bonded together using any one of photoresist, benzocyclobutene, and silicone.

[0141] The bonding temperature is 280–320°C. For example, the bonding temperature is 300°C.

[0142] In this embodiment, if the bonding temperature is too high, it will damage the semiconductor layer; if the bonding temperature is too low, it will be detrimental to the bonding effect. Using the above-mentioned temperature for bonding can ensure a good bonding effect without damaging the semiconductor layer.

[0143] Step 3: Remove the first temporary substrate.

[0144] Step 4: Form a bonding layer on the substrate surface.

[0145] In the embodiments disclosed herein, the substrate can be any one of a sapphire substrate, a Si substrate, etc., for example, a sapphire substrate.

[0146] In this embodiment of the disclosure, the bonding layer is made of any one of photoresist, benzocyclobutene, and silicone.

[0147] Step 5: Bond the substrate to the first semiconductor layer through the bonding layer.

[0148] The bonding temperature is 280–320°C. For example, the bonding temperature is 300°C.

[0149] Step 6: Remove the second temporary substrate.

[0150] In this embodiment of the disclosure, when removing the second temporary substrate, a solution can be used for treatment, and the adhesive material used for bonding on the surface is also removed at the same time as the second temporary substrate is removed.

[0151] S22. The first semiconductor layer, the active layer and the second semiconductor layer are patterned to form a stepped structure.

[0152] In one example, step S22 includes:

[0153] Etching techniques are used to pattern the sequentially stacked second semiconductor layer, active layer, and first semiconductor layer, exposing the first semiconductor layer to form a stepped structure.

[0154] In this embodiment of the disclosure, the stepped surface of the stepped structure is located within the first semiconductor layer.

[0155] In this embodiment of the disclosure, an etching technique is used to pattern the sequentially stacked second semiconductor layer, active layer, and first semiconductor layer to expose the first semiconductor layer and form a stepped structure. This may include:

[0156] The first step is to coat the surface of the second semiconductor layer with a layer of photoresist.

[0157] The second step involves using a photomask to expose the photoresist.

[0158] The third step is to develop the exposed photoresist to form a photoresist mask.

[0159] The fourth step involves etching the second semiconductor layer, the active layer, and the first semiconductor layer using a photoresist mask to form a stepped structure and an etching groove (ISO).

[0160] The fifth step is to remove the photoresist using a photoresist remover solution.

[0161] S23. Fabricate a first electrode and a second electrode, wherein the first electrode is located on the stepped surface and the second electrode is located on the surface of the second semiconductor layer.

[0162] In one example, step S23 includes:

[0163] A first electrode is formed on the step surface of the first semiconductor layer and a second electrode is formed on the surface of the second semiconductor layer using electron beam evaporation or magnetron sputtering technology.

[0164] S24. Fabricate a reflective layer, the reflective layer covering the stepped structure and the first electrode and the second electrode, the reflective layer having a first through hole and a second through hole.

[0165] In one example, step S24 includes:

[0166] A DBR layer is fabricated on the surface of the second semiconductor layer and the stepped structure using plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) techniques to form a reflective layer; the reflective layer is then patterned to form a first via and a second via.

[0167] S25. Fabricate a first electrode pad and a second electrode pad, wherein the first electrode pad is connected to the first electrode through the first through hole, and the second electrode pad is connected to the second electrode through the second through hole.

[0168] Wherein, the projection of the first via on the bottom surface of the first semiconductor layer is located at the edge of the projection of the first electrode pad on the bottom surface of the first semiconductor layer, and the bottom surface of the first semiconductor layer is the side away from the active layer.

[0169] For example, the projection of the first electrode pad onto the bottom surface of the first semiconductor layer is a first rectangle, and the projection of the first via onto the bottom surface of the first semiconductor layer is located at one corner of the first rectangle.

[0170] In this embodiment of the present disclosure, the first through hole is disposed at one corner of the first electrode pad, which can minimize the impact of the depression on the surface of the first electrode pad caused by the first through hole on the soldering yield.

[0171] exist Figure 4 In the implementation shown, the projection of the first via on the bottom surface of the first semiconductor layer is located at a corner of the first rectangle away from the second electrode pad.

[0172] In other implementations, the projection of the first via onto the bottom surface of the first semiconductor layer may also be located at the center of one side of the first rectangle.

[0173] In other embodiments, the projection of the first electrode pad onto the bottom surface of the first semiconductor layer can also be other shapes, such as circles, other polygons, etc.

[0174] like Figure 4 As shown, the bottom surface of the first semiconductor layer is a second rectangle, and the projection of the stepped surface of the stepped structure onto the bottom surface of the first semiconductor layer is located at one corner of the second rectangle.

[0175] In this implementation, the stepped structure is located at one corner of the first semiconductor layer. The stepped structure occupies a small area, which makes the overall light-emitting area of ​​the light-emitting diode larger.

[0176] exist Figure 4 In the structure shown, the step structure is a notch, and the sidewalls of the step structure are arc-shaped.

[0177] exist Figure 4 In the structure shown, the projection of the first through hole is circular, and the circular through hole and the arc are concentrically arranged.

[0178] In other implementations, the stepped structure sidewalls and / or the first through hole can also be of other shapes.

[0179] In other embodiments, the stepped structure may have a larger area, which is not limited in this disclosure.

[0180] In one example, step S25 includes:

[0181] The first step is to deposit a metal stack.

[0182] The metal stack is connected to the first electrode through a first through-hole and to the second electrode through a second through-hole.

[0183] In this embodiment of the disclosure, the metal stack includes a Cr layer, an Al layer, a Ti layer, a Ni layer and an Au alloy layer stacked sequentially.

[0184] In one example, the thickness of the Cr layer is 80–120 nm, the thickness of the Al layer is 2500–3500 nm, the thickness of the Ti layer is 450–550 nm, the thickness of the Ni layer is 1800–2200 nm, and the thickness of the Au alloy layer is 18000–22000 nm.

[0185] For example, the thickness of the Cr layer is 100 nm, the thickness of the Al layer is 3000 nm, the thickness of the Ti layer is 500 nm, the thickness of the Ni layer is 2000 nm, and the thickness of the Au alloy layer is 20000 nm.

[0186] The second step is to fabricate a photoresist mask layer on the metal stack.

[0187] The third step involves patterning the metal stack under the cover of the photoresist mask layer to obtain the first electrode pad and the second electrode pad.

[0188] For example, the metal stack can be patterned using dry etching, such as with an etching gas Cl2+BCl3. During this etching process, the temperature is room temperature, the pressure is 4 mTorr, and the etching rate is 100 angstroms / second.

[0189] Among them, the photoresist mask layer can be a positive photoresist mask layer.

[0190] The fourth step is to remove the photoresist mask layer.

[0191] In this embodiment of the disclosure, the first electrode and the first electrode pad form a first electrode structure, and the second electrode and the second electrode pad form a second electrode structure.

[0192] S26. Fabricate a first retaining wall structure and a second retaining wall structure, wherein the first retaining wall structure is located on the surface of the first electrode pad and arranged along the edge of the first electrode pad, and the second retaining wall structure is located on the surface of the second electrode pad and arranged along the edge of the second electrode pad.

[0193] In this implementation, by arranging a retaining wall structure at the edge of the pad surface, the easily flowing welding material can be confined to the middle of the pad surface during the welding process, preventing it from flowing outside the pad, thereby ensuring welding quality and avoiding the adverse effects caused by welding material overflow.

[0194] In one possible implementation of this disclosure, the first barrier structure 201 and the second barrier structure 202 are silicon oxide structures.

[0195] For example, the first retaining wall structure 201 and the second retaining wall structure 202 are silicon dioxide structures.

[0196] In this implementation, silicon oxide is used to make the barrier structure, which is convenient to manufacture and can be attached to the surface of the pads, and can also block the welding material.

[0197] In other implementations, the first retaining wall structure 201 and the second retaining wall structure 202 may also be structures made of other materials, and there are no restrictions on this.

[0198] See you again Figure 5 Both the first retaining wall structure 201 and the second retaining wall structure 202 are annular stepped retaining wall structures, and the stepped surfaces of the stepped retaining wall structures face the center of the annulus.

[0199] In this implementation, the stepped structure can better block the welding material and ensure that the welding material is in the center of the welding surface.

[0200] See you again Figure 5 Both the first retaining wall structure 201 and the second retaining wall structure 202 are three-stage stepped retaining wall structures, and the height of each step in the three-stage stepped retaining wall structure is 0.2 to 0.4 micrometers.

[0201] In this implementation, the height mentioned above can meet the requirements for the amount of welding material, while not being too high and affecting the overall thickness of the light-emitting diode.

[0202] For example, the height of each step in the three-step retaining wall structure is 0.3 micrometers.

[0203] In this embodiment of the disclosure, the width of the first retaining wall structure 201 and the second retaining wall structure 202 can be 4 to 6 micrometers, for example 5 micrometers.

[0204] In other implementations, the first retaining wall structure 201 and the second retaining wall structure 202 may also be non-step structures, and there are no restrictions on this.

[0205] For example, step S26 may include:

[0206] An insulating film layer is formed on the first electrode pad and the second electrode pad;

[0207] The insulating film layer is patterned to obtain the first retaining wall structure and the second retaining wall structure.

[0208] The process of patterning the insulating film layer includes:

[0209] The insulating film layer is subjected to multiple patterning processes to form the first retaining wall structure and the second retaining wall structure with a stepped structure.

[0210] S27. Fabricate a passivation layer, the passivation layer covering the sidewalls of the epitaxial structure and the reflective layer.

[0211] In one example, step S26 includes:

[0212] A SiO2 layer is fabricated on the surface of the stepped structure using plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) techniques; the SiO2 layer is then patterned to obtain a passivation layer.

[0213] In the embodiments disclosed herein, the passivation layer may also be a transparent insulating material such as Al2O3, and the material of the passivation layer is not limited in this disclosure.

[0214] Optionally, after the above steps, the method may further include: thinning the substrate to a thickness of 400–600 micrometers, for example, 500 micrometers. Following the thinning, subsequent processes for the light-emitting diode are performed to obtain a light-emitting diode chip.

[0215] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light-emitting diode, characterized in that, The light-emitting diode includes: an epitaxial structure (1000), a first electrode (105), a second electrode (106), a reflective layer (107), a first electrode pad (108), a second electrode pad (109), a first barrier structure (201), and a second barrier structure (202). The epitaxial structure (1000) includes a first semiconductor layer (101), an active layer (102), and a second semiconductor layer (103) stacked sequentially. The first semiconductor layer (101), the active layer (102), and the second semiconductor layer (103) form a stepped structure. The first electrode (105) is located on the step surface (120) of the stepped structure, and the second electrode (106) is located on the surface of the second semiconductor layer (103). The reflective layer (107) covers the stepped structure, the first electrode (105), and the second electrode (106). The reflective layer (107) has a first through hole (111) and a second through hole (112). The first electrode pad (108) is connected to the first electrode (105) through the first through hole (111), and the second electrode pad (109) is connected to the second electrode (106) through the second through hole (112). The projection of the first via (111) on the bottom surface of the first semiconductor layer (101) is located at the edge of the projection of the first electrode pad (108) on the bottom surface of the first semiconductor layer (101), and the bottom surface of the first semiconductor layer (101) is the side away from the active layer (102). The first barrier structure (201) is located on the surface of the first electrode pad (108) and arranged along the edge of the first electrode pad (108), and the second barrier structure (202) is located on the surface of the second electrode pad (109) and arranged along the edge of the second electrode pad (109); The projection of the first via (111) on the bottom surface of the first semiconductor layer (101) is outside the projection of the first barrier structure (201) on the bottom surface of the first semiconductor layer (101).

2. The light-emitting diode according to claim 1, characterized in that, The projection of the first electrode pad (108) onto the bottom surface of the first semiconductor layer (101) is a first rectangle, and the projection of the first via (111) onto the bottom surface of the first semiconductor layer (101) is located at one corner of the first rectangle.

3. The light-emitting diode according to claim 1, characterized in that, The bottom surface of the first semiconductor layer (101) is a second rectangle, and the projection of the step surface (120) of the step structure onto the bottom surface of the first semiconductor layer (101) is located at one corner of the second rectangle.

4. The light-emitting diode according to any one of claims 1 to 3, characterized in that, The first barrier structure (201) and the second barrier structure (202) are silicon oxide structures.

5. The light-emitting diode according to any one of claims 1 to 3, characterized in that, Both the first retaining wall structure (201) and the second retaining wall structure (202) are annular stepped retaining wall structures, and the stepped surfaces of the stepped retaining wall structures face the center of the annulus.

6. The light-emitting diode according to claim 5, characterized in that, Both the first retaining wall structure (201) and the second retaining wall structure (202) are three-stage stepped retaining wall structures, and the height of each step in the three-stage stepped retaining wall structure is 0.2~0.4 micrometers.

7. A method for fabricating a light-emitting diode, characterized in that, The method includes: A first semiconductor layer, an active layer, and a second semiconductor layer are formed in sequence, and the second semiconductor layer, the active layer, and the first semiconductor layer constitute an epitaxial structure. The extensional structure is graphically processed to form a stepped structure; A first electrode and a second electrode are fabricated, wherein the first electrode is located on the step surface of the stepped structure and the second electrode is located on the surface of the second semiconductor layer. A reflective layer is fabricated, which covers the stepped structure, the first electrode, and the second electrode, and the reflective layer has a first through hole and a second through hole; A first electrode pad and a second electrode pad are fabricated. The first electrode pad is connected to the first electrode through the first through-hole, and the second electrode pad is connected to the second electrode through the second through-hole. The projection of the first through-hole on the bottom surface of the first semiconductor layer is located at the edge of the projection of the first electrode pad on the bottom surface of the first semiconductor layer. The bottom surface of the first semiconductor layer is the side away from the active layer. An insulating film layer is formed on the first electrode pad and the second electrode pad; The insulating film layer is patterned to obtain a first barrier structure and a second barrier structure. The first barrier structure is located on the surface of the first electrode pad and arranged along the edge of the first electrode pad. The second barrier structure is located on the surface of the second electrode pad and arranged along the edge of the second electrode pad. The projection of the first via on the bottom surface of the first semiconductor layer is outside the projection of the first barrier structure on the bottom surface of the first semiconductor layer.

8. The method for fabricating a light-emitting diode according to claim 7, characterized in that, The patterning process of the insulating film layer includes: The insulating film layer is subjected to multiple patterning processes to form the first retaining wall structure and the second retaining wall structure with a stepped structure.

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