Display panel and display device

Abstract

This application relates to a display panel and a display device. The display panel includes a substrate; an array layer disposed on one side of the substrate, including a plurality of driving transistors; a plurality of first electrodes disposed on the side of the array layer away from the substrate; a plurality of first capacitors, each first capacitor including a first electrode plate and a second electrode plate disposed opposite to each other, the first electrode plate being disposed on one side of the substrate and connected to the control terminal of the corresponding driving transistor; and a pixel defining layer including a first pixel defining portion and a second pixel defining portion, the first pixel defining portion being disposed on the side of the corresponding first electrode plate away from the substrate, the second electrode plate being disposed on the side of the first pixel defining portion away from the first electrode plate, and the second pixel defining portion covering a portion of the corresponding first electrode; wherein the dielectric constant of the second pixel defining portion is smaller than the dielectric constant of the first pixel defining portion. Therefore, the display panel and display device provided by this application can improve the display effect of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Organic Light Emitting Diode (OLED) display technology is considered the most promising next-generation flat panel display technology. Compared to LCD technology, OLED technology has advantages such as low energy consumption, low cost, self-emissiveness, wide viewing angle, and fast response speed. However, current OLED display panels suffer from relatively poor display quality. Summary of the Invention

[0003] Therefore, it is necessary to provide a display panel and display device that can improve the display effect.

[0004] In a first aspect, embodiments of this application provide a display panel, comprising: a substrate; an array layer disposed on one side of the substrate, including a plurality of driving transistors; a plurality of first electrodes disposed on the side of the array layer away from the substrate, the first electrodes being connected to a first terminal of a corresponding driving transistor; a plurality of first capacitors, each first capacitor including a first electrode plate and a second electrode plate disposed opposite to each other, the first electrode plate being disposed on one side of the substrate and connected to a control terminal of a corresponding driving transistor; and a pixel defining layer including a first pixel defining portion and a second pixel defining portion, the first pixel defining portion being disposed on the side of the corresponding first electrode plate away from the substrate, the orthographic projection of the first pixel defining portion on the substrate overlapping the orthographic projection of the corresponding first electrode plate on the substrate, the second electrode plate being disposed on the side of the first pixel defining portion away from the first electrode plate, the second pixel defining portion covering a portion of the corresponding first electrode; wherein the dielectric constant of the second pixel defining portion is less than the dielectric constant of the first pixel defining portion.

[0005] The display panel provided in this application embodiment has a second pixel defining portion with a dielectric constant lower than that of the first pixel defining portion; that is, the dielectric constant of the first pixel defining portion is set to be larger, and the dielectric constant of the second pixel defining portion is set to be smaller. Since the dielectric constant of the first pixel defining portion is larger, using the first pixel defining portion as the capacitor dielectric of the first capacitor helps to increase the capacitance value of the first capacitor, thereby improving the stability of the control terminal voltage of the driving transistor and thus improving the display effect of the display panel.

[0006] In one embodiment, the pixel defining layer defines a plurality of pixel openings, and the display panel further includes:

[0007] Multiple light-emitting units are disposed within the corresponding pixel openings and located on the side of the corresponding first electrode away from the array layer;

[0008] Multiple second electrodes are disposed on the side of the corresponding light-emitting unit away from the array layer;

[0009] The second plate is electrically connected to the second electrode.

[0010] Preferably, the second plate and the second electrode are configured with a first power supply voltage;

[0011] Preferably, the display panel further includes:

[0012] A partition structure is disposed on the side of the pixel limiting layer away from the substrate. The partition structure defines multiple partition openings, and the partition openings are connected to the corresponding pixel openings.

[0013] At least part of the partition structure is reused as a second electrode plate;

[0014] Preferably, the second electrode overlaps with the partition structure;

[0015] Preferably, the partition structure is configured with a first power supply voltage.

[0016] In one embodiment, the number of first pixel defining portions is one, and the number of second pixel defining portions is multiple, wherein:

[0017] The orthographic projection of the first pixel limiting portion on the substrate surrounds the orthographic projection of the plurality of second pixel limiting portions on the substrate;

[0018] Preferably, the first pixel defining portion is connected to a plurality of second pixel defining portions;

[0019] Preferably, there is a gap between adjacent first electrodes, and the orthographic projection of the first pixel defining portion on the substrate covers the orthographic projection of the gap on the substrate.

[0020] In one embodiment, the orthographic projection of the first pixel defining portion on the substrate does not overlap with the orthographic projection of the first electrode on the substrate.

[0021] In one embodiment, the first electrode plate is disposed in the same layer as the first electrode and there is a gap between them;

[0022] Preferably, the first electrode plate surrounds at least a portion of the outer periphery of the corresponding first electrode.

[0023] In one embodiment, the orthographic projection of the first electrode plate onto the substrate is located within the orthographic projection of the first pixel defining portion onto the substrate.

[0024] In one embodiment, the orthographic projection of the second pixel defining portion on the substrate does not overlap with the orthographic projection of the first electrode plate on the substrate.

[0025] In one embodiment, the array layer further includes:

[0026] Multiple second capacitors, each second capacitor including a third plate and a fourth plate disposed opposite to each other, the control terminal of the driving transistor is multiplexed to the corresponding third plate, and the orthographic projection of the fourth plate on the substrate at least partially overlaps with the orthographic projection of the control terminal of the corresponding driving transistor on the substrate.

[0027] Preferably, the fourth electrode is configured with a second power supply voltage;

[0028] Preferably, the second electrode is configured with a first power supply voltage, the voltage value of the first power supply voltage being less than the voltage value of the second power supply voltage;

[0029] Preferably, the display panel further includes:

[0030] Multiple vias, with each end of the via connected to the corresponding first electrode plate and the control terminal of the corresponding driving transistor, respectively;

[0031] Preferably, the orthographic projection of the fourth electrode plate onto the substrate surrounds at least a portion of the outer periphery of the corresponding via.

[0032] In one embodiment, the dielectric constant of the first pixel defining portion is greater than or equal to 5 F / m;

[0033] Preferably, the dielectric constant of the second pixel defining portion is less than 5 F / m;

[0034] Preferably, the difference between the dielectric constant of the first pixel defining portion and the dielectric constant of the second pixel defining portion is greater than or equal to 1 F / m.

[0035] In one embodiment, the material of at least one of the first pixel defining portion and the second pixel defining portion includes an inorganic insulating material;

[0036] Preferably, the material of the first pixel defining portion includes silicon nitride;

[0037] Preferably, the material of the second pixel defining portion includes silicon oxide.

[0038] In one embodiment, the thickness of at least one of the first pixel defining portion and the second pixel defining portion is in the range of 200nm-1000nm.

[0039] Secondly, embodiments of this application provide a display panel, comprising: a substrate; an array layer disposed on one side of the substrate, including a plurality of driving transistors; a plurality of first electrodes disposed on the side of the array layer away from the substrate, the first electrodes being connected to a first terminal of a corresponding driving transistor; a plurality of first capacitors, each first capacitor including a first electrode plate and a second electrode plate disposed opposite to each other, the first electrode plate being disposed on one side of the substrate and connected to a control terminal of a corresponding driving transistor; a pixel defining layer defining a plurality of pixel openings and including a first pixel defining portion and a second pixel defining portion, the first pixel defining portion being disposed on the side of the corresponding first electrode plate away from the substrate, the orthographic projection of the first pixel defining portion on the substrate overlapping the orthographic projection of the corresponding first electrode plate on the substrate, the second electrode plate being disposed on the side of the first pixel defining portion away from the first electrode plate, the second pixel defining portion covering a portion of the corresponding first electrode; and a partition structure disposed on the side of the pixel defining layer away from the substrate, the partition structure defining a plurality of partition openings communicating with the corresponding pixel openings, at least a portion of the partition structure being reused as a second electrode plate; wherein the dielectric constant of the second pixel defining portion is less than the dielectric constant of the first pixel defining portion.

[0040] The display panel provided in this application embodiment has a second pixel defining portion with a dielectric constant lower than that of the first pixel defining portion; that is, the dielectric constant of the first pixel defining portion is set to be larger, and the dielectric constant of the second pixel defining portion is set to be smaller. Since the dielectric constant of the first pixel defining portion is larger, using the first pixel defining portion as the capacitor dielectric of the first capacitor helps to increase the capacitance value of the first capacitor, thereby improving the stability of the control terminal voltage of the driving transistor and thus improving the display effect of the display panel.

[0041] In one embodiment, a plurality of light-emitting units are disposed within corresponding pixel openings and located on the side of the corresponding first electrode facing away from the array layer;

[0042] Multiple second electrodes are disposed on the side of the corresponding light-emitting unit away from the array layer;

[0043] The second plate is electrically connected to the second electrode.

[0044] Preferably, the second plate and the second electrode are configured with a first power supply voltage;

[0045] Preferably, the second electrode overlaps with the partition structure;

[0046] Preferably, the partition structure is configured with a first power supply voltage.

[0047] In one embodiment, the number of first pixel defining portions is one, and the number of second pixel defining portions is multiple, wherein:

[0048] The orthographic projection of the first pixel limiting portion on the substrate surrounds the orthographic projection of the plurality of second pixel limiting portions on the substrate;

[0049] Preferably, the first pixel defining portion is connected to a plurality of second pixel defining portions;

[0050] Preferably, there is a gap between adjacent first electrodes, and the orthographic projection of the first pixel defining portion on the substrate covers the orthographic projection of the gap on the substrate.

[0051] Thirdly, embodiments of this application provide a display device including the display panel described in the first and second aspects above.

[0052] The display device provided in this application includes a display panel. The dielectric constant of the second pixel defining portion is less than that of the first pixel defining portion; that is, the dielectric constant of the first pixel defining portion is set to be larger, and the dielectric constant of the second pixel defining portion is set to be smaller. Since the dielectric constant of the first pixel defining portion is larger, using the first pixel defining portion as the capacitor dielectric of the first capacitor helps to increase the capacitance value of the first capacitor, thereby improving the stability of the control terminal voltage of the driving transistor and thus improving the display effect of the display panel. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 A top-view perspective view of the first electrode, the first electrode plate, and the pixel defining layer provided in an embodiment of this application.

[0055] Figure 2 A top view of the first electrode and the first electrode plate provided in an embodiment of this application.

[0056] Figure 3 for Figure 1 Sectional view along the AA direction.

[0057] Figure 4 for Figure 3 A magnified view of a portion of the image.

[0058] Figure 5 The equivalent circuit diagram of the driving transistor, the first capacitor, the second capacitor, and the light-emitting device provided in the embodiments of this application is shown.

[0059] Explanation of reference numerals in the attached figures:

[0060] 100, Display panel; 101, Array layer; 102, Semiconductor layer; 110, Substrate; 120, Partition structure; 121, First isolation portion; 122, Second isolation portion; 123, Blocking portion; 124, Partition opening; 130, Light-emitting device; 131, First electrode; 132, Second electrode; 133, Light-emitting unit; 140, Pixel defining layer; 141, First pixel defining portion; 142, Second pixel defining portion; 143, Pixel opening; 151, First electrode plate; 152, Second electrode plate; 54. Fourth electrode plate; 1711. First via; 1721. First connector; 1722. Second connector; 181. First encapsulation layer; 182. Second encapsulation layer; 183. Third encapsulation layer; 190. Insulating layer; 1911. First insulating layer; 1921. First planarization layer; M1. First metal layer; M2. Second metal layer; M3. Third metal layer; M4. Fourth metal layer; DT. Driver transistor; DT1. First terminal; DT2. Second terminal; DT3. Control terminal; DT4. Active layer. Detailed Implementation

[0061] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0062] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0064] Organic Light Emitting Diode (OLED) display technology is considered the most promising next-generation flat panel display technology. Compared with liquid crystal display technology, OLED display technology has advantages such as low energy consumption, low cost, self-emissiveness, wide viewing angle, and fast response speed.

[0065] In related OLED display panels, the inventors discovered that in high pixel density (Pixels Per Inch, PPI) display panels, the limited area of ​​a single sub-pixel makes it difficult to increase the size of the storage capacitor in the pixel circuit. This affects the stability of the gate voltage of the driving transistor in the pixel circuit, which can cause display abnormalities such as flickering, black screens, and bright spots, resulting in poor display performance.

[0066] In view of at least one of the above problems, embodiments of this application provide a display panel and a display device that can improve the display effect of the display panel.

[0067] The following will combine Figures 1-5 The display device provided in the embodiments of this application will be described.

[0068] This application provides a display device including a display panel 100. The display device can be an electronic paper device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, smart bracelet, smartwatch, supercomputer, navigator, wireless device, personal digital assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, clock, calculator, television monitor, computer monitor, automotive display (e.g., odometer display), cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic billboard or sign, projector, and other mobile or fixed terminals.

[0069] For example, the display panel 100 can be an organic light-emitting diode (OLED) display panel, a micro organic light-emitting diode (Micro OLED) display panel, a light-emitting diode (LED) display panel, a quantum dot light-emitting diode (QLED) display panel, a mini light-emitting diode (MiniLED) display panel, a micro light-emitting diode (Micro LED) display panel, or a liquid crystal display (LCD) display panel, etc. This application embodiment uses an OLED display panel 100 as an example for illustration.

[0070] The display panel 100 provided in the embodiments of this application will be described below.

[0071] See Figure 1 This application provides a display panel 100, which may include a substrate 110. The substrate 110 may provide support for other film layers subsequently applied.

[0072] In some embodiments, see Figure 1 and Figure 3 The display panel 100 may include a plurality of first electrodes 131, which are disposed on one side of the substrate 110.

[0073] In some embodiments, see Figure 3 The display panel 100 may further include a pixel defining layer 140, which is disposed on the side of the substrate 110 near the first electrode 131 and defines a plurality of pixel openings 143. The pixel openings 143 are correspondingly disposed to the first electrodes 131. A portion of the first electrode 131 may be located between the pixel opening 143 and the substrate 110, and the pixel opening 143 exposes this portion of the first electrode 131. Another portion of the first electrode 131 may be located between the pixel defining layer 140 and the substrate 110.

[0074] For example, see Figure 1 and Figure 3The pixel defining layer 140 includes a first pixel defining portion 141 and a plurality of second pixel defining portions 142. The second pixel defining portions 142 define pixel openings 143. The first pixel defining portions 141 are disposed on the outer periphery of each second pixel defining portion 142. The second pixel defining portions 142 cover a portion of the corresponding first electrode 131.

[0075] In some embodiments, see Figure 3 The display panel 100 may include a partition structure 120 disposed on the side of the pixel defining layer 140 opposite to the substrate 110. The partition structure 120 may define a plurality of partition openings 124, which may be spaced apart. Pixel openings 143 are correspondingly connected to the partition openings 124. The orthographic projection of the pixel openings 143 on the substrate 110 may lie within the orthographic projection of the partition openings 124 on the substrate 110. At least a portion of the partition structure 120 may be formed of a conductive material.

[0076] For example, see Figure 3 and Figure 4 The orthographic projection of the first electrode 131 covered by the second pixel defining portion 142 onto the substrate 110 and the orthographic projection of the partition structure 120 onto the substrate 110 can overlap. The dielectric constant of the second pixel defining portion 142 is smaller than that of the first pixel defining portion 141, that is, the dielectric constant of the first pixel defining portion 141 is set to be larger, and the dielectric constant of the second pixel defining portion 142 is set to be smaller. By setting the dielectric constant of the second pixel defining portion 142 to be smaller, the parasitic capacitance of the partition structure 120 and the first electrode 131 can be reduced, the charge charged into the first electrode 131 under low brightness can be reduced, which is beneficial to the display uniformity of the display panel 100 under low brightness, thereby improving the display effect of the display panel 100.

[0077] For example, see Figure 3 and Figure 4 The orthographic projection of the first pixel limiting portion 141 on the substrate 110 does not overlap with the orthographic projection of the first electrode 131 on the substrate 110, thereby avoiding the first pixel limiting portion 141 being disposed between the partition structure 120 and the first electrode 131, so as to alleviate the adverse effect of the first pixel limiting portion 141 on the parasitic capacitance between the partition structure 120 and the first electrode 131.

[0078] See Figure 4 The display panel 100 may include an array layer 101, which is disposed between the first electrode 131 and the substrate 110. The array layer 101 may contain a plurality of pixel circuits, which are electrically connected to their respective first electrodes 131.

[0079] For example, a pixel circuit may include a thin-film transistor (TFT). See also Figure 4 and Figure 5 The thin-film transistor in the pixel circuit may include a driving transistor DT. The driving transistor DT is electrically connected to a corresponding first electrode 131. The first electrode 131 is electrically connected to a first terminal DT1 of the corresponding driving transistor DT. The second terminal DT2 of the driving transistor DT is configured with a second power supply voltage. For example, the second terminal DT2 of the driving transistor DT may be electrically connected to a second power supply line that provides the second power supply voltage (e.g., ELVDD). One of the first terminal DT1 and the second terminal DT2 of the driving transistor DT is the source, and the other is the drain.

[0080] The first capacitor C1 provided in the embodiments of this application will be described below.

[0081] See Figure 3 and Figure 5 The display panel 100 may include a plurality of first capacitors C1, each first capacitor C1 including a first electrode 151 and a second electrode 152 disposed opposite to each other. The first electrode 151 is located on the side of the first pixel defining portion 141 facing the substrate 110, that is, the first pixel defining portion 141 is disposed on the side of the corresponding first electrode 151 facing away from the substrate 110. The orthographic projection of the first pixel defining portion 141 on the substrate 110 overlaps with the orthographic projection of the corresponding first electrode 151 on the substrate 110, and the second electrode 152 is disposed on the side of the first pixel defining portion 141 facing away from the first electrode 151. The first pixel defining portion 141 may electrically isolate the first electrode 151 and the second electrode 152. For example, the first electrode 151 is electrically connected to a corresponding driving transistor DT, and the first electrode 151 is electrically connected to the control terminal DT3 of the corresponding driving transistor DT. The dielectric constant of the second pixel limiting portion 142 is smaller than that of the first pixel limiting portion 141. Specifically, the dielectric constant of the first pixel limiting portion 141 is set to be larger, while the dielectric constant of the second pixel limiting portion 142 is set to be smaller. With this configuration, since the dielectric constant of the first pixel limiting portion 141 is larger, using the first pixel limiting portion 141 as the dielectric of the first capacitor C1 helps increase the capacitance value of the first capacitor C1. This, in turn, improves the stability of the voltage at the control terminal DT3 of the driving transistor DT, thereby improving the display effect of the display panel 100.

[0082] In some embodiments, see Figure 3 and Figure 4At least part of the partition structure 120 is reused as the second electrode plate 152. The existing partition structure 120 in the display panel 100 is reused as the second electrode plate 152 of the first capacitor C1. There is no need to set an additional second electrode plate 152. The second electrode plate 152 of the first capacitor C1 can be formed without adding an additional film layer and corresponding mask of the display panel 100. This is beneficial to simplify the manufacturing process of the display panel 100. In addition, using the first capacitor C1 as a storage capacitor is beneficial to increase the capacitance value of the storage capacitor and avoid the high PPI design restricting the capacitance value of the storage capacitor. By increasing the capacitance value of the storage capacitor, the stability of the voltage of the control terminal DT3 of the driving transistor DT is improved, thereby improving the display effect of the display panel 100 (for example, alleviating abnormal phenomena such as flickering, black screen and bright spots in the display panel 100).

[0083] For example, a portion of the partition structure 120 may be reused as a second electrode plate 152, and this portion of the partition structure 120 reused as the second electrode plate 152 may be disposed directly opposite to the first electrode plate 151 along the thickness direction of the substrate 110. Another portion of the partition structure 120 may not overlap with the first electrode plate 151 along the thickness direction of the substrate 110, and may not be reused as the second electrode plate 152.

[0084] In other examples, the second electrode 152 may also be served by a structure other than the partition structure 120. This application implements an example of reusing part of the partition structure 120 as the second electrode 152.

[0085] For example, the first electrode 151 can be located in the array layer 101, thereby making the arrangement position of the first electrode 151 along the thickness direction of the substrate 110 more flexible. For example, the first electrode 151 can be located in the fourth metal layer M4.

[0086] For example, see Figure 1 The first electrode plate 151 can be located between the array layer 101 and the pixel limiting layer 140, so that the distance between the first electrode plate 151 and the partition structure 120 is relatively close, that is, the distance between the two electrode plates of the first capacitor C1 along the thickness direction of the substrate 110 is relatively close, which is beneficial to increase the capacitance value of the first capacitor C1, so as to improve the stability of the voltage of the control terminal DT3 of the driving transistor DT, thereby improving the display effect of the display panel 100.

[0087] For example, see Figure 1The first electrode 151 and the first electrode 131 are disposed in the same layer. The first electrode 151 and the first electrode 131 can have a gap along the extension direction of the substrate 110, so that the first electrode 151 and the first electrode 131 can be fabricated at the same time, which helps to simplify the fabrication process of the first electrode 151 and the first electrode 131. In addition, it also makes the distance between the first electrode 151 and the partition structure 120 along the thickness direction of the substrate 110 closer, which helps to increase the capacitance value of the first capacitor C1, thereby improving the stability of the voltage of the control terminal DT3 of the driving transistor DT, and thus improving the display effect of the display panel 100. The principle has been explained and will not be repeated here.

[0088] For example, see Figure 3 The first electrode plate 151 surrounds at least a portion of the outer periphery of the corresponding first electrode 131. For example, the first electrode plate 151 can be annular, which is beneficial to increasing the coverage area of ​​the first electrode plate 151 along the circumference of the first electrode 131, and to increasing the area of ​​the first electrode plate 151, thereby increasing the capacitance value of the first capacitor C1, so as to improve the stability of the voltage at the control terminal DT3 of the driving transistor DT, and thus improve the display effect of the display panel 100.

[0089] For example, see Figure 1 and Figure 2 The orthographic projection of the first electrode plate 151 on the substrate 110 is located within the orthographic projection of the first pixel limiting portion 141 on the substrate 110, so that the first pixel limiting portion 141 completely covers the first electrode plate 151, so that the capacitor medium of the first capacitor C1 is the first pixel limiting portion 141, thereby increasing the capacitance value of the first capacitor C1, improving the stability of the voltage at the control terminal DT3 of the driving transistor DT, and thus improving the display effect of the display panel 100.

[0090] For example, see Figure 1 and Figure 2 The orthographic projection of the second pixel limiting portion 142 on the substrate 110 does not overlap with the orthographic projection of the first electrode plate 151 on the substrate 110, thereby avoiding the second pixel limiting portion 142 being disposed between the first electrode plate 151 and the second electrode plate 152, thereby mitigating the adverse effect of the second pixel limiting portion 142 on the capacitance value of the first capacitor C1.

[0091] The pixel limiting layer 140 provided in the embodiments of this application will be further described below.

[0092] For example, see Figure 1The number of first pixel limiting portions 141 is one, and the number of second pixel limiting portions 142 is multiple. The orthographic projection of the first pixel limiting portion 141 on the substrate 110 surrounds the orthographic projection of the multiple second pixel limiting portions 142 on the substrate, thereby simplifying the structure of the first pixel limiting portion 141 and reducing the manufacturing cost of the pixel limiting layer 140.

[0093] For example, see Figure 1 and Figure 3 The first pixel limiting portion 141 is connected to a plurality of second pixel limiting portions 142, thereby improving the structural stability of the pixel limiting layer 140.

[0094] For example, see Figure 1 There is a gap B between adjacent first electrodes 131. The orthographic projection of the first pixel defining portion 141 on the substrate 110 covers the orthographic projection of the gap B on the substrate 110, so that the first pixel defining portion 141 and the first electrode 131 do not overlap along the thickness direction of the substrate 110, which helps to reduce the adverse effect of the first pixel defining portion 141 on the parasitic capacitance between the first electrode 131 and the partition structure 120.

[0095] For example, the dielectric constant of the first pixel defining portion 141 is greater than or equal to 5 F / m, which helps to increase the capacitance value of the first capacitor C1, thereby improving the stability of the voltage at the control terminal DT3 of the driving transistor DT, and thus improving the display effect of the display panel 100. For example, the dielectric constant of the first pixel defining portion 141 can be any value greater than 5 F / m, such as 5.5 F / m, 6 F / m, 6.5 F / m, 7 F / m, 8 F / m, or 5 F / m.

[0096] For example, the dielectric constant of the second pixel defining portion 142 is less than 5 F / m, which helps to reduce the parasitic capacitance between the isolation structure 120 and the first electrode 131. This reduces the charge charged into the first electrode 131 under low brightness, which improves the display uniformity of the display panel 100 under low brightness, thereby enhancing the display effect of the display panel 100. For example, the dielectric constant of the second pixel defining portion 142 can be any value of 1 F / m, 1.5 F / m, 2 F / m, 2.5 F / m, 3 F / m, 4 F / m, 4.5 F / m, or less than 5 F / m.

[0097] For example, the difference between the dielectric constant of the first pixel defining portion 141 and the dielectric constant of the second pixel defining portion 142 is greater than or equal to 1 F / m, which helps to reduce the parasitic capacitance between the isolation structure 120 and the first electrode 131 while increasing the capacitance value of the first capacitor C1. For example, this difference can be any value of 1 F / m, 1.5 F / m, 2 F / m, 2.5 F / m, or greater than 1 F / m.

[0098] For example, the material of at least one of the first pixel defining portion 141 and the second pixel defining portion 142 may include an inorganic insulating material. For instance, the materials of both the first pixel defining portion 141 and the second pixel defining portion 142 may include inorganic insulating materials, which helps to reduce the manufacturing cost of the first pixel defining portion 141 and the second pixel defining portion 142, helps to reduce the film thickness of the first pixel defining portion 141 and the second pixel defining portion 142, and helps to make the display panel 100 thinner and lighter.

[0099] For example, the material of the first pixel defining portion 141 includes silicon nitride (SiNy).

[0100] For example, the material of the second pixel defining portion 142 includes silicon oxide (SiOx).

[0101] For example, the thickness of the first pixel defining portion 141 is in the range of 200nm-1000nm. This avoids the thickness being too small, allowing the first pixel defining portion 141 to have a better coverage effect on the first electrode plate 151. In addition, it avoids the thickness being too large, which is beneficial for the thinning of the display panel 100 and also helps to increase the capacitance value of the first capacitor C1. For example, the thickness of the first pixel defining portion 141 can be 200nm, 400nm, 600nm, 800nm, 1000nm, or any value between 200nm and 1000nm.

[0102] For example, the thickness of the second pixel defining portion 142 is in the range of 200nm-1000nm, thereby avoiding the thickness being too small and ensuring that the second pixel defining portion 142 has a good coverage effect on part of the first electrode 131. This helps to reduce the parasitic capacitance between the partition structure 120 and the first electrode 131. In addition, it avoids the thickness being too large, thereby contributing to the thinning of the display panel 100. For example, the thickness of the second pixel defining portion 142 can be 200nm, 400nm, 600nm, 800nm, 1000nm, or any value between 200nm and 1000nm.

[0103] The second capacitor C2 provided in the embodiments of this application will be described below.

[0104] In some embodiments, see Figure 4 and Figure 5 The array layer 101 includes a plurality of second capacitors C2. Each second capacitor C2 includes a third electrode plate and a fourth electrode plate 154 disposed opposite to each other. The control terminal DT3 of the driving transistor DT is multiplexed as the corresponding third electrode plate. The orthographic projection of the fourth electrode plate 154 on the substrate 110 at least partially overlaps with the orthographic projection of the control terminal DT3 of the corresponding driving transistor DT on the substrate 110.

[0105] For example, the fourth electrode plate 154 is disposed on the side of the control terminal DT3 of the corresponding driving transistor DT facing the partition structure 120, and the first insulating layer 1911 is disposed between the control terminal DT3 of the driving transistor DT and the fourth electrode plate 154. The fourth electrode plate 154 and the control terminal DT3 of the driving transistor DT are configured together as the two electrode plates of the second capacitor C2. With this configuration, the first capacitor C1 and the second capacitor C2 are used together as storage capacitors, and the total capacitance of the storage capacitors is the sum of the capacitance values ​​of the first capacitor C1 and the second capacitor C2. Even in high PPI designs, the capacitance value of the storage capacitors can be increased to further improve the stability of the voltage at the control terminal DT3 of the driving transistor DT, thereby further improving the display effect of the display panel 100.

[0106] For example, the fourth plate 154 may be electrically connected to a second power line for inputting a second power supply voltage (e.g., ELVDD) to the fourth plate 154.

[0107] For example, the display panel 100 also includes a plurality of vias, the two ends of which are respectively connected to the corresponding first electrode plate 151 and the control terminal DT3 of the corresponding driving transistor DT. For example, the via may include a first via 1711. The first insulating layer 1911 is provided with the first via 1711, and the first electrode plate 151 and the control terminal DT3 of the driving transistor DT are electrically connected at least through the first via 1711.

[0108] For example, the orthographic projection of the fourth electrode 154 onto the substrate 110 surrounds at least a portion of the outer periphery of the corresponding first via 1711. For instance, the fourth electrode 154 can be annular, which is beneficial for increasing the coverage area of ​​the fourth electrode 154 and increasing the area of ​​the fourth electrode 154, thereby increasing the capacitance value of the second capacitor C2 to improve the stability of the voltage at the control terminal DT3 of the driving transistor DT, thereby improving the display effect of the display panel 100.

[0109] The partition structure 120 provided in the embodiments of this application will be further described below.

[0110] In some embodiments, the partition structure 120 may refer to an undercut structure that is larger at the top and smaller at the bottom, capable of separating adjacent light-emitting units 133. The partition structure 120 may be a structure formed by a single film layer or a structure formed by stacking multiple film layers.

[0111] In some embodiments, see Figure 1The partition structure 120 may include a first isolation portion 121 and a blocking portion 123. The first isolation portion 121 is located on the side of the blocking portion 123 facing the substrate 110. The orthographic projection of the first isolation portion 121 on the substrate 110 is located within the orthographic projection of the blocking portion 123 on the substrate 110, thereby making the partition structure 120 form an undercut structure that is "larger at the top and smaller at the bottom", that is, the partition structure 120 has an "eaves". In this way, during the formation of the light-emitting unit 133, the partition structure 120 can separate two adjacent light-emitting units 133.

[0112] For example, the cross-sectional shape of the partition structure 120 can be an inverted trapezoid with a larger top and a smaller bottom, a "T" shape, or an "I" shape, etc.

[0113] In some embodiments, see Figure 1 The partition structure 120 may include a second isolation portion 122, which may be located on the side of the first isolation portion 121 away from the blocking portion 123. The orthographic projection of the first isolation portion 121 on the substrate 110 may be located within the orthographic projection of the second isolation portion 122 on the substrate 110. In this way, in embodiments where the material of the partition structure 120 is a conductive material, the partition structure 120 can reduce its resistance by providing the stacked first isolation portion 121, second isolation portion 122, and blocking portion 123. Since the resistance of the partition structure 120 is small, when the first power supply voltage (e.g., ELVSS) is carried by the partition structure 120, the in-plane ELVSS voltage drop can be ignored, ensuring that the in-plane ELVSS voltage distribution is uniform and is difficult to change due to other voltages. This ensures that the charge of the storage capacitor remains unchanged and that the voltage at the control terminal DT3 of the driving transistor DT is not affected by ELVSS fluctuations. At this time, the cross-sectional shape of the partition structure 120 formed by the first isolation part 121, the second isolation part 122 and the blocking part 123 can be "I" shaped.

[0114] For example, at least one of the first isolation portion 121, the second isolation portion 122, and the blocking portion 123 may be made of a conductive material. The material of at least one of the first isolation portion 121, the second isolation portion 122, and the blocking portion 123 may include metals such as titanium, silver, copper, aluminum, and molybdenum, or alloys, or conductive oxides, such as any one or more of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), gallium zinc oxide, tantalum titanium oxide, tin oxide, cadmium oxide, and indium oxide.

[0115] For example, the material of the blocking portion 123 may include at least one of titanium and molybdenum.

[0116] For example, the material of the first isolation section 121 may include at least one of aluminum, copper, and silver.

[0117] For example, the material of the second isolation section 122 may include at least one of titanium and molybdenum.

[0118] For example, the second electrode 132 overlaps with the partition structure 120. For instance, the second electrode 132 overlaps with at least one of the first isolation portion 121 and the two isolation portions to facilitate electrical connection with the partition structure 120.

[0119] In embodiments where at least one of the first isolation portion 121, the second isolation portion 122, and the blocking portion 123 is made of a conductive material, the second electrode 132 of the light-emitting device 130 can be electrically connected to the isolation structure 120, and the isolation structure 120 can be electrically connected to the second power line, through which a first power supply voltage (e.g., ELVSS) is input to the isolation structure 120. This facilitates the electrical connection of the second electrode 132 to the second power line via the isolation structure 120, thereby inputting the first power supply voltage to the second electrode 132, thus optimizing the wiring layout of the display panel 100.

[0120] In embodiments where the material of the first isolation portion 121 is a conductive material, the second electrode 132 can be electrically connected to the first isolation portion 121. In this way, the second electrodes 132 located in each isolation opening 124 can be connected into a whole through the first isolation portion 121 to apply a first power supply voltage to the second electrodes 132, thereby optimizing the wiring layout of the display panel 100.

[0121] In embodiments where the material of the second isolation portion 122 is a conductive material, the second electrode 132 of the light-emitting device 130 can be electrically connected to the second isolation portion 122. This allows a first power supply voltage to be applied to the second electrode 132 through the second isolation portion 122, thereby optimizing the wiring layout of the display panel 100.

[0122] In embodiments where both the first isolation portion 121 and the second isolation portion 122 are made of conductive materials, the second electrode 132 of the light-emitting device 130 can be electrically connected to at least one of the first isolation portion 121 and the second isolation portion 122. A first power supply voltage can be applied to the second electrode 132 through at least one of the first isolation portion 121 and the second isolation portion 122, thereby optimizing the wiring layout of the display panel 100. For example, the second electrode 132 of the light-emitting device 130 can be connected to both the first isolation portion 121 and the second isolation portion 122, thereby improving the connection stability between the second electrode 132 and the isolation structure 120.

[0123] The structure of the partition structure 120 is described in patents PCT / CN2023 / 134518, 202310759370.2, 202310740412.8, 202310707209.0, 202311346196.5, and 202310909421.5 for reference.

[0124] The following describes the light-emitting device 130 provided in the embodiments of this application.

[0125] In some embodiments, see Figure 1 A light-emitting unit 133 and a second electrode 132 are sequentially disposed on the side of the first electrode 131 facing away from the substrate 110. Multiple light-emitting units 133 can be disposed within corresponding pixel openings 143, and each light-emitting unit 133 is located on the side of the corresponding first electrode 131 facing away from the array layer 101. Multiple second electrodes 132 can also be disposed on the side of the corresponding light-emitting unit 133 facing away from the array layer 101. The correspondingly disposed first electrode 131, light-emitting unit 133, and second electrode 132 together form a light-emitting device 130.

[0126] For example, the second electrode 152 is electrically connected to the second electrode 132. This allows the first power supply voltage of the second electrode 132 to be reused as the fixed voltage required for the second electrode 152 to be input, eliminating the need to provide a separate fixed voltage to the second electrode 152. This reduces the number of signal terminals and signal lines used for transmitting voltage signals in the display panel 100, thereby simplifying the structure of the display panel 100. In this case, both the second electrode 152 and the second electrode 132 are configured with the first power supply voltage.

[0127] For example, one of the first electrode 131 and the second electrode 132 can be an anode, and the other of the first electrode 131 and the second electrode 132 can be a cathode. This application embodiment is illustrated using the example of the first electrode 131 being the anode and the second electrode 132 being the cathode.

[0128] For example, one of the first power line and the second power line is used to transmit a high-voltage signal. Figure 5 (ELVDD in the middle), the other is used to transmit low voltage signals ( Figure 5 (e.g., ELVSS in the original text). For example, the first power line is used to transmit high voltage, meaning the second power supply voltage is a high voltage signal, and the second power line is used to transmit low voltage, meaning the first power supply voltage is a low voltage signal. The voltage value of the first power supply voltage is less than the voltage value of the second power supply voltage.

[0129] For example, the light-emitting device 130 may also include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron injection layer (EIL), an electron transport layer (ETL), a hole block layer (HBL), and an electron block layer (EBL).

[0130] For example, the plurality of light-emitting devices 130 include, but are not limited to, red light-emitting devices, green light-emitting devices, and blue light-emitting devices. In other examples, the plurality of light-emitting devices 130 may also include white light-emitting devices. For example, the light-emitting unit 133 of the red light-emitting device is formed of red light-emitting material, the light-emitting unit 133 of the green light-emitting device is formed of green light-emitting material, and the light-emitting unit 133 of the blue light-emitting device is formed of blue light-emitting material.

[0131] The encapsulation layer provided in the embodiments of this application will be described below.

[0132] In some embodiments, see Figure 1 The display panel 100 includes a first encapsulation layer 181, which may include a plurality of encapsulation portions. The encapsulation portions are correspondingly disposed with the light-emitting devices 130. The encapsulation portions cover the side of the corresponding light-emitting device 130 away from the substrate 110, and the encapsulation portions extend to the sidewall of the partition structure 120 and the side of the partition structure 120 away from the substrate 110.

[0133] In some embodiments, see Figure 1 The display panel 100 may include a second encapsulation layer 182, which is located on the side of the first encapsulation layer 181 away from the substrate 110.

[0134] In some embodiments, the display panel 100 may include a third encapsulation layer 183 located on the side of the second encapsulation layer 182 away from the substrate 110.

[0135] For example, see Figure 1 The material of the second encapsulation layer 182 can be an organic material, which helps to relieve the stress of the film layer. For example, it can be prepared by coating, inkjet printing or other methods.

[0136] For example, at least one of the first encapsulation layer 181 and the third encapsulation layer 183 can be made of inorganic materials. Inorganic encapsulation layers have a better barrier effect against water vapor and oxygen, thus achieving a better encapsulation effect. For example, they can be prepared using deposition processes, such as atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD).

[0137] The array layer 101 provided in the embodiments of this application will be further described below.

[0138] In some embodiments, see Figure 1 The array layer 101 may include a semiconductor layer 102, a first metal layer M1, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4 sequentially stacked on the substrate 110, and an insulating layer 190 is provided between each two adjacent layers of the semiconductor layer 102, the first metal layer M1, the second metal layer M2, the third metal layer M3 and the fourth metal layer M4.

[0139] For example, see Figure 1 A first planarization layer 1921 may be disposed on the side of the fourth metal layer M4 facing away from the substrate 110. The first electrode 131 and the pixel defining layer 140 are both disposed on the side of the first planarization layer 1921 facing away from the substrate 110. The first planarization layer 1921 provides good planar support for the subsequent formation of film layers.

[0140] For example, the insulating layer 190 between the third metal layer M3 and the fourth metal layer M4 can be reused as a second planarization layer.

[0141] For example, see Figure 1 The active layer DT4 of the driving transistor DT can be formed by semiconductor layer 102, the control terminal DT3 of the driving transistor DT can be formed by first metal layer M1, the fourth electrode 154 of the second capacitor C2 can be formed by second metal layer M2, and the second terminal DT2 and the first terminal DT1 of the driving transistor DT can be formed by third metal layer M3. The first electrode 151 and the control terminal DT3 of the driving transistor DT can be connected by a first connector 1721, which can be formed by third metal layer M3 and fourth metal layer M4. The first electrode 131 and the first terminal DT1 of the driving transistor DT can be connected by a second connector 1722, which can be formed by fourth metal layer M4.

[0142] For example, thin-film transistors can include at least one of metal oxide (MO) thin-film transistors, low-temperature polycrystalline silicon (LTPS) thin-film transistors, high-temperature polycrystalline silicon thin-film transistors, and amorphous silicon thin-film transistors. For instance, low-temperature polycrystalline oxide (LTPO) technology can be used, simultaneously utilizing LTPS and MO thin-film transistors as thin-film transistors in the driving unit. LTPS thin-film transistors can serve as driving thin-film transistors, exhibiting high mobility, reducing driving voltage, and achieving high refresh rates and high resolutions; MO thin-film transistors can serve as switching thin-film transistors, exhibiting low leakage current, enabling the display panel 100 to maintain good display performance at low frame rates and reducing the power consumption of the display panel 100. LTPO combines the advantages of both types of thin-film transistors.

[0143] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0144] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0145] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes: substrate; An array layer, disposed on one side of the substrate, includes multiple driving transistors; Multiple first electrodes are disposed on the side of the array layer opposite to the substrate, and the first electrodes are connected to the first terminals of the corresponding driving transistors; Multiple first capacitors, each first capacitor including a first electrode plate and a second electrode plate disposed opposite to each other, the first electrode plate being disposed on one side of the substrate, and the first electrode plate being connected to the control terminal of the corresponding driving transistor; A pixel defining layer includes a first pixel defining portion and a second pixel defining portion. The first pixel defining portion is disposed on the side of the corresponding first electrode plate away from the substrate. The orthographic projection of the first pixel defining portion on the substrate overlaps with the orthographic projection of the corresponding first electrode plate on the substrate. The second electrode plate is disposed on the side of the first pixel defining portion away from the first electrode plate. The second pixel defining portion covers a portion of the corresponding first electrode. Wherein, the dielectric constant of the second pixel defining portion is less than the dielectric constant of the first pixel defining portion; The orthographic projection of the second pixel defining portion on the substrate does not overlap with the orthographic projection of the first electrode plate on the substrate.

2. The display panel according to claim 1, characterized in that, The pixel defining layer defines a plurality of pixel openings, and the display panel further includes: Multiple light-emitting units are disposed within the corresponding pixel openings and located on the side of the corresponding first electrode away from the array layer; Multiple second electrodes are disposed on the side of the corresponding light-emitting unit away from the array layer; The second plate is electrically connected to the second electrode.

3. The display panel according to claim 2, characterized in that, The second plate and the second electrode are configured with a first power supply voltage.

4. The display panel according to claim 2, characterized in that, The display panel also includes: A partition structure is disposed on the side of the pixel defining layer opposite to the substrate, the partition structure defining a plurality of partition openings, and the partition openings communicating with the corresponding pixel openings; At least a portion of the partition structure is reused as the second electrode plate.

5. The display panel according to claim 4, characterized in that, The second electrode overlaps with the partition structure.

6. The display panel according to claim 4, characterized in that, The partition structure is configured with a first power supply voltage.

7. The display panel according to claim 1, characterized in that, The number of the first pixel defining portion is one, and the number of the second pixel defining portions is multiple, wherein: The orthographic projection of the first pixel defining portion on the substrate surrounds the orthographic projections of a plurality of second pixel defining portions on the substrate.

8. The display panel according to claim 7, characterized in that, The first pixel defining portion is connected to a plurality of second pixel defining portions.

9. The display panel according to claim 7, characterized in that, There is a gap between adjacent first electrodes, and the orthographic projection of the first pixel defining portion on the substrate covers the orthographic projection of the gap on the substrate.

10. The display panel according to any one of claims 1-3, characterized in that, The orthographic projection of the first pixel defining portion on the substrate does not overlap with the orthographic projection of the first electrode on the substrate.

11. The display panel according to any one of claims 1-3, characterized in that, The first electrode plate is disposed in the same layer as the first electrode and there is a gap between them.

12. The display panel according to claim 11, characterized in that, The first electrode plate surrounds at least a portion of the outer periphery of the corresponding first electrode.

13. The display panel according to any one of claims 1-3, characterized in that, The orthographic projection of the first electrode plate on the substrate is located within the orthographic projection of the first pixel defining portion on the substrate.

14. The display panel according to any one of claims 1-3, characterized in that, The array layer further includes: Multiple second capacitors, each second capacitor including a third plate and a fourth plate disposed opposite to each other, the control terminal of the driving transistor is multiplexed to the corresponding third plate, and the orthographic projection of the fourth plate on the substrate at least partially overlaps with the orthographic projection of the control terminal of the corresponding driving transistor on the substrate.

15. The display panel according to claim 14, characterized in that, The fourth electrode plate is configured with a second power supply voltage.

16. The display panel according to claim 15, characterized in that, The second electrode is configured with a first power supply voltage, the voltage value of the first power supply voltage being less than the voltage value of the second power supply voltage.

17. The display panel according to claim 14, characterized in that, The display panel also includes: Multiple vias are provided, with each end of the via connected to the corresponding first electrode plate and the control terminal of the corresponding driving transistor, respectively.

18. The display panel according to claim 17, characterized in that, The orthographic projection of the fourth electrode plate onto the substrate surrounds at least a portion of the outer periphery of the corresponding via.

19. The display panel according to any one of claims 1-3, characterized in that, The dielectric constant of the first pixel definition portion is greater than or equal to 5 F / m.

20. The display panel according to any one of claims 1-3, characterized in that, The dielectric constant of the second pixel defining part is less than 5 F / m.

21. The display panel according to any one of claims 1-3, characterized in that, The difference between the dielectric constant of the first pixel defining portion and the dielectric constant of the second pixel defining portion is greater than or equal to 1 F / m.

22. The display panel according to any one of claims 1-3, characterized in that, The material of at least one of the first pixel defining portion and the second pixel defining portion includes an inorganic insulating material.

23. The display panel according to any one of claims 1-3, characterized in that, The material of the first pixel definition portion includes silicon nitride.

24. The display panel according to any one of claims 1-3, characterized in that, The material of the second pixel definition portion includes silicon oxide.

25. The display panel according to any one of claims 1-3, characterized in that, The thickness of at least one of the first pixel defining portion and the second pixel defining portion is in the range of 200nm-1000nm.

26. A display panel, characterized in that, The display panel includes: substrate; An array layer, disposed on one side of the substrate, includes multiple driving transistors; Multiple first electrodes are disposed on the side of the array layer opposite to the substrate, and the first electrodes are connected to the first terminals of the corresponding driving transistors; Multiple first capacitors, each first capacitor including a first electrode plate and a second electrode plate disposed opposite to each other, the first electrode plate being disposed on one side of the substrate, and the first electrode plate being connected to the control terminal of the corresponding driving transistor; A pixel defining layer defines a plurality of pixel openings and includes a first pixel defining portion and a second pixel defining portion. The first pixel defining portion is disposed on the side of the corresponding first electrode plate away from the substrate. The orthographic projection of the first pixel defining portion on the substrate overlaps with the orthographic projection of the corresponding first electrode plate on the substrate. The second electrode plate is disposed on the side of the first pixel defining portion away from the first electrode plate. The second pixel defining portion covers a portion of the corresponding first electrode. A partition structure is disposed on the side of the pixel limiting layer opposite to the substrate. The partition structure defines a plurality of partition openings, and the partition openings are connected to the corresponding pixel openings. At least a portion of the partition structure is reused as the second electrode plate. Wherein, the dielectric constant of the second pixel defining portion is less than the dielectric constant of the first pixel defining portion; The orthographic projection of the second pixel defining portion on the substrate does not overlap with the orthographic projection of the first electrode plate on the substrate.

27. The display panel according to claim 26, characterized in that, Multiple light-emitting units are disposed within the corresponding pixel openings and located on the side of the corresponding first electrode away from the array layer; Multiple second electrodes are disposed on the side of the corresponding light-emitting unit away from the array layer; The second plate is electrically connected to the second electrode.

28. The display panel according to claim 27, characterized in that, The second plate and the second electrode are configured with a first power supply voltage.

29. The display panel according to claim 27, characterized in that, The second electrode overlaps with the partition structure.

30. The display panel according to claim 27, characterized in that, The partition structure is configured with a first power supply voltage.

31. The display panel according to claim 26, characterized in that, The number of the first pixel defining portion is one, and the number of the second pixel defining portions is multiple, wherein: The orthographic projection of the first pixel defining portion on the substrate surrounds the orthographic projections of a plurality of second pixel defining portions on the substrate.

32. The display panel according to claim 31, characterized in that, The first pixel defining portion is connected to a plurality of second pixel defining portions.

33. The display panel according to claim 31, characterized in that, There is a gap between adjacent first electrodes, and the orthographic projection of the first pixel defining portion on the substrate covers the orthographic projection of the gap on the substrate.

34. A display device, characterized in that, Includes the display panel described in any one of claims 1-33 above.

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