Display panel motherboard, manufacturing method of display panel motherboard and display device

Abstract

This application provides a display panel motherboard, a method for manufacturing the display panel motherboard, and a display device. The display device includes: a substrate; at least one test assembly disposed on one side of the substrate, the test assembly including a lap electrode and a test element group electrically connected to the lap electrode; the test element group includes a first test isolation structure and a second test isolation structure that are mutually independent, the first test isolation structure and the second test isolation structure being disposed on opposite sides of the lap electrode; the second test isolation structure being electrically connected to the lap electrode. By setting the first test isolation structure and the second test isolation structure in the test element group to be located on opposite sides of the lap electrode, and ensuring that the second test isolation structure overlaps with the lap electrode, the problematic evaporation chamber in the evaporation source can be more accurately identified even when the lap electrode has poor overlap due to evaporation problems.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel motherboard, a method for manufacturing the display panel motherboard, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the current manufacturing process of OLED display products needs improvement. Summary of the Invention

[0004] To overcome the aforementioned shortcomings in the prior art, the purpose of this application is to provide a display panel motherboard, the display panel motherboard comprising:

[0005] Substrate;

[0006] At least one test assembly disposed on one side of the substrate, the test assembly comprising a lap electrode and a group of test elements electrically connected to the lap electrode;

[0007] The test element group includes a first test isolation structure and a second test isolation structure that are separate from each other, and the first test isolation structure and the second test isolation structure are disposed on opposite sides of the overlapping electrode.

[0008] The second test isolation structure is electrically connected to the lap electrode.

[0009] In some possible implementations, in at least one of the test components, the first test isolation structure is disposed on one side of the lap electrode in a first direction, and the second test isolation structure is located on the other side of the lap electrode; the first direction is the same as or opposite to the extension direction of the preset signal line in the display panel motherboard;

[0010] Preferably, in at least one additional test component, the first test isolation structure is disposed on one side of the lap electrode in a second direction, and the second test isolation structure is located on the other side of the lap electrode; the second direction is opposite to the first direction;

[0011] Preferably, in at least one additional test component, the first test isolation structure is disposed on one side of the overlapping electrode in a third direction, and the second test isolation structure is located on the other side of the overlapping electrode; the third direction intersects with the extension direction of some signal lines in the display panel motherboard.

[0012] In some possible implementations, the lap electrode has a first opening, the second test isolation structure is located within the first opening, and the lap electrode is connected to at least one side of the second test isolation structure;

[0013] Preferably, the lap electrode is connected to at least one side of the second test isolation structure facing the first direction or opposite to the first direction.

[0014] In some possible implementations, the length of the first test isolation structure is greater than the length of the second test isolation structure in a direction parallel to the substrate and intersecting the first direction.

[0015] In some possible implementations, the extension direction of the first test isolation structure is set perpendicular to the first direction;

[0016] Preferably, the side of the first test isolation structure facing the second test isolation structure is perpendicular to the first direction.

[0017] In some possible implementations, the display panel further includes a wiring layer located on one side of the substrate and an insulating layer located on the side of the wiring layer away from the substrate, and the test element group is disposed on the side of the insulating layer away from the substrate; the first test isolation structure and the second test isolation structure are respectively electrically connected to the connection wiring located in the wiring layer through through-holes penetrating the insulating layer, and the connection wiring respectively connects the first test isolation structure and the second test isolation structure to test contacts;

[0018] Preferably, the insulating layer includes at least one planarization layer and / or a pixel delimiting layer.

[0019] In some possible implementations, the insulating layer includes a first thickness region and a second thickness region, the second thickness region being thicker than the first thickness region, and the test element group being located in the second thickness region.

[0020] In some possible implementations, the display panel motherboard includes a display panel and a test area; the test element group is located in the test area;

[0021] The display panel includes a pixel isolation structure located on one side of the substrate. The first test isolation structure and the second test isolation structure are disposed on the same layer as the pixel isolation structure. The pixel isolation structure includes spaced isolation openings.

[0022] The display panel further includes a first pixel electrode, a pixel light-emitting unit, and a second pixel electrode, which are at least partially located in the isolation opening and stacked in a direction away from the substrate; the second pixel electrode is disposed in the same layer as the overlapping electrode.

[0023] The second pixel electrode extends from the isolation opening to the side of the pixel isolation structure facing the isolation opening and is electrically connected to the pixel isolation structure.

[0024] In some possible implementations, the display panel motherboard further includes a test light-emitting unit located on the side of the overlapping electrode closer to the substrate; the test light-emitting unit and the pixel light-emitting unit are disposed on the same layer;

[0025] Preferably, the pixel light-emitting unit includes a first light-emitting unit and a second light-emitting unit, and the display panel motherboard includes at least two test element groups, which are respectively disposed corresponding to the first light-emitting unit and the second light-emitting unit. The test element group disposed corresponding to the first light-emitting unit has the same material as the first light-emitting unit.

[0026] Preferably, in at least two test element groups with the same emission color of the test light-emitting unit, along the first direction, the first test isolation structure and the second test isolation structure are arranged sequentially in at least one test element group, and the second test isolation structure and the first test isolation structure are arranged sequentially in the other test element group;

[0027] Preferably, in at least two test element groups with the same emission color of the test light-emitting unit, two adjacent test element groups share the first test isolation structure, wherein the second test isolation structure of one test element group is disposed on one side of the first test isolation structure in the extension direction of the preset signal line in the display panel motherboard, and the second test isolation structure of the other test element group is disposed on the side of the first test isolation structure opposite to the extension direction of the preset signal line in the display panel motherboard.

[0028] Preferably, in at least two test element groups with the same emission color of the test light-emitting unit, two adjacent test element groups share the second test isolation structure, wherein the first test isolation structure of one test element group is disposed on one side of the second test isolation structure in the extension direction of the preset signal line in the display panel motherboard, and the first test isolation structure of the other test element group is disposed on the side of the second test isolation structure opposite to the extension direction of the preset signal line in the display panel motherboard.

[0029] In some possible implementations, the first test isolation structure, the second test isolation structure, and the pixel isolation structure include a first sub-layer and a second sub-layer stacked in a direction away from the substrate, wherein the orthographic projection of the first sub-layer on the substrate is located within the orthographic projection of the second sub-layer on the substrate;

[0030] Preferably, the material of the first sublayer includes aluminum, and / or the material of the second sublayer includes titanium;

[0031] Preferably, the first test isolation structure, the second test isolation structure, and the pixel isolation structure further include a third sub-layer located between the first sub-layer and the substrate;

[0032] Preferably, the orthographic projection of the third sublayer on the substrate lies within the orthographic projection of the second sublayer on the substrate;

[0033] Preferably, the material of the third sublayer includes molybdenum.

[0034] In some possible implementations, the display panel motherboard further includes a test packaging unit located on the side of the lap electrode away from the substrate and covering the lap electrode;

[0035] Preferably, at least a portion of the test packaging unit extends from between the first test isolation structure and the second test isolation structure to the side of the first test isolation structure and the second test isolation structure away from the substrate;

[0036] Preferably, the display panel motherboard further includes a pixel packaging unit located on the side of the second pixel electrode away from the substrate, at least a portion of the pixel packaging unit extending from the isolation opening to the side of the pixel isolation structure away from the substrate; the pixel packaging unit and the test packaging unit are disposed on the same layer;

[0037] Preferably, the display panel motherboard further includes a second encapsulation layer and a third encapsulation layer stacked on the side of the pixel encapsulation unit and the test encapsulation unit away from the substrate and in a direction away from the substrate;

[0038] Preferably, the materials of the pixel packaging unit, the test packaging unit, and the third packaging layer include inorganic materials, and the material of the second packaging layer includes organic materials.

[0039] Another object of this application is to provide a method for manufacturing a display panel motherboard, the method comprising:

[0040] Provide a substrate;

[0041] At least one test assembly is formed on one side of the substrate, the test assembly including a lap electrode and a group of test elements electrically connected to the lap electrode;

[0042] The test element group includes a first test isolation structure and a second test isolation structure that are separate from each other. The first test isolation structure and the second test isolation structure are disposed on opposite sides of the overlapping electrodes.

[0043] The second test isolation structure is electrically connected to the lap electrode.

[0044] In some possible implementations, the display panel motherboard includes a display panel and a test area, and the test components are disposed in the test area;

[0045] The display panel further includes a pixel isolation structure located on one side of the substrate, the pixel isolation structure being disposed on the same layer as the first test isolation structure and the second test isolation structure; the step of forming at least one test component on one side of the substrate includes:

[0046] A first test isolation structure and a second test isolation structure are formed in the test area, and a pixel isolation structure is formed in the display panel, the pixel isolation structure including spaced isolation openings;

[0047] An overlap electrode is disposed between the first test isolation structure and the second test isolation structure, and a second pixel electrode is formed in the display panel at least partially located in the isolation opening. The second pixel electrode extends from the isolation opening to the side of the pixel isolation structure facing the isolation opening and contacts the pixel isolation structure.

[0048] Preferably, the method further includes:

[0049] For the test element group, determine the bonding effect between the second pixel electrode and the pixel isolation structure;

[0050] After the test is completed, the test area is cut.

[0051] In some possible implementations, the evaporation directions of the second pixel electrode and the overlapping electrode include a first direction and a second direction in which they are disposed opposite to each other; the test assembly includes at least one first test isolation structure, the overlapping electrode and the second test isolation structure distributed along the first direction; the test assembly further includes at least one second test isolation structure, the overlapping electrode and the first test isolation structure distributed along the second direction.

[0052] Determining the overlap effect between the second pixel electrode and the pixel isolation structure on the test element group further includes:

[0053] The first lap resistance between the first test isolation structure and the second test isolation structure distributed along the first direction is obtained by the testing equipment; the second lap resistance between the first test isolation structure and the second test isolation structure distributed along the second direction is obtained by the testing equipment.

[0054] The overlap effect when the second pixel electrode overlaps with the pixel isolation structure along the second direction is determined based on the first overlap resistance; the overlap effect when the second pixel electrode overlaps with the pixel isolation structure along the first direction is determined based on the second overlap resistance.

[0055] Another object of this application is to provide a display device comprising a display panel manufactured by the manufacturing method of the display panel motherboard provided in this application.

[0056] Compared with the prior art, this application has the following beneficial effects:

[0057] This application provides a display panel motherboard, a method for manufacturing the display panel motherboard, and a display device. By setting the first test isolation structure and the second test isolation structure in the test element group to be located on both sides of the overlapping electrode, and ensuring that the second test isolation structure overlaps with the overlapping electrode, the problematic vapor deposition chamber in the vapor deposition source can be more accurately determined when the overlapping electrode has poor overlap due to vapor deposition problems. Attached Figure Description

[0058] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 A perspective view of the existing test component group;

[0060] Figure 2 This is a cross-sectional schematic diagram of the existing test component group;

[0061] Figure 3 This is one of the cross-sectional schematic diagrams of the display panel motherboard provided in this embodiment;

[0062] Figure 4 This is a second cross-sectional schematic diagram of the display panel motherboard provided in this embodiment;

[0063] Figure 5 This is one of the perspective schematic diagrams of the display panel motherboard provided in this embodiment;

[0064] Figure 6 This is the second perspective view of the display panel motherboard provided in this embodiment;

[0065] Figure 7 This is the third perspective view of the display panel motherboard provided in this embodiment;

[0066] Figure 8 This is the fourth perspective view of the display panel motherboard provided in this embodiment;

[0067] Figure 9 This is the fifth perspective view of the display panel motherboard provided in this embodiment;

[0068] Figure 10 This is the sixth perspective view of the display panel motherboard provided in this embodiment;

[0069] Figure 11 This is the third cross-sectional schematic diagram of the display panel motherboard provided in this embodiment;

[0070] Figure 12 This is the fourth cross-sectional schematic diagram of the display panel motherboard provided in this embodiment;

[0071] Figure 13 This is a schematic diagram of the area of ​​the display panel motherboard provided in this embodiment;

[0072] Figure 14 This is the seventh cross-sectional schematic diagram of the display panel motherboard provided in this embodiment;

[0073] Figure 15 This is the seventh perspective view of the display panel motherboard provided in this embodiment;

[0074] Figure 16 This is the eighth perspective view of the display panel motherboard provided in this embodiment;

[0075] Figure 17 This is a schematic diagram of the isolation structure layer provided in this embodiment;

[0076] Figure 18This is the eighth cross-sectional schematic diagram of the display panel motherboard provided in this embodiment;

[0077] Figure 19 This is the ninth cross-sectional schematic diagram of the display panel motherboard provided in this embodiment;

[0078] Figure 20 A flowchart illustrating the manufacturing method of the display panel provided in this embodiment.

[0079] Icons: 110 - Substrate; 111 - Array film structure; 112 - Other films; 113 - Connection traces; 114 - Planarization layer; 115 - Pixel boundary layer; 123 - First pixel electrode; 141, 141A, 141B - First test isolation structure; 142, 142A, 142B - Second test isolation structure; 145 - Pixel isolation structure; 150, 151, 151A, 151B - Test light-emitting unit; 153 - Pixel light-emitting unit; 160, 1 61, 161A, 161B - Overlapping electrodes; 163 - Second pixel electrode; 171, 171A, 171B - Test packaging unit; 173 - Pixel packaging unit; 180 - Second packaging layer; 190 - Third packaging layer; 200 - Test contact; 1401 - First sub-layer; 1402 - Second sub-layer; 1403 - Third sub-layer; AA - Display panel; NA1 - Test area; NA2 - Bonding area; D1 - First direction; D2 - Second direction; D3 - Third direction. Detailed Implementation

[0080] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0081] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0082] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0083] In the description of this application, it should be noted that the terms "center," "upper," "lower," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0084] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0085] In some display panels, an isolation structure is incorporated within the panel, allowing for the formation of different color light-emitting units and cathodes within different pixel openings through a process of etching after full-layer vapor deposition. Patent applications PCT / CN2023 / 134518, 202310759370.2, 202310740412.8, 202310707209.0, and 202311346196.5 describe relevant technical solutions for this isolation structure, the contents of which are incorporated herein by reference.

[0086] In such display panels, the vapor-deposited cathode typically needs to be overlapped with the sidewall of the isolation structure to allow a common voltage to be transmitted to the cathode through the isolation structure. To determine the vapor deposition effect of the cathode, a test area is set up outside the display panel during the manufacturing process of some display panel motherboards. The test area includes a Test Element Group (TEG). The overlap resistance between the isolation structure and the cathode in the TEG is measured to determine the overlap effect between each isolation structure and the cathode in the display area.

[0087] Specifically, please see Figure 1 , Figure 1 This is a partial perspective view of an existing test element group, which includes a first test isolation structure 141' disposed on the same layer as the pixel isolation structure of the display panel AA. The first test isolation structure 141' encloses and forms a test opening, and the test opening has a similar shape to the isolation opening of the pixel isolation structure located on the display panel AA. A second test isolation structure 142' is also disposed in the test opening.

[0088] Please see Figure 2 , Figure 2 for Figure 1A cross-sectional view of position AA shows that the existing display panel may include a substrate 110', a connection trace 113' located on one side of the substrate 110', and an insulating layer 130' located on the side of the connection trace 113' away from the substrate 110'. The first test isolation structure 141' and the second test isolation structure 142' are located on the side of the insulating layer 130' away from the substrate 110'.

[0089] While pixel light-emitting units and pixel cathodes are formed on the display panel AA through whole-layer vapor deposition, test light-emitting units 150' and test cathodes 160' are also formed in the test opening. Thus, the overlap effect of the first test isolation structure 141' and the test cathode 160' can reflect the overlap effect of the pixel isolation structure and pixel cathode in the display panel AA. Specifically, in scenarios using a linear vapor deposition source for moving vapor deposition, if the moving direction of the vapor deposition source is either the first direction D1 or the second direction D2 (the first direction D1 and the second direction D2 are opposite), the vapor-deposited test cathode ' mainly overlaps with the first test isolation structure 141' and the second test isolation structure 142' on the first direction D1 and the second direction D2.

[0090] Based on this, the method for testing the bonding effect of the first test isolation structure 141' and the test cathode 160' is to connect the first test isolation structure 141' and the second test isolation structure 142' to the test contacts respectively by connecting wire 113', and determine the bonding effect of the first test isolation structure 141' and / or the second test isolation structure 142' with the test cathode 160' by detecting the resistance between the first test isolation structure 141' and the second test isolation structure 142'.

[0091] However, in the above structure, since the first test isolation structure 141' is a ring structure and the second test isolation structure 142' is located inside the first test isolation structure 141', the second test isolation structure 142' will be covered in both directions of movement of the vapor deposition source. Furthermore, the first test isolation structure 141' on either side overlaps with the test cathode 160', and test results can be obtained. However, when an overlap problem is found based on the test results, it can only be determined that there is a problem with the vapor deposition source, but it cannot be directly determined which direction the vapor deposition chamber is facing due to the problem. Further testing and analysis are required, which increases the testing difficulty and cost.

[0092] In view of this, this embodiment provides a solution that can more accurately identify the vapor deposition chamber with problems in the vapor deposition source. The solution provided in this embodiment will be described in detail below.

[0093] Please see Figure 3 and Figure 4 , Figure 3 and Figure 4This is a schematic diagram of a display panel motherboard provided in this embodiment. The display panel motherboard may include a substrate 110 and at least one test component disposed on one side of the substrate 110.

[0094] The substrate 110 may be a flexible substrate or a rigid substrate. An array film structure 111 may be disposed on one side of the substrate 110. The array film structure 111 may include multiple film structures such as a buffer layer, an active layer, multiple metal layers, multiple insulating layers, and a planarization layer 114. Multiple thin-film transistors (TFTs) can be formed at different locations on the array film structure 111, and these TFTs can cooperate to form multiple pixel driving units.

[0095] The test assembly may include a lap electrode 161 and a group of test elements electrically connected to the lap electrode 161.

[0096] The test element group includes a first test isolation structure 141 and a second test isolation structure 142 that are separate from each other. The first test isolation structure 141 and the second test isolation structure 142 are disposed on opposite sides of the lap electrode 161.

[0097] The second test isolation structure 142 is electrically connected to the lap electrode 161. Depending on the vapor deposition formation of the lap electrode 161, the second test isolation structure 142 may at least partially overlap with or not contact the lap electrode 161.

[0098] Based on the above design, in this embodiment, by setting the first test isolation structure 141 and the second test isolation structure 142 in the test element group to be located on both sides of the overlapping electrode 161 respectively, and ensuring that the second test isolation structure 142 overlaps with the overlapping electrode 161, the problematic vapor deposition chamber in the vapor deposition source can be more accurately determined according to the relative position of the first test isolation structure 141 when the overlapping electrode 161 has poor overlap due to vapor deposition problems.

[0099] Optionally, in some possible implementations, in at least one test component, a first test isolation structure 141 is disposed on one side of the lap electrode 161 in a first direction D1, and a second test isolation structure 142 is located on the other side of the lap electrode 161. The first direction D1 is the extension direction of a preset signal line in the display panel motherboard.

[0100] Optionally, when the overlapping electrode 161 is formed by vapor deposition, the linear vapor deposition source usually moves along the extension direction of the preset signal line. Therefore, in this embodiment, the first direction D1 is the same as or opposite to the vapor deposition direction of the overlapping electrode 161. The vapor deposition direction is the moving direction of the vapor deposition source when the overlapping electrode 161 is formed by vapor deposition. The preset signal line can be a scan signal line, data signal line or power signal line used for the normal operation of the pixel circuit in the display panel, which is usually a scan signal line.

[0101] For example, please see again Figure 3 In a direction parallel to the substrate 110, the test element group includes a first test isolation structure 141 and a second test isolation structure 142 disposed at intervals, and a lap electrode 161 is located between the first test isolation structure 141 and the second test isolation structure 142.

[0102] Furthermore, please see again Figure 4 In some possible implementations, the lap electrode 161 has a first opening, the second test isolation structure 142 is located within the first opening, and the lap electrode 161 is connected to at least one side of the second test isolation structure 142. For example, the lap electrode 161 is connected to at least one side of the second test isolation structure 142 facing or opposite to the first direction D1, that is, the lap electrode 161 is connected to at least one side of the second test isolation structure 142 facing or opposite to the vapor deposition direction.

[0103] That is, in this embodiment, the orthogonal projection of the lap electrode 161 on the substrate 110 surrounds the orthogonal projection of the second test isolation structure 142 on the substrate 110. In this way, it can be ensured that the lap electrode 161 is connected to at least one side of the second test isolation structure 142, thereby eliminating the influence of the second test isolation structure 142 on the test results.

[0104] In this case, at most one side of the first test isolation structure 141 (the side facing the second test isolation structure 142) can overlap with the lap electrode 161. By testing the resistance between the first test isolation structure 141 and the second test isolation structure 142, it can be determined whether the lap electrode 161 is well overlapped with the first test isolation structure 141, thereby determining the vapor deposition effect of the lap electrode 161.

[0105] For example, in the preferred case of vapor deposition of the overlapping electrode 161, the overlapping electrode 161 overlaps with the side of the first test isolation structure 141 facing the second test isolation structure 142, and the overlapping electrode 161 also overlaps with the side of the second test isolation structure 142 facing the first test isolation structure 141 and the side away from the first test isolation structure 141. That is, the first test isolation structure 141 only overlaps with the overlapping electrode 161 on the side facing the second test isolation structure 142, while both sides of the second test isolation structure 142 overlap with the overlapping electrode 161. In this way, it can be detected that the resistance between the first test isolation structure 141 and the second test isolation structure 142 in the test assembly is normal, thereby determining that there is no problem with the vapor deposition chamber in the corresponding direction.

[0106] For example, if the vapor deposition of the lap electrode 161 is poor along the second direction D2, the lap electrode 161 will not contact the first test isolation structure 141, and the lap electrode 161 will only overlap with the side of the second test isolation structure 142 opposite to the first test isolation structure 141. In this way, an abnormal resistance between the first test isolation structure 141 and the second test isolation structure 142 in the test assembly can be detected, thereby determining that there is a problem with the vapor deposition chamber in the corresponding direction.

[0107] Optionally, the lap electrode 161 is connected to at least one side of the second test isolation structure 142 facing or opposite to the first direction D1. For example, the lap electrode 161 is connected to at least one side of the second test isolation structure 142 facing or opposite to the evaporation direction. In this way, the presence of a problem in the evaporation chamber with the evaporation source facing one direction can be determined by the test assembly.

[0108] For some possible implementations, please refer again. Figure 3 and Figure 4 In at least one test component, a first test isolation structure 141A is disposed on one side of the lap electrode 161A in a first direction D1, and a second test isolation structure 142A is located on the other side of the lap electrode 161A.

[0109] That is, in a direction parallel to the substrate 110, the test assembly includes a first test isolation structure 141A and a second test isolation structure 142A arranged sequentially along the first direction D1, and the lap electrode 161A is located between the first test isolation structure 141A and the second test isolation structure 142A.

[0110] The vapor deposition source may include a vapor deposition chamber that moves in a first direction D1 and another vapor deposition chamber that moves in a second direction D2, with the first direction D1 opposite to the second direction D2. Thus, this test assembly can determine whether there is a problem with the vapor deposition chamber moving in the second direction D2 within the vapor deposition source.

[0111] Alternatively, see [link to relevant documentation] for some possible implementations. Figure 5 and Figure 6 In at least one additional test component, a first test isolation structure 141B is disposed on one side of the lap electrode 161B in the second direction D2, and a second test isolation structure 142B is located on the other side of the lap electrode 161B.

[0112] That is, in a direction parallel to the substrate 110, the test assembly includes a first test isolation structure 141B and a second test isolation structure 142B arranged sequentially along the second direction D2, and the lap electrode 161B is located between the first test isolation structure 141B and the second test isolation structure 142B.

[0113] Thus, this test component can be used to determine whether there is a problem with the vapor deposition chamber in the vapor deposition source facing the first direction D1.

[0114] The two test components mentioned above, when used together, can determine which side of the vapor deposition chamber is facing in the direction the vapor deposition source is moving.

[0115] Specifically, when there is a problem with the vapor deposition of the overlapping electrode layer, if the resistance between the first test isolation structure 141A and the second test isolation structure 142A is abnormal, while the resistance between the first test isolation structure 141B and the second test isolation structure 142B is normal, it can be determined that there is a problem with the vapor deposition chamber in the vapor deposition source facing the second direction D2; if the resistance between the first test isolation structure 141A and the second test isolation structure 142A is normal, while the resistance between the first test isolation structure 141B and the second test isolation structure 142B is abnormal, it can be determined that there is a problem with the vapor deposition chamber in the vapor deposition source facing the first direction D1.

[0116] Alternatively, for other implementations, please refer to [link / reference]. Figure 7 In at least one additional test component, a first test isolation structure 141C is disposed on one side of the lap electrode 161C in a third direction D3, and a second test isolation structure 142C is located on the other side of the lap electrode 161C. The third direction D3 intersects with the first direction D1; for example, the third direction D3 intersects with the vapor deposition direction of the lap electrode 163C.

[0117] Thus, the bonding effect between the overlapping electrode 161C and the first test isolation structure 141C in the non-evaporation direction can be determined using this test assembly.

[0118] See also: [Information on possible implementations] Figure 8In a direction parallel to the substrate 110 and intersecting the evaporation direction, the length D1 of the first test isolation structure 141 is greater than the length D2 of the second test isolation structure 142. For example, the length D1 of the first test isolation structure 141 is greater than the length D3 of the lap electrode 161, and the length D2 of the second test isolation structure 142 is less than the length D3 of the lap electrode 161. The lap electrode 161 can be formed by evaporating a conductive material in a whole layer and then performing patterned etching. During this process, the length of the lap electrode 161 retained after etching can be controlled by controlling the distribution of the etching barrier material (e.g., photoresist).

[0119] In this way, it can be ensured that the overlapping electrode 161 overlaps with at most one side of the first test isolation structure 141. Moreover, the overlapping electrode 161 can cover and surround the second test isolation structure 142, ensuring that the overlapping electrode 161 overlaps with at least one side of the second test isolation structure 142, thus eliminating the interference of the second test isolation structure 142 on the test results.

[0120] In some possible implementations, the side of the first test isolation structure 141 facing the second test isolation structure 142 is perpendicular to the vapor deposition direction.

[0121] That is, the side of the first test isolation structure 141 facing the second test isolation structure 142 is perpendicular to the direction of movement of the vapor deposition source. In this way, the overlapping effect of the first test isolation structure 141 and the overlapping electrode 161 and the overlapping effect of the overlapping electrode 162B can more accurately reflect the vapor deposition effect of the vapor deposition chambers with the vapor deposition source facing different directions.

[0122] In some possible implementations, the first test isolation structure 141 and the second test isolation structure 142 are respectively connected to the test contact 200 through the connection trace 113 in the array film structure 111.

[0123] For example, please see again Figure 3 and Figure 5 The array film structure 111 includes other film layers 112 located on one side of the substrate 110, a wiring layer located on the side of the other film layers 112 away from the substrate 110, and an insulating layer located on the side of the wiring layer away from the substrate 110. The test element group is disposed on the side of the insulating layer away from the substrate 110. The insulating layer includes at least one planarization layer 114 and / or a pixel defining layer 115. The other film layers 112 include, but are not limited to, device layers, dielectric layers, wiring layers, etc. located on the substrate 110.

[0124] The first test isolation structure 141 and the second test isolation structure 142 are electrically connected to the connection trace 113 located in the trace layer through through-holes penetrating the insulation layer.

[0125] Please see Figure 9 and Figure 10 The connecting wires 113 connect the first test isolation structure 141 and the second test isolation structure 142 to the test contact 200 respectively.

[0126] Thus, the test equipment can detect the resistance between the first test isolation structure 141 and the second test isolation structure 142 connected by the lap electrode 161 through the test contact 200.

[0127] Optionally, the first test isolation structure 141 and the second test isolation structure 142 can both be connected to the two test contacts 200 via connecting lines 113. The two test contacts 200 can be used to connect to the current acquisition and voltage acquisition terminals of the test equipment, respectively.

[0128] In some possible implementations, the insulating layer includes a first thickness region WA1 and a second thickness region WA2, the thickness H2 of the second thickness region WA2 being greater than the thickness H1 of the first thickness region WA1, and the test element group being located in the second thickness region WA2.

[0129] Thus, the first test isolation structure 141 and the second test isolation structure 142 are located on the boss structure formed by the insulating layer, thereby avoiding excessive accumulation of etching solution between the test isolation structures during the wet etching process, which could damage the lap electrode 161 and ensure the accuracy of subsequent test results.

[0130] Alternatively, in some possible implementations, please refer again. Figure 11 and Figure 12 At the connection points between the first test isolation structure 141 and the second test isolation structure 142 and the connection trace 113 via a through-hole penetrating the insulating layer, the pixel defining layer 115 can cover the sidewall of the planarization layer 114 facing the through-hole. The material of the pixel defining layer 115 may include inorganic materials. In this way, the pixel defining layer 115 protects the planarization layer 114 at the through-hole from exposure, thereby reducing the risk of moisture intrusion into the planarization layer 114.

[0131] See also: [Information on possible implementations] Figure 13 The display panel motherboard includes the display panel AA and the test area NA1, and the test component group is located in the test area NA1.

[0132] For example, in one instance, a bonding area NA2 for connection to a driver chip or other circuit board may be provided on one side of the display panel AA, and a test area NA1 may be located on the side of the bonding area NA2 away from the display panel AA.

[0133] In other examples, the test area NA1 may also be located in other positions that do not overlap with the display panel AA, and this embodiment does not impose any specific limitations.

[0134] In this embodiment, please refer to Figure 14 The isolation structure layer also includes a pixel isolation structure 145 located on the display panel AA. That is, the first test isolation structure 141 and the second test isolation structure 142 are disposed in the same layer as the pixel isolation structure 145 on the display panel AA, and have similar or identical cross-sectional morphology. The display panel also includes an insulating layer, and the pixel isolation structure 145 is disposed on the side of the insulating layer facing away from the substrate 110. The pixel isolation structure 145 is located in the first thickness region WA1 of the insulating layer.

[0135] The pixel isolation structure 145 surrounds and forms spaced-apart isolation openings. The display panel also includes a first pixel electrode 123, a pixel light-emitting unit 153, and a second pixel electrode 163, which are at least partially located in the isolation openings and stacked in a direction away from the substrate 110. The second pixel electrode 163 is disposed in the same layer as the overlapping electrode 161. The second pixel electrode 163 extends from inside the isolation openings to the side of the pixel isolation structure 145 facing the isolation openings and is electrically connected to the pixel isolation structure 145.

[0136] For example, in the display panel AA, the array film structure 111 may further include a first pixel electrode 123 located on the side of the planarization layer 114 away from the substrate 110. A pixel defining layer 115 is located on the side of the first pixel electrode 123 away from the substrate 110, and the pixel defining layer 115 includes a pixel opening that exposes at least a portion of the first pixel electrode 123. A pixel isolation structure 145 is located on the side of the pixel defining layer 115 away from the substrate 110, and the orthographic projection of the pixel opening onto the substrate 110 lies within the orthographic projection of the isolation opening onto the substrate 110; that is, the isolation opening communicates with the pixel opening to expose at least a portion of the first pixel electrode 123.

[0137] At least a portion of the pixel light-emitting unit 153 is located within the pixel opening and / or the isolation opening, and is located on the side of the first pixel electrode 123 away from the substrate 110. At least a portion of the second pixel electrode 163 is located within the pixel opening and / or the isolation opening, and is located on the side of the pixel light-emitting unit 153 away from the substrate 110. The second pixel electrode 163 extends from the isolation opening and / or the pixel opening to the pixel isolation structure 145 on the side facing the isolation opening and contacts the pixel isolation structure 145.

[0138] Thus, in this embodiment, the first test isolation structure 141 and the second test isolation structure 142 are manufactured using the same process as the pixel isolation structure 145 located in the display panel AA, and the second pixel electrode 163 is manufactured using the same process as the overlapping electrode 161A and the overlapping electrode 161B. Therefore, the overlapping effect of the first test isolation structure 141 and the overlapping electrode 161 can directly reflect the overlapping effect of the pixel isolation structure 145 and the second pixel electrode 163 in the display panel AA.

[0139] In some possible implementations, when the second pixel electrode 163 extends to connect with the pixel isolation structure 145 on only one side, i.e., there is only one vapor deposition direction to fabricate the connection between the second pixel electrode 163 and the pixel isolation structure 145 on one side, only at least one test element group can be set. The first test isolation structure 141 and the second test isolation structure 142 within the at least one test element group are arranged in the same direction, which is the side where the second pixel electrode 163 overlaps with the pixel isolation structure 145. For example, if the second pixel electrode 163 overlaps with the pixel isolation structure 145 on the side facing the first direction D1, then the first test isolation structure 141 is set on the side of the overlapping electrode 161 according to the first direction D1.

[0140] In some possible implementations, when the second pixel electrode 163 extends to connect with the pixel isolation structure 145 on both sides, two opposing vapor deposition directions are required to fabricate the connection between the second pixel electrode 163 and the pixel isolation structure 145 located on opposite sides. Therefore, at least two test element groups are needed. In one test element group, the first test isolation structure 141 and the second test isolation structure 142 are arranged in one vapor deposition direction, while in the other test element group, the first test isolation structure 141 and the second test isolation structure 142 are arranged in the other vapor deposition direction. For example, if one vapor deposition direction is the first direction, then the first test isolation structure 141 is located on one side of the overlapping electrode 161 in the first direction. If the other vapor deposition direction is the second direction opposite to the first direction, then the first test isolation structure 141 is located on the side of the overlapping electrode 161 opposite to the first direction.

[0141] Please refer again to some possible implementation methods. Figure 3 and Figure 5 The display panel motherboard also includes a test light-emitting unit 151 located on the side of the lap electrode 161 near the substrate 110. The test light-emitting unit 151 and the pixel light-emitting unit 153 are disposed on the same layer. That is, the test light-emitting unit 151 is formed in the test area NA1 at the same time as the pixel light-emitting unit 153 is formed in the display panel AA.

[0142] It should be noted that in this embodiment, it is not necessary to set the test electrode corresponding to the first pixel electrode 123 at the position corresponding to the test element group, or the test electrode corresponding to the first pixel electrode 123 can be set at the test element group and the corresponding position. No specific limitation is made in this embodiment.

[0143] In this embodiment, the pixel light-emitting unit 153 includes a first light-emitting unit and a second light-emitting unit, and the display panel motherboard includes at least two test element groups. The at least two test element groups are respectively disposed corresponding to the first light-emitting unit and the second light-emitting unit. The test element group disposed corresponding to the first light-emitting unit has the same material as the first light-emitting unit.

[0144] For example, if the display panel includes sub-pixels with at least two emission colors, the display panel motherboard includes at least two test element groups, and the emission colors of the test emission units 151 corresponding to the at least two test element groups are different. If one side of the second pixel electrode 163 overlaps with the pixel isolation structure 145, at least one test element group is set to test the overlap of the second pixel electrode 163 corresponding to the first emission unit, and at least one test element group is also set to test the overlap of the second pixel electrode 163 corresponding to the second emission unit. If both sides of the second pixel electrode 163 overlap with the pixel isolation structure 145, at least two test element groups with different arrangement directions of the first test isolation structures 141 are required to test the overlap of the second pixel electrode corresponding to the first emission unit, and similarly, at least two test element groups with different arrangement directions of the first test isolation structures 141 are also required to test the overlap of the second pixel electrode corresponding to the second emission unit.

[0145] It should be noted that in this embodiment, the test light-emitting unit 151 does not actually emit light. The light emission color of the test light-emitting unit 151 refers to the light emission color that the material used in the test light-emitting unit 151 can produce when energized.

[0146] That is, in this embodiment, since the pixel light-emitting unit 153 and the second pixel electrode 163 corresponding to sub-pixels of different colors are formed in different evaporation processes and have certain differences, at least one test element group can be set for sub-pixels of different colors to test the overlap effect of the second pixel electrode 163 and the pixel isolation structure 145 of sub-pixels of different colors.

[0147] In some possible implementations, in at least two test element groups where the light emission color of the test light emission unit 151 is the same, along the first direction D1, at least one test element group has a first test isolation structure 141 and a second test isolation structure 142 arranged in sequence, and another test element group has a second test isolation structure 142 and a first test isolation structure 141 arranged in sequence.

[0148] That is, in at least two test element groups where the light emission color of the test light emission unit 151 is the same, the first test isolation structure 141 and the second test isolation structure 142 are arranged in different directions.

[0149] That is, for each sub-pixel of a given emission color, at least two test element groups can be set. For example, for each sub-pixel of a given emission color, at least two test element groups can be set. Figure 4 and Figure 6 The test element groups shown are arranged in two ways, or other arrangements can be set. The arrangement is such that the arrangement direction of the first test isolation structure 141 and the second test isolation structure 142 has a preset angle with the first direction, such as 30 degrees, 45 degrees, 60 degrees, 90 degrees, etc.

[0150] See also: [Information on possible implementations] Figure 15 In at least two test element groups with the same light emission color of the test light emission unit 151, two adjacent test element groups share the first test isolation structure 141. The second test isolation structure 142 of one test element group is disposed on one side of the first test isolation structure 141 in the extension direction of the preset signal line in the display panel motherboard, and the second test isolation structure 142 of the other test element group is disposed on the side of the first test isolation structure 141 away from the extension direction of the preset signal line in the display panel motherboard.

[0151] For example, along the first direction D1, the second test isolation structure 142A and the second test isolation structure 142B are located on both sides of the first test isolation structure 141, the lap electrode 161A is located between the second test isolation structure 142A and the first test isolation structure 141, and the lap electrode 161B is located between the second test isolation structure 142B and the first test isolation structure 141.

[0152] For some other possible implementations, please refer to Figure 16 In at least two test element groups with the same light emission color of the test light-emitting unit, two adjacent test element groups share the second test isolation structure 142. The first test isolation structure 141 of one test element group is located on one side of the second test isolation structure in the extension direction of the preset signal line in the display panel motherboard, and the first test isolation structure 141 of the other test element group is located on the side of the second test isolation structure 142 away from the extension direction of the preset signal line in the display panel motherboard.

[0153] For example, along the first direction D1, the first test isolation structure 141A and the first test isolation structure 141B are located on both sides of the second test isolation structure 142, and the overlapping electrode 161 and the second test isolation structure 142 are located between the first test isolation structure 141A and the first test isolation structure 141B.

[0154] See also: [Information on possible implementations] Figure 17The first test isolation structure 141, the second test isolation structure 142, and the pixel isolation structure 145 include a first sub-layer 1401 and a second sub-layer 1402 stacked in a direction away from the substrate 110. The orthographic projection of the first sub-layer 1401 on the substrate 110 lies within the orthographic projection of the second sub-layer 1402 on the substrate 110. That is, the first sub-layer 1401 is recessed relative to the second sub-layer 1402, forming an undercut structure.

[0155] Optionally, the material of the first sublayer 1401 includes aluminum, and / or the material of the second sublayer 1402 includes titanium.

[0156] Optionally, the first test isolation structure 141, the second test isolation structure 142 and the pixel isolation structure 145 may further include a third sublayer 1403 located between the first sublayer 1401 and the substrate 110.

[0157] Optionally, the orthographic projection of the third sublayer 1403 on the substrate 110 lies within the orthographic projection of the second sublayer 1402 on the substrate 110. Optionally, the orthographic projection of the first sublayer 1401 on the substrate 110 lies within the orthographic projection of the third sublayer 1403 on the substrate 110.

[0158] Optionally, the material of the third sublayer 1403 includes molybdenum.

[0159] In some possible implementations, the display panel motherboard also includes a first encapsulation layer; see [link to relevant documentation]. Figure 18 and Figure 19 The first encapsulation layer includes a test encapsulation unit 171, which is located on the side of the lap electrode 161 away from the substrate 110 and covers the lap electrode 161.

[0160] Optionally, at least a portion of the test package unit 171 extends from between the first test isolation structure 141 and the second test isolation structure 142 to the side of the first test isolation structure 141 and the second test isolation structure 142 away from the substrate 110.

[0161] Accordingly, please see again Figure 14 The first encapsulation layer also includes a pixel encapsulation unit 173 located on the side of the second pixel electrode 163 away from the substrate 110, at least a portion of the pixel encapsulation unit 173 extending from the isolation opening to the side of the pixel isolation structure 145 away from the substrate 110.

[0162] Optionally, the display panel motherboard may further include a second encapsulation layer 180 and a third encapsulation layer 190, which are stacked on the side of the first encapsulation layer away from the substrate 110 and in a direction away from the substrate 110.

[0163] Optionally, the materials of the first and third encapsulation layers 190 include inorganic materials, and the material of the second encapsulation layer 180 includes organic materials. For example, the first and third encapsulation layers 190 can be formed by chemical vapor deposition (CVD), and the second encapsulation layer 180 can be formed by inkjet printing (IJP).

[0164] This application also provides a method for manufacturing a display panel motherboard; please refer to [link to relevant documentation]. Figure 20 The method may include the following steps.

[0165] Step S210: Provide a substrate 110.

[0166] In step S220, at least one test component is formed on one side of the substrate 110. The test component may include a lap electrode 161 and a group of test elements electrically connected to the lap electrode 161.

[0167] The test element group includes a first test isolation structure 141 and a second test isolation structure 142 that are separate from each other. The first test isolation structure 141 and the second test isolation structure 142 are disposed on opposite sides of the lap electrode 161.

[0168] The second test isolation structure 142 is electrically connected to the lap electrode 161. Depending on the vapor deposition formation of the lap electrode 161, the second test isolation structure 142 may at least partially overlap with or not contact the lap electrode 161.

[0169] In some possible implementations, the display panel motherboard includes a display panel AA and a test area NA1, and the isolation structure layer also includes a pixel isolation structure 145 located on the display panel AA.

[0170] In step S220, a first test isolation structure 141 and a second test isolation structure 142 can be formed in the test area NA1, and a pixel isolation structure 145 can be formed in the display panel AA. The pixel isolation structures 145 together form an isolation opening.

[0171] An overlap electrode 161 is provided between the first test isolation structure 141 and the second test isolation structure 142, and a second pixel electrode 163 is formed on the display panel AA, which is at least partially located in the isolation opening. The second pixel electrode 163 extends from the isolation opening to the side of the pixel isolation structure 145 facing the isolation opening and contacts the pixel isolation structure 145.

[0172] Optionally, the manufacturing method of the display panel provided in this embodiment may further include the following steps.

[0173] Step S310: Test the test element group to determine the overlap effect of the second pixel electrode 163 and the pixel isolation structure 145.

[0174] Step S320: After the test is completed, cut the test area NA1.

[0175] That is, in this embodiment, the area where the test element group is located can be cut off after the test is completed.

[0176] In some possible implementations, the deposition directions of the second pixel electrode 163 and the overlapping electrode 161 include a first direction and a second direction in which they are arranged opposite to each other. The test assembly includes at least one first test isolation structure 141A, an overlapping electrode 161A, and a second test isolation structure 142A distributed along the first direction; the test assembly also includes at least one second test isolation structure 142B, an overlapping electrode 161B, and a first test isolation structure 141B distributed along the second direction, such as... Figure 10 As shown.

[0177] Step S310 may include the following sub-steps.

[0178] Step S311: Obtain the first lap resistance between the first test isolation structure 141A and the second test isolation structure 142A distributed along the first direction D1 using a detection device; obtain the second lap resistance between the first test isolation structure 141B and the second test isolation structure 142B distributed along the second direction D2 using a detection device.

[0179] Step S312: Determine the overlap effect when the second pixel electrode 163 overlaps with the pixel isolation structure 145 along the second direction D2 based on the first overlap resistance; determine the overlap effect when the second pixel electrode 163 overlaps with the pixel isolation structure 145 along the first direction D1 based on the second overlap resistance.

[0180] In this embodiment, the first test isolation structure 141 and the second test isolation structure 142 are manufactured using the same process as the pixel isolation structure 145 of the display panel AA, and the second pixel electrode 163 is manufactured using the same process as the overlapping electrode 161. The overlapping effect of the first test isolation structure 141 and the overlapping electrode 161 can directly reflect the overlapping effect of the pixel isolation structure 145 and the second pixel electrode 163.

[0181] Furthermore, the first test isolation structure 141 in the test element group has at most one side that overlaps with the overlapping electrode 161, so that if the overlapping electrode has poor overlap due to vapor deposition problems, the vapor deposition chamber with problems in the vapor deposition source can be more accurately identified.

[0182] In some other possible implementations, step S310 can involve the second pixel electrode 163 and the pixel isolation structure 145 overlapping on one side. If the overlapping direction is on the side of the second pixel electrode 163 facing the first direction D1, such as... Figure 9 As shown, the method may include the following steps.

[0183] Step S313: Obtain the first lap resistance between the first test isolation structure 141 and the second test isolation structure 142 distributed along the first direction D1 using a detection device.

[0184] Step S314: Determine the overlap effect when the second pixel electrode 163 overlaps with the pixel isolation structure 145 along the first direction D1 based on the first overlap resistor.

[0185] This application also provides an electronic device, which includes the display panel provided in this application, or a display panel prepared by the display panel master board manufacturing method provided in this embodiment. The electronic device may include mobile phones, tablet computers, smart wearable devices, televisions, laptops, monitors and other devices with display functions.

[0186] In summary, this application provides a display panel motherboard, a method for manufacturing the display panel motherboard, and an electronic device. By setting one of the test isolation structures in the test element group to overlap with the lap electrode on only one side, and setting two test element groups to test the effect of the test isolation structure and the lap electrode in two opposite directions, the problematic evaporation chamber in the evaporation source can be more accurately identified when the lap electrode has poor overlap due to evaporation problems.

[0187] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0188] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel motherboard, characterized in that, The display panel motherboard includes: Substrate; At least one test assembly disposed on one side of the substrate, the test assembly comprising a lap electrode and a group of test elements electrically connected to the lap electrode; The test element group includes a first test isolation structure and a second test isolation structure that are separate from each other, and the first test isolation structure and the second test isolation structure are disposed on opposite sides of the overlapping electrode. Along the same direction, the first test isolation structure has at most one side that overlaps with the overlapping electrode, and at least one side of the two opposite sides of the second test isolation structure is electrically connected to the overlapping electrode.

2. The display panel motherboard according to claim 1, characterized in that, In at least one of the test components, the first test isolation structure is disposed on one side of the overlapping electrode in a first direction, and the second test isolation structure is located on the other side of the overlapping electrode; the first direction is the same as or opposite to the extension direction of the preset signal line in the display panel motherboard.

3. The display panel motherboard according to claim 2, characterized in that, In at least one other test component, the first test isolation structure is disposed on one side of the lap electrode in a second direction, and the second test isolation structure is located on the other side of the lap electrode; the second direction is opposite to the first direction.

4. The display panel motherboard according to claim 3, characterized in that, In at least one other test component, the first test isolation structure is disposed on one side of the overlapping electrode in a third direction, and the second test isolation structure is located on the other side of the overlapping electrode; the third direction intersects with the extension direction of some signal lines in the display panel motherboard.

5. The display panel motherboard according to claim 2, characterized in that, The lap electrode has a first opening, and the second test isolation structure is located inside the first opening.

6. The display panel motherboard according to claim 2, characterized in that, In a direction parallel to the substrate and intersecting the first direction, the length of the first test isolation structure is greater than the length of the second test isolation structure.

7. The display panel motherboard according to claim 6, characterized in that, The extension direction of the first test isolation structure is perpendicular to the first direction.

8. The display panel motherboard according to claim 7, characterized in that, The side of the first test isolation structure facing the second test isolation structure is perpendicular to the first direction.

9. The display panel motherboard according to claim 1, characterized in that, The display panel further includes a wiring layer located on one side of the substrate and an insulating layer located on the side of the wiring layer away from the substrate. The test element group is disposed on the side of the insulating layer away from the substrate. The first test isolation structure and the second test isolation structure are electrically connected to the connection wiring in the wiring layer through through holes penetrating the insulating layer. The connection wiring connects the first test isolation structure and the second test isolation structure to the test contacts.

10. The display panel motherboard according to claim 9, characterized in that, The insulating layer includes at least one planarization layer and / or a pixel delimiting layer.

11. The display panel motherboard according to claim 9, characterized in that, The insulating layer includes a first thickness region and a second thickness region, the thickness of the second thickness region being greater than the thickness of the first thickness region, and the test element group being located in the second thickness region.

12. The display panel motherboard according to claim 2, characterized in that, The display panel motherboard includes a display panel and a test area; the test component group is located in the test area; The display panel includes a pixel isolation structure located on one side of the substrate. The first test isolation structure and the second test isolation structure are disposed on the same layer as the pixel isolation structure. The pixel isolation structure includes spaced isolation openings. The display panel further includes a first pixel electrode, a pixel light-emitting unit, and a second pixel electrode, which are at least partially located in the isolation opening and stacked in a direction away from the substrate; The second pixel electrode is disposed in the same layer as the overlapping electrode; The second pixel electrode extends from the isolation opening to the side of the pixel isolation structure facing the isolation opening and is electrically connected to the pixel isolation structure.

13. The display panel motherboard according to claim 12, characterized in that, The display panel motherboard also includes a test light-emitting unit located on the side of the overlapping electrode near the substrate; the test light-emitting unit and the pixel light-emitting unit are arranged on the same layer.

14. The display panel motherboard according to claim 13, characterized in that, The pixel light-emitting unit includes a first light-emitting unit and a second light-emitting unit. The display panel motherboard includes at least two test element groups. The at least two test element groups are respectively disposed corresponding to the first light-emitting unit and the second light-emitting unit. The test element group disposed corresponding to the first light-emitting unit has the same material as the first light-emitting unit.

15. The display panel motherboard according to claim 14, characterized in that, In at least two test element groups where the emission color of the test light-emitting unit is the same, along the first direction, the first test isolation structure and the second test isolation structure are arranged sequentially in at least one test element group, and the second test isolation structure and the first test isolation structure are arranged sequentially in the other test element group.

16. The display panel motherboard according to claim 15, characterized in that, In at least two test element groups with the same emission color of the test light-emitting unit, two adjacent test element groups share the first test isolation structure. The second test isolation structure of one test element group is disposed on one side of the first test isolation structure in the extension direction of the preset signal line in the display panel motherboard, and the second test isolation structure of the other test element group is disposed on the side of the first test isolation structure opposite to the extension direction of the preset signal line in the display panel motherboard.

17. The display panel motherboard according to claim 16, characterized in that, In at least two test element groups with the same emission color of the test light-emitting unit, two adjacent test element groups share the second test isolation structure. The first test isolation structure of one test element group is disposed on one side of the second test isolation structure in the extension direction of the preset signal line in the display panel motherboard, and the first test isolation structure of the other test element group is disposed on the side of the second test isolation structure opposite to the extension direction of the preset signal line in the display panel motherboard.

18. The display panel motherboard according to claim 12, characterized in that, The first test isolation structure, the second test isolation structure, and the pixel isolation structure include a first sub-layer and a second sub-layer stacked in a direction away from the substrate, wherein the orthogonal projection of the first sub-layer on the substrate is located within the orthogonal projection of the second sub-layer on the substrate.

19. The display panel motherboard according to claim 18, characterized in that, The material of the first sublayer includes aluminum, and / or the material of the second sublayer includes titanium.

20. The display panel motherboard according to claim 19, characterized in that, The first test isolation structure, the second test isolation structure, and the pixel isolation structure further include a third sublayer located between the first sublayer and the substrate.

21. The display panel motherboard according to claim 20, characterized in that, The orthographic projection of the third sublayer onto the substrate lies within the orthographic projection of the second sublayer onto the substrate.

22. The display panel motherboard according to claim 21, characterized in that, The material of the third sublayer includes molybdenum.

23. The display panel motherboard according to claim 12, characterized in that, The display panel motherboard also includes a test packaging unit, which is located on the side of the lap electrode away from the substrate and covers the lap electrode.

24. The display panel motherboard according to claim 23, characterized in that, At least a portion of the test packaging unit extends from between the first test isolation structure and the second test isolation structure to the side of the first test isolation structure and the second test isolation structure away from the substrate.

25. The display panel motherboard according to claim 24, characterized in that, The display panel motherboard also includes a pixel packaging unit located on the side of the second pixel electrode away from the substrate, at least a portion of the pixel packaging unit extending from the isolation opening to the side of the pixel isolation structure away from the substrate; the pixel packaging unit and the test packaging unit are disposed on the same layer.

26. The display panel motherboard according to claim 25, characterized in that, The display panel motherboard further includes a second encapsulation layer and a third encapsulation layer stacked on the side of the pixel encapsulation unit and the test encapsulation unit away from the substrate and in a direction away from the substrate.

27. The display panel motherboard according to claim 26, characterized in that, The materials of the pixel packaging unit, the test packaging unit, and the third packaging layer include inorganic materials, while the material of the second packaging layer includes organic materials.

28. A method for manufacturing a display panel motherboard, characterized in that, The method includes: Provide a substrate; At least one test assembly is formed on one side of the substrate, the test assembly including a lap electrode and a group of test elements electrically connected to the lap electrode; The test element group includes a first test isolation structure and a second test isolation structure that are separate from each other. The first test isolation structure and the second test isolation structure are disposed on opposite sides of the overlapping electrodes. Along the same direction, the first test isolation structure has only one side that overlaps with the overlapping electrode, while the two opposite sides of the second test isolation structure are electrically connected to the overlapping electrode.

29. The method for manufacturing a display panel motherboard according to claim 28, characterized in that, The display panel motherboard includes a display panel and a test area, and the test components are disposed in the test area; The display panel also includes a pixel isolation structure located on one side of the substrate, wherein the pixel isolation structure is disposed on the same layer as the first test isolation structure and the second test isolation structure; The step of forming at least one test component on one side of the substrate includes: A first test isolation structure and a second test isolation structure are formed in the test area, and a pixel isolation structure is formed in the display panel, the pixel isolation structure including spaced isolation openings; An overlap electrode is disposed between the first test isolation structure and the second test isolation structure, and a second pixel electrode is formed in the display panel at least partially located in the isolation opening. The second pixel electrode extends from the isolation opening to the side of the pixel isolation structure facing the isolation opening and contacts the pixel isolation structure.

30. The method for manufacturing a display panel motherboard according to claim 29, characterized in that, The method further includes: For the test element group, determine the bonding effect between the second pixel electrode and the pixel isolation structure; After the test is completed, the test area is cut.

31. The method for manufacturing a display panel motherboard according to claim 30, characterized in that, The evaporation directions of the second pixel electrode and the overlapping electrode include a first direction and a second direction in which they are disposed opposite to each other; the test assembly includes at least one first test isolation structure, the overlapping electrode and the second test isolation structure distributed along the first direction; the test assembly further includes at least one second test isolation structure, the overlapping electrode and the first test isolation structure distributed along the second direction. Determining the overlap effect between the second pixel electrode and the pixel isolation structure on the test element group further includes: The first lap resistance between the first test isolation structure and the second test isolation structure distributed along the first direction is obtained by the testing equipment; the second lap resistance between the first test isolation structure and the second test isolation structure distributed along the second direction is obtained by the testing equipment. The overlap effect when the second pixel electrode overlaps with the pixel isolation structure along the second direction is determined based on the first overlap resistance; the overlap effect when the second pixel electrode overlaps with the pixel isolation structure along the first direction is determined based on the second overlap resistance.

32. A display device, characterized in that, The display device includes a display panel manufactured by the method of manufacturing a display panel motherboard as described in claim 30.

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