Display panel motherboard, preparation method and testing method of display panel motherboard

Abstract

This application provides a display panel motherboard, a method for preparing the display panel motherboard, and a testing method, relating to the field of display technology. The display panel motherboard includes a substrate and at least one set of test elements. The set of test elements includes test electrodes and an isolation test structure disposed around the test electrodes. The isolation test structure includes at least two isolation test portions spaced apart from each other, with the orthographic projections of the at least two isolation test portions on the substrate not overlapping. The test electrodes are electrically connected to at least one isolation test portion. By configuring the isolation test structure to include at least two isolation test portions spaced apart from each other and electrically connecting the isolation test portions through test electrodes, this application can more accurately and directly test the overlap electrode between the isolation test structure and the test electrodes. This allows for a more accurate and direct evaluation of the overlap effect between the isolation structure and the cathode in the display area, thereby improving the performance of the display panel motherboard.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel motherboard, a method for preparing the display panel motherboard, and a testing method. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, there are still some problems that need to be solved in the process of manufacturing display devices. Summary of the Invention

[0004] To overcome the technical problems mentioned in the above background, this application provides a display panel motherboard, the display panel motherboard including a display area and a non-display area at least partially surrounding the display area, the non-display area including a test area, the display panel motherboard comprising:

[0005] Substrate;

[0006] At least one test element group located on one side of the substrate, the test element group including a test electrode and an isolation test structure disposed around the test electrode, the isolation test structure including at least two isolation test parts disposed at intervals from each other, the orthographic projections of the at least two isolation test parts on the substrate not overlapping each other.

[0007] In some possible implementations, the test element group further includes at least two partitions disposed between two adjacent isolated test sections, the isolated test sections and the partitions surrounding the test electrode;

[0008] Preferably, the partition portion includes an insulating material;

[0009] Preferably, at least two of the isolation test sections and at least two of the partition sections are continuously arranged to form an annular test opening, and the test electrode is disposed within the test opening.

[0010] In some possible implementations, the display panel motherboard further includes a conductive layer located on the side of the test element group near the substrate. The conductive layer includes multiple test traces, and each test element group is provided with at least two test traces. The isolation test section is electrically connected to one of the test traces.

[0011] Preferably, the display panel motherboard further includes a first insulating layer located on the side of the conductive layer away from the substrate, and the test element group is located on the side of the first insulating layer away from the substrate;

[0012] Preferably, along a direction perpendicular to the substrate, the first insulating layer has a plurality of first test vias, the first test vias exposing at least a portion of the test traces, and the isolation test section is electrically connected to the test traces through the first test vias;

[0013] Preferably, the first insulating layer includes a first protrusion extending in a direction away from the substrate, and at least a portion of the orthographic projection of the first protrusion on the substrate lies between the orthographic projections of adjacent isolation test portions on the substrate;

[0014] Preferably, along the side away from the substrate, the first protrusion extends to the side of the test element group opposite to the substrate to form a partition between adjacent isolation test structures;

[0015] Preferably, the test trace electrically connected to the isolation test section has at least two pins.

[0016] In some possible implementations, the display panel motherboard further includes a third insulating layer located on the side of the first insulating layer away from the substrate. Along a direction perpendicular to the substrate, the third insulating layer has a plurality of second test vias exposing at least a portion of the test traces. The isolation test portion is electrically connected to the test traces through the second test vias and the first test vias, respectively.

[0017] Preferably, the third insulating layer is further provided with a partition opening, and at least a portion of the first protrusion is disposed within the partition opening;

[0018] Preferably, the orthographic projection of the second test via on the substrate covers the orthographic projection of the first test via on the substrate.

[0019] In some possible implementations, the display panel motherboard further includes a first insulating layer and a third insulating layer disposed sequentially along the side away from the substrate, and the test element group is located on the side of the third insulating layer away from the substrate;

[0020] Preferably, the first insulating layer includes a first protrusion extending in a direction away from the substrate, and the third insulating layer includes a second protrusion located on the side of the first protrusion away from the substrate, extending in a direction away from the substrate to the side of the test element group opposite to the substrate, wherein the first protrusion and the second protrusion form a partition between adjacent isolation test structures.

[0021] Preferably, the orthographic projections of at least a portion of the first protrusion and at least a portion of the second protrusion on the substrate are both located between the orthographic projections of adjacent isolation test portions on the substrate;

[0022] Preferably, the display panel motherboard further includes a second insulating layer located on the side of the second protrusion away from the substrate, the second insulating layer covering at least a portion of the isolation test portion, and the orthographic projection of the second protrusion on the substrate being located within the orthographic projection range of the second insulating layer on the substrate;

[0023] Preferably, the second protrusion contacts the side of the two adjacent isolation test portions.

[0024] In some possible implementations, the display panel motherboard further includes a first insulating layer and a third insulating layer disposed sequentially on the side away from the substrate, and the test element group is located on the side of the third insulating layer away from the substrate;

[0025] Preferably, the third insulating layer includes a second protrusion extending in a direction away from the substrate, the second protrusion extending to the side of the test element group opposite to the substrate, to form a partition located between adjacent isolation test structures;

[0026] Preferably, at least a portion of the second protrusion's orthographic projection on the substrate lies between the orthographic projections of adjacent isolation test portions on the substrate;

[0027] Preferably, the second protrusion contacts the side surfaces of two adjacent isolation test portions;

[0028] Preferably, the display panel motherboard further includes a second insulating layer located on the side of the second protrusion away from the substrate, the second insulating layer covering at least a portion of the isolation test portion.

[0029] In some possible implementations, at least a portion of the third insulating layer extends to the sidewall of the first test via;

[0030] Preferably, the third insulating layer covers the sidewall of the first test via;

[0031] Preferably, the orthographic projection of the second test via on the substrate is located within the orthographic projection of the first test via on the substrate;

[0032] Preferably, the center of the orthographic projection of the first test via on the substrate coincides with the center of the orthographic projection of the second test via on the substrate;

[0033] Preferably, the third insulating layer extends to the display area of ​​the display panel motherboard, and the third insulating layer further includes pixel openings located in the display area.

[0034] In some possible implementations, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer are sequentially stacked in a direction away from the substrate, and the test trace is located in any one of the first conductive layer, the second conductive layer, the third conductive layer, or the fourth conductive layer;

[0035] Preferably, the test trace is located in the fourth conductive layer;

[0036] Preferably, a first planarization layer is provided between the third conductive layer and the fourth conductive layer, a second planarization layer is provided on the side of the fourth conductive layer away from the substrate, the first insulating layer includes the second planarization layer, and the first test via is disposed on the second planarization layer.

[0037] In some possible implementations, the test element group further includes a light-emitting test section located within the test opening, the light-emitting test section being located on the side of the test electrode closer to the substrate;

[0038] Preferably, the display panel motherboard includes a display panel and a test area located around the display panel, the test element group is disposed in the test area, and the display panel motherboard further includes an isolation structure located on the display panel, the isolation structure enclosing to form an isolation opening;

[0039] Preferably, the isolation structure and the isolation test structure are arranged on the same layer;

[0040] Preferably, the shape of the orthographic projection of the test opening onto the substrate is the same as the shape of the orthographic projection of the isolation opening onto the substrate;

[0041] Preferably, the area of ​​the test opening projected onto the substrate is N times the area of ​​the isolation opening projected onto the substrate, where N is greater than or equal to 1.

[0042] In some possible implementations, the display panel motherboard further includes light-emitting units located at least partially within the isolation opening;

[0043] Preferably, the light-emitting unit includes a first electrode, a light-emitting part, and a second electrode stacked sequentially along a direction away from the substrate, wherein the second electrode is electrically connected to the side of the isolation structure facing the isolation opening;

[0044] Preferably, the light-emitting part and the light-emitting test part are disposed in the same layer;

[0045] Preferably, the second electrode is disposed in the same layer as the test electrode;

[0046] Preferably, the light-emitting unit includes a first light-emitting unit and a second light-emitting unit with different light-emitting colors, and the test element group includes a first test element group for testing the first light-emitting unit and a second test element group for testing the second light-emitting unit. The light-emitting test part of the first test element group is made of the same material as the light-emitting part of the first light-emitting unit, and the light-emitting test part of the second test element group is made of the same material as the light-emitting part of the second light-emitting unit.

[0047] In some possible implementations, the display panel motherboard further includes a first encapsulation layer located on the side of the light-emitting unit away from the substrate, the first encapsulation layer including a plurality of encapsulation units spaced apart;

[0048] Preferably, at least a portion of the packaging unit extends from the side of the isolation structure to the side of the isolation structure away from the substrate, wherein the side of the isolation structure is the face of the isolation structure facing the isolation opening;

[0049] Preferably, at least a portion of the packaging unit extends from the side of the isolation structure to the side of the isolation structure away from the substrate;

[0050] Preferably, adjacent packaging units are spaced apart on the side of the isolation structure away from the substrate;

[0051] Preferably, there is a gap between the packaging unit located on the side of the isolation structure away from the substrate and the side of the isolation structure away from the substrate;

[0052] Preferably, the isolation structure includes a first isolation portion and a second isolation portion stacked sequentially along a direction away from the substrate, wherein the orthographic projection of the side of the first isolation portion away from the substrate on the substrate is located within the orthographic projection of the second isolation portion on the substrate;

[0053] Preferably, the second electrode of the light-emitting unit is electrically connected to the first isolation portion; and / or, the isolation structure further includes a third isolation portion located on the side of the first isolation portion facing the substrate, and the second electrode of the light-emitting unit is electrically connected to the third isolation portion;

[0054] Preferably, the material of the third isolation portion includes molybdenum metal; and / or, the material of the first isolation portion includes aluminum metal; and / or, the material of the second isolation portion includes titanium metal.

[0055] In some possible implementations, the isolation test structure includes a first test section and a second test section stacked sequentially along a direction away from the substrate, wherein the orthographic projection of the side of the first test section away from the substrate on the substrate is located within the orthographic projection of the second test section on the substrate, and the test electrode extends to be electrically connected to the first test section.

[0056] Preferably, the isolation test structure includes a first isolation test section and a second isolation test section arranged at intervals between each other, and the test element group further includes a first partition section and a second partition section located between the first isolation test section and the second isolation test section. The first isolation test section, the first partition section, the second isolation test section and the second partition section are arranged in sequence and surround to form a test opening, and the test electrode is disposed in the test opening.

[0057] In some possible embodiments, this application also provides a method for preparing a display panel motherboard, the method comprising:

[0058] Provide a substrate;

[0059] At least one test element group is formed on one side of the substrate. The test element group includes a test electrode and an isolation test structure disposed around the test electrode. The isolation test structure includes at least two isolation test parts disposed at intervals from each other, and the orthographic projections of the at least two isolation test parts on the substrate do not overlap.

[0060] In some possible implementations, the step of forming at least one group of test elements on one side of the substrate includes:

[0061] A first insulating material layer is formed on one side of the substrate;

[0062] A first protrusion is formed on the first insulating material layer using a halftone mask to form the first insulating layer;

[0063] A third insulating layer is formed on the side of the first insulating layer away from the substrate, and a second protrusion is formed at the first protrusion in the third insulating layer;

[0064] An isolation conductive layer is formed on the side of the third insulating layer away from the substrate, and the isolation conductive layer is patterned to form an isolation test structure. The isolation test structure has a first isolation test part and a second isolation test part that are spaced apart from each other at the second protrusion. The orthographic projection of the first isolation test part on the substrate is located outside the orthographic projection of the second isolation test part on the substrate.

[0065] A second insulating layer is formed on the side of the second protrusion away from the substrate, and the second insulating layer covers at least a portion of the first isolation test portion and the second isolation test portion;

[0066] A light-emitting test section and a test electrode are sequentially formed on the side away from the substrate within the test opening, and the test electrode extends to be electrically connected to the first isolation test section and the second isolation test section;

[0067] Preferably, the display panel motherboard includes a display panel and a test area, wherein the test element group is disposed in the test area;

[0068] The display panel also includes an isolation structure located on one side of the substrate, and the pixel isolation structure is disposed on the same layer as the first isolation test section and the second isolation test section;

[0069] The method for preparing the display panel motherboard further includes:

[0070] While forming the isolation test structure through the isolation conductive layer, the isolation structure and the isolation opening are also formed; while forming the light-emitting test part, a light-emitting part is formed within the isolation opening.

[0071] A second electrode is formed within the isolation opening simultaneously with the formation of the test electrode.

[0072] Preferably, the preparation method further includes:

[0073] The test element group is tested, and the overlap effect between the second electrode and the isolation structure is determined based on the test results of the test element group;

[0074] After the test is completed, the test area is cut and the display panel is separated.

[0075] In some possible implementations, this application also provides a testing method for a display panel motherboard, the display panel motherboard including the display panel motherboard described in this application, the testing method comprising:

[0076] Obtain the sum of the overlap resistances between the test electrode and any two of the isolation test sections;

[0077] Based on the sum of the overlap resistances of the test electrode and any two of the isolation test sections, the overlap effect between the isolation structure of the display area of ​​the display panel motherboard and the second electrode is determined.

[0078] Preferably, any two of the isolation test sections are selected to form a circuit to be tested with the test electrode, and the test angle is determined according to the connection angle between the centers of the two isolation test sections and the test electrode.

[0079] Based on the results of the test circuit, the connection effect between the isolation structure and the second electrode of the corresponding light-emitting unit at the test angle is determined.

[0080] Compared with the prior art, this application has the following beneficial effects:

[0081] This application provides a display panel motherboard, a method for preparing the display panel motherboard, and a testing method. By setting the isolation test structure to include at least two isolation test sections spaced apart from each other, and electrically connecting the isolation test sections through test electrodes, the overlap electrode between the isolation test structure and the test electrodes can be tested more accurately and directly. This allows for a more accurate and direct evaluation of the overlap effect between the isolation structure of the display area and the second electrode, thereby improving the performance of the display panel motherboard. Attached Figure Description

[0082] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0083] Figure 1 One of the top views of the display panel motherboard provided in the embodiments of this application;

[0084] Figure 2 One of the top views of the test components provided in the embodiments of this application;

[0085] Figure 3 Provided for the embodiments of this application Figure 2 One of the schematic cross-sectional views at point AA in the middle;

[0086] Figure 4 This is an equivalent circuit diagram of the test component being tested for its lap resistance, provided in an embodiment of this application.

[0087] Figure 5 Provided for the embodiments of this application Figure 2 One of the cross-sectional schematic diagrams at point BB in the middle;

[0088] Figure 6 Provided for the embodiments of this application Figure 2 Schematic diagram of the cross section at point BB (part 2);

[0089] Figure 7 Provided for the embodiments of this application Figure 2 Schematic diagram of the cross section at point BB (part 3);

[0090] Figure 8Provided for the embodiments of this application Figure 2 Fourth cross-sectional view at point BB;

[0091] Figure 9 A cross-sectional schematic diagram of the display panel motherboard provided in the embodiments of this application, including the isolation structure;

[0092] Figure 10 Provided for the embodiments of this application Figure 2 Schematic diagram of the cross section at point AA (part 2);

[0093] Figure 11 A cross-sectional schematic diagram of the display panel motherboard provided in this application embodiment, including the first encapsulation layer;

[0094] Figure 12 Provided for the embodiments of this application Figure 2 Schematic diagram of the cross section at point AA (part 3);

[0095] Figure 13 A cross-sectional schematic diagram of the display panel motherboard provided in the embodiments of this application, including a second encapsulation layer and a third encapsulation layer;

[0096] Figure 14 A cross-sectional schematic diagram of the isolation structure provided in the embodiments of this application;

[0097] Figure 15 A schematic flowchart illustrating a method for preparing a display panel motherboard according to an embodiment of this application;

[0098] Figure 16 This is a schematic diagram illustrating the specific execution flow of step S11 provided in the embodiments of this application;

[0099] Figure 17 A cross-sectional schematic diagram showing a first insulating material layer formed on one side of a substrate, provided for an embodiment of this application;

[0100] Figure 18 A cross-sectional schematic diagram showing the formation of a first protrusion on a first insulating material layer using a halftone mask, provided as an embodiment of this application.

[0101] Figure 19 A schematic cross-sectional view of a third insulating layer formed on the side of the first insulating layer away from the substrate, provided for an embodiment of this application;

[0102] Figure 20 A cross-sectional schematic diagram showing an isolation conductive layer formed on the side of the third insulating layer away from the substrate, provided for an embodiment of this application;

[0103] Figure 21 A schematic cross-sectional view of the isolation test structure on the side away from the substrate provided in this application embodiment;

[0104] Figure 22 This is a schematic diagram of the cross-section after removing the test area, provided in an embodiment of this application.

[0105] Figure 23 A flowchart illustrating a testing method for a display panel motherboard provided in an embodiment of this application;

[0106] Figure 24 This is a second top view of the test components provided in the embodiments of this application.

[0107] Reference numerals: 1. Test component group; 2. Pin; 3. Test trace; 4. Isolation test structure; 4001. Isolation test section; 41. First isolation test section; 42. Second isolation test section; 401. First test section; 402. Second test section; 5. Second insulating layer; 6. Substrate; 7. Conductive layer; 701. First conductive layer; 702. Second conductive layer; 703. Third conductive layer; 704. Fourth conductive layer; 8. Third insulating layer; 81. Second test via; 82. Second protrusion; 83. Pixel aperture; 84. Isolation aperture; 9. First insulating layer; 91. First test via; 92. 10. First protrusion; 11. Light-emitting test section; 12. Test electrode; 13. Test opening; 14. Isolation structure; 15. First isolation section; 16. Second isolation section; 17. Third isolation section; 18. Isolation opening; 19. First electrode; 20. Light-emitting section; 21. Second electrode; 22. Light-emitting unit; 23. Buffer layer; 24. First planarization layer; 25. Second planarization layer; 26. First encapsulation layer; 27. Encapsulation unit; 28. Second encapsulation layer; 29. ​​Third encapsulation layer; 20. First insulating material layer; 21. Partition section; 22. First partition section; 23. Second partition section. Detailed Implementation

[0108] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0109] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0110] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0111] In the description of this application, it should be noted that the terms "center," "upper," "lower," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0112] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0113] In related technologies, the display panel motherboard includes a substrate, an isolation structure located on one side of the substrate, and a light-emitting unit located at least partially within the isolation opening of the isolation structure. The bonding resistance between the cathode of the light-emitting unit and the isolation structure is a key indicator for measuring the process and product feasibility of the display panel motherboard.

[0114] In related technologies, a test area is included in the non-display area of ​​the display panel motherboard. This test area can be used to evaluate the bonding effect between the cathode and the isolation structure of the light-emitting unit in the display area. However, in these related technologies, the cathode and isolation structure of the simulated light-emitting unit tested in the test area are the same as the isolation structure in the display area, forming an integral ring. The test area isolation structure and the cathode that overlaps with the isolation structure form a test point, which also needs to form a test loop with other test points. This type of test loop can only detect whether there is an electrical signal in the test loop, and cannot accurately test the bonding resistance between the isolation structure and the cathode. This affects the accuracy of evaluating the bonding resistance between the cathode and the isolation structure of the light-emitting unit in the display area, and ultimately affects the performance of the display panel motherboard.

[0115] In view of this, this embodiment provides a solution that can improve the accuracy of evaluating the overlap resistance between the cathode and the isolation structure of the display panel motherboard. The solution provided in this embodiment will be described in detail below.

[0116] Please see Figures 1-3This embodiment provides a display panel motherboard, which includes a substrate 6 and at least one test element group 1. The test element group 1 is located on one side of the substrate 6; the test element group 1 includes an isolation conductive layer 7 located on one side of the substrate 6, the isolation conductive layer 7 includes an isolation test structure 4, the isolation test structure 4 is provided with a test opening 12, the isolation test structure 4 includes at least two isolation test parts 4001 arranged at intervals, the orthographic projections of the at least two isolation test parts 4001 on the substrate 6 do not overlap, the test element group 1 also includes a test electrode 11, the at least two isolation test parts 4001 are disposed around the test electrode 11, the test electrode 11 is located within the test opening 12, and the test electrode 11 extends to be electrically connected to at least one isolation test part 4001.

[0117] When there are multiple test element groups 1, the multiple test element groups 1 are mutually insulated, and the isolation test structure 4 of the test element group 1 is divided into a first isolation test section 41 and a second isolation test section 42 that are spaced apart from each other.

[0118] When testing the resistance of test element group 1 using the resistance display panel motherboard, the resistance tested by the resistance display panel motherboard is equivalent to the sum of the overlap resistances of any two isolated test sections 4001 and test electrodes 11.

[0119] The test electrode 11 is made of the same material as the cathode of the display area AA, and the isolation test structure 4 is made of the same material as the isolation structure 13 of the display area AA. Therefore, based on the overlap resistance between any two isolation test sections 4001 and the test electrode 11, the overlap resistance between the isolation structure 13 and the cathode can be known. Based on the overlap resistance between the isolation structure 13 and the cathode, the overlap effect between the isolation structure 13 and the cathode can be evaluated more accurately.

[0120] For example, the overlap resistance per unit overlap area between the isolation test structure 4 and the test electrode 11 can be calculated based on the overlap resistance between any two isolation test sections 4001 and the test electrode 11. Since the material of the isolation test structure 4 is the same as that of the isolation structure 13, and the materials of the test electrode 11 and the cathode are the same and formed in the same process, the overlap resistance per unit overlap area between the isolation test structure 4 and the test electrode 11 can accurately reflect the overlap area between the isolation structure 13 and the cathode in the same process. Therefore, it is possible to more directly and accurately determine whether there is poor overlap between the isolation structure 13 and the cathode.

[0121] Furthermore, the solution of this embodiment can also be applied to light-emitting units 18 with different morphologies, and the test structure is not affected by the size of the isolation test section 4001. That is, the sizes of the multiple isolation test sections 4001 into which the isolation test structure 4 is divided can be the same or different. In this way, the flexibility of setting up the test element group 1 can be increased.

[0122] Based on the above design, this embodiment sets the isolation test structure 4 to include at least two isolation test sections 4001 spaced apart from each other, and connects them to the isolation test sections 4001 via the test electrode 11. This allows for a more accurate and direct test of the overlap resistance between the isolation test structure 4 and the test electrode 11. Consequently, the overlap effect between the isolation structure 13 and the cathode in the display area AA can be evaluated more accurately and directly, thereby improving the performance of the display panel motherboard.

[0123] In some possible implementations, please refer again. Figure 1 and 2 The display panel motherboard includes a display area AA and a non-display area AB that at least partially surrounds the display area AA. The non-display area AB includes a test area AC. Test element group 1 is located in the test area AC. The test element group also includes at least two partitions 26. The partitions 26 are disposed between two adjacent isolation test sections 4001. The partitions 26 and the isolation test sections 4001 are arranged around the test electrode 11. The at least two isolation test sections 4001 and the at least two partitions 26 are continuously arranged to form an annular test opening 12. The partitions 26 include insulating material. The partitions 26 make it easier to divide the isolation test structure 4 into at least two mutually spaced isolation test sections 4001.

[0124] Preferably, please see again. Figure 2 The isolation test structure 4 includes a first isolation test section 41 and a second isolation test section 42 that are spaced apart from each other. The test element group 1 also includes a first partition section 261 and a second partition section 262 located between the first isolation test section 41 and the second isolation test section 42. The first isolation test section 41, the first partition section 261, the second isolation test section 42 and the second partition section 262 are arranged in sequence and surround each other to form a test opening 12.

[0125] Please see Figure 4 In this embodiment, the resistance tested by the resistance testing element group is equivalent to the overlap resistance R between the first isolation testing section 41 and the test electrode 11. 1搭接 The overlap resistance R between the second isolation test section 42 and the test electrode 11 2搭接 The sum of the lap resistances R1搭接 With lap resistor R2搭接 The sum of these values ​​represents the overlap resistance between the isolation test structure 4 and the test electrode 11.

[0126] For some possible implementations, please refer to Figure 5 The display panel motherboard also includes a first insulating layer 9 and a third insulating layer 8 located on the side of the first insulating layer 9 away from the substrate 6. The third insulating layer 8 is the pixel defining layer of the display panel.

[0127] In some embodiments, please refer again Figure 5 The first insulating layer 9 includes a first protrusion 92 extending in a direction away from the substrate 6, and at least a portion of the orthographic projection of the first protrusion 92 on the substrate 6 lies between the orthographic projections of the first isolation test portion 41 and the second isolation test portion 42 on the substrate 6. The third insulating layer 8 includes a second protrusion 82 extending in a direction away from the substrate 6, and at least a portion of the orthographic projection of the second protrusion 82 on the substrate 6 lies between the orthographic projections of the first isolation test portion 41 and the second isolation test portion 42 on the substrate 6.

[0128] In this embodiment, the second protrusion 82 is formed based on the first protrusion 92, thereby making it easier to form the second protrusion 82. The second protrusion 82 extends to the side of the test element group 1 facing away from the substrate 6. The second protrusion 82 and the first protrusion 92 form a partition 26 located between adjacent isolation test structures 4. In this embodiment, the second protrusion 82 and the first protrusion 92 form a partition opening 84, dividing the isolation test structure 4 into at least two mutually spaced isolation test sections 4001. The second protrusion 82 and the first protrusion 92 separate the first isolation test section 41 and the second isolation test section 42, forming a partition between the first isolation test section 41 and the second isolation test section 42. The second protrusion 82 insulates the first isolation test section 41 and the second isolation test section 42. In this way, the overlap resistance between the isolation test structure 4 and the test electrode 11 can be tested accurately and more directly.

[0129] Preferably, please see again. Figure 5 The orthographic projection of the second protrusion 82 on the substrate 6 lies within the orthographic projection of the first protrusion 92 on the substrate 6, and the center of the orthographic projection of the second protrusion 82 on the substrate 6 coincides with the center of the orthographic projection of the first protrusion 92 on the substrate 6. Thus, the second protrusion 82 can be more easily formed based on the first protrusion 92, thereby allowing the second protrusion 82 to better separate the first isolation test section 41 and the second isolation test section 42.

[0130] Preferably, the second protrusion 82 contacts the side surfaces of two adjacent isolation test sections 4001. In this way, the two adjacent isolation test sections 4001 can be insulated by the second protrusion 82.

[0131] In other embodiments, please refer to Figure 6Alternatively, the first insulating layer 9 can be flat, with a second protrusion 82 formed only on the third insulating layer 8. The second protrusion 82 extends to the side of the test element group 1 facing away from the substrate 6 to form a partition 26 located between adjacent isolation test structures 4. In this embodiment, the second protrusion 82 forms a partition opening 84, dividing the isolation test structure 4 into at least two mutually spaced isolation test sections 4001. For example, the isolation test structure 4 can be divided into a first isolation test section 41 and a second isolation test section 42 that are spaced apart.

[0132] In some embodiments, the first protrusion 92 is provided only in the first insulating layer 9 in the direction away from the substrate 6. Along the side away from the substrate 6, the first protrusion 92 extends to the side of the test element group 1 opposite to the substrate 6, forming a partition 26 located between adjacent isolation test structures 4. The third insulating layer 8 is also provided with an isolation opening 84, and at least a portion of the first protrusion 92 is disposed within the isolation opening 84. In this embodiment, the isolation opening 84 is formed by the first protrusion 92, dividing the isolation test structure 4 into at least two mutually spaced isolation test sections 4001.

[0133] In some possible implementations, please refer again. Figure 5 and Figure 6 The distance H1 from the side of the second protrusion 82 away from the substrate 6 is greater than or equal to the distance H2 from the side of the first isolation test portion 41 and the second isolation test portion 42 away from the substrate 6. The first isolation test portion 41 extends to contact the side of the second protrusion 82 facing the first isolation test portion 41, and the second isolation test portion 42 extends to contact the side of the second protrusion 82 facing the second isolation test portion 42. In this way, the second protrusion 82 can more effectively separate the first isolation test portion 41 and the second isolation test portion 42.

[0134] In some possible implementations, the display panel motherboard further includes a second insulating layer 5 located on the side of the second protrusion 82 away from the substrate 6. The second insulating layer 5 covers at least a portion of the first isolation test portion 41 and the second isolation test portion 42. The orthographic projection of the second protrusion 82 on the substrate 6 is located within the orthographic projection range of the second insulating layer 5 on the substrate 6.

[0135] In some embodiments, please refer again Figure 5 and Figure 6The second insulating layer 5 covers a portion of the isolation test section 4001, for example, covering the first isolation test section 41 and the second isolation test section 42. After removing the isolation test structure 4 on the side of the second protrusion 82 away from the substrate 6 to form the first isolation test section 41 and the second isolation test section 42, a portion of the first isolation test section 41 and the second isolation test section 42 will be exposed. The second insulating layer 5 covers the exposed portions of the first isolation test section 41 and the second isolation test section 42, which can protect the first isolation test section 41 and the second isolation test section 42 and prevent them from being oxidized.

[0136] In some embodiments, see Figure 7 and Figure 8 The second insulating layer 5 completely covers the first isolation test section 41 and the second isolation test section 42. Thus, the second insulating layer 5 provides better protection for the first isolation test section 41 and the second isolation test section 42.

[0137] In some possible implementations, please refer again. Figure 3 The test element group 1 also includes a light emission test section 10 located in the test opening 12, and the light emission test section 10 is located on the side of the test electrode 11 close to the substrate 6.

[0138] Preferably, please refer to Figure 9 The display panel motherboard includes a display panel and a test area located around the periphery of the display panel. An isolation conductive layer 7 extends to the display area AA. The isolation conductive layer 7 includes an isolation structure 13 located in the display area AA. The isolation structure 13 encloses and forms an isolation opening 14. The display panel motherboard also includes a light-emitting unit 18 located at least partially within the isolation opening 14. The light-emitting unit 18 includes a first electrode 15, a light-emitting part 16, and a second electrode 17 sequentially stacked along a direction away from the substrate 6. The isolation structure 13 is disposed on the same layer as the isolation test structure 4, the light-emitting part 16 is disposed on the same layer as the light-emitting test part 10, and the second electrode 17 is disposed on the same layer as the test electrode 11.

[0139] The light-emitting unit includes a first light-emitting unit and a second light-emitting unit with different light-emitting colors. The test element group 1 includes a first test element group for testing the first light-emitting unit and a second test element group for testing the second light-emitting unit. The light-emitting test part 10 of the first test element group is made of the same material as the light-emitting part 16 of the first light-emitting unit, and the light-emitting test part 10 of the second test element group is made of the same material as the light-emitting part 16 of the second light-emitting unit.

[0140] When the light-emitting functional layer is formed, the light-emitting functional layer is separated by the isolation structure 13 to form multiple light-emitting parts 16 spaced apart and located in the isolation opening 14. The light-emitting functional layer is also separated by the isolation conductive layer 7 to form a light-emitting test part 10 located in the test opening 12.

[0141] When forming the second electrode layer, the second electrode layer is separated by the isolation structure 13 to form multiple spaced second electrodes 17 located within the isolation opening 14. The isolation structure 13 includes a conductive material, and the second electrodes 17 are electrically connected to the isolation structure 13. The second electrode layer is also separated by the isolation conductive layer 7 to form test electrodes 11 located within the test opening 12. Both the first isolation test section 41 and the second isolation test section 42 include conductive materials, and the test electrodes 11 extend to be electrically connected to the first isolation test section 41 and the second isolation test section 42. A first electrode 15, a light-emitting section 16, and a second electrode 17 form a light-emitting unit 18. Among them, the first electrode 15 is the anode, and the second electrode 17 is the cathode.

[0142] Thus, when forming the light-emitting functional layer, the light-emitting part 16 can be formed in the display area AA and the light-emitting test part 10 can be formed in the test area AC at the same time; when forming the second electrode layer, the second electrode 17 can be formed in the display area AA and the test electrode 11 can be formed in the test area AC at the same time, so that it is not necessary to set the light-emitting test part 10 and the test electrode 11 through a special process, thereby reducing the cost of forming the light-emitting test part 10 and the test electrode 11.

[0143] In some possible implementations, please refer again. Figure 3 The display panel motherboard also includes a conductive layer 7 located on the side of the test element group 1 near the substrate 6. The conductive layer 7 includes multiple test traces 3. Each test element group 1 is provided with at least two test traces 3. The isolation test section 4001 is electrically connected to one test trace 3 respectively. For example, the first isolation test section 41 and the second isolation test section 42 are electrically connected to the test trace 3 respectively. The first insulating layer 9 is located on the side of the conductive layer 7 away from the substrate 6. Along the direction perpendicular to the substrate 6, the first insulating layer 9 is provided with multiple first test vias 91 that expose at least part of the test traces 3. The isolation test section 4001 is electrically connected to the test traces 3 through the first test vias 91. For example, the first isolation test section 41 and the second isolation test section 42 are both electrically connected to the test traces 3 through the first test vias 91 respectively.

[0144] When the isolation test structure 4 is formed, the first isolation test section 41 and the second isolation test section 42 are electrically connected to the test trace 3 through the first test via 91. In this way, the test trace 3 is finally electrically connected to the test electrode 11. By electrically connecting the test trace 3 through the resistance display panel motherboard, it is easier to test the overlap resistance between the isolation test structure 4 and the test electrode 11.

[0145] Preferably, please see again. Figure 3Along a direction perpendicular to the substrate 6, the third insulating layer 8 is provided with a plurality of second test vias 81 that expose at least part of the test traces 3. The isolation test section 4001 is electrically connected to the test traces 3 through the second test vias 81 and the first test vias 91 in sequence. For example, the first isolation test section 41 and the second isolation test section 42 are electrically connected to the test traces 3 through the second test vias 81 and the first test vias 91 in sequence.

[0146] Please see again Figure 9 The third insulating layer 8 extends to the display area AA, and the third insulating layer 8 in the display area AA also includes a pixel opening 83, with at least a portion of the light-emitting units 18 located within the pixel opening 83. A second test via 81 can be formed simultaneously with the pixel opening 83. Thus, a separate process for creating the second test via 81 is not required, thereby reducing the cost of creating the second test via 81.

[0147] For some possible implementations, please refer to Figure 10 The conductive layer 7 includes a first conductive layer 701, a second conductive layer 702, a third conductive layer 703 and a fourth conductive layer 704 stacked sequentially in a direction away from the substrate 6. The test trace 3 is located in any one of the first conductive layer 701, the second conductive layer 702, the third conductive layer 703 and the fourth conductive layer 704. Specifically, the test trace 3 is located in the fourth conductive layer 704.

[0148] The display panel motherboard also includes a buffer layer 19 located on one side of the substrate 6 and a semiconductor layer located on the side of the buffer layer 19 away from the substrate 6. The first conductive layer 701 is located on the side of the semiconductor layer away from the substrate 6. In the display area AA, the semiconductor layer includes a source region, a drain region, and a channel region. The first conductive layer 701 includes a gate and a first capacitor plate. The second conductive layer 702 includes a second capacitor plate. The first capacitor plate and the second capacitor plate form a capacitor. The third conductive layer 703 includes a drain and a source. The drain is electrically connected to the drain region, and the source is electrically connected to the source region. The gate, source, and drain form a switching device. The metal trace of the fourth conductive layer 704 is connected to the drain, and the metal trace of the fourth conductive layer 704 is then electrically connected to the first electrode 15. In this embodiment, the test trace 3 of the test area AC is located in the fourth conductive layer 704.

[0149] Preferably, please see again. Figure 10 A first planarization layer 20 is provided between the third conductive layer 703 and the fourth conductive layer 704. A second planarization layer 21 is provided on the side of the fourth conductive layer 704 away from the substrate 6. The first insulating layer 9 includes the second planarization layer 21. A first test via 91 is disposed on the second planarization layer 21.

[0150] The second planarization layer 21 extends to the test area AC. A first test via 91 is provided on the second planarization layer 21 along a direction perpendicular to the substrate 6. The first isolation test section 41 and the second isolation test section 42 are both electrically connected to the test trace 3 through the first test via 91.

[0151] In some possible implementations, please refer again. Figure 10 At least part of the third insulating layer 8 extends to the sidewall of the first test via 91.

[0152] The second planarization layer 21 is made of organic materials, and the test trace 3 is made of metallic materials. Contact between organic and metallic materials easily generates moisture. The third insulating layer 8 is made of inorganic materials, and moisture is not easily transmitted through inorganic materials. Therefore, in this embodiment, by setting the third insulating layer 8 to extend to the sidewall of the first test via 91, moisture from the second planarization layer 21 can be prevented from being transmitted to the light-emitting unit 18, and voids can be prevented from forming during the deposition of the insulating conductive layer 7, thereby improving the quality of the display panel motherboard.

[0153] Preferably, please see again. Figure 10 The third insulating layer 8 wraps around the sidewall of the first test via 91. The third insulating layer 8 completely wraps around the sidewall of the first test via 91, making it more difficult for moisture from the second planarization layer 21 to be transmitted towards the light-emitting unit 18.

[0154] Preferably, please see again. Figure 10 The orthographic projection of the second test via on the substrate 6 lies within the orthographic projection of the first test via on the substrate 6, and the center of the orthographic projection of the first test via 91 on the substrate 6 coincides with the center of the orthographic projection of the second test via 81 on the substrate 6. Thus, the thickness of the third insulating layer 8 located between the first test via 91 and the second test via 81 is equal, which not only makes it less likely for moisture from the second planarization layer 21 to propagate towards the light-emitting unit 18, but also improves the electrical connection between the first isolation test section 41 and the second isolation test section 42 and the test trace 3.

[0155] Preferably, please see again. Figure 2 The test trace 3, which is electrically connected to the first isolation test section 41, has at least two pins 2, and the test trace 3, which is electrically connected to the second isolation test section 42, has at least two pins 2. The test element group can be electrically connected to at least four pins 2, thereby improving the accuracy of the overlap resistance between the test isolation test structure 4 and the test electrode 11.

[0156] Preferably, the shape of the orthographic projection of the test opening 12 on the substrate 6 is the same as the shape of the orthographic projection of the isolation opening 14 on the substrate 6, and the area of ​​the orthographic projection of the test opening 12 on the substrate 6 is N times the area of ​​the orthographic projection of the isolation opening 14 on the substrate 6, where N is greater than or equal to 1.

[0157] The shape of the test opening 12 in the test area AC is set to be the same as the shape of the isolation opening 14 in the display area AA, and the size of the test opening 12 is enlarged compared to the isolation opening 14. In this way, the test opening 12 can imitate the isolation opening 14, and the final test resistance between the isolation test structure 4 and the test electrode 11 can more easily and directly reflect the resistance between the isolation structure 13 and the cathode.

[0158] If the isolation opening 14 of the display area AA has isolation sub-openings of different shapes, then each isolation sub-opening of different shapes is provided with at least one test opening 12 and a test element group located at the test opening 12. The test opening with the same shape as the isolation opening is prepared. The connection resistance between the pixel cathode and the isolation structure in the isolation opening of different shapes can be comprehensively tested through the test element group to accurately determine the connection status.

[0159] For example, the area of ​​the orthographic projection of the test opening 12 onto the substrate 6 can be set to five times the area of ​​the orthographic projection of the isolation opening 14 onto the substrate 6. By reducing the overlap resistance between the tested isolation test structure 4 and the test electrode 11 by a factor of five, the overlap resistance between the isolation structure 13 of the display area AA and the cathode can be obtained. This allows for a more accurate and direct determination of the overlap resistance between the isolation structure 13 and the cathode in the display area AA, and thus makes it easier and more accurate to evaluate the overlap effect between the isolation structure 13 and the cathode.

[0160] For some possible implementations, please refer to Figure 11 The display panel motherboard also includes a first encapsulation layer 22 located on the side of the light-emitting unit 18 away from the substrate 6. The first encapsulation layer 22 includes a plurality of encapsulation units 221 spaced apart. At least some of the encapsulation units 221 extend from the side of the isolation structure 13 to the side of the isolation structure 13 away from the substrate 6. The side of the isolation structure 13 is the face of the isolation structure 13 facing the isolation opening 14. At least some of the encapsulation units 221 extend from the side of the isolation structure 13 to the side of the isolation structure 13 away from the substrate 6. Adjacent encapsulation units 221 are spaced apart on the side of the isolation structure 13 away from the substrate 6. There is a gap between the encapsulation unit 221 located on the side of the isolation structure 13 away from the substrate 6 and the side of the isolation structure 13 away from the substrate 6.

[0161] The material of the first encapsulation layer 22 can be the same as the material of the second insulating layer 5. During the patterning process of the light-emitting unit 18, the first encapsulation layer 22 is broken at the isolation structure 13 to form an encapsulation unit 221. The encapsulation unit 221 can completely and independently encapsulate the corresponding light-emitting unit 18, thereby improving the display characteristics of the display panel.

[0162] Please see Figure 12 A packaging unit 221 is also formed on the side of the test electrode 11 away from the substrate 6. The packaging unit 221 extends from the side of the first isolation test section 41 and the second isolation test section 42 to the side of the first isolation test section 41 and the second isolation test section 42 away from the substrate 6, respectively.

[0163] Preferably, please refer to Figure 13 The display panel motherboard also includes a second encapsulation layer 23 located on the side of the first encapsulation layer 22 away from the substrate 6 and a third encapsulation layer 24 located on the side of the second encapsulation layer 23 away from the substrate 6. The materials of the first encapsulation layer 22 and the third encapsulation layer 24 both include inorganic materials, and the material of the second encapsulation layer 23 includes organic materials.

[0164] The second encapsulation layer 23 and the third encapsulation layer 24 can achieve a better encapsulation effect on the light-emitting unit 18, thereby further improving the encapsulation quality of the display panel.

[0165] Preferably, please see again. Figure 13 The isolation structure 13 includes a first isolation portion 131 and a second isolation portion 132 stacked sequentially along the direction away from the substrate 6. The orthographic projection of the side of the first isolation portion 131 away from the substrate 6 on the substrate 6 is located within the orthographic projection of the second isolation portion 132 on the substrate 6.

[0166] Since the second isolation portion 132 is located on the side of the first isolation portion 131 away from the substrate, and the lateral width of the second isolation portion 132 is greater than the lateral width of the first isolation portion 131, the second isolation portion 132 disconnects the light-emitting functional layer and the second electrode layer at the isolation structure 13. Thus, the isolation structure 13 formed by the first isolation portion 131 and the second isolation portion 132 makes it easier to independently package each light-emitting unit 18.

[0167] Preferably, please see again. Figure 13 The second electrode 17 of the light-emitting unit 18 is electrically connected to the first isolation part 131. The first isolation part 131 includes a conductive material, and the second electrode 17 corresponding to the light-emitting unit 18 extends to contact the side wall of the first isolation part 131 so as to realize the electrical connection between the second electrode 17 corresponding to the light-emitting unit 18 and the first isolation part 131.

[0168] Please see Figure 14The isolation structure 13 also includes a third isolation portion 133 located on the side of the first isolation portion 131 facing the substrate 6, and the second electrode 17 of the light-emitting unit 18 is electrically connected to the third isolation portion 133.

[0169] The third isolation section 133 includes a conductive material, and the second electrode 17 corresponding to the light-emitting unit 18 extends to contact the side wall of the third isolation section 133 so as to realize the electrical connection between the second electrode 17 corresponding to the light-emitting unit 18 and the third isolation section 133.

[0170] Preferably, the third isolation portion 133 is made of molybdenum; and / or, the first isolation portion 131 is made of aluminum; and / or, the second isolation portion 132 is made of titanium. Thus, when the isolation structure 13 isolates the second electrode layer as the second electrode 17, the second electrode 17 is more easily electrically connected to the first isolation portion 131 and / or the third isolation portion 133.

[0171] In some possible implementations, please refer again. Figure 12 The isolation test structure 4 includes a first test section 401 and a second test section 402 stacked sequentially along the direction away from the substrate 6. The orthographic projection of the side of the first test section 401 away from the substrate 6 on the substrate 6 is located within the orthographic projection of the second test section 402 on the substrate 6. The test electrode 11 extends to be electrically connected to the first test section 401.

[0172] Since the second test section 402 is located on the side of the first test section 401 away from the substrate, and the lateral width of the second test section 402 is greater than the lateral width of the first test section 401, the second test section 402 will disconnect the light-emitting functional layer and the second electrode layer at the isolation test structure 4, and form the light-emitting test section 10 and the test electrode 11 in the test opening 12 respectively, and make the test electrode 11 extend to be electrically connected to the first isolation test section 41 and the second isolation test section 42.

[0173] In summary, by configuring the isolation test structure 4 to include a first isolation test section 41 and a second isolation test section 42 spaced apart from each other, and electrically connecting the first isolation test section 41 and the second isolation test section 42 through the test electrode 11, the overlapping electrode between the isolation test structure 4 and the test electrode 11 can be tested more accurately and directly. This allows for a more accurate and direct evaluation of the overlapping effect between the isolation structure 13 and the cathode of the display area AA, thereby improving the performance of the display panel motherboard.

[0174] In some possible implementations, this application also provides a method for preparing a display panel motherboard; please refer to [link to relevant documentation]. Figure 15 The preparation method includes:

[0175] S10: Provides a substrate 6;

[0176] S11: At least one test element group 1 is formed on one side of the substrate 6. The test element group 1 includes a test electrode 11 and an isolation test structure 4 disposed around the test electrode 11. The isolation test structure 4 includes at least two isolation test parts 4001 disposed at intervals from each other. The orthographic projections of the at least two isolation test parts 4001 on the substrate 6 do not overlap. The test electrode 11 is electrically connected to at least one isolation test part 4001.

[0177] In the display panel motherboard prepared by the method of this embodiment, the test electrode 11 is made of the same material as the cathode of the display area AA, and the isolation test structure 4 is made of the same material as the isolation structure 13 of the display area AA. Therefore, based on the overlap resistance between the isolation test structure 4 and the test electrode 11, the overlap resistance between the isolation structure 13 and the cathode can be known. Based on the overlap resistance between the isolation structure 13 and the cathode, the overlap effect between the isolation structure 13 and the cathode can be evaluated more accurately.

[0178] For example, the overlap resistance per unit overlap area between the isolation test structure 4 and the test electrode 11 can be calculated based on the overlap resistance between the isolation test structure 4 and the test electrode 11. Since the material of the isolation test structure 4 is the same as that of the isolation structure 13, and the materials of the test electrode 11 and the cathode are the same, the overlap resistance per unit overlap area between the isolation test structure 4 and the test electrode 11 is equal to the overlap resistance per unit overlap area between the isolation structure 13 and the cathode. Therefore, the overlap resistance between the isolation structure 13 and the cathode can be calculated more directly and accurately.

[0179] For some possible implementations, please refer to Figure 1 and Figure 16 The display panel motherboard includes a display area AA and a non-display area AB that at least partially surrounds the display area AA. The non-display area AB includes a test area AC. The test element group 1 is located in the test area AC. The isolation test structure 4 includes a first isolation test section 41 and a second isolation test section 42 that are spaced apart from each other. The step of forming at least one test element group 1 on one side of the substrate 6 includes:

[0180] S111: A first insulating material layer 25 is formed on one side of the substrate 6.

[0181] Please see Figure 17 A first insulating material layer 25 is formed on one side of the substrate 6. The first insulating material layer 25 is made of the same material as the second planarization layer 21 of the display panel motherboard, which is an organic material and has an insulating function.

[0182] S112: A first protrusion 92 is formed on the first insulating material layer 25 using a halftone mask to form the first insulating layer 9.

[0183] Please see Figure 18A first protrusion 92 is formed on the first insulating material layer 25 using a halftone mask, and the first protrusion 92 extends in a direction away from the substrate 6.

[0184] S113: A third insulating layer 8 is formed on the side of the first insulating layer 9 away from the substrate 6, and a second protrusion 82 is formed at the first protrusion 92 in the third insulating layer 8; wherein, the third insulating layer 8 is a pixel defining layer.

[0185] Please see Figure 19 A third insulating layer 8 is formed on the side of the first insulating layer 9 away from the substrate 6. Since there is a first protrusion 92 on the first insulating layer 9, a second protrusion 82 is formed on the third insulating layer 8 at the first protrusion 92.

[0186] S114: An isolation conductive layer 7 is formed on the side of the third insulating layer 8 away from the substrate 6. The isolation conductive layer 7 is patterned to form an isolation test structure 4. The isolation test structure 4 is provided with a test opening 12. The isolation test structure 4 forms a first isolation test part 41 and a second isolation test part 42 that are spaced apart from each other at the second protrusion 82. The orthographic projection of the first isolation test part 41 on the substrate 6 is located outside the orthographic projection of the second isolation test part 42 on the substrate 6.

[0187] Please see Figure 20 An isolation conductive layer 7 is formed on the side of the third insulating layer 8 away from the substrate 6. The isolation conductive layer 7 includes an isolation structure 13 and an isolation test structure 4. The isolation structure 13 is located in the display area AA, and the isolation test structure 4 is located in the test area AC. The isolation structure 13 and the isolation test structure 4 are made of the same material.

[0188] Please see Figure 21 The isolation test structure 4 on the side away from the substrate 6 of the second protrusion 82 can be removed by etching. Therefore, the isolation test structure 4 is separated by the second protrusion 82 to form the first isolation test section 41 and the second isolation test section 42. The first isolation test section 41 and the second isolation test section 42 are insulated from each other by the second protrusion 82.

[0189] S115: A second insulating layer 5 is formed on the side of the second protrusion 82 away from the substrate 6, and the second insulating layer 5 covers at least a portion of the first isolation test portion 41 and the second isolation test portion 42.

[0190] Please see again Figure 5 A second insulating layer 5 is formed on the side of the second protrusion 82 away from the substrate 6. The material of the second insulating layer 5 can be the same as the material of the first encapsulation layer 22 of the display panel motherboard. The second encapsulation layer 23 can protect the exposed parts of the first isolation test part 41 and the second isolation test part 42.

[0191] S116: A light-emitting test section 10 and a test electrode 11 are sequentially formed on the side away from the substrate 6 within the test opening 12. The test electrode 11 extends to be electrically connected to the first isolation test section 41 and the second isolation test section 42.

[0192] Please see again Figure 3 A light-emitting test section 10 and a test electrode 11 are sequentially formed on the side away from the substrate 6 within the test opening 12.

[0193] When the light-emitting functional layer is formed, the light-emitting functional layer is separated by the isolation structure 13 to form multiple light-emitting parts 16 spaced apart and located in the isolation opening 14. The light-emitting functional layer is also separated by the isolation conductive layer 7 to form a light-emitting test part 10 located in the test opening 12.

[0194] When forming the second electrode layer, the second electrode layer is separated by the isolation structure 13 to form multiple spaced second electrodes 17 located within the isolation opening 14. The isolation structure 13 includes a conductive material, and the second electrodes 17 are electrically connected to the isolation structure 13. The second electrode layer is also separated by the isolation conductive layer 7 to form test electrodes 11 located within the test opening 12. Both the first isolation test section 41 and the second isolation test section 42 include conductive materials, and the test electrodes 11 extend to be electrically connected to the first isolation test section 41 and the second isolation test section 42. A first electrode 15, a light-emitting section 16, and a second electrode 17 form a light-emitting unit 18. Among them, the first electrode 15 is the anode, and the second electrode 17 is the cathode.

[0195] Thus, when forming the light-emitting functional layer, the light-emitting part 16 can be formed in the display area AA and the light-emitting test part 10 can be formed in the test area AC at the same time; when forming the second electrode layer, the second electrode 17 can be formed in the display area AA and the test electrode 11 can be formed in the test area AC at the same time, so that it is not necessary to set the light-emitting test part 10 and the test electrode 11 through a special process, thereby reducing the cost of forming the light-emitting test part 10 and the test electrode 11.

[0196] Thus, the first isolation test section 41 and the second isolation test section 42 of the display panel motherboard formed by the method of this embodiment can be more easily separated, thereby allowing the connection resistance between the isolation structure 13 and the cathode to be calculated more directly and accurately, and thus allowing the connection effect between the isolation structure 13 and the cathode of the display area AA to be evaluated more directly and accurately.

[0197] Please see Figure 22 Remove the AC test area. The AC test area of ​​the display panel motherboard will eventually be removed.

[0198] For some possible implementations, please refer to Figure 23This application also provides a testing method for a display panel motherboard, the display panel motherboard including the display panel motherboard of this application, the testing method including:

[0199] S20: Obtain the sum of the lap resistances of the test electrode 11 and any two isolation test sections 4001.

[0200] Please see again Figure 2 and Figure 3 For example, the resistor display panel motherboard can be electrically connected to pin 2 of the test trace 3, and the sum of the contact resistances between the first isolation test section 41 and the second isolation test section 42 and the test electrode 11 can be directly tested through the resistor display panel motherboard.

[0201] S21: Based on the sum of the overlap resistances of the test electrode 11 and any two isolation test sections 4001, determine the overlap effect between the isolation structure 13 of the display area AA of the display panel motherboard and the second electrode 17.

[0202] Since the test electrode 11 is made of the same material as the cathode of the display area AA, and the isolation test structure 4 is made of the same material as the isolation structure 13 of the display area AA, the connection resistance between the isolation structure 13 and the cathode can be determined by the sum of the connection resistances between the test electrode 11 and any two isolation test sections 4001, for example, the sum of the connection resistances between the test electrode 11 and the first isolation test section 41 and the second isolation section. The connection effect between the isolation structure 13 and the cathode can be evaluated more accurately based on the connection resistance between the isolation structure 13 and the cathode.

[0203] For example, the overlap resistance per unit overlap area between the isolation test structure 4 and the test electrode 11 can be calculated based on the overlap resistance between the isolation test structure 4 and the test electrode 11. Since the material of the isolation test structure 4 is the same as that of the isolation structure 13, and the materials of the test electrode 11 and the cathode are the same, the overlap resistance per unit overlap area between the isolation test structure 4 and the test electrode 11 is equal to the overlap resistance per unit overlap area between the isolation structure 13 and the cathode. Therefore, the overlap resistance between the isolation structure 13 and the cathode can be calculated more directly and accurately.

[0204] Preferably, please refer to Figure 24When multiple isolation test sections 4001 are included, any two isolation test sections 4001 are selected to form a circuit under test with the test electrode 11. The test angle β is determined based on the connection angle between the centers of the two isolation test sections 4001 and the test electrode 11. Based on the results of the test circuit, the overlap effect between the isolation structure 13 and the second electrode 17 of the light-emitting unit corresponding to the test element group in the test angle β is determined. The light-emitting part material of the light-emitting unit corresponding to the test element group is the same as the test light-emitting part material. Thus, the overlap effect between the isolation structure 13 and the second electrode 17 can be evaluated by testing the overlap resistance between any two isolation test sections 4001 and the test electrode 11.

[0205] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0206] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel motherboard, characterized in that, The display panel motherboard includes: Substrate; At least one test element group located on one side of the substrate, the test element group including a test electrode and an isolation test structure disposed around the test electrode, the isolation test structure including at least two isolation test parts disposed at intervals from each other, the orthographic projections of the at least two isolation test parts on the substrate not overlapping each other; The test element group further includes at least two partitions, which are disposed between two adjacent isolation test sections. The isolation test sections and the partitions are arranged around the test electrode. At least two isolation test sections and at least two partitions are arranged continuously to form an annular test opening.

2. The display panel motherboard according to claim 1, characterized in that, The test electrode is disposed within the test opening; The partition includes insulating material.

3. The display panel motherboard according to claim 1, characterized in that, The display panel motherboard also includes a conductive layer located on the side of the test element group near the substrate. The conductive layer includes multiple test traces, and each test element group is provided with at least two test traces. The isolation test section is electrically connected to one of the test traces.

4. The display panel motherboard according to claim 3, characterized in that, The display panel motherboard also includes a first insulating layer located on the side of the conductive layer away from the substrate, and the test element group is located on the side of the first insulating layer away from the substrate; Along a direction perpendicular to the substrate, the first insulating layer has a plurality of first test vias, the first test vias exposing at least a portion of the test traces, and the isolation test section is electrically connected to the test traces through the first test vias.

5. The display panel motherboard according to claim 4, characterized in that, The first insulating layer includes a first protrusion extending in a direction away from the substrate, wherein at least a portion of the orthographic projection of the first protrusion on the substrate lies between the orthographic projections of the adjacent isolation test portion on the substrate; Along the side away from the substrate, the first protrusion extends to the side of the test element group opposite to the substrate to form a partition between adjacent isolation test structures.

6. The display panel motherboard according to claim 5, characterized in that, The display panel motherboard further includes a third insulating layer located on the side of the first insulating layer away from the substrate. Along a direction perpendicular to the substrate, the third insulating layer has a plurality of second test vias exposing at least a portion of the test traces. The isolation test portion is electrically connected to the test traces through the second test vias and the first test vias, respectively.

7. The display panel motherboard according to claim 6, characterized in that, The third insulating layer is further provided with a partition opening, and at least a portion of the first protrusion is disposed within the partition opening.

8. The display panel motherboard according to claim 1, characterized in that, The display panel motherboard also includes a first insulating layer and a third insulating layer disposed sequentially along the side away from the substrate, and the test element group is located on the side of the third insulating layer away from the substrate.

9. The display panel motherboard according to claim 6, characterized in that, The first insulating layer includes a first protrusion extending in a direction away from the substrate, and the third insulating layer includes a second protrusion located on the side of the first protrusion away from the substrate, extending in a direction away from the substrate to the side of the test element group opposite to the substrate, wherein the first protrusion and the second protrusion form a partition between adjacent isolation test structures.

10. The display panel motherboard according to claim 9, characterized in that, At least a portion of the first protrusion and at least a portion of the second protrusion have their orthographic projections on the substrate located between the orthographic projections of the adjacent isolation test portions on the substrate.

11. The display panel motherboard according to claim 9, characterized in that, The display panel motherboard further includes a second insulating layer located on the side of the second protrusion away from the substrate. The second insulating layer covers at least a portion of the isolation test portion, and the orthogonal projection of the second protrusion on the substrate is located within the orthogonal projection range of the second insulating layer on the substrate.

12. The display panel motherboard according to claim 9, characterized in that, The second protrusion contacts the side of the two adjacent isolation test portions.

13. The display panel motherboard according to claim 12, characterized in that, The display panel motherboard also includes a first insulating layer and a third insulating layer disposed sequentially on the side away from the substrate, and the test element group is located on the side of the third insulating layer away from the substrate.

14. The display panel motherboard according to claim 13, characterized in that, The third insulating layer includes a second protrusion extending away from the substrate, the second protrusion extending to the side of the test element group opposite to the substrate, to form a partition between adjacent isolation test structures.

15. The display panel motherboard according to claim 14, characterized in that, At least a portion of the second protrusion's orthogonal projection on the substrate lies between the orthogonal projections of the adjacent isolation test portion on the substrate.

16. The display panel motherboard according to claim 14, characterized in that, The second protrusion contacts the side of the two adjacent isolation test portions.

17. The display panel motherboard according to claim 14, characterized in that, The display panel motherboard also includes a second insulating layer located on the side of the second protrusion away from the substrate, the second insulating layer covering at least a portion of the isolation test section.

18. The display panel motherboard according to claim 6, characterized in that, The third insulating layer extends to the display area of ​​the display panel motherboard, and the third insulating layer also includes pixel openings located in the display area.

19. The display panel motherboard according to claim 4, characterized in that, It also includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked sequentially in a direction away from the substrate, wherein the test trace is located in any one of the first conductive layer, the second conductive layer, the third conductive layer or the fourth conductive layer.

20. The display panel motherboard according to claim 19, characterized in that, The test trace is located in the fourth conductive layer.

21. The display panel motherboard according to claim 20, characterized in that, A first planarization layer is provided between the third conductive layer and the fourth conductive layer, and a second planarization layer is provided on the side of the fourth conductive layer away from the substrate. The first insulating layer includes the second planarization layer, and the first test via is disposed on the second planarization layer.

22. The display panel motherboard according to claim 1, characterized in that, The test element group also includes a light-emitting test section located within the test opening, the light-emitting test section being located on the side of the test electrode closer to the substrate.

23. The display panel motherboard according to any one of claims 1-22, characterized in that, The isolation test structure includes a first isolation test section and a second isolation test section that are spaced apart from each other. The test element group also includes a first partition section and a second partition section located between the first isolation test section and the second isolation test section. The first isolation test section, the first partition section, the second isolation test section and the second partition section are arranged in sequence and surround to form a test opening. The test electrode is disposed in the test opening.

24. A method for preparing a display panel motherboard, characterized in that, The preparation method includes: Provide a substrate; At least one test element group is formed on one side of the substrate. The test element group includes a test electrode and an isolation test structure disposed around the test electrode. The isolation test structure includes at least two isolation test portions disposed at intervals from each other. The orthographic projections of the at least two isolation test portions on the substrate do not overlap. The test element group also includes at least two partition portions disposed between two adjacent isolation test portions. The isolation test portions and the partition portions are disposed around the test electrode. The at least two isolation test portions and the at least two partition portions are continuously disposed and form an annular test opening.

25. A testing method for a display panel motherboard, characterized in that, The display panel motherboard includes the display panel motherboard as described in any one of claims 1-23, and the test method includes: Obtain the sum of the overlap resistances between the test electrode and any two of the isolation test sections; Based on the sum of the overlap resistances of the test electrode and any two of the isolation test sections, the overlap effect between the isolation structure of the display area of ​​the display panel motherboard and the second electrode is determined. Select any two of the isolation test sections and the test electrode to form a circuit to be tested, and determine the test angle based on the connection angle between the centers of the two isolation test sections and the test electrode; Based on the results of the test circuit, the connection effect between the isolation structure and the second electrode of the corresponding light-emitting unit at the test angle is determined.

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