A pre-routing timing prediction method for digital integrated circuit perceptual optimization, electronic equipment and storage medium

Abstract

The application discloses a wiring-before-timing prediction method for digital integrated circuit perceptible optimization, electronic equipment and storage medium, a heterogeneous graph is constructed according to a circuit netlist, the heterogeneous graph is fused with feature vectors corresponding to each unit and interconnection line, and then input into a trained heterogeneous graph neural network to obtain graph network embedding; a feature matrix of a layout is input into a trained convolutional neural network to obtain convolutional network embedding; the graph network embedding and the convolutional network embedding are spliced to obtain multi-modal local embedding; according to the connection relationship between logic units and interconnection lines in a path, a feature sequence of the path is constructed, the feature sequence of the path is input into a trained Transform network to obtain a wiring-after-path delay residual prediction value; the layout-after-path delay value and the wiring-after-path delay residual prediction value are added to finally obtain a wiring-after-path delay prediction value. The application can accurately and efficiently predict the wiring-after-path delay before wiring.

Description

Technical Field

[0001] This invention relates to a method for pre-routing timing prediction with perceptible optimization of digital integrated circuits, an electronic device, and a storage medium, belonging to the field of electronic design automation technology. Background Technology

[0002] In the circuit physical design process, multiple rounds of circuit optimization are typically required to achieve a trade-off between power consumption, performance, and area. Static timing analysis is frequently invoked to check whether the circuit timing is closed and converged, thereby guiding designers to fix timing violations in a timely manner and perform circuit optimization. Timing analysis and timing optimization often account for up to 60% of the total circuit design time; therefore, the accuracy and efficiency of static timing analysis are crucial to circuit design.

[0003] Circuit physical design begins with the circuit netlist obtained after logic synthesis, and proceeds through steps such as layout planning, placement, clock tree synthesis, and routing to ultimately generate the circuit layout. As the physical design progresses, the timing analysis results become increasingly accurate. However, during the placement phase, because the circuit has not yet been routed, the lack of actual parasitic parameters of the conductors leads to significant differences between the timing analysis results at this stage and the timing after routing. At advanced process nodes, wire delays account for a larger proportion, and routing behavior is more complex. Factors such as congestion, conductor detours, and metal layer allocation have a more significant impact on timing. Furthermore, during the routing phase, in addition to timing changes caused by conductor parasitic parameters, necessary timing optimization measures, such as gate size adjustments, threshold voltage allocation, buffer insertion, and logic reconfiguration, will also lead to further timing changes.

[0004] Therefore, how to perform accurate timing estimation before routing during the placement phase has become a pressing issue in circuit physical design. Inaccurate timing estimation results will significantly impact the quality and efficiency of circuit placement and routing. Summary of the Invention

[0005] Objective: To overcome the shortcomings of existing technologies, this invention provides a timing prediction method, electronic device, and storage medium for pre-routing optimization of digital integrated circuits. It can accurately predict the path delay after routing during the layout stage before routing, thereby effectively guiding the design and optimization of circuits before routing.

[0006] Technical solution: To solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0007] Firstly, a pre-routing timing prediction method for digital integrated circuits that is aware of optimization specifically includes:

[0008] Static timing analysis is performed on the laid-out circuit to obtain the circuit layout, the feature vectors corresponding to each cell and interconnect, and the path delay value after layout. The feature matrix of the layout is constructed based on the physical information of the circuit layout.

[0009] A heterogeneous graph is constructed based on the circuit netlist. The heterogeneous graph is then fused with the feature vectors corresponding to each cell and interconnect, and input into a trained heterogeneous graph neural network to obtain the graph network embedding. The feature matrix of the layout is then input into a trained convolutional neural network to obtain the convolutional network embedding. The graph network embedding and the convolutional network embedding are concatenated to obtain the multimodal local embedding.

[0010] The multimodal local embedding is concatenated according to the connection relationship between the logic unit and the interconnect in the path to obtain the temporal stage embedding of the path. The feature sequence of the path is constructed from the temporal stage embedding. The feature sequence of the path is input into the trained Transformer network to obtain the predicted value of the path delay residual after routing. The path delay value after placement is added to the predicted value of the path delay residual after routing to finally obtain the predicted value of the path delay after routing.

[0011] As a preferred embodiment, the feature vectors corresponding to each cell and interconnect include, but are not limited to: the timing information of each cell, the physical information of each cell, and the physical information of the interconnect. The feature matrix of the layout includes: cell density, pin density, rectangular uniform line density, and pin rectangular uniform line density.

[0012] As a preferred embodiment, the heterogeneous graph is constructed based on the circuit netlist. The heterogeneous graph is then fused with the feature vectors corresponding to each unit and interconnect, and input into a trained heterogeneous graph neural network to obtain a graph network embedding. The feature matrix of the layout is input into a trained convolutional neural network to obtain a convolutional network embedding. The graph network embedding and the convolutional network embedding are concatenated to obtain a multimodal local embedding, specifically including:

[0013] Based on the connection relationships in the circuit netlist, a heterogeneous graph is constructed using cell nodes, pin nodes, and interconnects. Among them, cell timing arcs, interconnect timing arcs, and edges connecting cell nodes and pin nodes represent three different adjacency relationships.

[0014] After fusing the heterogeneous graph with the feature vectors corresponding to each unit and interconnection, the graph is input into the trained heterogeneous graph neural network, and the output is the graph network embedding, which includes: graph network local node embedding and graph network local edge embedding.

[0015] The feature matrix of the layout is input into the trained convolutional neural network to obtain the convolutional network embedding, which includes: unit convolutional network embedding, pin convolutional network embedding, unit temporal arc convolutional network embedding and interconnection temporal arc convolutional network embedding.

[0016] In the local edge embedding of graph networks, the unit temporal arc graph network embedding, the interconnection temporal arc graph network embedding, and the local embedding of convolutional networks, the unit temporal arc convolutional network embedding and the interconnection temporal arc convolutional network embedding are all performed. According to the positional relationship of the temporal arcs in the layout, the unit temporal arcs and interconnection temporal arcs in the corresponding networks are spliced ​​together to obtain multimodal local embedding. The multimodal local embedding includes multimodal local embedding of unit temporal arcs and multimodal local embedding of interconnection temporal arcs.

[0017] As a preferred embodiment, the step of concatenating the multimodal local embeddings according to the connection relationship between logical units and interconnects in the path to obtain the embeddings of the temporal stages of the path, and constructing the feature sequence of the path from the embeddings of the temporal stages of the path, specifically includes:

[0018] Each unit timing arc and subsequent interconnect timing arcs are treated as a timing stage, and each timing path consists of a sequence of multiple timing stages.

[0019] The multimodal local embedding of cell timing arcs and interconnect timing arcs are spliced ​​together according to the connection relationship between cell timing arcs and interconnect timing arcs in the timing stage to obtain the timing stage embedding of the path.

[0020] The embedding of the temporal stages of the path is used to construct the feature sequence of the path.

[0021] As a preferred embodiment, the method for obtaining the trained heterogeneous graph neural network and convolutional neural network specifically includes:

[0022] Obtain the feature matrix of the layout of the circuit after layout, and the feature vectors corresponding to each cell and interconnect.

[0023] Obtain the unit and interconnect delay values ​​of the circuit after layout and routing.

[0024] The feature matrix of the layout of the circuit after layout, the feature vectors corresponding to each unit and interconnect, and the delay values ​​of the units and interconnects of the circuit after routing are used as training samples. The training samples are used to train the local prediction model composed of the convolutional neural network, the heterogeneous graph neural network, and the first multilayer sensing mechanism to obtain the trained convolutional neural network and the heterogeneous graph neural network.

[0025] As a preferred embodiment, the method for obtaining the trained Transformer network specifically includes:

[0026] Obtain the circuit layout corresponding to the laid-out circuit and the feature vectors corresponding to each unit and interconnect. Construct the feature matrix of the layout based on the physical information of the circuit layout.

[0027] A heterogeneous graph is constructed based on the circuit netlist. The heterogeneous graph is then fused with the feature vectors corresponding to each cell and interconnect, and input into a trained heterogeneous graph neural network to obtain the graph network embedding. The feature matrix of the layout is then input into a trained convolutional neural network to obtain the convolutional network embedding. The graph network embedding and the convolutional network embedding are concatenated to obtain the multimodal local embedding.

[0028] The multimodal local embedding is spliced ​​together according to the connection relationship between the logical units and interconnects in the path to obtain the embedding of the temporal stage of the path, and the feature sequence of the path is constructed from the embedding of the temporal stage of the path.

[0029] Obtain the path delay value of the circuit after layout and routing.

[0030] The feature sequence of the path and the path delay value of the circuit after wiring are used as training samples. The training samples are used to train all the prediction models composed of the Transformer network, pooling layer and second multilayer sensing mechanism to obtain the trained Transformer network.

[0031] In a second aspect, a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a digital integrated circuit-aware optimized pre-routing timing prediction method as described in any of the first aspects.

[0032] Thirdly, a computer device comprising:

[0033] Memory is used to store instructions.

[0034] A processor for executing the instructions, causing the computer device to perform operations of a digital integrated circuit-aware optimized pre-routing timing prediction method as described in any of the first aspects.

[0035] Beneficial Effects: This invention provides a pre-routing timing prediction method, electronic device, and storage medium for digital integrated circuits with perceptible optimization. First, this invention establishes a local timing prediction model based on graph neural networks and convolutional neural networks. This model aligns and fuses netlist heterogeneous graph embeddings and layout image embeddings to generate multimodal local embeddings of circuit pins, cells, and interconnects for local timing prediction. Second, this invention establishes a global timing prediction model based on transformer networks. This model uses the multimodal local embeddings of cells and interconnects generated by the local timing prediction model as feature inputs. It captures global physical and timing correlations on timing paths through a multi-head self-attention mechanism to generate multimodal global embeddings of timing paths for global timing prediction.

[0036] Compared with the traditional static timing analysis process, the advantages of this invention are as follows:

[0037] This invention can accurately and efficiently predict the path delay after routing before routing, and can better identify optimization difficulties, thereby effectively guiding the design and optimization of circuits before routing, which is of great significance for accelerating the digital integrated circuit design process. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the overall framework of the delay prediction method of the present invention.

[0039] Figure 2 This is a schematic diagram of a local time series prediction method.

[0040] Figure 3 This is a schematic diagram of the convolutional neural network structure used in this invention.

[0041] Figure 4 This is a schematic diagram of a global time series prediction method. Detailed Implementation

[0042] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0043] The present invention will be further described below with reference to specific embodiments.

[0044] Example 1:

[0045] This embodiment introduces a pre-routing timing prediction method for digital integrated circuits that is aware of optimization, such as... Figure 1 As shown, the post-routing delay prediction refers to the prediction of post-routing delay after circuit optimization during the placement stage of the digital integrated circuit back-end design flow; the delay prediction includes the prediction of local delay and path delay; the local delay includes the delay of timing arcs of combinational logic units and timing arcs of metal interconnects; the path contains at least two levels of combinational logic units and does not contain sequential logic units; the method includes the following steps:

[0046] Step S1: Perform physical design on the circuit netlist after logic synthesis using physical design tools. The design steps include placement planning, placement, placement optimization, clock tree synthesis, and routing to obtain the circuit after placement and the circuit after routing.

[0047] Step S2: Extract sample data. Perform static timing analysis on the circuit after placement and the circuit after routing in Step S1 using a static timing analysis tool. Extract the timing and physical information of each cell and interconnect, as well as the path delay value after placement, from the static timing report and circuit layout information of the circuit after placement. Extract the connection relationship of the circuit netlist and construct the feature vectors corresponding to the circuit layout and each cell and interconnect. Construct the feature matrix of the layout based on the physical information of the overall circuit layout. Extract the delay values ​​of the corresponding cells, interconnects, and paths as labels from the static timing analysis report of the circuit after routing.

[0048] Furthermore, the feature vectors corresponding to each unit and interconnect include, but are not limited to: the timing of each unit, the physical information of each unit, and the physical information of the interconnect.

[0049] The timing information for each unit includes: the timing arc delay of the current unit and the timing information of the current unit's pins. Specifically, the timing arc delay of the current unit is selected as the worst-case delay among all timing arcs of the current unit; the timing information of the current unit's pins is selected as the longest transition time among all pins of the current unit.

[0050] The physical information of each unit includes: the number of fan-in units, the drive strength of units, the number of fan-out units, the type of units, the threshold voltage type of units, whether the drive strength of units is adjustable, the threshold voltage type, and the physical information of unit pins.

[0051] Physical information of the interconnect includes the distances between the drive and receive pins of the interconnect in the x-axis and y-axis directions, respectively.

[0052] The timing arc delay of this unit includes the rising delay and falling delay of the timing arc.

[0053] The timing of the unit pins at this level includes: the rise and fall transition times of the unit pins, and the rise and fall timing margins of the unit pins.

[0054] The physical information of the unit pin includes: whether the unit pin is an output pin, the rising and falling capacitance of the unit pin, and the position coordinates of the unit pin in the x and y directions.

[0055] Furthermore, the feature matrix of the layout includes: cell density, pin density, rectangular uniform line density (RUDY), and pin rectangular uniform line density (pinRUDY).

[0056] The element density represents the number of elements in the mesh, and its expression is as follows:

[0057] (1)

[0058] in, Let be the cell density of the grid in the k-th row and l-th column. For the grid in row k and column l, and Let be the coordinates of element c along the x-axis and y-axis. Element coordinates are defined as the coordinates of the center of the element.

[0059] Pin density indicates the number of pins in the grid.

[0060] The rectangular uniform line density represents the sum of the rectangular uniform line densities of all interconnects within the mesh.

[0061] The rectangular uniform line density expression for one interconnect line e is as follows:

[0062] (2)

[0063] in, The rectangular uniform line density of the interconnect line e of the grid in row k and column l. , , and These represent the minimum coordinates, maximum coordinates, minimum coordinates, and maximum coordinates of the network along the x-axis, respectively. This indicates the grid where interconnect line e is located.

[0064] The pin rectangular uniform line density represents the rectangular uniform line density of the interconnects connecting the pins, where the pin rectangular uniform line density within the grid is the sum of the pin rectangular uniform line densities of all pins in the grid.

[0065] Furthermore, the circuit layout is divided into 512×512 grids.

[0066] S3: Construct a heterogeneous graph using the circuit netlist connection information, and input the feature vectors of cells and interconnects into the heterogeneous graph neural network for aggregation and updating to obtain the graph network embedding. Input the feature matrix of the layout into a convolutional neural network to obtain the convolutional network embedding. According to the position of cells and interconnects in the circuit layout, concatenate the two embeddings to obtain a multimodal local embedding, and then pass it through a multilayer perceptron to obtain the delay prediction values ​​of cells and interconnects. Use the post-routing cell and interconnect delays extracted in step S2 as labels to train the heterogeneous graph neural network and the convolutional neural network.

[0067] Furthermore, step S3, as follows: Figure 2 , 3 As shown, it specifically includes:

[0068] S31: Based on the connection relationship of the circuit netlist, construct a heterogeneous graph using cell nodes, pin nodes, and interconnects. Among them, cell timing arcs, interconnect timing arcs, and edges connecting cell nodes and pin nodes are three different adjacency relationships.

[0069] S32: Based on the feature vectors corresponding to each unit and interconnect, assign initial feature vectors to each node and edge in the heterogeneous graph. Then, pass the initial feature vectors of each node and edge through a fully connected layer to output a dimension of d. n eigenvectors of nodes eigenvectors of edges of dimension de ,in, This represents the feature vector of the node at layer 0. This represents the feature vector of the 0th layer unit node. The feature vector representing the pin node of layer 0; This represents the feature vector of the edge at layer 0. This represents the feature vector of the temporal arc edge of the 0th layer unit. This represents the feature vector of the timing arc edge of the layer 0 interconnect.

[0070] S33: Input the feature vectors of the heterogeneous graph, nodes, and edges into the heterogeneous graph neural network to perform neighbor aggregation and information update for node and edge embeddings. For the k-th layer network, the embeddings output by the (k-1)-th layer are aggregated. First, edge aggregation and node aggregation are performed. The edge and node embeddings before and after aggregation are then added and normalized through residual connections to finally obtain the node and edge graph network embeddings output by the k-th layer network.

[0071] S34: The total number of layers in the heterogeneous graph neural network is K1. The output embedding of each layer is fed into a second fully connected layer after passing through residual connections to retain the node and edge embeddings from different neighbor aggregation distances in each layer. After concatenation and transformation, the graph network local node embedding H and graph network local edge embedding E are finally generated. The process expression is as follows:

[0072] { H = W h K 1 [ H ( 1 ) ‖ … ‖ H ( K 1 ) ] E = W e K 1 [ E ( 1 ) ‖ … ‖ E ( K 1 ) ] (3)

[0073] in, This represents the node weight parameters of the K1-th layer network. This represents the node embedding of the first-layer network. This represents the node embedding of the K1 layer network. This represents the edge weight parameters of the K1-th layer network. This represents the edge embedding of the first layer network. This represents the edge embedding of the K1-th layer network. Indicates splicing.

[0074] S35: The feature matrix of the layout is input into the convolutional neural network, first passing through a K2 encoder layer, and then through a K2 decoder layer. With each encoder layer, the image height and width are halved, but the number of channels doubles; with each decoder layer, the image height and width double, but the number of channels is halved. Skip connections exist between the encoder and decoder layers to concatenate the outputs of the encoder and decoder layers, resulting in the next decoder layer. The decoder's output image has the same size and number of channels as the input. Finally, the output image passes through one output convolutional layer, generating four types of convolutional network local embeddings for the circuit's units, pins, unit timing arcs, and interconnect timing arcs. .

[0075] S36: Embedding local edges of the graph network into the unit time-series arc graph network in E Interconnect time-series arc diagram network embedding and convolutional network local embedding Embedding of Mid-Unit Temporal Arc Convolutional Networks Interconnected temporal arc convolutional network embedding Based on the positional relationship of the temporal arcs in the layout, the graph network embeddings and convolutional network embeddings in the corresponding grid points are concatenated to obtain the multimodal local embeddings of the unit temporal arcs. Multimodal local embedding of interconnect timing arcs .

[0076] Furthermore, the heterogeneous graph neural network employs a heterogeneous graph attention network (HGAT).

[0077] Furthermore, the convolutional neural network is a U-shaped convolutional neural network.

[0078] S4: After training the heterogeneous graph neural network and the convolutional neural network, the multimodal local embedding of the concatenated outputs of the two networks is performed. Following the connection relationships in the circuit, the embeddings are concatenated according to the cell-interconnection rules to obtain the embeddings for the timing stages. Then, according to the connection relationships of each stage in the timing path, the feature matrix of each timing path is constructed and input into the Transformer network to obtain the difference between the predicted path delay after routing and the laid-out path delay. The output is then processed through pooling and a multilayer perceptron to obtain the predicted path delay after routing. The path delay after routing extracted in step S2 is used as a label to train the Transformer network.

[0079] Furthermore, step S4, as follows: Figure 4 As shown, it specifically includes:

[0080] S41: Serialize the timing paths in the circuit. Each unit timing arc and its subsequent interconnect timing arcs are considered a timing stage, and each timing path is considered a sequence of multiple timing stages. Multimodal local embeddings are concatenated according to the connection relationships of the timing stages to obtain the timing stage embeddings. The initial features of each timing stage in the timing path constitute the initial feature sequence of that timing path, which will be used to generate the global embedding of the timing path through sequence learning.

[0081] S42: During the input embedding process, each input feature sequence has a dedicated trainable embedding layer that transforms each element in the input feature sequence into a dimension of dim. k A vector. That is, converting the input feature sequence of dimension (samples, max_len) into a vector of dimension (samples, max_len, dim). k A tensor of ), where samples is the number of samples, max_len is the maximum number of levels in the path, and dim k is the word vector dimension specified by the k-th feature sequence in the embedding layer, k=1,2,…,n, where n is the number of feature sequences. During positional encoding, the trigonometric functions shown in formulas (4) and (5) are used to help the network understand the positional relationships of features at each level of the path within the sequence. Here, pos represents the position of a feature value in the sequence, pos =1,2,…,max_len, and m is the dimension index of the positional encoding sequence for that feature value, m=0,1,…,dim. k / 2-1, where even-numbered dimensions (2m) are encoded using a sine function (sin), and odd-numbered dimensions (2m+1) are encoded using a cosine function (cos). After positional encoding, the output tensor also has dimensions (samples, max_len, dim). k That is, the position of the feature value at the feature sequence pos is encoded as PE at 2m. (pos,2m) The encoded value at 2m+1 is PE. (pos,2m+1) For each feature sequence, the position-encoded output tensor is added to the input-embedded output tensor to obtain n-dimensional tensors with dimensions (samples, max_len, dim). k The new tensor of ).

[0082] (4)

[0083] (5)

[0084] S43: Merge the n new tensors from step S42 to obtain a tensor of dimension (samples, max_len, dim), which serves as the input X for the multi-head self-attention mechanism, where dim = dim1 + dim2 + ... + dim n n is the number of input feature sequences. The j-th row vector of X is the comprehensive feature representation of the j-th level unit in the path in terms of temporal and physical information, j=1,2,…,max_len. This is achieved through three trainable matrices W... i Q W i K W i V Let i = 1, 2, ..., h. Perform h linear transformations on X to obtain h sets of word vectors, each with a dimension of d. k =dim / h matrix Q i K i V i , where h is the number of heads in the self-attention mechanism, and Q, K, and V represent query, key, and value, respectively. For h groups Q i K i V i The attention function is executed in parallel, and the calculation formula based on the dot product attention mechanism is Equation (6). First, Q is calculated. i With K i The dot product of the transpose and divided by the coefficient d k 1 / 2 The weight matrix C is then obtained through softmax operation, and finally the weight matrix C is multiplied by V. i The dimension is d k The matrix Z i This is the computational result of the attention mechanism: Attention (Q) i ,K i V i The elements in the a-th row and b-th column of the weight matrix C can be considered as the temporal and physical dependencies of the a-th and b-th level units in the path, where a = 1, 2, ..., max_len; b = 1, 2, ..., max_len. Matrix Z... i The number of row vectors is the same as the input X, therefore Z i Row vectors also have similar unit timing and physical meanings to X.

[0085] (6)

[0086] The calculation results of the merged head attention mechanism are head i Let i = 1, 2, ..., h, and pass through a trainable matrix W. OA linear transformation is performed to obtain the output MultiHead(X) of the multi-head self-attention mechanism. The calculation formula for the multi-head self-attention mechanism is Equation (7), where X is the input of the multi-head self-attention mechanism, W... i Q W i K W i V W O Let i be a trainable matrix, i = 1, 2, ..., h.

[0087] (7)

[0088] S44: Add the input X and output MultiHead(X) of the multi-head self-attention mechanism in step S43 and standardize them to avoid gradient vanishing and gradient explosion. The output of the standardization layer of the multi-head self-attention mechanism can be expressed as formula (8), where LayerNorm() is the output function of the standardization layer.

[0089] (8)

[0090] S45: The output standardized by the multi-head self-attention mechanism in step S44 is fed into a fully connected feedforward neural network, where neurons in adjacent layers are fully connected. First, the input undergoes a linear transformation, then passes through the linear rectified activation function max(0,s), where s is the input of the linear rectified activation function, and finally undergoes another linear transformation. t is the input of the fully connected feedforward neural network, and W1, b1 and W2, b2 are the parameters of the two linear transformations, respectively. The output calculation formula of the fully connected feedforward neural network is formula (9):

[0091] (9)

[0092] S46: Add the input t and output FFN(t) of the fully connected feedforward neural network in step S45 and standardize them to avoid gradient vanishing and gradient explosion. The output of the standardization layer of the feedforward neural network can be expressed as formula (10), where LayerNorm() is the output function of the standardization layer.

[0093] (10)

[0094] S47: The output of the normalized layer of the fully connected feedforward neural network in step S46 is fed into a pooling layer to flatten the 3D data into 2D data, and then fed into a fully connected (dense) layer for nonlinear transformation. A dropout function is used to randomly discard some information to prevent overfitting. Subsequently, the data is merged with the pre-route path delay features after nonlinear transformation and random information discarding, and the merged data is nonlinearly transformed to one dimension to obtain the predicted path delay residual values ​​before and after routing.

[0095] Furthermore, the transformer network includes: input embedding and position encoding, multi-head self-attention mechanism, fully connected feedforward network, addition and normalization.

[0096] S5: The circuit layout connection information and feature vectors of each unit and interconnect extracted after step S2 are input into the trained heterogeneous graph neural network. After aggregation, the graph network embedding outputs of each unit and interconnect are obtained. The extracted layout feature matrix is ​​input into the trained convolutional neural network. According to the positional relationship of each unit and interconnect in the circuit layout, the corresponding convolutional network embedding outputs of each unit and interconnect are obtained. The two different embedding outputs are concatenated according to the positional relationship of each unit and interconnect in the circuit layout to obtain the multimodal local embeddings of each unit and interconnect.

[0097] S6: The multimodal local embeddings of the cells and interconnects obtained in step S5 are used to concatenate the multimodal local embeddings of each cell and interconnect according to the connection relationship between the logic cells and interconnects in the path, thus obtaining the temporal stage embedding of the path. The feature matrix of the temporal path is constructed from the temporal stage embedding of the path and input into the trained Transformer network to obtain the predicted value of the path delay residual after routing. The path delay value after placement is added to the predicted value of the path delay residual after routing to obtain the final predicted value of the path delay after routing.

[0098] Example 2:

[0099] This embodiment describes a computer-readable storage medium storing a computer program that, when executed by a processor, implements a digital integrated circuit-aware optimization pre-routing timing prediction method as described in any of Embodiment 1.

[0100] Example 3

[0101] This embodiment describes a computer device, including:

[0102] Memory is used to store instructions.

[0103] A processor is configured to execute the instructions, causing the computer device to perform operations of a digital integrated circuit-aware optimized pre-routing timing prediction method as described in any of Embodiment 1.

[0104] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0105] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0106] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0107] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0108] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A pre-routing timing prediction method for digital integrated circuits with perceptible optimization, characterized in that: Specifically, it includes: Static timing analysis is performed on the laid-out circuit to obtain the circuit layout, the feature vectors corresponding to each cell and interconnect, and the path delay value after placement. The feature matrix of the layout is constructed based on the physical information of the circuit layout. A heterogeneous graph is constructed based on the circuit netlist. The heterogeneous graph is then fused with the feature vectors corresponding to each unit and interconnect and input into a trained heterogeneous graph neural network to obtain the graph network embedding. The feature matrix of the layout is input into a trained convolutional neural network to obtain the convolutional network embedding. The graph network embedding and the convolutional network embedding are concatenated to obtain the multimodal local embedding. The multimodal local embedding is concatenated according to the connection relationship between the logic unit and the interconnect in the path to obtain the temporal stage embedding of the path. The feature sequence of the path is constructed from the temporal stage embedding. The feature sequence of the path is input into the trained Transformer network to obtain the predicted value of the path delay residual after routing. The path delay value after placement is added to the predicted value of the path delay residual after routing to finally obtain the predicted value of the path delay after routing. The process involves constructing a heterogeneous graph based on the circuit netlist, fusing the heterogeneous graph with the feature vectors corresponding to each unit and interconnect, and then inputting the fused graph into a trained heterogeneous graph neural network to obtain a graph network embedding. The feature matrix of the layout is then input into a trained convolutional neural network to obtain a convolutional network embedding. Finally, the graph network embedding and the convolutional network embedding are concatenated to obtain a multimodal local embedding, specifically including: Based on the connection relationship of the circuit netlist, a heterogeneous graph is constructed using cell nodes, pin nodes, and interconnects. Among them, cell timing arcs, interconnect timing arcs, and edges connecting cell nodes and pin nodes are three different adjacency relationships. After fusing the heterogeneous graph with the feature vectors corresponding to each unit and interconnection, the graph is input into the trained heterogeneous graph neural network, and the output is the graph network embedding, which includes: graph network local node embedding and graph network local edge embedding. The feature matrix of the layout is input into the trained convolutional neural network to obtain the convolutional network embedding, which includes: unit convolutional network embedding, pin convolutional network embedding, unit temporal arc convolutional network embedding and interconnection temporal arc convolutional network embedding. In the local edge embedding of graph networks, the unit temporal arc graph network embedding, the interconnection temporal arc graph network embedding, and the local embedding of convolutional networks, the unit temporal arc convolutional network embedding and the interconnection temporal arc convolutional network embedding are all performed. According to the positional relationship of the temporal arcs in the layout, the unit temporal arcs and interconnection temporal arcs in the corresponding networks are concatenated to obtain multimodal local embedding. The multimodal local embedding includes: multimodal local embedding of unit temporal arcs and multimodal local embedding of interconnection temporal arcs. The step of concatenating multimodal local embeddings based on the connection relationships between logical units and interconnects in the path to obtain the temporal stage embeddings of the path, and constructing the feature sequence of the path from the temporal stage embeddings, specifically includes: Each unit timing arc and subsequent interconnect timing arcs are treated as a timing stage, and each timing path consists of a sequence of multiple timing stages; The multimodal local embedding of the cell timing arc and the multimodal local embedding of the interconnect timing arc are spliced ​​together according to the connection relationship between the cell timing arc and the interconnect timing arc in the timing stage to obtain the timing stage embedding of the path. The embedding of the temporal stages of the path is used to construct the feature sequence of the path.

2. The method for pre-routing timing prediction of digital integrated circuits with perceptible optimization according to claim 1, characterized in that: The feature vectors corresponding to each cell and interconnect include, but are not limited to: the timing of each cell, the physical information of each cell and the physical information of the interconnect; the feature matrix of the layout includes: cell density, pin density, rectangular uniform line density and pin rectangular uniform line density.

3. The method for pre-routing timing prediction of digital integrated circuits with perceptible optimization according to claim 1, characterized in that: The method for obtaining the trained heterogeneous graph neural network and convolutional neural network specifically includes: Obtain the feature matrix of the layout of the circuit after layout, and the feature vectors corresponding to each cell and interconnect; Obtain the unit and interconnect delay values ​​of the circuit after layout and routing; The feature matrix of the layout of the circuit after layout, the feature vectors corresponding to each unit and interconnect, and the delay values ​​of the units and interconnects of the circuit after routing are used as training samples. The training samples are used to train the local prediction model composed of the convolutional neural network, the heterogeneous graph neural network, and the first multilayer sensing mechanism to obtain the trained convolutional neural network and the heterogeneous graph neural network.

4. The method for pre-routing timing prediction of digital integrated circuits with perceptible optimization according to claim 1, characterized in that: The method for obtaining the trained Transformer network specifically includes: Obtain the circuit layout corresponding to the laid-out circuit and the feature vectors corresponding to each unit and interconnection. Construct the feature matrix of the layout based on the physical information of the circuit layout. A heterogeneous graph is constructed based on the circuit netlist. The heterogeneous graph is then fused with the feature vectors corresponding to each unit and interconnect and input into a trained heterogeneous graph neural network to obtain the graph network embedding. The feature matrix of the layout is input into a trained convolutional neural network to obtain the convolutional network embedding. The graph network embedding and the convolutional network embedding are concatenated to obtain the multimodal local embedding. The multimodal local embedding is spliced ​​together according to the connection relationship between the logical units and interconnects in the path to obtain the embedding of the temporal stage of the path, and the feature sequence of the path is constructed from the embedding of the temporal stage of the path. Obtain the path delay value of the circuit after layout and routing; The feature sequence of the path and the path delay value of the circuit after wiring are used as training samples. The training samples are used to train the entire prediction model consisting of the Transformer network, the pooling layer, and the second multilayer sensing mechanism to obtain the trained Transformer network.

5. A computer-readable storage medium, characterized in that: It stores a computer program that, when executed by a processor, implements a pre-wiring timing prediction method for digital integrated circuits that is aware of optimization, as described in any one of claims 1 to 4.

6. A computer device, characterized in that: include: Memory, used to store instructions; A processor for executing the instructions, causing the computer device to perform the operation of a digital integrated circuit-aware optimized pre-routing timing prediction method as described in any one of claims 1 to 4.

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