Pixel circuit sharing storage capacitor and writing method

Abstract

This invention discloses a pixel circuit and writing method sharing a storage capacitor, including a first sub-pixel circuit and a second sub-pixel circuit. The first and second sub-pixel circuits have identical circuit structures. Both the first and second sub-pixel circuits include a storage capacitor. One end of the storage capacitor is coupled to the second source-drain terminal of the second transistor of the first sub-pixel circuit. The other end of the storage capacitor is coupled to the second sub-pixel circuit. The first and second sub-pixel circuits share the storage capacitor. The beneficial effect achieved by this invention is that by coupling both ends of a storage capacitor to two adjacent sub-pixel circuits, normal writing and display of multiple sub-pixel circuits can be completed, thereby reducing the number of storage capacitors used and thus improving the aperture ratio.

Description

Technical Field

[0001] This invention relates to the field of pixel display technology, and in particular to a pixel circuit with a shared storage capacitor and a writing method thereon. Background Technology

[0002] Field sequential or color sequential display driving technology leverages the persistence of vision to directly mix RGB three-color light sources, achieving full-color display effects. It eliminates the need for color filters, improving light source utilization and reducing power consumption. The backlight can only be turned on after all image data has been written and the liquid crystal has reached a stable state; otherwise, image distortion will occur. Therefore, a significant time must be allowed for the liquid crystal to deflect before the backlight is activated. This makes it difficult to achieve high brightness and high frequency display over an average time, while also increasing the requirements for backlight brightness specifications and lifespan, thus raising costs.

[0003] While achieving high refresh rate and high brightness, it is also necessary to ensure the aperture ratio of the pixel circuit. Therefore, this invention proposes a pixel circuit with a shared storage capacitor and a writing method to improve the aperture ratio of the pixel circuit. Summary of the Invention

[0004] The purpose of this invention is to propose a pixel circuit and writing method with a shared storage capacitor, thereby improving the aperture ratio of the pixel circuit.

[0005] The present invention aims to achieve a pixel circuit with a shared storage capacitor through the following technical solution, including a first sub-pixel circuit and a second sub-pixel circuit, wherein the first sub-pixel circuit and the second sub-pixel circuit have the same circuit structure; the first sub-pixel circuit and the second sub-pixel circuit share a storage capacitor.

[0006] Furthermore, the first sub-pixel circuit includes a first transistor, a pre-storage capacitor, a second transistor, a storage capacitor, and a pixel electrode; the first source and drain of the first transistor of the first sub-pixel circuit are coupled to a data signal line, the gate of the first transistor of the first sub-pixel circuit is coupled to a first row gate signal line, and the second source and drain of the first transistor of the first sub-pixel circuit are coupled to one end of the pre-storage capacitor; the other end of the pre-storage capacitor is coupled to a first common signal line.

[0007] The first source and drain of the second transistor in the first sub-pixel circuit are coupled to the second source and drain of the first transistor in the first sub-pixel circuit. The gate of the second transistor in the first sub-pixel circuit is coupled to the first transfer signal line. The second source and drain of the second transistor in the first sub-pixel circuit are coupled to one end of the pixel electrode. The other end of the pixel electrode is coupled to the first common signal line. One end of the storage capacitor is coupled to the second source and drain of the second transistor in the first sub-pixel circuit. The other end of the storage capacitor is coupled to the second sub-pixel circuit.

[0008] Furthermore, the second sub-pixel circuit includes a first transistor, a second pre-storage capacitor, a second transistor, a storage capacitor, and a second pixel electrode; the first source and drain of the first transistor of the second sub-pixel circuit are coupled to a data signal line, the gate of the first transistor of the second sub-pixel circuit is coupled to a second row gate signal line, the second source and drain of the first transistor of the second sub-pixel circuit are coupled to one end of the second pre-storage capacitor, and the other end of the second pre-storage capacitor is coupled to a second common signal line;

[0009] The first source and drain of the second transistor of the second sub-pixel circuit are coupled to the second source and drain of the second transistor of the second sub-pixel circuit. The gate of the second transistor of the second sub-pixel circuit is coupled to the second transfer signal line. The second source and drain of the second transistor of the second sub-pixel circuit are coupled to one end of the second pixel electrode. The other end of the second pixel electrode is coupled to the first common signal line. One end of the storage capacitor is coupled to the second source and drain of the second transistor of the second sub-pixel circuit. The other end of the storage capacitor is coupled to the first sub-pixel circuit.

[0010] Furthermore, the pixel circuit also includes a third sub-pixel circuit, which includes a third transistor and a third pixel electrode;

[0011] The gate of the third transistor is coupled to the placement signal line; the first source and drain of the third transistor are coupled to the third common signal line; the second source and drain of the third transistor are coupled to one end of the storage capacitor, and the second source and drain of the third transistor are also coupled to one end of the third pixel electrode; the other end of the third pixel electrode is coupled to the third common signal line.

[0012] Furthermore, the first common signal line and the second common signal line are the same common signal line; the first transfer signal line and the second transfer signal line are the same signal line.

[0013] Furthermore, the first sub-pixel circuit also includes a fourth transistor, the first source and drain of the fourth transistor being coupled to the second source and drain of the second transistor, the second source and drain of the fourth transistor being coupled to the first common signal line, and the gate of the fourth transistor being coupled to the reset signal line.

[0014] The second sub-pixel circuit further includes a fourth transistor of the second sub-pixel circuit. The first source-drain of the fourth transistor of the second sub-pixel circuit is coupled to the second source-drain of the second transistor of the second sub-pixel circuit. The second source-drain of the fourth transistor of the second sub-pixel circuit is coupled to the second common signal line. The gate of the fourth transistor of the second sub-pixel circuit is coupled to the second reset signal line.

[0015] Furthermore, the reset signal line and the second reset signal line are the same signal line.

[0016] The present invention also provides a pixel circuit writing method with a shared storage capacitor, comprising:

[0017] Obtain the pixel voltage of the target pixel circuit at frame n;

[0018] Based on pixel voltage, the data signal voltage required for the pixel electrode potential to change to pixel voltage during charge transfer is calculated according to the principle of charge conservation.

[0019] The calculated data signal voltage is written into the pre-storage capacitor.

[0020] Furthermore, when the pixel circuit includes a first sub-pixel circuit and a second sub-pixel circuit, the writing method includes:

[0021] Obtain the first pixel voltage of the first sub-pixel circuit and the second pixel voltage of the second sub-pixel circuit at frame n;

[0022] Based on the first pixel voltage and the second pixel voltage, the first data signal voltage required for the pixel electrode potential to change to the pixel voltage during the charge transfer process is calculated according to the principle of charge conservation.

[0023] Based on the first pixel voltage and the second pixel voltage, the second data signal voltage required when the potential of the second pixel electrode changes to the pixel voltage during the charge transfer process is calculated according to the principle of charge conservation.

[0024] The calculated first data signal voltage is written into the pre-storage capacitor, and the second data signal voltage is written into the second pre-storage capacitor.

[0025] Further, the method for calculating the voltage of the first data signal includes:

[0026] A first transferred charge is generated based on the first pixel voltage, the second pixel voltage, the pixel electrode, and the storage capacitor;

[0027] Based on the first transferred charge amount, the first pixel voltage, and the pre-storage capacitor, the potential of the pre-storage electrode required before the charge transfer stage is calculated, and this potential is the first data signal voltage.

[0028] Further, the method for calculating the voltage of the second data signal includes:

[0029] A second transferred charge is generated based on the first pixel voltage, the second pixel voltage, the second pixel electrode, and the storage capacitor;

[0030] Based on the second transferred charge amount, the second pixel voltage, and the second pre-storage capacitor, the potential of the second pre-storage electrode required before the charge transfer stage is calculated, and this potential is the second data signal voltage.

[0031] Furthermore, when the storage capacitor contains the pixel voltage of the (n-1)th frame, the method for calculating the data signal voltage includes:

[0032] Obtain the pixel voltage of the target pixel circuit at frame n;

[0033] The amount of transferred charge is generated based on the pixel voltage of the nth frame, the pixel voltage of the (n-1)th frame, the pixel electrode, and the storage capacitor.

[0034] Based on the amount of transferred charge, the pixel voltage of the nth frame, the pixel voltage of the (n-1)th frame, and the pre-storage capacitance, the potential of the pre-storage electrode required before charge transfer is calculated, and this potential is the data signal voltage.

[0035] Furthermore, the writing method also includes:

[0036] Obtain the voltage of the third pixel in the third sub-pixel circuit;

[0037] Based on the first pixel voltage and the third pixel voltage, the first transferred charge amount during the charge transfer process is calculated according to the principle of charge conservation;

[0038] Based on the second pixel voltage and the third pixel voltage, the second transferred charge amount during the charge transfer process is calculated according to the principle of charge conservation.

[0039] Based on the first pixel voltage, the second pixel voltage, the third pixel voltage, the first transferred charge, the second transferred charge, the pre-storage capacitor, and the second pre-storage capacitor, the first data signal voltage and the second data signal voltage are calculated according to the principle of charge conservation.

[0040] The present invention has the following advantages:

[0041] This invention couples the two ends of a storage capacitor to multiple sub-pixel circuits. In the nth frame, the data signal line inputs different data signal voltages to the first and second sub-pixel circuits according to the calculation results. By inputting different data signal voltages, the normal writing and display of multiple pixel circuits are completed. This reduces the number of storage capacitors used and thus increases the aperture ratio.

[0042] The invention also includes a third sub-pixel circuit, which shares a storage capacitor with the first sub-pixel circuit and a second storage capacitor with the second sub-pixel circuit. First, the pixel voltage required by each sub-pixel circuit is obtained. Based on the first pixel voltage, the second pixel voltage, and the third voltage, the potentials of the pixel electrode, the second pixel electrode, and the third pixel electrode are calculated to reach the first and second transfer charge amounts, respectively. Based on the principle of charge conservation, an equation for the charge conservation of the third pixel point is obtained, thereby calculating the first data signal voltage input to the pre-storage capacitor and the second data signal voltage input to the second pre-storage capacitor. The input first and second data signal voltages satisfy the condition that, during the reset phase, when the third transistor is turned off, the charge transferred from the storage capacitor, the second storage capacitor, the pixel electrode, the second pixel electrode, and the third pixel electrode to the third pixel electrode due to the principle of charge conservation can reach the third pixel voltage, thus completing the writing of the third pixel voltage.

[0043] In simple terms, writing three pixel voltages can be achieved through two sub-pixel circuits. This can be understood as reducing the need for three complete sub-pixel circuits to write three pixel voltages, which can now be accomplished with just two complete sub-pixel circuits, plus one transistor and one capacitor. This reduces the use of multiple transistors and capacitors, lowers costs, and increases the aperture ratio of the pixel circuit. Attached Figure Description

[0044] Figure 1 This is a circuit diagram of Embodiment 1 of the present invention;

[0045] Figure 2 This is a timing diagram of Embodiment 1 of the present invention;

[0046] Figure 3 This is a circuit diagram of Embodiment 2 of the present invention;

[0047] Figure 4 This is a timing diagram of Embodiment 2 of the present invention;

[0048] Figure 5 This is a circuit diagram of Embodiment 3 of the present invention;

[0049] Figure 6 This is a timing diagram of Embodiment 3 of the present invention. Detailed Implementation

[0050] The present invention will be further described below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description.

[0051] It should be noted that the orientation or positional relationship indicated by terms such as "left" and "right" is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, or the orientation or positional relationship in which those skilled in the art would conventionally understand it. Such terms are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0052] It should be noted that, unless otherwise specified, the embodiments and features and technical solutions in the present invention can be combined with each other. Example

[0053] See Figure 1 This embodiment provides a pixel circuit with a shared storage capacitor, including a first sub-pixel circuit and a second sub-pixel circuit. The first sub-pixel circuit and the second sub-pixel circuit have the same circuit structure; the first sub-pixel circuit and the second sub-pixel circuit share a storage capacitor Cs2.

[0054] In this first embodiment, the first sub-pixel circuit includes a first transistor T1, a pre-storage capacitor Cs1, a second transistor T2, a storage capacitor Cs2, and a pixel electrode Clc; the first source and drain of the first transistor T1 of the first sub-pixel circuit are coupled to the data signal line Data, the gate of the first transistor T1 of the first sub-pixel circuit is coupled to the first row gate signal line Scan1, and the second source and drain of the first transistor T1 of the first sub-pixel circuit are coupled to one end of the pre-storage capacitor Cs1; the other end of the first pre-storage capacitor Cs1-1 is coupled to the first common signal line Com1;

[0055] The first source and drain of the second transistor T2 in the first sub-pixel circuit are coupled to the second source and drain of the first transistor T1 in the first sub-pixel circuit. The gate of the second transistor T2 in the first sub-pixel circuit is coupled to the first transfer signal line Tran1. The second source and drain of the second transistor T2 are coupled to one end of the pixel electrode Clc. The other end of the pixel electrode Clc is coupled to the common signal line Com. One end of the storage capacitor Cs2 is coupled to the second source and drain of the second transistor T2. The other end of the storage capacitor Cs2 is coupled to the second sub-pixel circuit. The first sub-pixel circuit and the second sub-pixel circuit share the same storage capacitor Cs2.

[0056] In this embodiment, the second sub-pixel circuit includes a first transistor T1', a second pre-storage capacitor Cs1', a second transistor T2', a storage capacitor Cs2, and a second pixel electrode Clc'. The first source and drain of the first transistor T1' are coupled to the data signal line Data, the gate of the first transistor T1' is coupled to the second row gate signal line Scan2, and the second source and drain of the first transistor T1' are coupled to one end of the second pre-storage capacitor Cs1'. The other end of the second pre-storage capacitor Cs1' is coupled to the second common signal line Com2.

[0057] The first source and drain of the second transistor T2' of the second sub-pixel circuit are coupled to the second source and drain of the first transistor T1' of the second sub-pixel circuit. The gate of the second transistor T2' of the second sub-pixel circuit is coupled to the second transfer signal line Tran2. The second source and drain of the second transistor T2' of the second sub-pixel circuit are coupled to one end of the second pixel electrode Clc'. The other end of the second pixel electrode Clc' is coupled to the first common signal line Com2. One end of the storage capacitor Cs2 is coupled to the second source and drain of the second transistor T2' of the second sub-pixel circuit. The other end of the storage capacitor Cs2 is coupled to the first sub-pixel circuit.

[0058] At work, such as Figure 2 As shown, the timing diagram of the pixel circuit is configured as follows:

[0059] Backlight on stage:

[0060] When the first row gate signal line Scan1 jumps to a high level, the first transistor T1 is turned on, so that the data signal line Data writes the first data signal voltage of the first sub-pixel circuit of the nth frame into the pre-storage capacitor Cs1.

[0061] After the write operation is complete, the row gate signal line Scan1 switches to the normal level; the normal level is the common signal level Vcom, which will not cause the transistor to turn on or off.

[0062] When the second row gate signal line Scan2 jumps to a high level, the data signal line Data writes the second data signal voltage of the second sub-pixel circuit into the second pre-storage capacitor Cs1'.

[0063] After the write operation is completed, both the second row gate signal line Scan2 and the data signal line Data switch to normal levels.

[0064] Backlight off phase:

[0065] When the first transfer signal line Tran1 jumps to a high level, the second transistor T2 is turned on, and the first data signal voltage Vd1n in the pre-storage capacitor Cs1 is transferred to the storage capacitor Cs2 and the pixel electrode Clc through the second transistor T2.

[0066] When the second transfer signal line Tran2 jumps to a high level, the second transistor T2' turns on, and the second data signal voltage in the second pre-storage capacitor Cs1' is transferred to the second storage capacitor Cs2' and the pixel electrode Clc' through the second transistor T2'.

[0067] The first data voltage and the second data voltage transfer charge to the storage capacitor Cs2, the pixel electrode Clc, and the second pixel electrode. According to the principle of charge conservation, the potential of the pixel electrode Clc reaches the first pixel voltage, and the potential of the second pixel electrode Clc' reaches the second pixel voltage.

[0068] After the transfer is completed, the first transfer signal line Tran1 and the second transfer signal line Tran2 switch to normal level.

[0069] In this embodiment, the first common signal line Com1 and the second common signal line Com2 can be the same signal line or they can be prepared as two separate signal lines; the first transfer signal line Tran1 and the second transfer signal line Tran2 can be the same signal line or they can be prepared as two separate signal lines.

[0070] In this embodiment, the first sub-pixel circuit and the second sub-pixel circuit share the storage capacitor Cs2. Based on the principle of charge conservation, the correct writing of the two pixel voltages is achieved according to the input of different data signal voltages under different pixel voltage requirements.

[0071] This embodiment employs a pixel circuit writing method with a shared storage capacitor when the pixel voltage of the (n-1)th frame exists in the storage capacitor Cs2. In this embodiment, the capacitance values ​​of the pre-storage capacitor Cs1 and the second pre-storage capacitor Cs1' are equal, and the capacitance values ​​of the pixel electrode Clc and the second pixel electrode Clc' are equal.

[0072] Based on charge sharing, the equations at the first pixel electrode and the second pixel electrode are obtained respectively, and the equations are as follows:

[0073] (V1dn-V1n)*C1=(V1n-V2n-V1n-1+V2n-1)*C2+(V1n-V1n-1)*C;

[0074] (V2dn-V2n)*C1=(V2n-V1n-V2n-1+V1n-1)*C2+(V2n-V2n-1)*C;

[0075] In the formula:

[0076] V1n: Voltage of the first pixel in the nth frame;

[0077] V2n: The voltage of the second pixel in the nth frame;

[0078] V1n-1: The voltage of the first pixel in the (n-1)th frame;

[0079] V2n-1: The voltage of the second pixel in the (n-1)th frame;

[0080] Vd1n: The voltage of the first pixel in the nth frame corresponds to the voltage of the first data signal;

[0081] Vd2n: The voltage of the second pixel in the nth frame corresponds to the voltage of the second data signal;

[0082] C1: The capacitance value of the pre-stored capacitor Cs1 / the second pre-stored capacitor Cs1';

[0083] C2: The capacitance value of the storage capacitor Cs2;

[0084] C: Capacitance value of pixel electrode Clc / second pixel electrode Clc';

[0085] Referring to the right side of the first equation above, based on the first pixel voltage, the second pixel voltage, the storage capacitor Cs2, and the pixel electrode Clc, we obtain the first amount of transferred charge required when the potential of the pixel electrode Clc changes to the first pixel voltage during the charge transfer process.

[0086] Combining the left side of the first equation, based on the first transferred charge, the first pixel voltage, and the pre-storage capacitor Cs1, the first data signal voltage can be calculated. The expression for the first data signal voltage corresponding to the first pixel of the nth frame is as follows:

[0087] Vd1n=V1n*(C+ C1+ C2) / C1-C2*V2n / C1-V1n-1*(C+C2) / C1+C2*V2n-1 / C1.

[0088] Referring to the right side of the second equation above, based on the first pixel voltage, the second pixel voltage, the storage capacitor Cs2, and the second pixel electrode Clc', the second amount of transferred charge required for the potential of the second pixel electrode Clc' to change to the second pixel voltage during the charge transfer process is obtained;

[0089] Based on the left side of the second equation, and using the second transferred charge, the first pixel voltage, the second pixel voltage, and the second pre-storage capacitor Cs1', the expression for the data signal voltage corresponding to the second pixel in the nth frame can be calculated:

[0090] Vd2n=V2n*(C+ C1+ C2) / C1-C2*V1n / C1-V2n-1*(C+C2) / C1+C2*V2n-1 / C1.

[0091] Therefore, this invention couples the two ends of a storage capacitor Cs2 to two adjacent sub-pixel circuits respectively. At the same time, the data signal line Data inputs different data signal voltages to the two sub-pixel circuits according to the calculation results in the nth frame, thereby completing the normal writing and display of the two sub-pixel circuits. This allows the two sub-pixel circuits to share a single storage capacitor, reducing the number of storage capacitors used and thus increasing the aperture ratio. Example

[0092] like Figure 3 As shown, in this second embodiment, the first sub-pixel circuit further includes a fourth transistor T4. The gate of the fourth transistor T4 is coupled to the reset signal line Reset1, the first source and drain of the fourth transistor T4 are coupled to the first common signal line Com1, and the first source and drain of the fourth transistor T4 are coupled to the second source and drain of the fourth transistor T4.

[0093] The second sub-pixel circuit also includes a fourth transistor T4' of the second sub-pixel circuit. The first source and drain of the fourth transistor T4' of the second sub-pixel circuit are coupled to the second source and drain of the second transistor T2' of the second sub-pixel circuit. The second source and drain of the fourth transistor T4' of the second sub-pixel circuit are coupled to the second common signal line Com2. The gate of the fourth transistor T4' of the second sub-pixel circuit is coupled to the second reset signal line Reset2.

[0094] Furthermore, in some specific embodiments, the reset signal line Reset1 and the second reset signal line Reset2 are the same signal line; the first common signal line Com1, the second common signal line Com2 and the third common signal line Com3 are the same common signal line.

[0095] When working in Example 2, as Figure 4 As shown, the timing diagram of the pixel circuit is configured as follows during the backlight-off phase:

[0096] Backlight off phase:

[0097] When the reset signal line Reset1 of the first sub-pixel circuit goes high, the fourth transistor T4 of the first sub-pixel circuit is turned on; the reset signal line Reset1 completes the reset of the storage capacitor Cs2 and the pixel electrode Clc through the fourth transistor T4.

[0098] After the reset is completed, the reset signal line Reset1 jumps to the normal level, and at the same time, the level of the first transfer signal line Tran1 jumps to the high level;

[0099] That is, the fourth transistor T4 is turned off, the second transistor T2 is turned on, and the first data signal voltage of the pre-storage capacitor Cs1 is transferred to the pixel electrode Clc and the storage capacitor Cs2 through the second transistor T2, so that the potential of the pixel electrode Clc is the first pixel voltage.

[0100] Meanwhile, the process of the second sub-pixel circuit during the backlight-off phase is the same as that of the first sub-pixel circuit, completing the reset of the second pixel electrode Clc'. After the reset is completed, the voltage of the second pixel electrode Clc' is made to be the second pixel voltage.

[0101] In this embodiment, because the fourth transistor T4 of the first sub-pixel circuit can reset the storage capacitor Cs2 and the pixel electrode Clc; similarly, the fourth transistor T4' of the second sub-pixel circuit can reset the storage capacitor Cs2 and the second pixel electrode Clc'. Therefore, neither the first nor the second sub-pixel circuit is affected by the signal voltage of the previous frame. Thus, during the backlight-on stage, when writing the data signal voltage, the equations at the first and second pixel electrodes in the nth frame are derived based on the principle of charge sharing conservation. The equations are as follows:

[0102] (V1dn-V1n)*C1=(V1n-V2n)*C2+V1n*C;

[0103] (V2dn-V2n)*C1=(V2n-V1n)*C2+V2n*C;

[0104] Referring to the derivation process of Embodiment 1 and the above equation, the expression for the voltage of the first data signal in the nth frame is:

[0105] Vd1n=(C*V1n + C1*V1n + C2*V1n - C2*V2n - C*Vc) / C1;

[0106] Referring to the second equation above, the voltage of the second data signal can be calculated, as shown in the following expression:

[0107] Vd2n=(C*V2n - C2*V1n + C1*V2n + C2*V2n - C*Vc) / C1;

[0108] In this embodiment, although a fourth transistor T4 is added to the first sub-pixel circuit or a fourth transistor T4' is added to the second sub-pixel circuit, the calculation of the data signal voltage corresponding to the first pixel voltage and the second data signal voltage corresponding to the second pixel voltage is simplified.

[0109] Example

[0110] See Figure 5In embodiment three, the pixel circuit further includes a third sub-pixel circuit, which includes a third transistor T3 and a third pixel electrode Clc”; the capacitance value of the third pixel electrode Clc” is the same as the capacitance value of the pixel electrode Clc or the second pixel electrode Clc’.

[0111] The gate of the third transistor T3 is coupled to the placement signal line Set; the first source and drain of the third transistor T3 are coupled to the third common signal line Com3; the second source and drain of the third transistor T3 are coupled to one end of the storage capacitor Cs2, and the second source and drain of the third transistor T3 are also coupled to one end of the third pixel electrode Clc”; the other end of the third pixel electrode Clc” is coupled to the third common signal line Com3.

[0112] In this embodiment, the first pixel voltage and the second pixel voltage are both driven by their respective complete sub-pixel circuits, and the third pixel voltage is obtained by the mutual coupling of the first pixel voltage and the second pixel voltage through the storage capacitor Cs2 and the second storage capacitor Cs2'.

[0113] During the backlight-on phase, the first data signal voltage and the second data signal voltage are written to the pre-storage capacitor Cs1 of the first sub-pixel circuit and the second pre-storage capacitor Cs1' of the second sub-pixel circuit respectively through the data signal line Data.

[0114] During the transition in the backlight off phase, the placement signal line Set jumps to a high level, the third transistor T3 is turned on, and the third pixel point at the third pixel electrode Clc” is reset;

[0115] After the reset is complete, the placement signal line Set jumps to the normal level, and at the same time, the first transfer signal line Tran1 jumps to the high level. At this time, the third transistor T3 is turned off, and the second transistor T2 is turned on. The charge in the pre-storage capacitor Cs1 in the first sub-pixel circuit is transferred to the pixel electrode Clc and the storage capacitor Cs2. The equation for charge transfer is as follows:

[0116] (V1dn-V1n)*C1=(V1n-V3n-V1n-1+Vc)*C2+(V1n-V1dn)*C;

[0117] Simultaneously, the second transfer signal line Tran2 jumps to a high level, and the second pre-storage capacitor Cs1' in the second sub-pixel circuit of the second transistor T2' also begins to transfer charge to the second pixel electrode Clc' and the second storage capacitor Cs2'. The charge transfer equation is as follows:

[0118] (V2dn-V2n)*C1=(V2n-V3n-V2n-1+Vc)*C3+(V2n-V2n-1)*C;

[0119] After the transfer is complete, both the first transfer signal line Tran1 and the second transfer signal line Tran2 switch back to normal levels. According to the principle of charge conservation, the equation for the third pixel can be obtained as follows:

[0120] (Vm-V1n-1)*C2+(Vc-V2n-1)*C2=(V3n-V1n)*C2+(V3n-V2n)*C2+(V3n-Vc)*C;

[0121] In the formula:

[0122] V3n: The voltage of the third pixel in the nth frame;

[0123] V3n-1: The voltage of the third pixel in the (n-1)th frame.

[0124] Based on the three equations above, the first data signal voltage corresponding to the first sub-pixel circuit of the nth frame can be obtained:

[0125] V1dn=(C*V1n + C1*V1n + C2*V1n - C2*V3n + C2*Vc - C*V1n-1 - C2*V1n-1) / C1;

[0126] The second data signal voltage corresponds to the second sub-pixel circuit in the nth frame:

[0127] V2dn=(C*V2n - C2*V3n + C1*V2n + C2*V2n + C2*Vc - C*V2n-1 - C2*V2n-1) / C1;

[0128] In this embodiment, it is equivalent to driving three pixel electrodes through two pixel circuits, and the third sub-pixel circuit is formed by the third transistor T3 and the third pixel capacitor Clc". At this time, the first sub-pixel circuit and the third sub-pixel circuit share the storage capacitor Cs2, and the second sub-pixel circuit and the third sub-pixel circuit share the second storage capacitor Cs2'. The first sub-pixel circuit and the second sub-pixel circuit realize the writing of the three pixel voltages. It can be understood that the three pixel voltages that originally required three pixel circuits can now be completed through only two pixel circuits.

[0129] This embodiment first obtains the pixel voltage required for each sub-pixel circuit. Based on the first pixel voltage, second pixel voltage, and third voltage, it calculates the potentials of pixel electrode Clc, second pixel electrode Clc', and third pixel electrode Clc” to reach the first and second transfer charge amounts, respectively. Based on the principle of charge conservation, it derives the equation for charge conservation at the third pixel point, thereby calculating the first data signal voltage input to the pre-storage capacitor Cs1 and the second data signal voltage input to the second pre-storage capacitor Cs1'. The input first and second data signal voltages satisfy the requirement that, during the reset phase, when the third transistor T3 is turned off, the charge transferred from storage capacitor Cs2, second storage charge Cs2', pixel electrode Clc, second pixel electrode Clc', and third pixel electrode Clc” to the third pixel electrode due to the principle of charge conservation reaches the required third pixel voltage, thus achieving the writing of the third pixel voltage. This reduces the use of multiple transistors and capacitors, lowers costs, and increases the aperture ratio of the pixel circuit.

[0130] Meanwhile, in addition to forming the third sub-pixel circuit, the third transistor T3 also works with the switching of the signal line Set to reset the third pixel electrode Clc”.

[0131] Example

[0132] The present invention also provides an embodiment four, which is a pixel circuit writing method with a shared storage capacitor, applied to embodiments one to three, including circuits obtained by modification of embodiments one, two and three;

[0133] S1. Obtain the pixel voltage of the target pixel circuit at frame n;

[0134] Specifically, obtain the first pixel voltage of the first sub-pixel circuit and the second pixel voltage of the second sub-pixel circuit at frame n;

[0135] V1n=(C1^2*Vd1n + C^2*V1n-1 + C*C1*Vd1n + C1*C2*Vd1n + C1*C2*Vd2n + C*C1*V1n-1 + 2*C*C2*V1n-1 + C1*C2*V1n-1 - C1*C2*V2n-1) / ((C + C1)*(C + C1 + 2*C2));

[0136] V2n=(C1^2*Vd2n + C^2*V2n-1 + C*C1*Vd2n + C1*C2*Vd1n + C1*C2*Vd2n -C1*C2*V1n-1 + C*C1*V2n-1 + 2*C*C2*V2n-1 + C1*C2*V2n-1) / ((C + C1)*(C + C1 + 2*C2));

[0137] S2. Based on the pixel voltage, calculate the data signal voltage required for the pixel electrode potential to change to the pixel voltage during charge transfer, according to the principle of charge conservation.

[0138] Specifically, based on the first pixel voltage and the second pixel voltage, the first data signal voltage required for the potential of the pixel electrode Clc to change to the first pixel voltage during the charge transfer process is calculated according to the principle of charge conservation.

[0139] The method for calculating the voltage of the first data signal includes:

[0140] Based on the first pixel voltage, the second pixel voltage, the pixel electrode Clc, and the storage capacitor Cs2, a first transferred charge is generated;

[0141] Based on the first transferred charge amount, the first pixel voltage, and the pre-storage capacitor Cs1, the potential of the pre-storage electrode required before the charge transfer stage is calculated, and this potential is the first data signal voltage.

[0142] Vd1n=V1n*(C+ C1+ C2) / C1-C2*V2n / C1-V1n-1*(C+C2) / C1+C2*V2n-1 / C1;

[0143] Based on the first pixel voltage and the second pixel voltage, the second data signal voltage required for the potential of the second pixel electrode Clc' to change to the pixel voltage during the charge transfer process is calculated according to the principle of charge conservation.

[0144] The method for calculating the voltage of the second data signal includes:

[0145] A second transferred charge is generated based on the first pixel voltage, the second pixel voltage, the second pixel electrode Clc', and the storage capacitor Cs2;

[0146] Based on the second transferred charge amount, the second pixel voltage, and the second pre-storage capacitor Cs1', the potential of the second pre-storage electrode required before the charge transfer stage is calculated, and this potential is the second data signal voltage.

[0147] Vd2n=V2n*(C+ C1+ C2) / C1-C2*V1n / C1-V2n-1*(C+C2) / C1+C2*V2n-1 / C1.

[0148] S3. Write the calculated data signal voltage into the pre-storage capacitor;

[0149] Specifically, the calculated first data signal voltage is written into the pre-storage capacitor Cs1, and the second data signal voltage is written into the second pre-storage capacitor Cs1'.

[0150] Furthermore, the writing method also includes:

[0151] S101, Obtain the voltage of the third pixel in the third sub-pixel circuit;

[0152] V3n=(C^2*Vc + C1*C2*V1n + C1*C2*V3n + C*C1*Vc + 3*C*C2*Vc + 2*C1*C2*Vc - C1*C2*V1n-1 - C1*C2*V2n-1) / (C^2 + C*C1 + 3*C*C2 + 2*C1*C2);

[0153] S102. Based on the first pixel voltage and the third pixel voltage, calculate the potential of pixel electrode Clc and the first transferred charge amount of the third pixel electrode Clc during the charge transfer process according to the principle of charge conservation.

[0154] Based on the second pixel voltage and the third pixel voltage, the second transfer charge amount during the charge transfer process is calculated according to the principle of charge conservation;

[0155] S103. Based on the first pixel voltage, the second pixel voltage, the third pixel voltage, the first transferred charge, the second transferred charge, the pre-storage capacitor Cs1, and the second storage capacitor Cs1', calculate the first data signal voltage and the second data signal voltage according to the principle of charge conservation.

[0156] V1dn=(C*V1n + C1*V1n + C2*V1n - C2*V3n + C2*Vc - C*V1n-1 - C2*V1n-1) / C1;

[0157] V2dn=(C*V2n + C1*V2n + C2*V2n - C2*V3n+ C2*Vc - C*V3n-1 - C2*V3n-1) / C1.

[0158] S104. Write the calculated first data signal voltage into the pre-storage capacitor Cs1, and write the second data signal voltage into the second pre-storage capacitor Cs1'.

[0159] The above embodiments only illustrate preferred implementation methods, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from this invention, and these all fall within the protection scope of this invention.

Claims

1. A pixel circuit with a shared storage capacitor, characterized in that: It includes a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit, with the first and second sub-pixel circuits having the same circuit structure. The third sub-pixel circuit includes a third transistor (T3) and a third pixel electrode (Clc”); The gate of the third transistor (T3) is coupled to the placement signal line (Set); the first source and drain of the third transistor (T3) are coupled to the third common signal line (Com3); the second source and drain of the third transistor (T3) are coupled to one end of the storage capacitor (Cs2) and one end of the second storage capacitor (Cs2'), and the second source and drain of the third transistor (T3) are also coupled to one end of the third pixel electrode (Clc); the other end of the third pixel electrode (Clc) is coupled to the third common signal line (Com3). The first sub-pixel circuit and the third sub-pixel circuit share a storage capacitor (Cs2); the second sub-pixel circuit and the third sub-pixel circuit share a second storage capacitor (Cs2').

2. The pixel circuit with a shared storage capacitor according to claim 1, characterized in that, The first sub-pixel circuit includes a first transistor (T1), a pre-storage capacitor (Cs1), a second transistor (T2), a storage capacitor (Cs2), and a pixel electrode (Clc). The first source and drain of the first transistor (T1) are coupled to a data signal line (Data), the gate of the first transistor (T1) is coupled to a first row gate signal line (Scan1), and the second source and drain of the first transistor (T1) are coupled to one end of the pre-storage capacitor (Cs1). The other end of the pre-storage capacitor (Cs1) is coupled to a first common signal line (Com1). The first source and drain of the second transistor (T2) of the first sub-pixel circuit are coupled to the second source and drain of the first transistor (T1) of the first sub-pixel circuit. The gate of the second transistor (T2) of the first sub-pixel circuit is coupled to the first transfer signal line (Tran1). The second source and drain of the second transistor (T2) of the first sub-pixel circuit are coupled to one end of the pixel electrode (Clc). The other end of the pixel electrode (Clc) is coupled to the first common signal line (Com1). One end of the storage capacitor (Cs2) is coupled to the second source and drain of the second transistor (T2). The other end of the storage capacitor (Cs2) is coupled to the third sub-pixel circuit.

3. A pixel circuit with a shared storage capacitor according to claim 2, characterized in that, The second sub-pixel circuit includes a first transistor (T1'), a second pre-storage capacitor (Cs1'), a second transistor (T2'), a second storage capacitor (Cs2'), and a second pixel electrode (Clc'). The first source and drain of the first transistor (T1') are coupled to a data signal line (Data), the gate of the first transistor (T1') is coupled to a second row gate signal line (Scan2), and the second source and drain of the first transistor (T1') are coupled to one end of the second pre-storage capacitor (Cs1'). The other end of the second pre-storage capacitor (Cs1') is coupled to a second common signal line (Com2). The first source and drain of the second transistor (T2') of the second sub-pixel circuit are coupled to the second source and drain of the first transistor (T1') of the second sub-pixel circuit. The gate of the second transistor (T2') of the second sub-pixel circuit is coupled to the second transfer signal line (Tran2). The second source and drain of the second transistor (T2') of the second sub-pixel circuit are coupled to one end of the second pixel electrode (Clc'). The other end of the second pixel electrode (Clc') is coupled to the second common signal line (Com2). One end of the second storage capacitor (Cs2') is coupled to the second source and drain of the second transistor (T2') of the second sub-pixel circuit. The other end of the second storage capacitor (Cs2') is coupled to the third sub-pixel circuit.

4. A pixel circuit with a shared storage capacitor according to claim 3, characterized in that, The first sub-pixel circuit further includes a fourth transistor (T4), the first source and drain of the fourth transistor (T4) are coupled to the second source and drain of the second transistor (T2), the second source and drain of the fourth transistor (T4) are coupled to the first common signal line (Com1), and the gate of the fourth transistor (T4) is coupled to the reset signal line (Reset1).

5. A pixel circuit writing method with a shared storage capacitor, applied in any of the pixel circuits described in claims 1 to 4, characterized in that, include: Obtain the pixel voltage of the target pixel circuit at frame n; Based on pixel voltage, the data signal voltage required for the pixel electrode potential to change to pixel voltage during charge transfer is calculated according to the principle of charge conservation. The calculated data signal voltage is written into the pre-storage capacitor.

6. The pixel circuit writing method with a shared storage capacitor according to claim 5, characterized in that, When the pixel circuit includes a first sub-pixel circuit and a second sub-pixel circuit, the writing method includes: Obtain the first pixel voltage of the first sub-pixel circuit and the second pixel voltage of the second sub-pixel circuit at frame n; Based on the first pixel voltage and the second pixel voltage, the first data signal voltage required for the potential of the pixel electrode (Clc) to change to the first pixel voltage during the charge transfer process is calculated according to the principle of charge conservation. Based on the first pixel voltage and the second pixel voltage, the second data signal voltage required for the potential of the second pixel electrode (Clc') to change to the pixel voltage during the charge transfer process is calculated according to the principle of charge conservation. The calculated first data signal voltage is written into the pre-storage capacitor (Cs1), and the second data signal voltage is written into the second pre-storage capacitor (Cs1').

7. The pixel circuit writing method with a shared storage capacitor according to claim 6, characterized in that, The method for calculating the voltage of the first data signal includes: A first transferred charge is generated based on the first pixel voltage, the second pixel voltage, the pixel electrode (Clc), and the storage capacitor (Cs2); Based on the first transferred charge amount, the first pixel voltage, and the pre-storage capacitor (Cs1), the potential of the pre-storage electrode required before the charge transfer stage is calculated, and this potential is the first data signal voltage. The method for calculating the voltage of the second data signal includes: A second transferred charge is generated based on the first pixel voltage, the second pixel voltage, the second pixel electrode (Clc'), and the storage capacitor (Cs2); Based on the second transferred charge amount, the second pixel voltage, and the second pre-storage capacitor (Cs1'), the potential of the second pre-storage electrode required before the charge transfer stage is calculated, and this potential is the second data signal voltage.

8. The pixel circuit writing method with a shared storage capacitor according to claim 5, characterized in that, If the storage capacitor (Cs2) contains the pixel voltage of the (n-1)th frame, the method for calculating the data signal voltage includes: Obtain the pixel voltage of the target pixel circuit at frame n; The amount of transferred charge is generated based on the pixel voltage of the nth frame, the pixel voltage of the (n-1)th frame, the pixel electrode (Clc), and the storage capacitor (Cs2). Based on the amount of transferred charge, the pixel voltage of the nth frame, the pixel voltage of the (n-1)th frame, and the pre-storage capacitance (Cs1), the potential of the pre-storage electrode required before charge transfer is calculated, and this potential is the data signal voltage.

9. A pixel circuit writing method with a shared storage capacitor according to claim 5, characterized in that, The writing method further includes: Obtain the voltage of the third pixel in the third sub-pixel circuit; Based on the first pixel voltage and the third pixel voltage, the potential of the pixel electrode (Clc) and the amount of first transferred charge of the third pixel electrode (Clc) during the charge transfer process are calculated according to the principle of charge conservation. Based on the second pixel voltage and the third pixel voltage, the second transfer charge amount of the potential of the second pixel electrode (Clc') and the third pixel electrode (Clc") during the charge transfer process is calculated according to the principle of charge conservation; Based on the first pixel voltage, the second pixel voltage, the third pixel voltage, the first transferred charge, the second transferred charge, the pre-storage capacitor (Cs1), and the second pre-storage capacitor (Cs1'), the first data signal voltage and the second data signal voltage are calculated according to the principle of charge conservation.

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