Semiconductor structure and its formation method

Abstract

This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself. The semiconductor structure includes multiple channel layers, and bit lines and capacitors are electrically connected to the source and drain ends of the channel layers, respectively. The channel layers contain a single-crystal material, which effectively reduces leakage caused by high scattering in polycrystalline channels and ensures the conductivity of the channel layers. Furthermore, the multiple channel layers are stacked in a first direction intersecting the surface of the substrate, which allows for more efficient use of the space above the substrate, thereby achieving stacking of the channel layers in the direction intersecting the substrate surface and significantly increasing the stacking density of the channel layers.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] Traditional Dynamic Random Access Memory (DRAM) typically has a 1T1C structure, meaning each memory cell includes one transistor and one capacitor. To ensure transistor conduction performance, the transistor channels are usually arranged sequentially along the surface of the substrate. This arrangement limits further miniaturization of device size and further increases in transistor density. Therefore, the density of current semiconductor devices still needs to be further improved. Summary of the Invention

[0003] Therefore, it is necessary to provide a semiconductor structure that addresses the problems mentioned in the background art, so as to further improve the density of semiconductor devices while ensuring the conduction performance of transistors.

[0004] According to some embodiments of this disclosure, a method for fabricating a semiconductor structure is provided, comprising:

[0005] A multilayer support layer and a multilayer precursor layer are fabricated on a substrate, wherein the support layer and the precursor layer are alternately stacked along a first direction;

[0006] One side surface of the precursor layer is subjected to amorphization treatment to form an amorphous portion;

[0007] A crystallization-inducing layer in contact with the amorphous portion is prepared and subjected to heat treatment to transform the precursor layer into a single crystal material and form a channel layer having a source end and a drain end.

[0008] A bit line is formed, the bit line extending in a third direction;

[0009] A capacitor is formed, wherein the bit line is electrically connected to the source terminal and the drain terminal of the capacitor, respectively;

[0010] A word line is formed, the word line extending along the first direction, and the word line is used to control the channel layer.

[0011] In some embodiments of this disclosure, the precursor layer comprises silicon, and the crystallization induction layer is made of a silicon-nickel metal compound.

[0012] In some embodiments of this disclosure, the precursor layer is polycrystalline silicon, and the precursor layer further includes a dopant element, wherein the doping concentration of the dopant element in the polycrystalline silicon is 10. 16 cm -3 ~1019 cm -3 .

[0013] In some embodiments of this disclosure, the step of preparing a crystallization-inducing layer in contact with the amorphous portion includes: preparing a nickel metal material layer on the amorphous portion, and reacting the nickel metal material layer with the amorphous portion to form the crystallization-inducing layer.

[0014] In some embodiments of this disclosure, the step of amorphizing one side surface of the precursor layer includes: implanting ions into the surface of the precursor layer by ion implantation.

[0015] In some embodiments of this disclosure, the precursor layer includes a plurality of spacers and a connecting portion connected to one end of the spacers in a second direction. The plurality of spacers are arranged side by side and spaced apart along a third direction, and the first direction, the second direction, and the third direction intersect each other.

[0016] Before performing amorphization treatment on one side surface of the precursor layer, the method further includes the following steps: removing the connection portion to form a bit line accommodating region, removing a portion of the spacer portion away from the connection portion to form a capacitor accommodating region, and preparing a bit line sacrificial layer and a capacitor sacrificial layer in the bit line accommodating region and the capacitor accommodating region, respectively.

[0017] After forming the channel layer, the method further includes the following steps: removing the bit line sacrificial layer and the capacitor sacrificial layer, and fabricating the bit line and the capacitor in the bit line accommodating region and the capacitor accommodating region, respectively.

[0018] Furthermore, this disclosure also provides a semiconductor structure including: a substrate, a channel layer, a bit line, a word line, and a capacitor. Multiple channel layers are stacked along a first direction intersecting the surface of the substrate. Each channel layer comprises a single-crystal material and has a source terminal and a drain terminal. The bit line and the capacitor are electrically connected to the source terminal and the drain terminal, respectively. The word line is used to control the channel layer.

[0019] In some embodiments of this disclosure, the capacitor is elongated and extends along a second direction. The capacitor includes an inner electrode, a dielectric layer, and an outer electrode extending along a third direction. The dielectric layer is disposed between the inner electrode and the outer electrode, surrounds the inner electrode, and surrounds the outer electrode. The inner electrode or the outer electrode is electrically connected to the channel layer.

[0020] In some embodiments of this disclosure, the protective layer is disposed between the bit line and the capacitor, and the protective layer is connected to the channel layer, the bit line and the capacitor.

[0021] In some embodiments of this disclosure, the single-crystal material is single-crystal silicon.

[0022] The semiconductor structure disclosed herein includes multiple channel layers, which can serve as the main functional components of a transistor. Bit lines and capacitors can be electrically connected to the source and drain terminals, respectively, and the bit lines, capacitors, and channel layers can collectively form a memory cell. The channel layers contain a single-crystal material, which effectively reduces leakage problems caused by high scattering in polycrystalline channels, ensuring the conductivity of the channel layers. Furthermore, the multiple channel layers are stacked in a first direction intersecting the surface of the substrate. This allows for more efficient use of the space above the substrate, thereby achieving stacking of the channel layers in the direction intersecting the substrate surface and significantly increasing the stacking density of the channel layers.

[0023] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1A This is a schematic diagram of a semiconductor structure according to the present disclosure. Figure 1B This is a schematic diagram of the cross-sectional structure along AA' in Figure 1. Figure 1C Figure 1 shows a schematic diagram of the cross-sectional structure along BB'.

[0026] Figure 2A This is a schematic diagram of the structure for fabricating multiple support layers and multiple precursor layers on a substrate. Figure 2B for Figure 2A Schematic diagram of the cross-sectional structure along AA'. Figure 2C for Figure 2A Schematic diagram of the cross-sectional structure along the middle edge BB';

[0027] Figure 3A In order to be in Figure 2AThis is a schematic diagram of the structure after the first trench is formed based on the structure shown. Figure 3B for Figure 3A Schematic diagram of the cross-sectional structure along AA'. Figure 3C for Figure 3A Schematic diagram of the cross-sectional structure along the middle edge BB';

[0028] Figure 4A In order to be in Figure 3A A schematic diagram of the structure for fabricating the first isolation filling layer based on the structure shown. Figure 4B for Figure 4A Schematic diagram of the cross-sectional structure along AA'. Figure 4C for Figure 4A Schematic diagram of the cross-sectional structure along the middle edge BB';

[0029] Figure 5A In order to be in Figure 4A This is a schematic diagram showing the structure in which the bit line accommodating region and the capacitor accommodating region are formed based on the structure shown. Figure 5B for Figure 5A Schematic diagram of the cross-sectional structure along AA'. Figure 5C for Figure 5A Schematic diagram of the cross-sectional structure along the middle edge BB';

[0030] Figure 6A In order to be in Figure 5A A schematic diagram showing the fabrication of a bit line sacrificial layer and a capacitor sacrificial layer based on the structure shown. Figure 6B for Figure 6A Schematic diagram of the cross-sectional structure along AA'. Figure 6C for Figure 6A Schematic diagram of the cross-sectional structure along the middle edge BB';

[0031] Figure 7A In order to be in Figure 6A The diagram shows the formation of a second trench and the subsequent ion implantation based on the existing structure. Figure 7B for Figure 7A Schematic diagram of the cross-sectional structure along AA'. Figure 7C for Figure 7A Schematic diagram of the cross-sectional structure along the middle edge BB';

[0032] Figure 8A In order to be in Figure 7A A schematic diagram of a structure in which a layer of nickel metal is deposited on top of the structure shown. Figure 8B for Figure 8A Schematic diagram of the cross-sectional structure along AA'. Figure 8C for Figure 8A Schematic diagram of the cross-sectional structure along the middle edge BB';

[0033] Figure 9A In order to be in Figure 8A This is a schematic diagram of a structure in which a third trench is formed and the precursor layer is etched based on the structure shown. Figure 9B for Figure 9A Schematic diagram of the cross-sectional structure along AA'. Figure 9C for Figure 9A Schematic diagram of the cross-sectional structure along the middle edge BB';

[0034] Figure 10A In order to be in Figure 9A A schematic diagram of the structure for fabricating a protective layer based on the structure shown. Figure 10B for Figure 10A Schematic diagram of the cross-sectional structure along AA'. Figure 10C for Figure 10A Schematic diagram of the cross-sectional structure along the middle edge BB';

[0035] Figure 11A In order to be in Figure 10A A schematic diagram of the structure shown, based on which the bit line sacrificial layer is removed and word line vias are fabricated. Figure 11B for Figure 11A Schematic diagram of the cross-sectional structure along AA'. Figure 11C for Figure 11A Schematic diagram of the cross-sectional structure along the middle edge BB';

[0036] Figure 12A In order to be in Figure 11A A schematic diagram of the structure for fabricating bit lines and word lines based on the structure shown. Figure 12B for Figure 12A Schematic diagram of the cross-sectional structure along AA'. Figure 12C for Figure 12A Schematic diagram of the cross-sectional structure along the middle edge BB';

[0037] Figure 13A In order to be in Figure 12A A schematic diagram of the structure shown, with the capacitor sacrificial layer removed. Figure 13B for Figure 13A Schematic diagram of the cross-sectional structure along AA'. Figure 13C for Figure 13A Schematic diagram of the cross-sectional structure along the middle edge BB';

[0038] The reference numerals and their meanings in the attached figures are as follows:

[0039] 100, Substrate; 110, Channel layer; 120, Bit line; 130, Word line; 140, Capacitor; 141, Inner electrode; 142, Dielectric layer; 143, Outer electrode; 150, Protective layer; 210, Precursor layer; 211, Connector; 212, Spacer; 213, Bit line sacrificial layer; 214, Capacitor sacrificial layer; 215, Nickel metal material layer; 2101, Bit line accommodating region; 2102, Capacitor accommodating region; 220, Support layer; 310, First trench; 311, First isolation fill layer; 320, Second trench; 321, Second isolation fill layer; 330, Third trench; 331, Third isolation fill layer. Detailed Implementation

[0040] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0041] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0042] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0043] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0044] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0045] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0046] Figure 1A This is a schematic diagram of a semiconductor structure according to the present disclosure. Figure 1B This is a schematic diagram of the cross-sectional structure along AA' in Figure 1. Figure 1C This is a schematic diagram of the cross-sectional structure along BB' in Figure 1. (Combined with...) Figures 1A to 1C As shown, the semiconductor structure in this disclosure includes a substrate 100, a channel layer 110, a bit line 120, a word line 130, and a capacitor 140. Multiple channel layers 110 are stacked along a first direction intersecting the substrate 100. Each channel layer 110 comprises a single-crystal material and has a source terminal and a drain terminal. The bit line 120 and the capacitor 140 are electrically connected to the source terminal and the drain terminal, respectively. The word line 130 is used to control the channel layer.

[0047] The semiconductor structure disclosed herein includes multiple channel layers 110, which can serve as the main functional parts of a transistor. Bit lines 120 and capacitors 140 can be electrically connected to the source and drain terminals, respectively. The bit lines 120, capacitors 140, and channel layers 110 can jointly form a memory cell. The channel layers 110 are provided with a single-crystal material, which effectively reduces leakage problems caused by high scattering in polycrystalline channels, ensuring the conductivity of the channel layers 110. Furthermore, the multiple channel layers 110 are stacked in a first direction intersecting the surface of the substrate 100. This allows for more efficient use of the space above the substrate 100, thereby achieving the stacking of the channel layers 110 in the direction intersecting the surface of the substrate 100 and significantly improving the stacking density of the channel layers.

[0048] Reference Figures 1A to 1C As shown, the surface of substrate 100 refers to the side surface on which the channel layers 110 are disposed. The first direction can intersect the surface of substrate 100 obliquely or perpendicularly. In this embodiment, the first direction can intersect the surface of substrate 100 perpendicularly, in which case multiple channel layers 110 can be stacked along a direction perpendicular to the surface of substrate 100. In this embodiment, the first direction can refer to... Figure 1A The z-direction is shown in the figure.

[0049] Reference Figures 1A to 1C As shown, in some examples of this embodiment, the channel layer 110 in the semiconductor structure can be elongated, and the channel layer 110 can extend along a second direction intersecting the first direction. The source and drain ends are located at opposite ends of the channel layer 110 in the second direction, and the bit line 120 and capacitor 140 are respectively disposed on both sides of the channel layer 110 in the second direction. In this embodiment, the second direction can refer to... Figure 1AThe x-direction is shown in the diagram. Furthermore, in some examples of this embodiment, the second direction may be perpendicular to the first direction.

[0050] Reference Figures 1A to 1C As shown, in some examples of this embodiment, the capacitor 140 may also be elongated, and the capacitor 140 may extend along the second direction.

[0051] Reference Figure 1B As shown, in some examples of this embodiment, the capacitor 140 may include an inner electrode 141, a dielectric layer 142, and an outer electrode 143 extending along a second direction. The dielectric layer 142 is disposed between the inner electrode 141 and the outer electrode 143, and the dielectric layer 142 may surround the inner electrode 141, and the outer electrode 143 may surround the dielectric layer 142. The inner electrode 141 or the outer electrode 143 is electrically connected to the channel layer. By providing the inner electrode 141, the dielectric layer 142, and the capacitor 140 extending along the second direction, space in the third direction can be saved, and a relatively large capacitor 140 can be obtained, thereby increasing the capacitance.

[0052] In some examples of this embodiment, the material of the inner electrode 141 may be the same as the material of the outer electrode 143.

[0053] In some examples of this embodiment, the material of the inner electrode 141 may be selected from one or more of titanium and titanium nitride.

[0054] In some examples of this embodiment, the material of the external electrode 143 may be selected from one or more of titanium and titanium nitride.

[0055] In some examples of this embodiment, the material of the dielectric layer 142 may be selected from insulating materials. Further, the material of the dielectric layer 142 may be a high-k dielectric material, wherein the dielectric constant of the high-k dielectric material may be 4 or higher. Further, the material of the dielectric layer 142 may be selected from hafnium dioxide (HfO2).

[0056] Reference Figure 1B As shown, in some examples of this embodiment, the outer electrode 143 in the capacitor 140 can be electrically connected to the channel layer 110, and correspondingly, the inner electrode 141 can be electrically connected to the external circuit.

[0057] Reference Figures 1A to 1C As shown, in some examples of this embodiment, multiple channel layers arranged side-by-side along a first direction form a channel group, and the word line 130 can be used to control the multiple channel layers in the channel group. Furthermore, the word line 130 can extend along the first direction to correspond to the multiple channel layers in the channel group.

[0058] Reference Figures 1A to 1C As shown, in some examples of this embodiment, there can be multiple channel groups, and these multiple channel groups can be arranged side-by-side in a third direction intersecting the first direction. The third direction can refer to the y-direction shown in FIG1. ​​Furthermore, the first direction, the second direction, and the third direction can be perpendicular to each other, and the plane defined by the second direction and the third direction can be parallel to the surface of the substrate 100. It is understood that in the multiple channel groups, there are multiple channel layers 110 arranged side-by-side in the third direction. Bit lines 120 can extend along the third direction, and the bit lines 120 are electrically connected to the multiple channel layers 110 arranged side-by-side in the third direction.

[0059] In some examples of this embodiment, the material of bit line 120 can be a conductive material. Further, the material of bit line 120 can be selected from one or more of titanium and titanium nitride, which have strong adhesion to the channel layer 110, thus improving the stability of the semiconductor structure.

[0060] Reference Figure 1C As shown, in some examples of this embodiment, the semiconductor structure may further include a protective layer 150. The protective layer 150 may be disposed between the bit line 120 and the capacitor 140, and the protective layer 150 connects the channel layer 110, the bit line 120, and the capacitor 140. By providing the protective layer 150, not only can the upper channel layer 110 be better supported, but the bonding strength between the channel layer 110, the bit line 120, and the capacitor 140 can also be further enhanced, ensuring the overall stability of the semiconductor structure.

[0061] Furthermore, in some examples of this embodiment, the protective layer 150 may be disposed on the third-side upward side of the channel layer 110.

[0062] In some examples of this embodiment, the material of the protective layer 150 may be an insulating material. For example, the material of the protective layer 150 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0063] Reference Figures 1A to 1C As shown, in some examples of this embodiment, the channel layer 110 can be disposed between the word line 130 and the guard layer 150. By disposing the channel layer 110 between the word line 130 and the guard layer 150, the position of the channel layer 110 can be further fixed by means of the word line 130 and the guard layer 150, ensuring the structural stability of the semiconductor structure. In this embodiment, the guard layer 150 and the word line 130 can be disposed on both sides of the channel layer 110 in a third direction.

[0064] In some examples of this embodiment, word line 130 may include a gate and a gate dielectric layer disposed between the gate and the channel layer and insulatingly separating the gate and the channel layer.

[0065] In some examples of this embodiment, the material of the gate dielectric layer can be an insulating material, for example, the material of the gate dielectric layer can be selected from silicon oxide.

[0066] In some examples of this embodiment, the gate material can be a conductive material. Furthermore, the gate material can be the same as the bit line 120 material, which allows the gate and bit line 120 to be fabricated in the same fabrication step, simplifying the actual fabrication process.

[0067] Reference Figures 1A to 1C As shown, in some examples of this embodiment, the semiconductor structure may further include a protective layer 150, which may be disposed between two adjacent channel layers 110 in a first direction for insulating the two adjacent channel layers 110 and supporting the upper channel layer 110.

[0068] Furthermore, referring to Figures 1A to 1C As shown, there can be multiple bit lines 120. Corresponding to multiple channel layers 110, multiple bit lines 120 can be stacked sequentially in the first direction. The protective layer 150 can also be disposed between two adjacent bit lines 120 to insulate the two adjacent bit lines 120 and support the bit line 120 located above.

[0069] Furthermore, referring to Figures 1A to 1C As shown, there can be multiple capacitors 140. Corresponding to multiple channel layers 110, multiple capacitors 140 can be stacked sequentially in the first direction. The protective layer 150 can also be disposed between two adjacent capacitors 140 to insulate the two adjacent capacitors 140 and support the capacitor 140 located above.

[0070] Reference Figures 1A to 1C As shown, in some examples of this embodiment, the semiconductor structure may further include an isolation structure, which may be disposed between two adjacent channel groups and used to insulate the adjacent channel groups. Further, there may be an isolation gap between two adjacent channel groups, and the isolation structure may fill the gap to maintain the stability of the semiconductor structure.

[0071] Reference Figures 1A to 1C As shown, in some examples of this embodiment, the isolation structure may be provided with a word line hole extending along a first direction, and the word line 130 may be disposed in the word line hole. In two channel groups adjacent to the isolation structure, the word line hole may be disposed close to one channel group and away from the other channel group to reduce the interference of the word line 130 to the other channel group.

[0072] In some examples of this embodiment, the material of the single-crystal material in the channel layer 110 may be single-crystal silicon.

[0073] In conventional techniques, polycrystalline silicon is typically used as the channel material. However, due to the numerous grain boundaries in polycrystalline silicon, charge carriers are subject to significant scattering, resulting in poor channel mobility and stability, and making it unsuitable for fabricating channels stacked along the height direction. This disclosure uses monocrystalline silicon as the channel layer material, which can significantly reduce charge carrier scattering, thereby improving channel mobility and stability and ensuring the quality of the semiconductor structure.

[0074] This disclosure also provides a method for preparing a semiconductor structure, which includes steps S1 to S5, as detailed below.

[0075] Step S1: A multilayer support layer 220 and a multilayer precursor layer 210 are prepared on the substrate 100, with the support layer 220 and the precursor layer 210 being stacked alternately along a first direction.

[0076] Figure 2A This is a schematic diagram of the structure of a multilayer support layer 220 and a multilayer precursor layer 210 fabricated on a substrate 100. Figure 2B for Figure 2A Schematic diagram of the cross-sectional structure along AA'. Figure 2C for Figure 2A A schematic diagram of the cross-sectional structure along the middle edge BB'. (Refer to...) Figures 2A to 2C As shown, multiple support layers 220 and multiple precursor layers 210 are alternately stacked on the substrate 100.

[0077] In some examples of this embodiment, the material of the substrate 100 may be a semiconductor material. For example, the material of the substrate 100 may include one or more of silicon, germanium, silicon-germanium alloy and gallium nitride.

[0078] The precursor layer 210 can be used as a precursor to a single-crystal material and undergoes subsequent processing to form the single-crystal material. It is understood that the precursor layer 210 may contain elements found in the single-crystal material. In some examples of this embodiment, the precursor layer 210 contains silicon.

[0079] In some examples of this embodiment, the material of the precursor layer 210 may include polycrystalline silicon. Furthermore, the precursor layer 210 may also include dopant elements doped into the polycrystalline silicon. By pre-setting dopant elements in the precursor layer 210, the subsequently formed single-crystal material can also contain dopant elements, which can help regulate the voltage of the channel layer.

[0080] In some examples of this embodiment, the doping concentration in the polysilicon can be 10. -16 cm-3 ~10 -19 cm -3 By setting the doping concentration within this range, it is possible to ensure good quality of the subsequently formed single-crystal material.

[0081] In some examples of this embodiment, the doping element in the precursor layer 210 may be a p-type doping element. Further, the p-type doping element may be selected from one or more of boron, aluminum, and gallium.

[0082] The support layer 220 is used to space adjacent precursor layers 210 and support the precursor layers 210 located above them. In some examples of this embodiment, the material of the support layer 220 may include an insulating material. For example, the material of the support layer 220 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0083] In some examples of this embodiment, the precursor layer 210 can be prepared by chemical vapor deposition.

[0084] In some examples of this embodiment, the support layer 220 can be prepared by chemical vapor deposition.

[0085] In some examples of this embodiment, after preparing the multilayer support layer 220 and the multilayer precursor layer 210, the step of forming the first trench 310 is also included. Figure 3A In order to be in Figure 2A This is a schematic diagram of the structure after the first groove 310 is formed based on the structure shown. Figure 3B for Figure 3A Schematic diagram of the cross-sectional structure along AA'. Figure 3C for Figure 3A A schematic diagram of the cross-sectional structure along the middle edge BB'. (Refer to...) Figures 3A-3C As shown, the first trench 310 can penetrate multiple support layers 220 and multiple precursor layers 210 along the first direction. The first trench 310 can be formed by etching, and the etching method can be dry etching.

[0086] In some examples of this embodiment, the first trench 310 may also extend along a second direction. Furthermore, there may be multiple first trenches 310, which are arranged side by side.

[0087] Referring to FIG3, in some examples of this embodiment, after the first trench 310 is formed, the precursor layer 210 may include a plurality of spacers 212 and a connecting portion 211 connected to one end of the plurality of spacers 212 in a second direction. The connecting portion 211 may extend along a third direction, and the first trench 310 may be located between two adjacent spacers 212. The spacers 212 may be used to prepare the trench layer in subsequent processes.

[0088] In some examples of this embodiment, after forming the first trench 310, a step of filling the first trench 310 with a first insulating filler layer 311 may also be included. Figure 4A In order to be in Figure 3A A schematic diagram of the structure of the first isolation filling layer 311 prepared based on the structure shown. Figure 4B for Figure 4A Schematic diagram of the cross-sectional structure along AA'. Figure 4C for Figure 4A A schematic diagram of the cross-sectional structure along the middle BB'. The first insulating filler layer 311 is used as the channel layer for subsequent fabrication of the insulating spacer.

[0089] Reference Figures 4A to 4C As shown, the first insulating filler layer 311 can fill the first trench 310 and contact the two insulating portions located on both sides. The material of the insulating portions may include an insulating material. Further, the material of the first insulating filler layer 311 may be the same as the material of the support layer 220.

[0090] In some instances of this embodiment, the material of the first isolation filling layer 311 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0091] Step S2: Amorphization treatment is performed on one side surface of the precursor layer 210 to form an amorphous portion.

[0092] In some examples of this embodiment, before amorphizing one side surface of the precursor layer 210, the following step is included: removing the connection portion 211 in the precursor layer 210 to form a bit line accommodating region 2101. Further, in some examples of this embodiment, before amorphizing one side surface of the precursor layer 210, the following step is included: removing a portion of the spacer portion 212 away from the connection portion 211 to form a capacitor accommodating region 2102. Figure 5A In order to be in Figure 4A This is a schematic diagram showing the structure in which the bit line accommodating region 2101 and the capacitor accommodating region 2102 are formed based on the structure shown. Figure 5B for Figure 5A Schematic diagram of the cross-sectional structure along AA'. Figure 5C for Figure 5A A schematic diagram of the cross-sectional structure along the middle edge BB'. (Refer to...) Figures 5A to 5C As shown, bit line accommodating region 2101 and capacitor accommodating region 2102 can be disposed between two adjacent support layers 220. It is understood that there can be a reserved spacer 212 between bit line accommodating region 2101 and capacitor accommodating region 2102. Bit line accommodating region 2101 and capacitor accommodating region 2102 can serve as the fabrication areas for bit line 120 and capacitor 140.

[0093] In the steps of forming the bit line accommodating region 2101 and the capacitor accommodating region 2102, wet etching can be used to remove the connecting portion 211 and part of the spacer portion 212. Furthermore, when removing the connecting portion 211 and part of the spacer portion 212, the etching rate of the etchant on the precursor layer 210 can be controlled to be greater than its etching rate on the support layer 220, so as to minimize damage to the support layer 220. For example, the etching selectivity ratio of the etchant for the precursor layer 210 and the support layer 220 can be controlled to be (10 to 100):1.

[0094] In some examples of this embodiment, before the amorphization process and after the formation of bit line accommodating region 2101 and capacitor accommodating region 2102, the following steps are also included: preparing bit line sacrificial layer 213 in bit line accommodating region 2101 and preparing capacitor sacrificial layer 214 in capacitor accommodating region 2102. Figure 6A In order to be in Figure 5A A schematic diagram of the structure for fabricating bit line sacrificial layer 213 and capacitor sacrificial layer 214 based on the structure shown. Figure 6B for Figure 6A Schematic diagram of the cross-sectional structure along AA'. Figure 6C for Figure 6A A schematic diagram of the cross-sectional structure along the middle edge BB'. (Refer to...) Figures 6A to 6C As shown, the bit line sacrificial layer 213 and the capacitor sacrificial layer 214 can fill the bit line accommodating region 2101 and the capacitor accommodating region 2102. The bit line sacrificial layer 213 and the capacitor sacrificial layer 214 can temporarily fill the vacancies in the bit line accommodating region 2101 and the capacitor accommodating region 2102 and protect the precursor layer 210 located therein.

[0095] In some examples of this embodiment, the bit line sacrificial layer 213 and the capacitor sacrificial layer 214 may be made of the same material.

[0096] In some examples of this embodiment, the materials of the protective fill layer and the capacitor sacrificial layer 214 can be insulating materials. Furthermore, the materials of the protective fill layer and / or the capacitor sacrificial layer 214 can be different from the material of the first insulating fill layer 311, so that they can be etched with different etchants respectively, and the mutual influence between them during the etching process can be reduced.

[0097] In some examples of this embodiment, the materials of the bit line sacrificial layer 213 and the capacitor sacrificial layer 214 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the material of the first isolation filling layer 311 may be silicon oxide, and the material of the protective filling layer may be silicon nitride.

[0098] In some examples of this embodiment, before the step of amorphizing one side surface of the precursor layer 210, the following step may be included: forming a second trench 320 in the first isolation filling layer 311 to expose the precursor layer 210.

[0099] In some examples of this embodiment, the step of amorphizing one side surface of the precursor layer 210 includes: implanting ions into the surface of the precursor layer 210 by means of ion implantation. Figure 7A In order to be in Figure 6A The diagram shows the formation of a second trench 320 based on the structure shown, and the subsequent ion implantation. Figure 7B for Figure 7A Schematic diagram of the cross-sectional structure along AA'. Figure 7C for Figure 7A A schematic diagram of the cross-sectional structure along the middle edge BB'.

[0100] Reference Figures 7A to 7C As shown, the second trench 320 can penetrate the first insulating fill layer 311 along the first direction, and the second trench 320 can be located on the third-direction side of the precursor layer 210, exposing the third-direction side surface of the precursor layer 210. Furthermore, since the side surface of the precursor layer 210 is exposed from the second trench 320, ions can be directly implanted into the surface layer of the precursor layer 210. After ion implantation, the original lattice in the precursor layer 210 is destroyed, thereby forming an amorphous portion.

[0101] In some examples of this embodiment, the injected element may be of the same type as the element in the precursor layer 210. For example, the precursor layer 210 may include silicon, and the injected element may also be silicon.

[0102] Step S3: Prepare a crystallization-inducing layer in contact with the amorphous phase and perform heat treatment so that at least part of the precursor layer 210 is converted into a single crystal material and forms a channel layer.

[0103] In some examples of this embodiment, the precursor layer 210 comprises silicon, and the crystallization inducing layer comprises a nickel-silicon metal compound. Further, the nickel-silicon metal compound may comprise nickel disilicide (NiSi2), which has a lattice mismatch rate of only 0.4% with monocrystalline silicon. Therefore, silicon atoms in amorphous silicon can rearrange themselves on their surface to form monocrystalline silicon. Specifically, the nickel-silicon metal compound can be attached to the surface of the amorphous portion. During heat treatment, the atoms in the amorphous portion first rearrange to form a monocrystalline material. Subsequently, this transformation process proceeds gradually towards the interior of the precursor layer 210 in a direction away from the amorphous inducing layer, causing the atoms located inside to gradually rearrange and form a monocrystalline material as well. Ultimately, this transforms part or all of the precursor layer 210 into a monocrystalline material, forming the desired channel layer.

[0104] In some examples of this embodiment, the step of preparing a crystallization-inducing layer in contact with the amorphous portion includes: preparing a nickel metal material layer 215 on the amorphous portion, and reacting the nickel metal material layer 215 with the amorphous portion to form the crystallization-inducing layer. Figure 8A In order to be in Figure 7A A schematic diagram of a structure in which a nickel metal layer 215 is deposited on the basis of the structure shown. Figure 8B for Figure 8A Schematic diagram of the cross-sectional structure along AA'. Figure 8C for Figure 8A A schematic diagram of the cross-sectional structure along the middle edge BB'. (Refer to...) Figures 8A to 8C As shown, the nickel metal material layer 215 can be filled in the second trench 320. The nickel metal material layer 215 is located on the third-direction side of each precursor layer 210 and is in direct contact with each precursor layer 210.

[0105] In some examples of this embodiment, the nickel metal material layer 215 can be deposited in the second trench 320 by physical vapor deposition or chemical vapor deposition. After depositing the nickel metal material layer 215, the nickel metal material layer 215 and the precursor layer 210 can be heated to cause the nickel metal material layer 215 and the amorphous portion to react, and a silicon-nickel metal compound is formed at the interface between them as a crystallization induction layer.

[0106] In some examples of this embodiment, during the step of heating the nickel metal material layer 215 and the precursor layer 210, the heating temperature can be controlled below 280°C to ensure the formation of nickel disilicide with a better lattice structure, thereby improving the quality of the final formed single crystal silicon.

[0107] In some examples of this embodiment, after forming the crystallization-inducing layer, a step of removing the nickel metal material layer 215 may be included. The nickel metal material layer 215 may be removed by wet etching, which selectively removes the nickel metal material layer 215 while retaining the crystallization-inducing layer.

[0108] In some examples of this embodiment, during the heat treatment of the crystallization induction layer and the precursor layer 210, the heat treatment temperature can be controlled to be between 400°C and 600°C to induce the precursor layer 210 to transform into a single-crystal material and ensure the quality of the single-crystal material. Further, the heat treatment temperature can be controlled to be 400°C, 420°C, 450°C, 470°C, 500°C, 520°C, 550°C, 570°C, or 600°C, or the heat treatment temperature can be within any two of the above temperatures.

[0109] In some examples of this embodiment, for the precursor layer 210 containing doped elements, the doped elements are incorporated into the single crystal material during the heat treatment process to obtain a channel layer with high carrier mobility.

[0110] In some examples of this embodiment, after removing the nickel metal material layer 215, a step of preparing a second isolation protective layer 150 in the second trench 320 may be included, which may fill the second trench 320.

[0111] In some examples of this embodiment, the material of the second isolation filler layer 321 may be the same as the material of the first isolation filler layer 311.

[0112] In some examples of this embodiment, the material of the second isolation filling layer 321 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the material of the second isolation filling layer 321 may be silicon oxide.

[0113] During the process of inducing the formation of single-crystal materials through the crystallization induction layer, the transformation process proceeds gradually in the direction away from the crystallization induction layer. However, there may be solid phase materials in the precursor layer 210 that hinder this transformation process, resulting in the precursor layer 210 not being completely transformed into single-crystal materials. At this time, there may still be some untransformed precursor layer 210 on the side of the single-crystal material away from the crystallization induction layer, which affects the quality of the channel layer.

[0114] To address the aforementioned issues, in some examples of this embodiment, after forming the single-crystal material, the following steps may be included: forming a third trench 330 on the side of the precursor layer 210 away from the second isolation filling layer 321, and etching the precursor layer 210 exposed in the third trench 330 to remove at least a portion of the precursor layer 210. The third trench 330 may be formed by etching at least a portion of the retained first isolation filling layer 311.

[0115] Figure 9A In order to be in Figure 8A A schematic diagram showing the formation of a third trench 330 and etching of the precursor layer 210 based on the structure shown. Figure 9B for Figure 9A Schematic diagram of the cross-sectional structure along AA'. Figure 9C for Figure 9A A schematic diagram of the cross-sectional structure along the middle edge BB'. (Refer to...) Figures 9A to 9CAs shown, the surface of the precursor layer 210 away from the second isolation filling layer 321 can be exposed from the third trench 330 and is etched away during the etching process. In some examples of this embodiment, the precursor layer 210 can be etched using wet etching. It is understood that due to the difference in crystal phase, the precursor layer 210 has a relatively high etching rate compared to single-crystal materials, thus allowing single-crystal materials to be preserved during the etching process. The etching of the precursor layer 210 creates a vacancy region located between the bit line sacrificial layer 213 and the capacitor sacrificial layer 214.

[0116] In some examples of this embodiment, after etching the precursor layer 210, a step of preparing a protective layer 150 in the vacant area may also be included. Figure 10A In order to be in Figure 9A A schematic diagram of the structure for fabricating the protective layer 150 based on the structure shown. Figure 10B for Figure 10A Schematic diagram of the cross-sectional structure along AA'. Figure 10C for Figure 10A A schematic diagram of the cross-sectional structure of the middle edge BB'. The protective layer 150 can be located between the bit line sacrificial layer 213 and the capacitor sacrificial layer 214 and fill the empty area. The protective layer 150 can also be connected to the bit line sacrificial layer 213, the capacitor sacrificial layer 214 and the channel layer 110 to protect the channel layer and enhance its structural stability.

[0117] Reference Figures 10A to 10C As shown, in some examples of this embodiment, after etching the precursor layer 210, a step of preparing a third isolation fill layer 331 in the third trench 330 may be included. Further, the third isolation fill layer 331 may be located on the side of the protective layer 150 away from the trench layer.

[0118] In some examples of this embodiment, the material of the third isolation filler layer 331 may be the same as the material of the protective layer 150. Furthermore, the third isolation filler layer 331 and the protective layer 150 may be prepared simultaneously.

[0119] In some examples of this embodiment, the material of the third isolation filler layer 331 may be the same as the material of the second isolation filler layer 321.

[0120] In some examples of this embodiment, the material of the third isolation filling layer 331 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the material of the third isolation filling layer 331 may be silicon oxide.

[0121] It is understood that, through steps S1 to S3, in this embodiment, after forming the channel layer 110, the steps of forming bit lines 120, word lines 130 and capacitors 140 may also be included.

[0122] Step S4: Prepare bit line 120 and word line 130.

[0123] In this embodiment, bit line 120 can be fabricated in bit line receiving region 2101 and contact channel layer 110, and word line 130 can be fabricated on the third-direction side of channel layer 110. Further, word line 130 can be fabricated on the side of channel layer 110 away from protective layer 150.

[0124] In some examples of this embodiment, the steps of fabricating bit line 120 and word line 130 may include: removing bit line sacrificial layer 213, fabricating word line vias in second isolation fill layer 321, and fabricating bit line 120 and word line 130 in bit line receiving region 2101 and word line vias, respectively.

[0125] Figure 11A In order to be in Figure 10A A schematic diagram of the structure shown, based on which the bit line sacrificial layer 213 is removed and the word line via is fabricated. Figure 11B for Figure 11A Schematic diagram of the cross-sectional structure along AA'. Figure 11C for Figure 11A A schematic diagram of the cross-sectional structure along the middle edge BB'. (Refer to...) Figures 11A to 11C As shown, the bit line sacrificial layer 213 is removed, thereby exposing the bit line receiving area 2101, and the axial direction of the word line hole can be along the first direction, and the word line hole can penetrate the second isolation fill layer 321 in the first direction.

[0126] Figure 12A In order to be in Figure 11A Based on the structure shown, a schematic diagram of the structure of bit line 120 and word line 130 is prepared. Figure 12B for Figure 12A Schematic diagram of the cross-sectional structure along AA'. Figure 12C for Figure 12A A schematic diagram of the cross-sectional structure along the middle edge BB'. (Refer to...) Figures 12A-12C As shown, bit line 120 can be disposed in bit line receiving area 2101, and bit line 120 can extend along a third direction. Bit line 120 can be electrically connected to a plurality of channel layers 110 arranged in parallel in the third direction. Word line 130 can be disposed in word line hole, and word line 130 can extend along a first direction. Word line 130 can be electrically connected to a plurality of channel layers 110 arranged in parallel in the first direction.

[0127] In some examples of this embodiment, word line 130 includes a gate dielectric layer and a gate. The material of the gate can be the same as the material of bit line 120, so that the gate and bit line 120 can be fabricated in the same process.

[0128] In some examples of this embodiment, the material of bit line 120 may be selected from one or more of titanium and titanium nitride, and the material of gate may also be selected from one or more of titanium and titanium nitride.

[0129] In some examples of this embodiment, the gate dielectric layer can be formed by deposition, or the gate dielectric layer can be formed by oxidizing the channel layer 110.

[0130] Step S5: Prepare capacitor 140.

[0131] In this embodiment, capacitor 140 may be fabricated in capacitor accommodating region 2102 and in contact with channel layer 110.

[0132] In some examples of this embodiment, the steps of fabricating capacitor 140 may include: removing capacitor sacrificial layer 214, and sequentially fabricating outer electrode 143, dielectric layer 142 and inner electrode 141 in capacitor accommodating region 2102.

[0133] Figure 13A In order to be in Figure 12A A schematic diagram of the structure shown, with the capacitor sacrificial layer 214 removed. Figure 13B for Figure 13A Schematic diagram of the cross-sectional structure along AA'. Figure 13C for Figure 13A A schematic diagram of the cross-sectional structure along the middle edge BB'. (Refer to...) Figures 13A-13C As shown, the channel layer 110 has a capacitor accommodating region 2102 on the side away from the bit line 120. The capacitor accommodating region 2102 is located between two adjacent support layers 220, and is also located between the second isolation fill layer 321 and the third isolation fill layer 331.

[0134] In some examples of this embodiment, the capacitor sacrificial layer 214 can be removed by dry etching or wet etching. It is understood that since the material of the capacitor sacrificial layer 214 is different from the materials of the second and third isolation layers, the capacitor sacrificial layer 214 can be removed more preferentially to obtain the aperture-shaped capacitor accommodating region 2102.

[0135] The outer electrode 143, dielectric layer 142, and inner electrode 141 can be sequentially fabricated in the capacitor accommodating region 2102. In some examples of this embodiment, the outer electrode 143, dielectric layer 142, and inner electrode 141 can be fabricated by deposition. During fabrication, the deposition time can be controlled so that the outer electrode 143 adheres to the hole wall of the capacitor accommodating region 2102, and the side of the outer electrode 143 away from the hole wall also has an inner hole. Further, the dielectric layer 142 can adhere to the hole wall of the inner hole of the outer electrode 143, and the side of the dielectric layer 142 away from the outer electrode 143 also has an inner hole, and the inner electrode 141 can fill the inner hole of the dielectric layer 142.

[0136] It is understandable that, through steps S1 to S5, the following can be prepared: Figures 1A to 1C The semiconductor structure shown.

[0137] Traditional techniques typically only allow the fabrication of polycrystalline materials. However, due to the high scattering of polycrystalline materials, they are not suitable for fabricating multiple transistors stacked along the height direction. In the semiconductor structure fabrication method disclosed herein, multiple support layers and a precursor layer are first fabricated. The precursor layer is then amorphized to form an amorphous portion. A crystallization induction layer is then used to transform the precursor layer into a single-crystal material and form a channel layer. This process ensures that the channel layer, stacked along a first direction, includes single-crystal material, which significantly improves the stacking density of the channel layer while maintaining its carrier mobility.

[0138] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0139] It should be understood that, unless explicitly stated herein, there is no strict order in which the steps are performed; these steps may be performed in other orders. Moreover, at least some steps in the preparation process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0140] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0141] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A multilayer support layer and a multilayer precursor layer are fabricated on a substrate, wherein the support layer and the precursor layer are alternately stacked along a first direction, wherein the precursor layer includes a connecting portion and a plurality of spacer portions connected in a second direction, the connecting portion extending along a third direction, and the plurality of spacer portions being spaced along the third direction; Remove the connecting portion to form a bit line receiving area, and remove the portion of the spacing portion away from the connecting portion to form a capacitor receiving area; One side surface of the remaining spacer portion is subjected to amorphization treatment to form an amorphous portion; A crystallization-inducing layer in contact with the amorphous portion is prepared and subjected to heat treatment to transform the precursor layer into a single crystal material and form a channel layer having a source end and a drain end. A bit line is formed in the bit line receiving area, and the bit line extends in a third direction; A capacitor is formed in the capacitor accommodating region, and the bit line is electrically connected to the source terminal and the drain terminal of the capacitor, respectively. A word line is formed, the word line extending along the first direction, the word line being used to control the channel layer, the first direction being perpendicular to the surface of the substrate, and the plane defined by the second direction and the third direction being parallel to the surface of the substrate.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The precursor layer comprises silicon, and the crystallization induction layer is made of a silicon-nickel metal compound.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The precursor layer is polycrystalline silicon, and the precursor layer further includes doping elements, wherein the doping concentration of the doping elements in the polycrystalline silicon is 10. 16 cm -3 ~10 19 cm -3 .

4. The method for preparing a semiconductor structure according to claim 2, characterized in that, The step of preparing a crystallization-inducing layer in contact with the amorphous portion includes: preparing a nickel metal material layer on the amorphous portion, and reacting the nickel metal material layer with the amorphous portion to form the crystallization-inducing layer.

5. The method for preparing a semiconductor structure according to any one of claims 1-4, characterized in that, The step of amorphizing one side surface of the precursor layer includes: implanting ions into the surface of the precursor layer by means of ion implantation.

6. The method for preparing a semiconductor structure according to any one of claims 1-4, characterized in that, A bit line sacrificial layer and a capacitor sacrificial layer are respectively fabricated in the bit line accommodating region and the capacitor accommodating region; After forming the channel layer, the bit line sacrificial layer and the capacitor sacrificial layer are removed, and the bit line and the capacitor are fabricated in the bit line accommodating region and the capacitor accommodating region, respectively.

7. A semiconductor structure formed by the preparation method according to any one of claims 1-6, characterized in that, The device includes a substrate, a channel layer, a bit line, a word line, and a capacitor. There are multiple channel layers stacked along a first direction intersecting the surface of the substrate. Each channel layer is made of a single crystal material and has a source end and a drain end. The bit line and the capacitor are electrically connected to the source end and the drain end, respectively. The word line is used to control the channel layer.

8. The semiconductor structure according to claim 7, characterized in that, The capacitor is elongated and extends along a second direction. The capacitor includes an inner electrode, a dielectric layer, and an outer electrode extending along a third direction. The dielectric layer is disposed between the inner electrode and the outer electrode, surrounds the inner electrode, and surrounds the outer electrode. The inner electrode or the outer electrode is electrically connected to the channel layer.

9. The semiconductor structure according to claim 7, characterized in that, It also includes a protective layer disposed between the bit line and the capacitor, and the protective layer is connected to the channel layer, the bit line and the capacitor.

10. The semiconductor structure according to any one of claims 7-9, characterized in that, The single-crystal material is single-crystal silicon.

11. A method for fabricating a semiconductor structure, characterized in that, include: A multilayer support layer and a multilayer precursor layer are deposited on a substrate, wherein the support layer and the precursor layer are alternately stacked along a first direction; Etch multiple layers of the support layer and multiple layers of the precursor layer to expose the side surface of the precursor layer in the third direction; The exposed side surface of the precursor layer is amorphized from the third party to form an amorphous portion; A crystallization-inducing layer is formed on the surface of the amorphous portion and heat-treated to transform the amorphous portion into a single-crystal material and form a channel layer, the channel layer having a source end, a channel region, and a drain end arranged sequentially in a second direction; Forming a bit line extending along the third direction; A capacitor is formed, wherein the bit line is electrically connected to the source terminal and the drain terminal of the capacitor, respectively. A word line is formed extending along the first direction, the word line being used to control the channel layer, the first direction being perpendicular to the surface of the substrate, and the plane defined by the second direction and the third direction being parallel to the surface of the substrate.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The precursor layer comprises silicon, and the crystallization induction layer is made of a silicon-nickel metal compound.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The precursor layer is polycrystalline silicon, and the precursor layer further includes doping elements, wherein the doping concentration of the doping elements in the polycrystalline silicon is 10. 16 cm -3 ~10 19 cm -3 .

14. The method for preparing a semiconductor structure according to claim 12, characterized in that, The step of preparing a crystallization-inducing layer in contact with the amorphous portion includes: preparing a nickel metal material layer on the amorphous portion, and reacting the nickel metal material layer with the amorphous portion to form the crystallization-inducing layer.

15. The method for preparing a semiconductor structure according to any one of claims 11-14, characterized in that, The step of amorphizing one side surface of the precursor layer includes: implanting ions into the surface of the precursor layer by means of ion implantation.

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