Cell Structure of Integrated Gate Commutated Thyristor and Its Preparation Method

Abstract

The present application provides a cell structure of an integrated gate-commutated thyristor and a preparation method thereof, the cell structure comprising: a substrate; a drift layer having a first surface on a side away from the substrate; a first doping layer comprising a first sub-doping region and a second sub-doping region, the first sub-doping region and the second sub-doping region being arranged alternately along a first direction, the first sub-doping region having a first doping type, and the second sub-doping region having a second doping type; a surface of the second doping layer on a side away from the substrate being a second surface; a portion of the cathode structure being located in the second doping layer, and another portion being located on the second surface; and a plurality of gates being located on both sides of the cathode structure in the first direction. By forming a semi-superjunction structure formed by the first sub-doping region and the second sub-doping region on the drift layer, the thickness of the drift layer is reduced, and the reduction in the thickness of the drift layer can also reduce the on-resistance of the thyristor and improve the switching speed of the thyristor. The problem of a large size of the cell structure and poor overall performance is solved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more particularly, to a cell structure of an integrated gate-commutated thyristor, a method for manufacturing the same, and an integrated gate-commutated thyristor. Background Art

[0002] The cell structure of a conventional integrated gate-commutated thyristor (GCT) mainly consists of four layers: a P + anode region, an N - drift region, a P-base region, and an N + cathode region. During operation, when a forward voltage is applied to the device, the charges in the N - drift region are depleted, forming a depletion region to withstand the longitudinal electric field. Although this longitudinal voltage withstand structure can provide a relatively high blocking voltage, due to the need for a relatively large drift region thickness to ensure sufficient voltage withstand capacity, the overall size of the device is relatively large, increasing the on-resistance and thus the on-state loss. In addition, the overly thick drift region also limits the switching speed of the device, reducing its performance in high-frequency applications, and consequently resulting in relatively poor comprehensive performance of the integrated gate-commutated thyristor.

[0003] The above information disclosed in the background art section is only used to enhance the understanding of the background art of the technology described herein. Therefore, the background art may contain certain information that is not prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of the present application is to provide a cell structure of an integrated gate-commutated thyristor, a method for manufacturing the same, and an integrated gate-commutated thyristor, so as to solve the problems in the prior art that the integrated gate-commutated thyristor has a relatively large size and relatively poor comprehensive performance.

[0005] To achieve the above object, according to one aspect of the present application, a cell structure of an integrated gate-commutated thyristor is provided, including: a substrate having a first doping type; a drift layer located on one side of the substrate, the drift layer having a first surface on the side facing away from the substrate, the drift layer having a second doping type different from the first doping type; a first doping layer located on the first surface, the first doping layer including a first sub-doping region and a second sub-doping region, the first sub-doping region and the second sub-doping region being alternately arranged along a first direction, the first sub-doping region having the first doping type, the second sub-doping region having the second doping type, the first direction being perpendicular to the direction from the substrate to the drift layer; a second doping layer located on the side of the first doping layer facing away from the substrate, the surface of the second doping layer facing away from the substrate being a second surface, the second doping layer having the first doping type; a cathode structure, a part of which is located in the second doping layer and another part is located on the second surface; and a plurality of gate electrodes spaced apart and located on the second surface, the plurality of gate electrodes being located on both sides of the cathode structure in the first direction.

[0006] Optionally, the contact surface between the first sub-doping region and the second sub-doping region is perpendicular to the first surface.

[0007] Optionally, the second doping layer includes a first sub-doping layer and a second sub-doping layer, where: the first sub-doping layer is located on the side of the first doping layer facing away from the substrate; the second sub-doping layer is located on the side of the first sub-doping layer facing away from the substrate, and the doping concentration of the second sub-doping layer is greater than that of the first sub-doping layer.

[0008] Optionally, the widths of the first sub-doping region and the second sub-doping region in the first direction are 1 μm to 10 μm.

[0009] Optionally, the cathode structure includes: a cathode emitter and a cathode, where: at least part of the cathode emitter is located in the second doping layer; the cathode is located on the side of the cathode emitter facing away from the drift layer, and the cathode is in contact with the cathode emitter.

[0010] Optionally, the cell structure further includes a plurality of first insulating layers located between the gate electrodes and the cathode structure, the first insulating layers being in contact with the gate electrodes and the cathode and covering the sidewalls of the cathode emitter.

[0011] Optionally, the cell structure further includes a plurality of second insulating layers covering the gate electrodes and the first insulating layers.

[0012] According to another aspect of the present application, a method for preparing a cell structure of an integrated gate-commutated thyristor is provided, which is used to prepare the cell structure of the integrated gate-commutated thyristor. The preparation method includes: providing a substrate having a first doping type; forming a drift layer on the substrate, the drift layer having a first surface on a side facing away from the substrate, the drift layer having a second doping type, and the first doping type being different from the second doping type; forming a first doping layer on the first surface, the first doping layer including a first sub-doping region and a second sub-doping region, the first sub-doping region and the second sub-doping region being alternately arranged in a first direction, the first sub-doping region having the first doping type, the second sub-doping region having the second doping type, the first direction being parallel to the first surface and perpendicular to the direction from the substrate to the drift layer; forming a second doping layer on a side of the first doping layer facing away from the substrate, a surface of the second doping layer facing away from the substrate being a second surface, the second doping layer having the first doping type; forming a cathode structure at least in the second doping layer; and forming a plurality of spaced-apart gate electrodes on the second surface, the plurality of gate electrodes being located on two sides of the cathode structure in the first direction.

[0013] Optionally, the step of forming the first doping layer on the first surface includes: forming a first semiconductor layer on the first surface, the first semiconductor layer having a plurality of first regions and second regions, the second regions and the first regions being alternately arranged in the first direction; performing a first ion implantation on the first regions to form the first sub-doping regions; and performing a second ion implantation on the second regions to form the second sub-doping regions, the first sub-doping regions and the second sub-doping regions forming the first doping layer.

[0014] According to still another aspect of the present application, an integrated gate-commutated thyristor is provided, which includes at least one of the cell structures of the integrated gate-commutated thyristor.

[0015] By applying the technical solution of the present application, a cell structure of an integrated gate-commutated thyristor includes a substrate, a drift layer, a first doping layer, a second doping layer, a cathode structure and a gate, wherein the first doping layer is located on the drift layer, the first doping layer includes a first sub-doping region and a second sub-doping region with different doping types, the first sub-doping region and the second sub-doping region are alternately arranged along a first direction, and the first direction is perpendicular to the direction from the substrate to the drift layer; the second doping layer is located on a side of the first doping layer away from the substrate, a surface of the second doping layer away from the substrate is a second surface, and the second doping layer has a first doping type; a portion of the cathode structure is located in the second doping layer, and another portion is located on the second surface; a plurality of gates are located on the second surface at intervals, and a plurality of gates are located on both sides of the cathode structure in the first direction. In the prior art, a larger drift layer thickness and width are required to ensure sufficient longitudinal voltage resistance, resulting in a larger overall size of the device. In the present application, the contact area between the first sub-doping region and the second sub-doping region in the first doping layer is the depletion region of the thyristor. By arranging the first sub-doping region and the second sub-doping region alternately, a semi-superjunction structure is formed on the drift layer. The semi-superjunction structure converts a part of the original longitudinal depletion region into a transverse depletion region to generate a transverse electric field. Since the transverse electric field can share the voltage stress laterally, the stress intensity of the longitudinal voltage is reduced, thereby reducing the requirement for the drift layer to disperse the longitudinal voltage stress. Therefore, the thickness and width of the drift layer in the cell structure can be reduced, thereby reducing the size of the overall thyristor. Moreover, the reduction in the thickness of the drift layer can also reduce the on-resistance of the thyristor and increase the switching speed of the thyristor. The cell structure of the integrated gate-commutated thyristor proposed in the present application solves the problem that the integrated gate-commutated thyristor in the prior art is large in size and has poor overall performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A schematic cross-sectional structure diagram of a cell structure of a first integrated gate-commutated thyristor according to an embodiment of the present application is shown;

[0018] Figure 2 A schematic cross-sectional structure diagram of a cell structure of a second integrated gate-commutated thyristor according to an embodiment of the present application is shown;

[0019] Figure 3 A schematic cross-sectional structure diagram of a first doping layer according to an embodiment of the present application is shown;

[0020] Figure 4Shows a schematic cross-sectional structure of a cell structure of a third integrated gate-commutated thyristor according to an embodiment of the present application;

[0021] Figure 5 Shows a schematic cross-sectional structure of a cell structure of a fourth integrated gate-commutated thyristor according to an embodiment of the present application;

[0022] Figure 6 Shows a schematic cross-sectional structure of a cell structure of a fifth integrated gate-commutated thyristor according to an embodiment of the present application;

[0023] Figure 7 Shows a schematic flow structure of a preparation method of a cell structure of an integrated gate-commutated thyristor according to an embodiment of the present application;

[0024] Figure 8 Shows a schematic cross-sectional structure of forming a first doped layer in a preparation method of a cell structure of an integrated gate-commutated thyristor according to an embodiment of the present application;

[0025] Figure 9 Shows a schematic cross-sectional structure of forming a first doped layer in a preparation method of another cell structure of an integrated gate-commutated thyristor according to an embodiment of the present application;

[0026] Figure 10 Shows a schematic cross-sectional structure of an integrated gate-commutated thyristor according to an embodiment of the present application.

[0027] Among them, the above-mentioned drawings include the following reference numerals:

[0028] 1. Cell structure; 10. Substrate; 20. Drift layer; 30. First doped layer; 31. First sub-doped region; 32. Second sub-doped region; 310. First region; 320. Second region; 40. Second doped layer; 41. First sub-doped layer; 42. Second sub-doped layer; 50. Cathode structure; 51. Cathode emitter; 52. Cathode; 60. Gate; 70. First insulating layer; 80. Second insulating layer; 90. Anode; 100. Carbon nanotube; 300. First semiconductor layer. Detailed implementation manners

[0029] It should be noted that the following detailed description is exemplary and is intended to provide further illustration of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs.

[0030] It should be noted that the terms used herein are merely for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they specify the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0031] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so as to implement the embodiments of the present invention described herein. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0032] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element can be directly on the other element, or there may also be an intermediate element. Moreover, in the description and claims, when an element is described as "connected" to another element, the element can be "directly connected" to the other element, or "connected" to the other element through a third element.

[0033] As introduced in the background art, the cell structure of a traditional Gate-Commutated Thyristor (GCT) in the prior art mainly consists of four layers: an anode region, a drift region, a base region, and a cathode region. During operation, when a forward voltage is applied to the device, the charges in the drift region are depleted, forming a depletion region to withstand the longitudinal electric field. Although this longitudinal voltage withstand structure can provide a relatively high blocking voltage, due to the need for a relatively large thickness and width of the drift region to ensure sufficient voltage withstand capacity, the overall size of the device is relatively large, increasing the on-resistance and thus increasing the on-state loss. In addition, the overly thick drift region also limits the switching speed of the device and reduces its performance in high-frequency applications. To solve the problems of the relatively large size and poor comprehensive performance of the integrated gate-commutated thyristor in the prior art, embodiments of the present application provide a cell structure of an integrated gate-commutated thyristor, a preparation method thereof, and an integrated gate-commutated thyristor.

[0034] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention.

[0035] According to one aspect of the present application, a cell structure of an integrated gate-commutated thyristor is proposed, such as Figure 1 and Figure 2 As shown, it includes: a substrate 10 having a first doping type; a drift layer 20 located on one side of the substrate 10, the drift layer 20 having a first surface on the side away from the substrate 10, the drift layer 20 having a second doping type, and the first doping type is different from the second doping type; a first doping layer 30 located on the first surface, the first doping layer 30 including a first sub-doping region 31 and a second sub-doping region 32, the first sub-doping region 31 and the second sub-doping region 32 are alternately arranged along a first direction X, the first sub-doping region 31 has the first doping type, and the second sub-doping region 32 has the second doping type, and the first direction X is perpendicular to the direction from the substrate 10 to the drift layer 20; a second doping layer 40 located on the side of the first doping layer 30 away from the substrate 10, the side surface of the second doping layer 40 away from the substrate 10 is the second surface, and the second doping layer 40 has the first doping type; a cathode structure 50, a part of which is located in the second doping layer 40, and the other part is located on the second surface; a plurality of gate electrodes 60, which are located on the second surface at intervals, and the plurality of gate electrodes 60 are located on both sides of the cathode structure 50 in the first direction X.

[0036] The problem of large size and poor overall performance of the integrated gate-commutated thyristor is solved by setting a first doping layer on the drift layer of the cell structure of the integrated gate-commutated thyristor. The first doping layer includes a first sub-doping region and a second sub-doping region, and the contact area between the two is the depletion region of the thyristor. The contact area between the first sub-doping region and the second sub-doping region can generate a lateral electric field. Since the lateral electric field can share the voltage stress, the stress intensity of the longitudinal voltage is reduced, thereby reducing the thyristor's demand for the drift layer to disperse the longitudinal voltage stress (voltage resistance). Therefore, the thickness and width of the drift layer in the cell structure can be reduced, thereby reducing the size of the overall thyristor, and the reduction in the thickness of the drift layer can also reduce the on-resistance of the thyristor and increase the switching speed of the thyristor. By setting a semi-superjunction structure formed by the first doping layer on the drift layer, the overall performance of the thyristor is improved.

[0037] In a traditional vertically structured thyristor device, the electric field is mainly distributed along the opposite direction of current flow (i.e., vertically). This means that the electric field will concentrate on a certain part in the thickness direction of the device, resulting in a higher electric field intensity in that part, which is likely to form an electric field hot spot and then trigger local early breakdown. In this application, a first doped layer with alternately distributed first and second sub-doped regions is introduced into the thyristor. The current and electric field generating the transverse electric field are distributed in directions perpendicular to each other. The electric field is evenly distributed in the depletion region in the width direction of the device, making the electric field intensity more uniform, avoiding the early breakdown phenomenon caused by excessive local electric field. This uniformly distributed transverse electric field can significantly improve the overall voltage withstand capacity of the device, effectively increase the blocking voltage of the device, and enable the device to perform better in high-voltage applications.

[0038] The traditional superjunction structure forms alternately distributed first and second sub-doped regions on the substrate. The superjunction structure penetrates the drift layer and has a relatively deep depth, making the manufacturing process difficult. In this application, a semi-superjunction structure with alternately arranged first and second sub-doped regions is formed above the drift layer, which is easier to achieve uniform doping and precise columnar structure of the semi-superjunction structure.

[0039] The thyristor proposed in this application improves the on-resistance, switching speed, overall voltage withstand capacity, blocking voltage and manufacturing process of the thyristor in the case of a smaller size, and improves the comprehensive performance of the device.

[0040] In some embodiments, the materials of the substrate, drift layer, first doped layer and second doped layer can be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide and aluminum gallium nitride. Among them, the substrate is located at the top of the device as the main channel for current injection. The drift layer is used to withstand the reverse voltage when the thyristor is in the off state. The first doped layer is used to convert the longitudinal electric field into a transverse electric field and uniform the electric field intensity. The second doped layer can enable the current to flow smoothly when the device is in the on state and block the current when the device is in the off state, playing a role in controlling the current flow.

[0041] In some embodiments, the material of the gate can be any one of aluminum, titanium, tungsten and molybdenum, or an alloy of the above metals.

[0042] In some embodiments, the first doping type can be N-type doping, the second doping type can be P-type doping, or the first doping type can be P-type doping, the second doping type can be N-type doping. The P-type dopant can be boron, and the N-type dopant is phosphorus or arsenic.

[0043] In some alternative embodiments, such as Figure 1 and Figure 2As shown, the contact surface between the first sub-doped region 31 and the second sub-doped region 32 is perpendicular to the first surface. In this case, a lateral electric field close to the first direction X can be generated in the contact region between the first sub-doped region 31 and the second sub-doped region 32, which can better reduce the requirement of the thyristor for the breakdown voltage of the drift layer 20 to disperse the longitudinal voltage. Furthermore, the thickness and width of the drift layer 20 can be reduced. The reduction of the thickness of the drift layer 20 reduces the on-resistance of the drift layer 20 and reduces the conduction loss. Moreover, by introducing a lateral electric field and making the lateral electric field act synergistically with the longitudinal electric field, the overall breakdown voltage and blocking voltage of the device can be improved. The semi-superjunction structure in this application can balance the breakdown voltage and conduction loss of the device. Among them, the doping concentrations of the first sub-doped region and the second sub-doped region can be 10 16 ~10 18 cm -3 , such as 10 17 cm -3 .

[0044] It should be noted that in the case of forming the first sub-doped region and the second sub-doped region by ion implantation, due to partial diffusion during ion implantation, the contact surface between the first sub-doped region and the second sub-doped region will not be a flat plane. However, the depletion region is a region and will not be affected by the non-flat contact surface between the first sub-doped region and the second sub-doped region in generating a lateral electric field in the depletion region.

[0045] In some alternative embodiments, as Figure 1 and Figure 2 shown, the cathode structure 50 includes: a cathode emitter 51 and a cathode 52, where: at least part of the cathode emitter 51 is located in the second doped layer 40; the cathode 52 is located on the side of the cathode emitter 51 away from the drift layer 20, and the cathode 52 is in contact with the cathode emitter 51. The cathode structure 50 is used to receive the current conducted from the second doped layer 40. The cathode emitter 51 can collect the current flowing from the second doped layer 40 and transmit it to the cathode 52. The doping type of the cathode emitter 51 is opposite to the doping type of the second doped layer 40, and a PN junction structure is formed therebetween, which can control the flow of the device current.

[0046] In some alternative embodiments, as Figure 2As shown, the second doping layer 40 includes a first sub-doping layer 41 and a second sub-doping layer 42, where: the first sub-doping layer 41 is located on the side of the first doping layer 30 away from the substrate 10; the second sub-doping layer 42 is located on the side of the first sub-doping layer 41 away from the substrate 10, and the doping concentration of the second sub-doping layer 42 is greater than that of the first sub-doping layer 41. A higher doping concentration of the second sub-doping layer 42 can more easily form an ohmic contact with the gate 60 and reduce the contact resistance of the gate 60. When a positive voltage is applied to the gate 60, the turn-on voltage of the PN junction formed by the second sub-doping layer 42 and the cathode emitter 51 can be made smaller and easier to turn on, prompting electrons of the cathode emitter 51 to be injected into the first sub-doping layer 41 and the second sub-doping layer 42. The electron injection can significantly reduce the resistance of the first sub-doping layer 41 and the second sub-doping layer 42, thereby reducing the conduction voltage drop of the entire device and reducing the power loss in the conduction state.

[0047] In some alternative embodiments, as Figure 3 shown, the widths of the first sub-doping region 31 and the second sub-doping region 32 in the first direction X are 1 μm to 10 μm. With the widths of the first sub-doping region 31 and the second sub-doping region 32 within the above range, the device can simultaneously have the advantages of uniform internal electric field distribution, good voltage withstand ability, and easy manufacturability of the manufacturing process.

[0048] In some alternative embodiments, as Figure 1 and Figure 2 shown, the cell structure 1 further includes a plurality of first insulating layers 70. The first insulating layers 70 are located between the gate 60 and the cathode structure 50, and the first insulating layers 70 are in contact with the gate 60 and the cathode 52 and cover the sidewalls of the cathode emitter 51. The material of the first insulating layer 70 can be insulating materials such as silicon dioxide, silicon oxide, and silicon oxynitride. The first insulating layer 70 is used to insulate the gate 60 and the cathode structure 50.

[0049] In some alternative embodiments, as Figure 1 and Figure 2 shown, the cell structure 1 further includes a plurality of second insulating layers 80. The second insulating layers 80 cover the gate 60 and the first insulating layers 70. The second insulating layer 80 can be PI glue (Polyimide), or other insulating materials. The second insulating layer 80 is used to further insulate and encapsulate the gate 60 to prevent the gate 60 from being eroded by external moisture. The thicknesses of the first insulating layer 70 and the second insulating layer 80 can be 100 nm to 500 nm, such as 200 nm, 300 nm, or 400 nm. Limiting the thicknesses of the first insulating layer 70 and the second insulating layer 80 within the above range can not only ensure the insulation performance of the device but also ensure that the device has a low parasitic capacitance.

[0050] In the above optional implementation, if Figure 1 and Figure 2 As shown, the cell structure 1 also includes an anode 90, which is located on the side of the substrate 10 away from the drift layer 20. The material of the anode 90 can be any one or more of aluminum, copper and silver, and can also be a multilayer metal formed by multiple types of titanium, aluminum, copper, nickel and gold.

[0051] The present application can also form a multi-level semi-superjunction structure on the drift layer, such as Figure 4 As shown, multiple layers of semi-super junction structures are stacked in the depth direction of the device, so that the contact area between the first sub-doping region 31 and the second sub-doping region 32 is stepped, forming a multi-level semi-super junction structure. Figure 5 As shown, multiple layers of semi-super junction structures are stacked in the depth direction of the device, so that the first sub-doping region 31 and the second sub-doping region 32 form more columnar structures, forming a multi-level semi-super junction structure. The depletion region of the multi-level semi-super junction structure becomes larger, and the lateral electric field distribution can be further made more uniform while converting part of the longitudinal electric field into the lateral electric field, thereby optimizing the electric field distribution and further improving the withstand voltage capability of the device.

[0052] like Figure 6 As shown, carbon nanotubes 100 are placed in the second doping layer 40 and the cathode emitter 51 of the thyristor. The carbon nanotubes 100 in the second doping layer 40 are in contact with the gate 60. The surface of the carbon nanotubes 100 facing away from the substrate 10 is located at the interface between the gate 60 and the second doping layer 40. The carbon nanotubes 100 in the cathode emitter 51 are in contact with the cathode 52. The surface of the carbon nanotubes 100 facing away from the substrate 10 is located at the interface between the cathode 52 and the cathode emitter 51. The carbon nanotubes 100 serve as a transition layer at the interface between the gate 60 and the second doping layer 40 (gold semi-contact interface), and an embedding medium for the second doping layer 40 and the cathode emitter 51. The carbon nanotubes 100 have high electron mobility, which can effectively improve the carrier input and extraction speed of the device and improve the switching efficiency of the device. The good conductivity of carbon nanotubes 100 can reduce the resistance of the gold semiconductor interface and reduce device loss. The good flexibility of carbon nanotubes 100 can make the gold semiconductor contact more closely and improve the density of the gold semiconductor contact. The overall performance of the device is improved. Figures 4 to 6 The label structure not mentioned in Figures 1 to 3 The description is consistent with .

[0053] Figure 7 FIG. 1 is a flow chart of a method for preparing a cell structure of an integrated gate-commutated thyristor according to an embodiment of the present application. Figure 7 As shown, the method comprises the following steps:

[0054] Step S201: Provide a substrate having a first doping type.

[0055] Specifically, the material of the substrate can be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide, and aluminum gallium nitride. The first doping type can be N-type doping or P-type doping. The P-type dopant can be boron, and the N-type dopant can be phosphorus or arsenic.

[0056] Step S202: Form a drift layer on the substrate. The drift layer has a first surface on the side facing away from the substrate, and the drift layer has a second doping type different from the first doping type.

[0057] Specifically, the material of the drift layer can be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide, and aluminum gallium nitride. The drift layer is used to withstand the reverse voltage when the thyristor is in the off state. The doping type of the drift layer is opposite to that of the substrate. For example, if the doping type of the substrate is P-type, the doping type of the drift layer is N-type. The doping concentration of the drift layer is about 10 13 cm -3 .

[0058] Step S203: Form a first doping layer on the first surface. The first doping layer includes a first sub-doping region and a second sub-doping region, which are arranged alternately along a first direction. The first sub-doping region has the first doping type, and the second sub-doping region has the second doping type. The first direction is parallel to the first surface and perpendicular to the direction from the substrate to the drift layer.

[0059] Specifically, the material of the first doping layer can be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide, and aluminum gallium nitride. The first sub-doping region and the second sub-doping region are arranged alternately along the first direction, converting the original longitudinal electric field into a transverse electric field, sharing the longitudinal voltage stress for the drift layer, so that the thickness of the drift layer can be significantly reduced, reducing the size of the device. The reduction of the thickness of the drift layer can reduce the on-resistance of the drift layer and reduce the conduction loss.

[0060] Step S204: Form a second doping layer on the side of the first doping layer facing away from the substrate. The surface of the second doping layer facing away from the substrate is the second surface, and the second doping layer has the first doping type.

[0061] Specifically, the material of the second doping layer can be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide, and aluminum gallium nitride. The second doping layer can enable the current to flow smoothly when the device is in the on state and prevent the current from flowing when the device is in the off state, playing a role in controlling the current flow.

[0062] Step S205: Form a cathode structure at least in the second doping layer.

[0063] Specifically, the cathode structure is used to receive the current conducted from the second doped layer. The cathode structure includes a cathode emitter and a cathode. The doping type of the cathode emitter is opposite to that of the second doped layer. The cathode emitter and the second doped layer form a PN junction structure to control the turn-on and turn-off of the thyristor. The material of the cathode can be any one or more of aluminum, copper, tungsten, and molybdenum.

[0064] Step S206, form a plurality of gate electrodes distributed at intervals on the second surface. The plurality of gate electrodes are located on both sides of the cathode structure in the first direction.

[0065] Specifically, the material of the gate electrode can be any one or more of aluminum, titanium, tungsten, and molybdenum. The material of the gate electrode can be the same as or different from that of the cathode.

[0066] The cell structure prepared by the above method for preparing the cell structure of an integrated gate-commutated thyristor has a semi-superjunction structure formed by alternating arrangement of a first sub-doped region and a second sub-doped region on the drift layer, which converts a part of the original longitudinal electric field of the device into a transverse electric field, sharing the longitudinal voltage stress for the drift layer. In this way, the thickness and width of the drift layer can be reduced, thereby reducing the on-resistance and on-loss of the drift layer. Since it is a semi-superjunction structure, it is easier to form a columnar structure with uniform doping, making the electric field intensity distribution more uniform, avoiding the early breakdown phenomenon caused by too high local electric field. This uniformly distributed electric field can significantly improve the overall breakdown voltage withstand ability of the device and increase the blocking voltage. The reduction of the thickness and width of the drift layer also reduces the size of the device and improves the performance of the thyristor, solving the problems of large size and poor comprehensive performance of the integrated gate-commutated thyristor in the prior art.

[0067] Exemplary embodiments of the method for preparing the cell structure of an integrated gate-commutated thyristor according to the present application will be described in more detail below. However, these exemplary embodiments can be implemented in many different forms and should not be construed as being limited only to the embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete and to fully convey the concept of these exemplary embodiments to those of ordinary skill in the art.

[0068] In some alternative embodiments, such as Figure 8 and Figure 9As shown in the figure, the step of forming the first doping layer 30 on the first surface in the above step S203 includes: forming a first semiconductor layer 300 on the first surface of the drift layer 20, the first semiconductor layer 300 having a plurality of first regions 310 and second regions 320, the second regions 320 and the first regions 310 being arranged alternately along the first direction X; performing a first ion implantation on the first regions 310 to form first sub-doped regions 31; performing a second ion implantation on the second regions 320 to form second sub-doped regions 32, the first sub-doped regions 31 and the second sub-doped regions 32 forming the first doping layer 30.

[0069] In the above optional embodiment, as Figure 8 shown, a first semiconductor layer 300 is deposited on the drift layer 20 on the substrate 10, and the first regions 310 and the second regions 320 are defined in the first semiconductor layer 300. As Figure 9 shown, a first mask plate is placed on the surface of the first semiconductor layer facing away from the substrate 10, and ion implantation is performed on the first regions to form first sub-doped regions 31. Then, a second mask layer is placed on the surface of the first semiconductor layer facing away from the drift layer 20, and ion implantation is performed on the second regions to form second sub-doped regions 32. The first sub-doped regions 31 and the second sub-doped regions 32 form the first doping layer 30. Ion implantation will cause some diffusion phenomena, but it will not affect the generation of a lateral electric field in the depletion region between the first sub-doped regions 31 and the second sub-doped regions 32. The first sub-doped regions 31 and the second sub-doped regions 32 can also be formed by an epitaxial growth process or a diffusion method. The present application does not make specific limitations. The material of the first semiconductor layer 300 can be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide, and aluminum gallium nitride.

[0070] According to another aspect of the present application, an integrated gate-commutated thyristor is provided. As Figure 10 shown, it includes at least one cell structure 1 of the integrated gate-commutated thyristor. A semi-superjunction structure formed by alternately arranging first sub-doped regions and second sub-doped regions is formed in the integrated gate-commutated thyristor, which can convert the longitudinal electric field in the integrated gate-commutated thyristor into a lateral electric field, thereby sharing the voltage stress for the drift layer, reducing the thickness and width of the drift layer in the integrated gate-commutated thyristor, and further reducing the size of the integrated gate-commutated thyristor. The reduction of the thickness of the drift layer can reduce the on-resistance and on-loss of the drift layer. Since the thickness of the semi-superjunction structure is small, columnar first sub-doped regions and second sub-doped regions with uniform doping can be prepared, thereby making the electric field uniform and improving the breakdown voltage of the device.

[0071] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the method for preparing the cell structure of the integrated gate-commutated thyristor of the present application will be described in detail below in combination with specific embodiments.

[0072] This embodiment relates to a specific method for preparing a cell structure of an integrated gate-commutated thyristor, comprising the following steps:

[0073] Step S1: providing a P-type substrate, cleaning and polishing the substrate to ensure that its surface is flat and defect-free, and forming an N-type drift layer on the substrate;

[0074] Step S2: forming a first doping layer on the drift layer, the first doping layer comprising a P-type first sub-doping region and an N-type second sub-doping region alternately arranged along a first direction, and performing a high-temperature annealing treatment on the device to activate dopants in the first sub-doping region and the second sub-doping region and repair lattice damage;

[0075] Step S3: forming a P-type second doping layer on the first doping layer, and forming a portion of an N-type cathode emitter in the second doping layer, with another portion of the cathode emitter protruding from the second doping layer;

[0076] Step S4: depositing a first insulating layer on the cathode emitter, and etching the first insulating layer to form a gate and cathode preparation area;

[0077] Step S5: depositing a metal material on the first insulating layer, and etching the metal material to retain the metal material in the gate and cathode preparation regions, forming a gate in the gate preparation region, and forming a cathode in the cathode preparation region;

[0078] Step S6: depositing a second insulating layer on the cathode and the gate, the second insulating layer also covering the first insulating layer, and etching the second insulating layer to expose the top of the cathode;

[0079] Step S7: depositing a metal material on the side of the substrate away from the drift layer to form an anode.

[0080] The above-mentioned deposition process can be a preparation process of chemical vapor deposition or physical vapor deposition, but is not limited thereto. The annealing temperature can range from 900° C. to 1200° C., and the time can range from 30 minutes to several hours.

[0081] The prepared integrated gate-commutated thyristors are cut into individual chips and packaged to ensure the reliability and stability of the devices in practical applications. Electrical tests are also performed on the packaged devices to verify whether their withstand voltage and conduction loss meet the design requirements.

[0082] From the above description, it can be seen that the cell structure of the integrated gate-commutated thyristor provided by this application achieves the following technical effects:

[0083] 1) By providing a first doped layer on the drift layer of the cell structure of the integrated gate-commutated thyristor, the problems of large size and poor comprehensive performance of the integrated gate-commutated thyristor are solved. The first doped layer includes a first sub-doped region and a second sub-doped region, and the contact region between the two is the depletion region of the thyristor. A lateral electric field can be generated in the contact region between the first sub-doped region and the second sub-doped region. Since the lateral electric field can share the voltage stress, the requirement of the thyristor for the drift layer to disperse the longitudinal voltage stress (breakdown voltage) can be reduced, the thickness and width of the drift layer can be reduced, and thus the size of the thyristor can be reduced.

[0084] 2) Since the reduction of the thickness of the drift layer reduces the on-resistance of the thyristor and improves the switching speed of the thyristor.

[0085] 3) A half-superjunction structure in which the above-mentioned first sub-doped region and second sub-doped region are alternately arranged is formed above the drift layer. The depth of the half-superjunction structure in the longitudinal direction of the device is smaller than the depth of the superjunction structure in the longitudinal direction of the device. In the manufacturing process, the half-superjunction structure is easy to achieve uniform doping and an accurate columnar structure.

[0086] The above are only the preferred embodiments of this application and are not used to limit this application. For those skilled in the art, this application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included in the protection scope of this application.

Claims

1. A cell structure of an integrated gate-commutated thyristor, characterized in that: include: a substrate having a first doping type; a drift layer, located on one side of the substrate, the drift layer having a first surface on a side facing away from the substrate, the drift layer having a second doping type, the first doping type being different from the second doping type; A first doping layer, located on the first surface, the first doping layer comprising a first sub-doping region and a second sub-doping region, the first sub-doping region having the first doping type, and the second sub-doping region having the second doping type; A second doping layer is located on a side of the first doping layer away from the substrate, a surface of the second doping layer away from the substrate is a second surface, and the second doping layer has the first doping type; a cathode structure, a portion of which is located in the second doped layer and another portion of which is located on the second surface; A plurality of gate electrodes are spaced apart and located on the second surface, and the plurality of gate electrodes are located on both sides of the cathode structure in a first direction, wherein the first direction is perpendicular to a direction from the substrate to the drift layer; Wherein, the second sub-doping region includes two parts, the first part is below the cathode structure, and the second part is located on both sides of the first part in the first direction, the first part and the second part both include a plurality of protrusions and a plurality of recesses arranged alternately, the lower surfaces of the first part and the second part are flush, the upper surface of each of the protrusions of the first part is higher than the upper surface of each of the protrusions of the second part, in the direction from the cathode structure to the gate, the heights of the plurality of protrusions of the second part decrease successively, the plurality of recesses of the first part and the plurality of recesses of the second part are both provided with the first sub-doping region, the lower surface of the first sub-doping region at the plurality of recesses of the first part is higher than the lower surface of the first sub-doping region at the plurality of recesses of the second part, and the upper surface of the plurality of protrusions of the first part is flush with the upper surface of the first sub-doping region.

2. The cellular structure according to claim 1, characterized in that: A contact surface between the first sub-doping region and the second sub-doping region is perpendicular to the first surface.

3. The cellular structure according to claim 1, characterized in that: The second doping layer includes a first sub-doping layer and a second sub-doping layer, wherein: The first sub-doped layer is located on a side of the first doped layer away from the substrate; The second sub-doping layer is located on a side of the first sub-doping layer away from the substrate, and the doping concentration of the second sub-doping layer is greater than the doping concentration of the first sub-doping layer.

4. The cellular structure according to claim 1, characterized in that: The cathode structure comprises: a cathode emitter and a cathode, wherein: At least part of the cathode emitter is located in the second doped layer; The cathode is located at a side of the cathode emitter away from the drift layer, and the cathode is in contact with the cathode emitter.

5. The cellular structure according to claim 4, characterized in that: The cell structure further includes a plurality of first insulating layers, wherein the first insulating layers are located between the gate and the cathode structure, and the first insulating layers are in contact with the gate and the cathode and cover the side walls of the cathode emitter.

6. The cellular structure according to claim 5, characterized in that: The cell structure further includes a plurality of second insulating layers, wherein the second insulating layers cover the gate and the first insulating layer.

7. A method for preparing a cell structure of an integrated gate-commutated thyristor, characterized in that: A cell structure for preparing an integrated gate-commutated thyristor according to any one of claims 1 to 6, the preparation method comprising: providing a substrate having a first doping type; forming a drift layer on the substrate, wherein the drift layer has a first surface on a side facing away from the substrate, and the drift layer has a second doping type, wherein the first doping type is different from the second doping type; forming a first doping layer on the first surface, the first doping layer comprising a first sub-doping region and a second sub-doping region, the first sub-doping region having the first doping type, and the second sub-doping region having the second doping type; forming a second doping layer on a side of the first doping layer away from the substrate, wherein a surface of the second doping layer on a side away from the substrate is a second surface, and the second doping layer has the first doping type; forming a cathode structure at least in the second doped layer; forming a plurality of gate electrodes distributed at intervals on the second surface, wherein the plurality of gate electrodes are located on both sides of the cathode structure in a first direction, wherein the first direction is perpendicular to a direction from the substrate to the drift layer; Wherein, the second sub-doping region includes two parts, the first part is below the cathode structure, and the second part is located on both sides of the first part in the first direction, the first part and the second part both include a plurality of protrusions and a plurality of recesses arranged alternately, the lower surfaces of the first part and the second part are flush, the upper surface of each of the protrusions of the first part is higher than the upper surface of each of the protrusions of the second part, in the direction from the cathode structure to the gate, the heights of the plurality of protrusions of the second part decrease successively, the plurality of recesses of the first part and the plurality of recesses of the second part are both provided with the first sub-doping region, the lower surface of the first sub-doping region at the plurality of recesses of the first part is higher than the lower surface of the first sub-doping region at the plurality of recesses of the second part, and the upper surface of the plurality of protrusions of the first part is flush with the upper surface of the first sub-doping region.

8. An integrated gate-commutated thyristor, characterized in that: A cell structure comprising at least one integrated gate-commutated thyristor according to any one of claims 1 to 6.

Images