Power semiconductor device and method for manufacturing the same

Abstract

The present application discloses a power semiconductor device and a method for manufacturing the same. The power semiconductor device includes a central region and a peripheral region located on the outer periphery of the central region. Both the central region and the peripheral region include a plurality of cell structures. The cell structure and the pseudo-cell structure both include a buffer region and a base region sequentially arranged in a first direction. The central region further includes a pseudo-cell structure having a conductive channel. In the pseudo-cell structure, the buffer region has a contact surface with the base region and a first surface opposite to the contact surface along the first direction. At least a part of the conductive channel is embedded in a predetermined region in the buffer region. The predetermined region is spaced from the contact surface. The part of the conductive channel embedded in the predetermined region extends from the second surface to the inside of the predetermined region. The predetermined region is used to form a breakdown region when the power semiconductor device withstands the designed breakdown voltage. The present application solves the problem that the overvoltage protection technology applied in the related art to power semiconductor devices results in poor breakdown voltage consistency.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor devices, and more particularly, to a power semiconductor device and a method for manufacturing the same. Background Art

[0002] In the field of power electronics, high power density and high reliability are the two major driving forces for promoting the technological innovation of semiconductor devices. However, an important challenge faced by devices under extreme operating conditions is overvoltage protection, that is, to ensure that the device can conduct safely or bypass excessive voltage when the designed voltage specification is exceeded, so as to prevent damage to the entire system. Traditional overvoltage protection mechanisms, such as edge passivation technology and Breakdown Over Diode (BOD) structures for overvoltage protection, although improve the overvoltage resistance of the device to a certain extent, they have obvious limitations in terms of temperature stability, process complexity, and breakdown voltage consistency.

[0003] Among them, edge passivation technology improves the breakdown voltage of the device by modifying the physical and chemical properties of the device edge to reduce electric field concentration. However, it is difficult to overcome the voltage dispersion caused by material defects and process variations. Especially in high-voltage applications, this dispersion may seriously threaten the safety and reliability of the system. The BOD structure, as an internal protection mechanism, realizes overvoltage protection through a pre-designed weak point. Although the BOD can effectively stabilize the breakdown voltage in some cases, due to the extreme sensitivity of the avalanche breakdown mechanism to temperature, the same structure may exhibit significant performance differences at different temperatures, which limits its broad applicability in applications with large temperature variations and high power density.

[0004] In recent years, with the rapid development of power electronics technology, especially the wide application of high-density modular multilevel converters, more stringent requirements have been put forward for power semiconductor devices, especially in terms of overvoltage breakdown control. Although it is feasible to directly use an external circuit to achieve overvoltage protection, it may be affected by electromagnetic interference and abnormal system power supply, resulting in the failure of the protection mechanism. Therefore, researching and developing overvoltage protection technologies that can be realized at the chip structure level has become a key direction for improving the performance and stability of power electronic systems. Summary of the Invention

[0005] This application provides a power semiconductor device and a method for manufacturing the same to solve the problem of poor breakdown voltage consistency caused by the overvoltage protection technology applied to power semiconductor devices in related technologies.

[0006] According to one aspect of the present application, a power semiconductor device is provided, including a central region and a peripheral region located on the outer periphery of the central region. Both the central region and the peripheral region include a plurality of cell structures. The central region further includes a dummy cell structure. The cell structure and the dummy cell structure both include a buffer region and a base region arranged in sequence along a first direction. The dummy cell structure further includes a conductive channel. In the dummy cell structure: the buffer region has a contact surface with the base region and a first surface opposite to the contact surface along the first direction; at least a part of the conductive channel is embedded in a predetermined region in the buffer region. The predetermined region has a second surface in the first surface, and the predetermined region is spaced from the contact surface. The part of the conductive channel embedded in the predetermined region extends from the second surface into the interior of the predetermined region. The predetermined region is configured to form a breakdown region when the power semiconductor device withstands a breakdown voltage.

[0007] Optionally, the conductive channel includes a nanowire.

[0008] Optionally, the nanowire is selected from any one or more of carbon nanotubes, silicon nanowires, silicon germanium nanowires, silicon carbide nanowires, and metallic nanowires.

[0009] Optionally, the base region includes a first doped region and a second doped region distributed in sequence along the first direction, and the first doped region and the second doped region have different doping types.

[0010] Optionally, the buffer region has the same doping type as the first doped region, where: the buffer region is a third doped region, or the buffer region includes a fourth doped region and a fifth doped region distributed along a second direction perpendicular to the first direction. The predetermined region is located in the fourth doped region, and the doping concentration of the fourth doped region is less than that of the fifth doped region.

[0011] Optionally, the buffer region includes the fourth doped region and the fifth doped region. A side surface of the buffer region facing away from the base region is a third surface. A first projection of the fourth doped region on the third surface is a first projection, and a second projection of the fifth doped region on the third surface is a second projection. The area of the first projection is smaller than the area of the second projection.

[0012] Optionally, the power semiconductor device is an integrated gate-commutated thyristor, and the integrated gate-commutated thyristor further includes a first electrode structure, a second electrode structure, and a third electrode, where: the first electrode structure is located on a side of the buffer region away from the base region, and the first electrode structure includes an anode and an anode emitter sequentially distributed along the first direction; the second electrode structure and the third electrode are located on the same side of the base region, the second electrode structure includes a cathode and a cathode emitter sequentially distributed along the first direction, a part of the cathode emitter is located in the second doped region, and the third electrode is a gate electrode in contact with the second doped region; the conductive channel extends from a surface of the anode emitter away from the buffer region to the inside of the predetermined region; the first doped region and the cathode emitter have a first doping type, and the second doped region and the anode emitter have a second doping type.

[0013] According to another aspect of the present application, a method for manufacturing a power semiconductor device is provided, which is used for the power semiconductor device described above. The manufacturing method includes the following steps: providing a first substrate, in which a buffer region and a base region are sequentially formed along a first direction, the buffer region has a contact surface with the base region and a first surface opposite to the contact surface along the first direction; embedding at least a part of the conductive channel in a predetermined region of the buffer region to obtain a power semiconductor device with a pseudo-cell structure, the predetermined region has a second surface located in the first surface, and the predetermined region is spaced from the contact surface, and the part of the conductive channel embedded in the predetermined region extends from the second surface to the inside of the predetermined region, and the power semiconductor device includes a central region and a peripheral region located outside the central region, and the pseudo-cell structure is provided in the central region.

[0014] Optionally, the step of embedding at least a part of the conductive channel in the predetermined region includes: forming at least one hole in the predetermined region, and the hole extends at least from the second surface to the inside of the predetermined region; filling a conductive material in the hole and curing it to form the conductive channel.

[0015] Optionally, the power semiconductor device is an integrated gate-commutated thyristor, the base region includes a first doped region and a second doped region sequentially distributed along the first direction, the first substrate also includes an anode emitter and a cathode emitter, the anode emitter is located on a side of the base region close to the first doped region, a portion of the cathode emitter is located on a side of the base region close to the second doped region, and another portion of the cathode emitter is located in the second doped region, and the step of forming the hole includes: forming the hole from a side surface of the anode emitter away from the buffer zone to penetrate into the predetermined area; after the step of forming the conductive path, the conductive path extends from a side surface of the anode emitter away from the buffer zone to the inside of the predetermined area.

[0016] Through the present application, a power semiconductor device is proposed, including a central area and a peripheral area located outside the central area. The central area also has a pseudo-cellular structure. By embedding a conductive channel in a predetermined area of ​​the buffer zone in the pseudo-cellular structure to change the local conductivity, the breakdown point can be guided to occur precisely in the predetermined area to form a breakdown area, so that at a certain high voltage, the electric field can reach the predetermined area with the conductive channel in advance, so that the area is broken down. The introduction of the above-mentioned conductive channel not only overcomes the limitations of traditional methods, such as poor temperature stability and uncontrollable breakdown point position, but also can achieve precise control of overvoltage breakdown points without significantly increasing manufacturing complexity, thereby improving the reliability of the device under extreme conditions. In addition, the present application also locally optimizes the electric field distribution by introducing the above-mentioned conductive channel, thereby avoiding the need for complex design of each doping area in the entire buffer zone structure and dependence on process control, and achieving a more consistent breakdown voltage. Therefore, the cellular structure provided in the present application can achieve overvoltage protection with high breakdown voltage consistency and controllable breakdown point, so as to overcome the limitations of traditional edge passivation and BOD structure, especially in high voltage and high power applications, and solve the problem of poor breakdown voltage consistency caused by the overvoltage protection technology applied to power semiconductor devices in the related technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 A schematic diagram of a partial cross-sectional structure of a power semiconductor device according to an embodiment of the present application is shown;

[0019] Figure 2 Shows Figure 1 A schematic cross-sectional structure diagram of a pseudo-cell structure in a power semiconductor device shown in FIG.

[0020] Figure 3 The cross-sectional structure diagram of a buffer region with an embedded conductive channel in a power semiconductor device according to an embodiment of the present application is shown;

[0021] Figure 4 The cross-sectional structure diagram of a buffer region with an embedded conductive channel in another power semiconductor device according to an embodiment of the present application is shown;

[0022] Figure 5 is shown Figure 1 The cross-sectional structure diagram of the cell structure in the power semiconductor device shown in

[0023] Figure 6 The flow structure diagram of a method for manufacturing a power semiconductor device according to an embodiment of the present application is shown.

[0024] Among them, the above-mentioned drawings include the following reference numerals:

[0025] 1. Pseudo-cell structure; 2. Cell structure; 10. First electrode structure; 110. Anode; 120. Anode emitter; 20. Buffer region; 201. Predetermined region; 210. Fourth doping region; 220. Fifth doping region; 30. Base region; 310. First doping region; 320. Second doping region; 40. Second electrode structure; 410. Cathode emitter; 420. Cathode; 50. Third electrode; 60. Conductive channel; 70. Insulating layer. Detailed implementation manners

[0026] It should be noted that the following detailed descriptions are all exemplary and are intended to provide further descriptions of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs.

[0027] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary implementation manners according to the present application. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0028] It should be noted that in the description, claims and drawings of the present invention, terms such as "first", "second", etc. are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances for the embodiments of the present invention described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0029] It should be understood that when an element (such as a layer, film, region, or substrate) is described as "on" another element, the element can be directly on the other element, or there can also be an intermediate element. Moreover, in the description and claims, when an element is described as "connected" to another element, the element can be "directly connected" to the other element, or "connected" to the other element through a third element.

[0030] As introduced in the background art, traditional overvoltage protection mechanisms, such as edge passivation technology and the Breakdown Over Diode (BOD) structure for overvoltage protection, although improve the overvoltage resistance of devices to a certain extent, they have obvious limitations in terms of temperature stability, process complexity, and breakdown voltage consistency. To solve the problem of poor breakdown voltage consistency in the overvoltage protection technology applied to power semiconductor devices in the prior art, embodiments of the present application provide a power semiconductor device and a method for manufacturing the same.

[0031] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention.

[0032] According to an embodiment of the present application, a power semiconductor device is provided, as Figures 1 to 5 shown, wherein, Figure 1 shows a partial cross-sectional structure of a power semiconductor device, Figure 2 shows Figure 1 the cross-sectional structure of the pseudo-cell structure 1 in Figure 3 and Figure 4 respectively show Figure 2 the cross-sectional structures of the buffer zone 20 in Figure 5 shows Figure 1The cross-sectional structure of the cell structure 2 in [description]. The above-mentioned power semiconductor device includes a central region A and a peripheral region B located outside the central region A. Both the central region A and the peripheral region B include a plurality of cell structures 2. The central region A further includes a dummy cell structure 1. The cell structure 2 and the dummy cell structure 1 both include a buffer region 20 and a base region 30 arranged in sequence along the first direction a. The dummy cell structure 1 further includes a conductive channel 60. In the dummy cell structure 1, at least a part of the conductive channel 60 is embedded in a predetermined region 201 of the buffer region 20. The predetermined region 201 has a second surface located in the first surface, and the predetermined region 201 is spaced from the contact surface. The part of the conductive channel 60 embedded in the predetermined region 201 extends from the second surface into the interior of the predetermined region 201. The predetermined region 201 is used to form a breakdown region when the power semiconductor device withstands the breakdown voltage.

[0033] In the above-mentioned embodiments of the present application, by embedding the conductive channel 60 in the predetermined region of the buffer region 20 in the dummy cell structure 1, the local conductivity can be changed, and the breakdown point can be precisely guided to occur in the predetermined region to form a breakdown region. Thus, at a certain high voltage, the electric field can reach the predetermined region with the conductive channel in advance, causing this region to be broken down. The introduction of the above-mentioned conductive channel 60 not only overcomes the limitations of traditional methods, such as poor temperature stability and uncontrollable breakdown point position, but also can achieve precise control of the overvoltage breakdown point without significantly increasing the manufacturing complexity, improving the reliability of the device under extreme conditions. In addition, the present application also locally optimizes the electric field distribution by introducing the above-mentioned conductive channel 60, thereby avoiding the need for complex design of each doping region in the entire buffer region 20 structure and the dependence on process control, and achieving a more consistent breakdown voltage. Therefore, the present application can achieve overvoltage protection with high breakdown voltage consistency and controllable breakdown point, overcoming the limitations of traditional edge passivation and BOD structures, especially in high-voltage and high-power applications, and solving the problem of poor breakdown voltage consistency in the overvoltage protection technology applied to power semiconductor devices in the related art.

[0034] Furthermore, in the mass production of power semiconductor devices, there are differences in the breakdown voltages of each device within a certain range. Although traditional edge passivation treatment and BOD structures can improve the breakdown voltage to a certain extent, they are affected by process stability and temperature fluctuations and it is difficult to achieve ideal breakdown voltage consistency, especially under extreme operating conditions. However, in the embodiments of the present application, by embedding a conductive channel 60 (such as a nanowire) in a predetermined area of the buffer layer 20, precise control of local conductivity can be achieved, thereby guiding the breakdown point to occur precisely in this predetermined area. This design can significantly improve the consistency of the breakdown voltage because it not only reduces the voltage differences caused by process and material uncertainties, but also ensures that the breakdown voltage is more uniform and controllable among all devices through local optimization. Even under temperature changes and high voltage and large current applications, it can maintain good performance and reliability, thus solving the limitations of traditional technologies in terms of breakdown voltage consistency.

[0035] In some alternative embodiments, such as Figures 1 to 5 shown, the conductive channel 60 embedded in the buffer layer 20 includes nanowires. Nanowires have an extremely high aspect ratio and excellent electrical properties, and can significantly improve the conductivity of power semiconductor devices. For example, carbon nanotubes are widely regarded as ideal conductive channel materials due to their unique structure and extremely low resistivity. Silicon nanowires and silicon-germanium nanowires can effectively improve the conductivity of devices without damaging the overall structure of the device due to their good compatibility with silicon-based semiconductor materials.

[0036] Furthermore, temperature stability is a key performance indicator in power semiconductor devices, especially in working environments with high temperatures or large temperature fluctuations. For traditional power semiconductor devices, such as IGBTs, MOSFETs, and thyristor devices such as GTOs and IGCTs, their breakdown voltages or avalanche breakdown voltages may be affected by temperature changes, resulting in performance degradation or instability. This is because temperature changes can affect the carrier concentration, mobility, and recombination rate of materials, thereby affecting the conductivity and breakdown characteristics of the device. In the embodiments of the present application, by embedding a conductive channel 60 in a predetermined area of the buffer layer 20, a region with highly controllable conductivity can be created to increase the local conductivity. Thus, by precisely controlling the type, size, distribution, and density of the nanowires, a conductivity distribution map that is relatively insensitive to temperature changes can be formed in the predetermined area of the buffer layer 20. This is because nanostructures may have different thermoelectric properties from bulk materials, such as a smaller coefficient of thermal expansion, different temperature-dependent carrier concentrations or mobilities, and possible quantum confinement effects.

[0037] For example, certain metal nanoparticles have relatively stable electrical conductivity within a specific temperature range, which can reduce the sensitivity of the overall device's electrical conductivity to temperature; the band structure and carrier behavior of semiconductor nanowires may be less affected by temperature than bulk semiconductor materials, especially the quantum effects commonly found in low-dimensional structures can provide an additional temperature stabilization mechanism.

[0038] Therefore, when the electrical conductivity of the predetermined region 201 in the buffer 20 is relatively stable with respect to temperature changes, the electric field distribution and breakdown characteristics of the overall device will also remain stable with temperature variations. This means that even when the ambient temperature rises or falls, the breakdown voltage of the device can be maintained at a relatively constant level, thereby improving the performance reliability and stability of the power semiconductor device under different temperature conditions. This improvement in temperature stability is crucial for the operation of power semiconductor devices in extreme environments, enabling them to remain efficient and safe within a wider temperature range.

[0039] In some alternative embodiments, the above-mentioned nanowires are selected from any one or more of carbon nanotubes, silicon nanowires, silicon-germanium nanowires, carbosilicide nanowires, and metallic nanowires.

[0040] Specifically, the selection of carbon nanotubes, silicon nanowires, silicon-germanium nanowires, carbosilicide nanowires, and metallic nanowires as the materials for the conductive channels is based on their excellent electrical properties and compatibility with semiconductor devices. Due to its unique structure and high conductivity, carbon nanotubes can effectively reduce the energy loss during current transmission and improve the efficiency of the device. Silicon nanowires and silicon-germanium nanowires, due to their compatibility with silicon-based materials, can optimize the electrical properties of the device without changing the basic structure of the device. Carbosilicide nanowires and metallic nanowires, due to their high conductivity and stability, can maintain the performance stability of the device under extreme conditions. The use of these materials not only solves the problem of performance degradation of traditional power semiconductor devices in high-voltage and high-current applications but also improves the reliability of the device, enabling it to maintain a stable working state in harsh environments.

[0041] It should be noted that the material selection for the conductive channels also includes but is not limited to other types of highly conductive nanomaterials. The use of these materials should be based on the performance requirements and application environment of the device, and in the case of multiple conductive channels, their distribution can be reasonably set according to actual needs.

[0042] In the embodiments of the present application, graphene and / or two-dimensional materials (such as transition metal dichalcogenides, TMDs) can also be used as the material of the conductive channel. The two-dimensional structure of the above materials has high electron mobility and excellent thermal conductivity, so that compared with traditional nanowires such as silicon nanowires or carbon nanotubes, the electrical conductivity and thermal stability of the device can be improved.

[0043] Specifically, the material of the conductive channel in the embodiments of the present application can be graphene, which can significantly reduce the conductance loss in the device and improve the efficiency of the device; moreover, graphene also has an extremely high thermal conductivity (theoretically up to 5300 W / mK), which enables it to effectively conduct heat out of the device and avoid local overheating, thereby enhancing the thermal stability of the device; in addition, the chemical stability of graphene also enables it to maintain its electrical performance without attenuation under harsh conditions.

[0044] Specifically, the material of the conductive channel in the embodiments of the present application can also be TMDs. TMDs (such as MoS 2 2, WS 2 2) have semiconductor properties, and their energy band structure can be adjusted to obtain better electrical properties, so that they can exhibit a relatively high carrier mobility under specific conditions; moreover, TMDs materials also have relatively high thermal stability and can maintain structural integrity under high-temperature conditions.

[0045] In some alternative embodiments, metal nanoparticles and / or semiconductor nanoparticles, such as gold, silver, or indium particles, are also embedded in a predetermined area of the buffer layer. By embedding the above nanoparticles, the enhancement of local conductivity can be achieved, and at the same time, the high thermal conductivity of the nanoparticles is used to improve the thermal management of the device.

[0046] In some alternative embodiments, nanowires arranged in an array are used, such as a carbon nanotube array. The above nanowires arranged in an array can effectively adjust the conductivity of the buffer layer, and at the same time improve the thermal stability of the device by increasing the heat dissipation path.

[0047] Exemplarily, as Figure 2 shown, in the first direction a, the thickness of the above buffer layer 20 is 20 to 50 μm, the above conductive channel 60 is a nanowire with a height in the range of 10 to 35 μm and a diameter in the range of 3 to 50 μm, and the above nanowires are multiple and arranged in an array along the second direction and the third direction. The arrangement mode of the nanowires in the above predetermined area 201, as well as the process dimensions of the above buffer layer and nanowires, are not limited to the above range and can be adjusted in combination with the nanowire process and the deep trench etching process. The embodiments of the present application do not make specific limitations.

[0048] In some alternative embodiments, such asFigure 2 As shown, the above-mentioned base region 30 includes a first doped region 310 and a second doped region 320 that are sequentially distributed along the first direction a, and the first doped region 310 and the second doped region 320 have different doping types. When the power semiconductor device in the embodiment of the present application withstands the breakdown voltage, an electric field is generated in the first doped region 310 and the second doped region 320.

[0049] In the above optional embodiment, as Figure 2 shown, the first doped region 310 and the second doped region 320 have different doping types, that is, the first doped region 310 and the second doped region 320 are P-type doping and N-type doping respectively. Specifically, when the first doped region 310 is a P-type doped region, the second doped region 320 is an N-type doped region, and when the first doped region 310 is an N-type doped region, the second doped region 320 is a P-type doped region.

[0050] In the above optional embodiment, as Figure 2 shown, the buffer region 20 has the same doping type as the first doped region 310. At this time, the buffer region 20 can be a third doped region. As Figure 2 and Figure 3 shown, that is, the buffer region 20 is a region with a single doping concentration and the same doping type as the first doped region 310. When the power semiconductor device in the embodiment of the present application withstands the breakdown voltage, the third doped region will withstand the electric field generated in the first doped region and the second doped region, and breakdown will occur in the predetermined region 201 of the third doped region.

[0051] In some other optional embodiments, as Figure 4 shown, the above-mentioned buffer region 20 includes a fourth doped region 210 and a fifth doped region 220 that are distributed along the second direction b, the predetermined region 201 is located in the fourth doped region 210, the doping concentration of the fourth doped region 210 is less than the doping concentration of the fifth doped region 220, and the second direction b is perpendicular to Figure 2 the first direction a shown in

[0052] In the above optional embodiment, the buffer region 20 can be divided into multiple regions with different doping concentrations and the same doping type as the first doped region 310. Taking the buffer region 20 having the fourth doped region 210 and the fifth doped region 220 as an example, when the power semiconductor device in the embodiment of the present application withstands the breakdown voltage, since the doping concentration of the fourth doped region 210 is less than the doping concentration of the fifth doped region 220, the fourth doped region 210 will withstand the electric field generated in the first doped region 310 and the second doped region 320, and breakdown will occur in the predetermined region 201 of the fourth doped region 210.

[0053] In some optional embodiments, as Figure 2 andFigure 4 As shown, the surface of the buffer layer 20 facing away from the base region 30 is the third surface. The orthographic projection of the fourth doped region 210 on this third surface is the first projection, and the orthographic projection of the fifth doped region 220 on this third surface is the second projection. The area of the first projection is smaller than the area of the second projection.

[0054] Adopting the above optional implementation manner can optimize the electric field distribution inside the device and improve the breakdown voltage of the device. Specifically, if the area of the first projection is smaller than the area of the second projection, then when the device is operating, the current will pass more concentratedly through the predetermined region 201 in the fourth doped region 210, reducing the energy loss during the current transmission process and improving the efficiency of the device. At the same time, the control of the size of the fourth doped region 210 can also optimize the electrical performance of the device and improve its stability under high voltage and large current conditions. Therefore, the above optional implementation manner not only solves the problem of performance degradation of traditional power semiconductor devices in high-voltage and large-current applications, but also improves the reliability of the device, enabling it to maintain a stable operating state in harsh environments.

[0055] The above power semiconductor device can be an integrated gate-commutated thyristor (IGCT), or a gate turn-off thyristor (GTO), an insulated gate bipolar transistor (IGBT), etc. The embodiments of the present application do not make specific limitations.

[0056] Taking the power semiconductor device in the embodiments of the present application as an integrated gate-commutated thyristor as an example, as Figures 1 to 3 and Figure 5 shown, the integrated gate-commutated thyristor further includes a first electrode structure 10, a second electrode structure 40, and a third electrode 50, where: the first electrode structure 10 is located on the side of the buffer layer 20 facing away from the base region 30, and the first electrode structure 10 includes an anode 110 and an anode emitter 120 sequentially distributed along the first direction a; the second electrode structure 40 and the third electrode 50 are located on the same side of the base region 30. In the first direction a, the base region 30 includes a first doped region 310 and a second doped region 320 sequentially distributed. The second electrode structure 40 includes a cathode 420 and a cathode emitter 410. A part of the cathode emitter 410 is located in the second doped region 320. The third electrode 50 in the cell structure 2 is a gate in contact with the second doped region 320; the conductive channel 60 extends from the surface of the anode emitter 120 facing away from the buffer layer 20 to the inside of the predetermined region 201; the first doped region 310 and the cathode emitter 410 have a first doping type, and the second doped region 320 and the anode emitter 120 have a second doping type.

[0057] Specifically, in an integrated gate-commutated thyristor (IGCT), the settings of the first doped region 310 and the second doped region 320, as well as the distributions of the first electrode structure 10 and the second electrode structure 40, are based on the specific operating principle and performance requirements of the device. Among them, the base region 30 is the core of the IGCT, which is composed of the first doped region 310 and the second doped region arranged in sequence. The first doped region 310 has a first doping type (such as N-type doping), which provides a path for the transmission of electrons when the IGCT is turned on. The second doped region 320 has a second doping type (such as P-type doping), adjacent to the first doped region 310, which provides a path for the transmission of holes when the IGCT is turned on; the anode 110 and the cathode 420 serve as the ports for the forward and reverse flow of current respectively, while the anode emitter 120 and the cathode emitter 410 are used to enhance current control. The gate, as a control element, realizes the fast turn-on and turn-off control of the IGCT through contact with the second doped region 320.

[0058] For example, the first doped region 310 and the cathode emitter 410 are N-type doped, while the second doped region 320 and the anode emitter 120 are P-type doped, or the first doped region 310 and the cathode emitter 410 are P-type doped, while the second doped region 320 and the anode emitter 120 are N-type doped. The P-type dopant may include boron, and the N-type dopant may include phosphorus and / or arsenic.

[0059] In some alternative embodiments, as Figure 5 shown, the cell structure 2 further includes a plurality of insulating layers 70. The insulating layers 70 are located between the third electrode 50 and the second electrode structure 40 for insulating the third electrode 50 and the second electrode structure 40. Taking the power semiconductor device in the embodiment of the present application as an IGCT, the insulating layer 70 is located between the gate and the second electrode structure 40 composed of the cathode emitter 410 and the cathode 420. The insulating layer 70 contacts the gate and the cathode 420 and covers the sidewall of the cathode emitter 410. The material of the insulating layer 70 may be insulating materials such as silicon dioxide, silicon oxide, and silicon oxynitride, which are not specifically limited in the embodiment of the present application.

[0060] According to the embodiment of the present application, a method for manufacturing a power semiconductor device is also provided for the power semiconductor device.

[0061] Figure 6 is a flowchart of a method for manufacturing a cell structure of a power semiconductor device tube according to the embodiment of the present application. As Figure 6 shown, the method includes the following steps:

[0062] Step S201, providing a first substrate, in which a buffer region and a base region are formed in sequence along a first direction. The buffer region has a contact surface with the base region and a first surface opposite to the contact surface along the first direction;

[0063] Step S202: Embed at least a part of a conductive channel in a predetermined region of the buffer zone, and obtain a power semiconductor device having a pseudo-cell structure. The predetermined region has a second surface located in the first surface, and the predetermined region is spaced from the contact surface. The part of the conductive channel embedded in the predetermined region extends from the second surface into the interior of the predetermined region. The power semiconductor device includes a central region and a peripheral region located outside the central region, and the central region has a pseudo-cell structure.

[0064] In the above embodiments of the present application, by embedding a conductive channel in a predetermined region of the buffer zone in the pseudo-cell structure, the local conductivity can be changed, and the breakdown point can be accurately guided to occur in the predetermined region to form a breakdown region. Thus, at a certain high voltage, the electric field can reach the predetermined region with the conductive channel in advance, causing this region to be broken down. The introduction of the above conductive channel not only overcomes the limitations of traditional methods, such as poor temperature stability and uncontrollable breakdown point position, but also can achieve precise control of the overvoltage breakdown point without significantly increasing the manufacturing complexity, improving the reliability of the device under extreme conditions. In addition, the present application also optimizes the electric field distribution locally by introducing the above conductive channel, thereby avoiding the need for complex design of each doping region in the entire buffer zone structure and the dependence on process control, and achieving a more consistent breakdown voltage. Therefore, the cell structure provided in the present application can achieve overvoltage protection with high breakdown voltage consistency and controllable breakdown point, overcoming the limitations of traditional edge passivation and BOD structures, especially in high-voltage and high-power applications, and solving the problem of poor breakdown voltage consistency in the overvoltage protection technology applied to power semiconductor devices in related technologies.

[0065] Exemplary embodiments of the method for manufacturing a power semiconductor device according to the present application will be described in more detail below. However, these exemplary embodiments can be implemented in many different forms and should not be construed as being limited only to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of the present application is thorough and complete, and the concept of these exemplary embodiments is fully conveyed to those of ordinary skill in the art.

[0066] First, perform step S201: Provide a first substrate, in which a buffer zone and a base region are formed in sequence along a first direction. The buffer zone has a contact surface with the base region and a first surface opposite to the contact surface along the first direction.

[0067] The above first substrate is obtained by performing ion implantation in a substrate to form a buffer zone and a base region. The material of the substrate can be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide, and aluminum gallium nitride, and the substrate can be a doped substrate.

[0068] After providing the first substrate, step S202 is performed: embedding at least a part of a conductive channel in a predetermined area of the buffer, and obtaining a power semiconductor device having a pseudo-cell structure. The predetermined area has a second surface located in the first surface, and the predetermined area is spaced from the contact surface. The part of the conductive channel embedded in the predetermined area extends from the second surface into the interior of the predetermined area. The power semiconductor device includes a central area and a peripheral area located outside the central area, and the central area has a pseudo-cell structure.

[0069] In some alternative embodiments, the step of embedding the conductive channel in the predetermined area of the buffer includes: forming at least one hole in the predetermined area, the hole extending from the second surface into the interior of the predetermined area; filling the hole with a conductive material and curing it to form the conductive channel.

[0070] Exemplarily, embedding the above conductive channel may include the following steps:

[0071] Electrochemical treatment: In a specific electrolyte solution, perform electrochemical treatment on the predetermined area of the buffer. The electrochemical treatment can form nano-scale holes or trenches to create space for the embedding of nano-materials;

[0072] Nano-material embedding: Introduce a solution containing the target nano-material (such as a solution containing Si NWs) into the holes or trenches in the above-mentioned predetermined area, and through electrochemical deposition or penetration, embed the nano-material into the predetermined area;

[0073] Curing and cleaning: After the embedding process is completed, perform cleaning and curing to remove the excess material and ensure that the embedded nano-wires or particles are stably fixed in the predetermined area. The above curing method can be reasonably selected according to the prior art, such as annealing or standing.

[0074] It should be noted that the embodiments of the present application are not limited to the above embodiments of embedding the conductive channel in the buffer. In other embodiments, nanoimprint technology, laser-induced doping technology, and embedding technology based on etching and deposition can also be used.

[0075] Exemplarily, embedding the above conductive channel using nanoimprint technology includes the following steps:

[0076] Use electron beam lithography or nanoimprint lithography technology to prepare a mold containing a nano-wire or particle pattern, and the concave-convex structure on the surface of the mold corresponds one-to-one to the target nano-structure;

[0077] Set a mask layer on the surface of the buffer facing away from the base region, place the mold above the mask layer, and apply appropriate pressure and temperature to transfer the nano-structure on the mold into the mask layer to obtain a patterned mask layer;

[0078] A barrier layer is provided on the patterned mask layer to expose a predetermined area in the patterned mask layer, and the buffer layer is etched through the exposed patterned mask layer to form grooves corresponding one by one to the target nanostructures in a predetermined area of the buffer zone;

[0079] Using chemical vapor deposition (CVD) or atomic layer deposition (ALD) process, a solution of the target nanomaterial (such as a solution containing Si NWs) is filled into the grooves and cured to form nanowires. The above curing method can be reasonably selected according to the existing technology, such as annealing or standing still.

[0080] In another example, embedding the above conductive channel using laser-induced doping technology includes the following steps:

[0081] Laser pretreatment: Use high-energy laser pulses to process a predetermined area of the buffer zone. The laser pulses can be precisely focused on the predetermined area, causing the surface of the local material to melt, creating conditions for the subsequent embedding of dopants;

[0082] Dopant embedding: After laser pretreatment, immediately spray or deposit a dopant containing nanoparticles or nanowires (such as doped Si NWs) onto the above predetermined area. Since the surface material of the predetermined area is in a molten state, the nanomaterials can penetrate deep into the material to form an embedded structure;

[0083] Annealing treatment: Through heat treatment processes such as annealing or rapid thermal annealing (RTA), the doped area is recrystallized to ensure that the nanowires or particles are firmly embedded and evenly distributed.

[0084] After embedding the conductive channel in the buffer zone, step S203 is performed: A first electrode structure is formed on one side of the second substrate close to the buffer zone, and a second electrode structure and a third electrode are formed on one side of the second substrate close to the base region.

[0085] Specifically, taking a power semiconductor device as an integrated gate-commutated thyristor (IGCT) as an example, the first electrode structure includes an anode and an anode emitter, the second electrode structure includes a cathode and a cathode emitter, a part of the cathode emitter is located in the second doping region, and the third electrode is a gate in contact with the second doping region. The material types of the above anode, anode emitter, cathode, cathode emitter, and gate can be reasonably selected according to the existing technology, and the embodiments of the present application do not make specific limitations.

[0086] The above power semiconductor device can be an integrated gate-commutated thyristor (IGCT), or a gate turn-off thyristor (GTO), an insulated gate bipolar transistor (IGBT), etc. The embodiments of the present application do not make specific limitations.

[0087] Taking the integrated gate-commutated thyristor in the embodiment of the present application as an example of the power semiconductor device, the base region includes a first doping region and a second doping region sequentially distributed along a first direction. The first substrate further includes an anode emitter and a cathode emitter. The anode emitter is located on one side of the base region close to the first doping region, a part of the cathode emitter is located on one side of the base region close to the second doping region, and another part of the cathode emitter is located in the second doping region.

[0088] At this time, the step of forming the hole in step S202 may include: forming a hole penetrating from the surface of the anode emitter facing away from the buffer region to a predetermined region. After the step of forming the conductive channel, the conductive channel extends from the surface of the anode emitter facing away from the buffer region to the inside of the predetermined region.

[0089] After embedding the conductive channel in the predetermined region of the buffer region, the above step S203 may include: forming an anode on the side of the anode emitter facing away from the buffer region, forming a cathode on the side of the cathode emitter facing away from the base region, and forming a gate on the second doping region. The types and preparation processes of the above anode, cathode and gate can be reasonably selected according to actual needs, and the embodiments of the present application do not make specific limitations.

[0090] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, commodity or device including the element.

[0091] The above are only the embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. A power semiconductor device, characterized in that: The invention comprises a central region and a peripheral region located outside the central region, wherein the central region and the peripheral region both comprise a plurality of cellular structures, the central region further comprises a pseudo cellular structure, the cellular structure and the pseudo cellular structure both comprise a buffer region and a base region sequentially arranged along a first direction, the pseudo cellular structure further comprises a conductive channel, and in the pseudo cellular structure: The buffer region has a contact surface with the base region and a first surface opposite to the contact surface along the first direction; At least part of the conductive path is embedded in a predetermined area in the buffer zone, the predetermined area has a second surface located in the first surface, and the predetermined area is spaced from the contact surface, and the part of the conductive path embedded in the predetermined area extends from the second surface to the inside of the predetermined area, and the predetermined area is used to form a breakdown area when the power semiconductor device is subjected to a breakdown voltage.

2. The power semiconductor device according to claim 1, characterized in that: The conductive pathway comprises nanowires.

3. The power semiconductor device according to claim 2, characterized in that: The nanowires are selected from any one or more of carbon nanotubes, silicon nanowires, silicon germanium nanowires, silicon carbide nanowires and metallic nanowires.

4. The power semiconductor device according to any one of claims 1 to 3, characterized in that: The base region includes a first doping region and a second doping region sequentially distributed along the first direction, and the first doping region and the second doping region have different doping types.

5. The power semiconductor device according to claim 4, characterized in that: The buffer region and the first doping region have the same doping type, wherein: The buffer region is a third doping region, or The buffer zone includes a fourth doping region and a fifth doping region distributed along a second direction, the predetermined area is located in the fourth doping region, the doping concentration of the fourth doping region is less than the doping concentration of the fifth doping region, and the second direction is perpendicular to the first direction.

6. The power semiconductor device according to claim 5, characterized in that: The buffer zone includes a surface along the fourth doping zone and the fifth doping zone, a surface of the buffer zone facing away from the base zone is a third surface, an orthographic projection of the fourth doping zone on the third surface is a first projection, an orthographic projection of the fifth doping zone on the third surface is a second projection, and an area of ​​the first projection is smaller than an area of ​​the second projection.

7. The power semiconductor device according to claim 4, characterized in that: The power semiconductor device is an integrated gate-commutated thyristor, and the integrated gate-commutated thyristor further comprises a first electrode structure, a second electrode structure and a third electrode, wherein: The first electrode structure is located at a side of the buffer region away from the base region, and the first electrode structure includes an anode and an anode emitter sequentially distributed along the first direction; The second electrode structure and the third electrode are located on the same side of the base region, the second electrode structure comprises a cathode metal and a cathode emitter sequentially distributed along the first direction, a portion of the cathode emitter is located in the second doping region, and the third electrode is a gate in contact with the second doping region; The conductive channel extends from a surface of the anode emitter facing away from the buffer zone to the inside of the predetermined area; The first doping region and the cathode emitter have a first doping type, and the second doping region and the anode emitter have a second doping type.

8. A method for preparing a power semiconductor device, characterized in that: For preparing a power semiconductor device according to any one of claims 1 to 7, the preparation method comprises the following steps: Providing a first substrate, in which a buffer region and a base region are sequentially distributed along a first direction, the buffer region having a contact surface with the base region and a first surface opposite to the contact surface along the first direction; At least a portion of the conductive channel is embedded in a predetermined area of ​​the buffer zone to obtain a power semiconductor device with a pseudo-cellular structure, wherein the predetermined area has a second surface located in the first surface, and the predetermined area is spaced from the contact surface, and a portion of the conductive channel embedded in the predetermined area extends from the second surface to the inside of the predetermined area, and the power semiconductor device includes a central area and a peripheral area located outside the central area, and the pseudo-cellular structure is provided in the central area.

9. The preparation method according to claim 8, characterized in that: The step of embedding at least part of the conductive path in the predetermined area comprises: forming at least one hole in the predetermined area, wherein the hole extends from the second surface to the inside of the predetermined area; The holes are filled with conductive material and cured to form the conductive paths.

10. The preparation method according to claim 9, characterized in that: The power semiconductor device is an integrated gate-commutated thyristor, the base region includes a first doping region and a second doping region sequentially distributed along the first direction, the first substrate also includes an anode emitter and a cathode emitter, the anode emitter is located on a side of the base region close to the first doping region, a portion of the cathode emitter is located on a side of the base region close to the second doping region, and another portion of the cathode emitter is located in the second doping region, The step of forming the hole comprises: forming the hole penetrating from a surface of the anode emitter away from the buffer zone to the predetermined area; After the step of forming the conductive channel, the conductive channel extends from a surface of the anode emitter facing away from the buffer zone to the inside of the predetermined region.

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