A solar cell, its fabrication method, and its assembly

Abstract

This application discloses a solar cell, its fabrication method, and a cell assembly. The solar cell includes a silicon substrate with opposing first and second surfaces. A first doped layer and a first electrode are sequentially stacked on the first surface. The first doped layer includes adjacent first crystalline doped regions and first amorphous doped regions. A second doped layer and a second electrode are sequentially stacked on the second surface of the silicon substrate. The doping types of the first and second doped layers are opposite. The projection of the first electrode onto the silicon substrate overlaps with the projection of the first crystalline doped region onto the silicon substrate, and the projected area of ​​the first electrode onto the silicon substrate is smaller than the projected area of ​​the first crystalline doped region. This solar cell can reduce contact resistance while avoiding leakage.

Description

[0001] This application claims priority to Chinese Patent Application No. 202410190935.4, filed on February 20, 2024, entitled "A Solar Cell and its Preparation Method and Battery Component", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the photovoltaic field, specifically to a solar cell, its preparation method, and a cell assembly. Background Technology

[0003] The front-back contact crystalline silicon-amorphous silicon heterojunction (SHJ) solar cell utilizes intrinsic amorphous silicon passivation, resulting in excellent passivation performance. The commonly used 130μm n-type silicon wafer can achieve a maximum Voc of 751mV, significantly higher than TOPCon. However, the contact resistance of the crystalline silicon-amorphous silicon structure is higher than that of tunneling silicon oxide passivated contact structures (TOPCon) and high-temperature diffused homojunctions, making it a major factor limiting the efficiency of SHJ cells. The contact resistance mentioned above includes the contact resistance on both sides of the SHJ, where the N-side is the c-Si / ia-Si:H / na-Si:H / TCO contact (N-segment contact), and the P-side is the c-Si / ia-Si:H / pa-Si:H / TCO contact (P-end contact). To improve these contact characteristics, the commonly used process is PECVD deposition, depositing doped microcrystalline / nanocrystalline films instead of conventional doped amorphous silicon. However, PECVD deposition of microcrystalline / nanocrystalline films is slow and requires high equipment investment, necessitating other methods to achieve film crystallization. On the other hand, when amorphous silicon films are crystallized, their conductivity increases by an order of magnitude (from 10E-4 to 1E10), but SHJ cells exhibit significant edge leakage. Summary of the Invention

[0004] To address the aforementioned problems, this application provides a solar cell that can reduce contact resistance while preventing leakage.

[0005] This application provides a solar cell, including a silicon substrate having a first surface and a second surface opposite to each other. A first doped layer and a first electrode are sequentially stacked on the first surface. The first doped layer includes a first crystalline doped region and a first amorphous doped region. A second doped layer and a second electrode are sequentially stacked on the second surface of the silicon substrate. The doping types of the first doped layer and the second doped layer are opposite.

[0006] The projection of the first electrode on the silicon substrate overlaps with the projection of the first crystal doped region on the silicon substrate, and the projected area of ​​the first electrode on the silicon substrate is smaller than the projected area of ​​the first crystal doped region on the silicon substrate.

[0007] Furthermore, the second doped layer includes an adjacent first region and a second region, the crystallinity of the second region is greater than that of the first region; the projection of the second electrode on the silicon substrate overlaps with the projection of the second region on the silicon substrate, and the projection area of ​​the second electrode on the silicon substrate is smaller than the projection area of ​​the second region on the silicon substrate.

[0008] Furthermore, the first region is a second amorphous doped region, and the second region is a second crystalline doped region.

[0009] Furthermore, the second doped layer comprises doped polycrystalline silicon.

[0010] Furthermore, the solar cell also includes a second passivation layer located on the side of the second doped layer near the silicon substrate; and / or,

[0011] The solar cell also includes a dielectric layer that covers the side of the second doped layer away from the silicon substrate, and the second electrode passes through the dielectric layer and is electrically connected to the second doped layer.

[0012] Furthermore, within the first crystal-doped region, at least the portion on the side furthest from the silicon substrate has crystals; and / or

[0013] Within the second crystal doped region, at least the portion on the side furthest from the silicon substrate has crystals.

[0014] Further, the total width of the first crystal doped region is 0% to 100% of the width of the first doped layer, excluding 0% and 100%; and / or

[0015] The total width of the second crystal doped region is 0% to 100% of the width of the second doped layer, excluding 0% and 100%.

[0016] Furthermore, in the width direction, the first amorphous doped region includes a first amorphous doped region A located at both ends of the first doped layer, the width of the first amorphous doped region A being 0.05–6 mm, preferably 0.5–1 mm; and / or

[0017] In the width direction, the second amorphous doped region includes a second amorphous doped region A located at both ends of the second doped layer, and the width of the second amorphous doped region A is 0.05 to 6 mm, preferably 0.5 to 1 mm.

[0018] Furthermore, the first crystal doped region is a first microcrystalline doped region, a first nanocrystalline doped region, or a first polycrystalline doped region.

[0019] Further, the first amorphous doped region is selected from one of a first amorphous silicon doped region, a first amorphous silicon carbide doped region, or a first amorphous silicon oxide doped region; and / or

[0020] The first crystal doped region is selected from one of the first crystal silicon doped region, the first crystal silicon carbide doped region, or the first crystal silicon oxide doped region.

[0021] Furthermore, the crystallinity of the first crystal doped region is 0.01-100%; and / or

[0022] The crystallinity of the second crystal doped region is 0.01-100%.

[0023] A method for preparing a solar cell includes the following steps:

[0024] A silicon substrate is provided, the silicon substrate having opposing first and second surfaces;

[0025] A first doped layer is formed on one side of the first surface, wherein the first doped layer is a first amorphous doped layer;

[0026] The first doped layer is subjected to crystallization treatment, so that a portion of the first amorphous doped layer is transformed into a first crystalline doped region, and the portion that does not undergo crystallization is the first amorphous doped region.

[0027] A first electrode is formed on the side of the first crystal doped region away from the silicon substrate;

[0028] A second doped layer is formed on one side of the second surface, wherein the doping type of the first doped layer is opposite to that of the second doped layer;

[0029] A second electrode is formed on the side of the second doped layer opposite to the silicon substrate;

[0030] The projection of the first electrode on the silicon substrate overlaps with the projection of the first crystal doped region on the silicon substrate, and the projected area of ​​the first electrode on the silicon substrate is smaller than the projected area of ​​the first crystal doped region on the silicon substrate.

[0031] Furthermore, the second doped layer is a polycrystalline silicon doped layer.

[0032] Furthermore, the second doped layer is a second amorphous doped layer; the method for fabricating the solar cell further includes the following steps:

[0033] The second doped layer is subjected to crystallization treatment, so that a part of the second doped layer is transformed into a second crystalline doped region, and the part that does not undergo crystallization is a second amorphous doped region;

[0034] The projection of the second electrode on the silicon substrate overlaps with the projection of the second crystal doped region on the silicon substrate, and the projection area of ​​the second electrode on the silicon substrate is smaller than the projection area of ​​the second crystal doped region on the silicon substrate.

[0035] Furthermore, after crystallizing the first doped layer, before forming the first electrode on the side of the first crystal doped region away from the silicon substrate, a first conductive layer is also formed on the side of the first doped layer away from the silicon substrate.

[0036] Furthermore, the crystallization process of the first doped layer is performed by irradiating the first doped layer with a laser.

[0037] Furthermore, the solar cell prepared is the aforementioned solar cell.

[0038] This application provides a battery assembly, which includes the aforementioned solar cell or a solar cell prepared by the aforementioned preparation method.

[0039] In the solar cell of this application, since the projection of the first electrode on the silicon substrate overlaps with the projection of the first crystalline doped region on the silicon substrate, and the projected area of ​​the first electrode on the silicon substrate is smaller than the projected area of ​​the first crystalline doped region on the silicon substrate, the current density is highest when photogenerated carriers are transported to the first electrode through the first doped layer. Since the transport efficiency of the first crystalline doped region is higher than that of the first amorphous doped region, the larger the projected area of ​​the first crystalline doped region on the silicon substrate, the higher the transport efficiency and the smaller the contact resistance. Attached Figure Description

[0040] The accompanying drawings are provided to better understand this application and do not constitute an undue limitation thereof. Wherein:

[0041] Figure 1 This is a schematic diagram of the structure of the solar cell provided in this application.

[0042] Figure 2 This is a partial structural schematic diagram of the solar cell provided in this application.

[0043] Figure 3 This is a partial structural schematic diagram of the solar cell provided in this application.

[0044] Figure 4 This is a partial structural schematic diagram of the solar cell provided in this application.

[0045] Figure 5 This is a partial structural schematic diagram of the solar cell provided in this application.

[0046] Figure 6 This is a schematic diagram of the structure of the solar cell provided in this application.

[0047] Explanation of reference numerals in the attached figures

[0048] 1-First electrode, 2-First conductive layer, 3-First amorphous doped region, 4-First passivation layer, 5-Silicon substrate, 6-Second passivation layer, 7-Second amorphous doped region, 8-Second conductive layer, 9-Second electrode, 10-First crystalline doped region, 11-Second crystalline doped region, 12-Dielectric layer. Detailed Implementation

[0049] The following description provides exemplary embodiments of this application, including various details to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0050] For growth films of the same thickness, amorphous silicon has a faster growth rate than crystalline (microcrystalline or nanocrystalline) films. However, amorphous silicon lacks the high electrical conductivity of crystalline silicon, which is detrimental to the electrical contact of solar cells. Therefore, using laser-induced transformation of amorphous silicon into microcrystalline silicon to fabricate solar cells offers significant production capacity advantages. Taking an n-type silicon wafer as an example, ideally, under the influence of the field effect, photogenerated carriers, particularly holes, are transported towards the p-end. Through thermal emission or diffusion, they enter the second doped layer, then tunnel into the second conductive layer 8, and finally converge into the second electrode 9. Electrons, on the other hand, pass through the first doped layer and the first conductive layer 2 to converge into the first electrode 1. During this transport process, the second conductive layer 8 exhibits very strong lateral conductivity, and photogenerated carriers are primarily collected and converged through it. Therefore, the contact surfaces between the second conductive layer 8, the second doped layer, and the silicon substrate 5 all play a role in transporting carriers. The contact resistance between the second conductive layer 8, the second doped layer, and the silicon substrate 5 is limited by the doping concentration of the second doped layer. Conventional doped amorphous silicon, due to its low doping efficiency, primarily relies on defect-assisted tunneling for transport between the conductive layer and the silicon substrate 5, resulting in low efficiency. If laser crystallization of the amorphous silicon in this region is used to improve its doping efficiency, the contact between the conductive layer and the doped layer will be heavily doped, changing the transport mode from defect-assisted tunneling to direct tunneling, significantly reducing resistivity. Therefore, in the entire battery contact area, the higher the proportion of crystalline doped layers compared to amorphous doped layers, the lower the battery contact resistance. Based on this, this application provides the following technical solution.

[0051] This application provides a solar cell, including a silicon substrate 5. The silicon substrate 5 has opposing first and second surfaces. A first doped layer and a first electrode 1 are sequentially stacked on the first surface. The first doped layer includes adjacent first crystalline doped regions 10 and first amorphous doped regions 3. The projection of the first electrode 1 onto the silicon substrate 5 overlaps with the projection of the first crystalline doped region 10 onto the silicon substrate 5, and the projected area of ​​the first electrode 1 onto the silicon substrate 5 is smaller than the projected area of ​​the first crystalline doped region 10 onto the silicon substrate 5. There can be multiple first electrodes 1, which extend along a first direction and are spaced apart along a second direction. Correspondingly, there can also be multiple first crystalline doped regions 10, each corresponding to one of the first electrodes 1.

[0052] In the solar cell provided by this application, since the projection of the first electrode 1 on the silicon substrate 5 overlaps with the projection of the first crystal doped region 10 on the silicon substrate 5, and the projected area of ​​the first electrode 1 on the silicon substrate 5 is smaller than the projected area of ​​the first crystal doped region 10 on the silicon substrate 5, the current density is highest when photogenerated carriers are transported to the first electrode 1 through the first doped layer. Since the transport efficiency of the first crystallized doped region is higher than that of the first amorphous doped region 3, the larger the projected area of ​​the first crystal doped region 10 on the silicon substrate 5, the higher the transport efficiency and the smaller the contact resistance.

[0053] like Figure 1 As shown, in some embodiments, a second doped layer and a second electrode 9 are sequentially stacked on the second surface of the silicon substrate 5, and the second electrode 9 is electrically connected to the second doped layer. Furthermore, the first doped layer and the second doped layer have opposite doping types to collect and export electrons and holes respectively, facilitating the formation of photocurrent.

[0054] The specific structure of the above-mentioned solar cell will be described in detail below through several embodiments.

[0055] Example 1:

[0056] In embodiment one, the second doped layer includes an adjacent first region and a second region, with the crystallinity of the second region being greater than that of the first region. That is, the first and second regions are arranged along a direction parallel to the second surface. The projection of the second electrode onto the silicon substrate 5 overlaps with the projection of the second region onto the silicon substrate 5, and the projected area of ​​the second electrode onto the silicon substrate 5 is smaller than the projected area of ​​the second region onto the silicon substrate 5. In other words, the projection of the second electrode onto the silicon substrate 5 is located inside the projection of the second region onto the silicon substrate 5. Thus, the contact resistance between the second electrode and the second doped layer is lower, and the transport efficiency is higher.

[0057] In some embodiments, the first region is a second amorphous doped region 7, and the second region is a second crystalline doped region 11. That is, the second doped layer includes the adjacent second amorphous doped region 7 and the second crystalline doped region 11.

[0058] The projection of the second electrode 9 onto the silicon substrate 5 overlaps with the projection of the second crystal doped region 11 onto the silicon substrate 5, and the projected area of ​​the second electrode 9 onto the silicon substrate 5 is smaller than the projected area of ​​the second crystal doped region 11 onto the silicon substrate 5.

[0059] There are multiple second electrodes 9, and the multiple second electrodes 9 can be multiple strip structures arranged in parallel. Along the direction perpendicular to the second electrodes 9, the second crystal doped region 11 and the second amorphous doped region 7 are arranged alternately in sequence. The lower part of each second electrode 9 overlaps with the projection of the second crystal doped region 11 on the silicon substrate 5. There can be multiple second crystal doped regions 11 to correspond one-to-one with the multiple second electrodes 9.

[0060] In some embodiments, the first electrode 1 is a plurality of strip structures arranged in parallel. Along the direction perpendicular to the first electrode 1, the first crystal doped region 10 and the first amorphous doped region 3 are arranged alternately in sequence. The lower part of each first electrode 1 overlaps with the projection of the first crystal doped region 10 on the silicon substrate. There can be multiple first crystal doped regions 10 to correspond one-to-one with multiple first electrodes 1.

[0061] In some embodiments, the first amorphous doped region 3 is disposed around the first crystalline doped region 10.

[0062] Specifically, the projection of the first crystal doped region 10 onto the silicon substrate 5 can be a regular shape, such as a circle, a rectangle, or an irregular shape.

[0063] In some embodiments, the second crystal doped region 11 and the second amorphous doped region 7 are arranged sequentially.

[0064] In some embodiments, the second amorphous doped region 7 is disposed around the second crystalline doped region 11.

[0065] Specifically, the projection of the second crystal doped region 11 onto the silicon substrate 5 can be a regular shape, such as a circle, a rectangle, or an irregular shape.

[0066] A first passivation layer 4 is also stacked between the silicon substrate 5 and the first doped layer. The first passivation layer 4 is located on the side of the first doped layer closer to the silicon substrate 5. That is, the first passivation layer 4 is located between the first doped layer and the silicon substrate 5. When the first doped layer includes one or more of microcrystalline silicon, nanocrystalline silicon, and amorphous silicon, the first passivation layer 4 includes one or more of intrinsic microcrystalline silicon, intrinsic nanocrystalline silicon, and intrinsic amorphous silicon.

[0067] A first conductive layer 2 is disposed between the first doped layer and the first electrode 1.

[0068] A second passivation layer 6 is also stacked between the silicon substrate 5 and the second doped layer. The second passivation layer 6 is located on the side of the second doped layer closer to the silicon substrate 5. When the second doped layer includes one or more of microcrystalline silicon, nanocrystalline silicon, and amorphous silicon, the second passivation layer 6 includes one or more of intrinsic microcrystalline silicon, intrinsic nanocrystalline silicon, and intrinsic amorphous silicon.

[0069] A second conductive layer 8 is disposed between the second doped layer and the second electrode 9.

[0070] The silicon substrate 5 can be either a p-type doped silicon substrate 5 or an n-type doped silicon substrate 5.

[0071] The first passivation layer 4 can be intrinsic hydrogenated amorphous silicon with a thickness of 1nm-20nm.

[0072] The second passivation layer 6 can be intrinsic hydrogenated amorphous silicon with a thickness of 1nm-20nm.

[0073] The first passivation layer 4 and the second passivation layer 6 are different layers, for example, they can have different hydrogen content, thickness and processes.

[0074] The thickness of the first doped layer is 5nm-200nm.

[0075] The thickness of the second doped layer is 5nm-200nm.

[0076] The first conductive layer 2 is a TCO layer with a thickness of 5nm-200nm.

[0077] The second conductive layer 8 is a TCO layer with a thickness of 5nm-200nm.

[0078] The first electrode 1 is made of silver, aluminum, copper, or an alloy thereof.

[0079] The second electrode 9 is made of silver, aluminum, copper, or an alloy thereof.

[0080] In the solar cell provided by this application, the projection of the first electrode 1 on the silicon substrate 5 overlaps with the projection of the first crystal doped region 10 on the silicon substrate 5, and the projected area of ​​the first electrode 1 on the silicon substrate 5 is smaller than the projected area of ​​the first crystal doped region 10 on the silicon substrate 5. The projection of the second electrode 9 on the silicon substrate 5 overlaps with the projection of the second crystal doped region 11 on the silicon substrate 5, and the projected area of ​​the second electrode 9 on the silicon substrate 5 is smaller than the projected area of ​​the second crystal doped region 11 on the silicon substrate 5. When photogenerated carriers are transported to the first electrode 1 / second electrode 9 through the first doped layer / second doped layer, the current density is highest at this point. Since the transport efficiency of the first crystal doped region and the second crystal doped region is higher than that of the first amorphous doped region 3 and the second amorphous doped region 7, the larger the projected area of ​​the first crystal doped region 10 and the second crystal doped region 11 on the silicon substrate 5, the higher the transport efficiency and the smaller the contact resistance.

[0081] In this application, the doping types of the first doped layer and the second doped layer are opposite.

[0082] The first crystal doped region 10 and the second crystal doped region 11 have opposite conductivity types.

[0083] The first amorphous doped region 3 has the same conductivity type as the first crystalline doped region 10.

[0084] The second amorphous doped region 7 has the same conductivity type as the second crystalline doped region 11.

[0085] In some implementations, the element doped in the first doped layer is phosphorus or boron. For example, when the element doped in the first doped layer is phosphorus, the element doped in the second doped layer is boron.

[0086] In some implementations, when the element doped in the first doped layer is boron, the element doped in the second doped layer is phosphorus.

[0087] In some embodiments, the doping element in the first crystal doped region 10 is the same as the doping element in the first amorphous doped region 3.

[0088] In some embodiments, the concentration of doping elements in the first crystal doped region 10 is greater than the concentration of doping elements in the first amorphous doped region 3, which can improve the conductivity of the first doped layer.

[0089] In some embodiments, the doping element in the second crystal doped region 11 is the same as the doping element in the second amorphous doped region 7.

[0090] In some embodiments, the concentration of doping elements in the second crystal doped region 11 is greater than the concentration of doping elements in the second amorphous doped region 7, which can improve the conductivity of the second doped layer.

[0091] In this application, the first crystal doped region 10 is a first microcrystalline doped region, a first nanocrystalline doped region, or a first polycrystalline doped region.

[0092] The second crystal doping region 11 is a second microcrystalline doping region, a second nanocrystalline doping region, or a second polycrystalline silicon doping region.

[0093] In this application, the first amorphous doped region 3 is selected from one of the first amorphous silicon doped region, the first amorphous silicon carbide doped region, or the first amorphous silicon oxide doped region.

[0094] The first crystal doped region 10 is selected from one of the first crystal silicon doped region, the first crystal silicon carbide doped region, or the first crystal silicon oxide doped region.

[0095] The second amorphous doped region 7 is selected from one of the second amorphous silicon doped region, the second amorphous silicon carbide doped region, or the second amorphous silicon oxide doped region.

[0096] The second crystal doped region 11 is selected from one of the second crystal silicon doped region, the second crystal silicon carbide doped region, or the second crystal silicon oxide doped region.

[0097] In some embodiments, the first crystal doped region 10 is a first crystalline silicon doped region, the first amorphous doped region 3 is a first amorphous silicon doped region, the second crystal doped region 11 is a second crystalline silicon doped region, and the second amorphous doped region 7 is a second amorphous silicon doped region.

[0098] In this application, the crystallinity of the first crystal doped region 10 is 0.01-100%. For example, it can be 0.01%, 1%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, etc.

[0099] The crystallization rate of the second crystal doped region 11 is 0.01-100%, for example, it can be 0.01%, 1%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, etc.

[0100] Crystallinity can be measured using Raman spectroscopy. Amorphous silicon / silicon carbide / silicon oxide, microcrystalline silicon / silicon carbide / silicon oxide, and crystalline silicon / silicon carbide / silicon oxide have different wavenumbers; for example, amorphous silicon is approximately 480 / cm², microcrystalline silicon is approximately 510 / cm², and crystalline silicon is 520.7 / cm². The amount of each component affects the Raman spectral intensity of the corresponding peak, and the crystallinity is obtained by integration. Crystallinity is a parameter characterizing the degree of crystallization. Increased crystallinity leads to increased carrier mobility, increased effective doping concentration, and improved conductivity of the doped layer. Microcrystalline silicon has a short-range ordered atomic structure, while amorphous silicon is amorphous; therefore, the crystallization region and grain size can be observed using transmission electron microscopy.

[0101] The grain size of the first crystal doped region 10 is in the nanometer range, not exceeding 100 nm, for example, it can be 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm or 30 nm.

[0102] The grain size of the second crystal doped region 11 is in the nanometer range, not exceeding 100nm, for example, it can be 100nm, 90nm, 80nm, 70nm, 60nm, 50nm, 40nm or 30nm.

[0103] Grain size can be observed using a transmission electron microscope.

[0104] In this application, at least a portion of the first crystal doped region 10, located away from the silicon substrate 5, contains crystals. Similarly, at least a portion of the second crystal doped region 11, located away from the silicon substrate 5, also contains crystals.

[0105] In some embodiments, the first crystal doped region 10 is entirely composed of crystal.

[0106] In some embodiments, the crystallinity of the first crystallized doped layer gradually decreases in the direction from near the first electrode 1 to the first passivation layer 4 within the first crystal doped region 10.

[0107] In some embodiments, the crystallinity of the first crystallized doped layer is the same in the direction from near the first electrode 1 to the first passivation layer 4 within the first crystal doped region 10.

[0108] In some embodiments, the second crystal doped region 11 is entirely composed of crystal.

[0109] In some embodiments, the crystallinity of the second crystallized doped layer gradually decreases in the direction from near the second electrode 9 to the second passivation layer 6 within the second crystal doped region 11.

[0110] In some embodiments, the crystallinity of the second crystal doped region 11 is the same from the direction near the second electrode 9 to the second passivation layer 6.

[0111] In this application, the total width of the first crystal doped region 10 is 0% to 100% of the width of the first doped layer, excluding 0% and 100%; for example, it can be 1%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, 99.9%, etc.

[0112] The total width of the second crystal doped region 11 is 0% to 100% of the width of the second doped layer, excluding 0% and 100%; for example, it can be 1%, 5%, 10%, 15%, 20%, 25%, 30%, etc.

[0113] 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%,

[0114] 90%, 95%, 99.9%, etc.

[0115] In some embodiments, the projection of the first electrode 1 on the silicon substrate 5 overlaps with the projection of the first crystal doped region 10 on the silicon substrate 5, and the projection of the first electrode 1 is located at the center of the projection of the first crystal doped region 10.

[0116] Because the transport efficiency of the first crystalline doped region 10 is higher than that of the first amorphous doped region 3, the larger the overlap area between the projection of the first electrode 1 onto the silicon substrate 5 and the projection of the first crystalline doped region 10 onto the silicon substrate 5, the smaller the contact resistance. Therefore, with this structure, when photogenerated carriers are transported to the first electrode 1 through the first doped layer, the current density is highest at this location, which can fully utilize the electronic conduction capability of the first crystalline doped region 10, thereby reducing the contact resistance or series resistance and improving the battery efficiency. (Contact resistance = contact resistivity / contact area; the contact resistivity of the first crystalline doped region 10 is lower than that of the first amorphous doped region 3)

[0117] In some embodiments, the projection of the first electrode 1 onto the silicon substrate 5 overlaps with the projection of the first crystal-doped region 10 onto the silicon substrate 5, and the projection of the first electrode 1 is located at any position within the projection of the first crystal-doped region 10 (excluding the center of the projection of the first crystal-doped region 10). With this structure, since the conductivity of the first crystallized doped region 10 is much greater than that of the first amorphous doped region 3, the positional requirements of the metal electrons are reduced, and thus a certain degree of displacement can occur.

[0118] In some embodiments, the projection of the second electrode 9 onto the silicon substrate 5 overlaps with the projection of the second crystal doped region 11 onto the silicon substrate 5, and the projection of the second electrode 9 is located at the center of the projection of the second crystal doped region 11.

[0119] In some embodiments, the projection of the second electrode 9 onto the silicon substrate 5 overlaps with the projection of the second crystal doped region 11 onto the silicon substrate 5, and the projection of the second electrode 9 is located at any position within the projection of the second crystal doped region 11 (excluding the center of the projection of the second crystal doped region 11).

[0120] In this application, in the width direction, the first amorphous doped region 3 includes first amorphous doped regions A located at both ends of the first doped layer. The width of the first amorphous doped region A is 0.05–6 mm, preferably 0.5–1 mm, for example, 0.05 mm, 0.1 mm, 0.2 mm, etc.

[0121] 0.3mm, 0.4mm, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm,

[0122] 1.1mm, 1.2mm, 1.3mm, 1.4mm, 1.5mm, 1.6mm, 1.7mm, 1.8mm,

[0123] 1.9mm, 2mm, 2.1mm, 2.2mm, 2.3mm, 2.4mm, 2.5mm, 2.6mm,

[0124] 2.7mm, 2.8mm, 2.9mm, 3mm, 3.1mm, 3.2mm, 3.3mm, 3.4mm,

[0125] 3.5mm, 3.6mm, 3.7mm, 3.8mm, 3.9mm, 4mm, 4.1mm, 4.2mm,

[0126] 4.3mm, 4.4mm, 4.5mm, 4.6mm, 4.7mm, 4.8mm, 4.9mm, 5mm,

[0127] 5.1mm, 5.2mm, 5.3mm, 5.4mm, 5.5mm, 5.6mm, 5.7mm, 5.8mm,

[0128] 5.9mm, 6mm, etc.

[0129] In some embodiments, the first doped layer includes a first crystallized doped region 10 and a first amorphous doped region 3. The first amorphous doped region 3 includes a first amorphous doped region A and a first amorphous doped region B. In the width direction, the first amorphous doped region A is located at both ends of the first doped layer, and the first crystal doped region and the first amorphous doped region B are alternately disposed in the middle of the first doped layer. The first crystal doped region is located between the first amorphous doped region A and the first amorphous doped region B.

[0130] In this application, in the width direction, the second amorphous doped region 7 includes second amorphous doped regions A located at both ends of the second doped layer. The width of the second amorphous doped region A is 0.05–6 mm, preferably 0.5–1 mm, for example, 0.05 mm, 0.1 mm, 0.2 mm, etc.

[0131] 0.3mm, 0.4mm, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm,

[0132] 1.1mm, 1.2mm, 1.3mm, 1.4mm, 1.5mm, 1.6mm, 1.7mm, 1.8mm,

[0133] 1.9mm, 2mm, 2.1mm, 2.2mm, 2.3mm, 2.4mm, 2.5mm, 2.6mm,

[0134] 2.7mm, 2.8mm, 2.9mm, 3mm, 3.1mm, 3.2mm, 3.3mm, 3.4mm,

[0135] 3.5mm, 3.6mm, 3.7mm, 3.8mm, 3.9mm, 4mm, 4.1mm, 4.2mm,

[0136] 4.3mm, 4.4mm, 4.5mm, 4.6mm, 4.7mm, 4.8mm, 4.9mm, 5mm,

[0137] 5.1mm, 5.2mm, 5.3mm, 5.4mm, 5.5mm, 5.6mm, 5.7mm, 5.8mm, 5.9mm, 6mm, etc.

[0138] In some embodiments, the second doped layer includes a second crystalline doped region 11 and a second amorphous doped region 7, wherein the second amorphous doped region 7 includes a second amorphous doped region A and a second amorphous doped region B. In the width direction, the second amorphous doped region A is located at both ends of the second doped layer, and the second crystalline doped region and the second amorphous doped region B are alternately disposed in the middle of the second doped layer, with the second crystalline doped region between the second amorphous doped region A and the second amorphous doped region B.

[0139] Since the first and second crystallized doped regions have high conductivity, if both ends of the first and second doped layers are crystallized doped regions, the carriers separated on the front and back sides will recombine from the edges, resulting in leakage. Therefore, both ends of the first and second doped layers are set as amorphous doped regions, which can reduce the risk of battery leakage.

[0140] In this application, the first crystal doped region 10 is formed by laser irradiation. That is, the first crystal doped region 10 is formed by laser irradiation of the amorphous doped layer, and the amorphous layer is at least partially transformed into a crystal under the action of the laser.

[0141] The second crystal doped region 11 is also formed by laser irradiation. That is, the second crystal doped region 11 is formed by laser irradiation of the amorphous doped layer, and the amorphous layer is at least partially transformed into crystal under the action of the laser.

[0142] In this application, the selective action of lasers can be used to precisely crystallize the region. The first doped layer and the second doped layer are partially crystallized, so that they both have crystalline and amorphous regions. This not only maintains their high resistivity, but also limits the lateral leakage current. At the same time, it can increase the effective doping concentration in the crystalline region and reduce the contact resistance, thereby helping to reduce the resistance loss of the battery.

[0143] The wavelength of a laser affects its absorption depth in amorphous films and its longitudinal range of action within the film. The longer the wavelength of the laser, the deeper the absorption depth, and the easier it is for amorphous films to transform into crystalline films in the longitudinal or thickness direction. In practical applications, the wavelength of the laser can be determined according to actual needs.

[0144] The greater the laser power, the greater the energy generated by the laser, and the easier it is for amorphous materials to be transformed into crystals.

[0145] Laser power, laser spot overlap rate, laser pulse width, and the number of laser irradiations affect the energy received per unit area, thus influencing the crystallization range, crystallization rate, and the degree of passivation damage to the silicon wafer surface beneath the film. Higher laser energy facilitates the transformation of amorphous materials into crystals, but also increases the degree of passivation damage to the silicon wafer surface. Therefore, in practical applications, the laser parameters should be designed according to specific conditions.

[0146] In this application, the single-spot energy density of a functional laser can be used to characterize the laser energy, and those skilled in the art can control the laser energy by adjusting the above parameters.

[0147] In the method of this application, for example, a single-spot energy density of the laser can be used, such as a single-spot energy density of the laser > 60 mJ / cm². 2 For example, it can be 61 mJ / cm. 2 65mJ / cm 2 ,

[0148] 70mJ / cm 2 75mJ / cm 2 80mJ / cm 2 85mJ / cm 2 90mJ / cm 2 100mJ / cm 2 ,

[0149] 110mJ / cm 2 120mJ / cm 2 130mJ / cm 2 140mJ / cm 2 150mJ / cm 2 ,

[0150] 160mJ / cm 2 170mJ / cm 2 180mJ / cm 2 190mJ / cm 2 200mJ / cm 2 wait.

[0151] Example 2:

[0152] In Example 2, the second doped layer comprises doped polycrystalline silicon. Doped polycrystalline silicon has a high current transport capability; therefore, when the second doped semiconductor layer is a doped polycrystalline silicon layer, the carrier recombination rate can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the hybrid solar cell. Generally, the second doped layer is disposed on the light-receiving surface of the solar cell; in some embodiments, it can also be disposed on the back surface of the solar cell.

[0153] In some embodiments, such as Figure 6 As shown, the solar cell also includes a second passivation layer 6, which is located on the side of the second doped layer closest to the silicon substrate. That is, the second passivation layer 6 is located between the second doped layer and the silicon substrate. For example, the second passivation layer 6 can be a tunneling oxide layer. Thus, the second doped layer and the second passivation layer 6 form a tunneling oxide passivation contact. The tunneling oxide passivation technology can form a tunneling film between the second electrode 9 and the silicon substrate, isolating the second electrode from the silicon substrate, reducing contact recombination losses, and ensuring that electrons tunneling through the film do not affect current transfer. Simultaneously, passivation can bend the surface bandgap, reducing surface recombination losses on the silicon wafer, effectively improving the front passivation and metal contact problems.

[0154] In other embodiments, such as Figure 6 As shown, the solar cell further includes a dielectric layer 12, which covers the side of the second doped layer opposite to the silicon substrate. A second electrode 9 passes through the dielectric layer 12 and is electrically connected to the second doped layer. The dielectric layer 12 may have openings corresponding to the second doped layer, through which the second electrode 9 passes to be electrically connected. Alternatively, the second electrode 9 may pass through the dielectric layer 12 and be electrically connected to the second doped layer by burning through it.

[0155] The dielectric layer 12 may be made of one or more of silicon nitride, silicon oxynitride, and silicon oxide, which can passivate the surface of the semiconductor substrate or doped layer, reduce its carrier recombination rate, and further improve the photoelectric conversion efficiency of the solar cell. Furthermore, the dielectric layer 12 can be a single-layer structure or a multi-layer structure.

[0156] In this second embodiment, the characteristics of the first crystal doped region 10 and the first amorphous doped region 3, as well as the characteristics of the silicon substrate, can be referred to in the first embodiment, and will not be repeated here.

[0157] This application provides a method for preparing a solar cell, comprising the following steps:

[0158] Step 1: Provide a silicon substrate 5, the silicon substrate 5 having opposing first and second surfaces;

[0159] Step 2: Form a first doped layer on one side of the first surface. The first doped layer is a first amorphous doped layer.

[0160] Step 3: Perform crystallization treatment on the first doped layer, so that a part of the first amorphous doped layer is transformed into the first crystalline doped region 10, and the part that does not undergo crystallization is the first amorphous doped region 3;

[0161] Step 4: A first electrode 1 is formed on the side of the first crystal doped region 10 away from the silicon substrate 5; the projection of the first electrode 1 on the silicon substrate 5 overlaps with the projection of the first crystal doped region 10 on the silicon substrate 5, and the projection area of ​​the first electrode 1 on the silicon substrate 5 is smaller than the projection area of ​​the first crystal doped region 10 on the silicon substrate 5.

[0162] Step 5: Form a second doped layer on one side of the second surface, wherein the doping type of the first doped layer is opposite to that of the second doped layer;

[0163] Step 6: Form a second electrode 9 on the side of the second doped layer opposite to the silicon substrate 5.

[0164] It is understood that the formation of the second doped layer on one side of the second surface can be performed either before or after the formation of the first doped layer.

[0165] In some embodiments, the second doped layer is a polycrystalline silicon doped layer. Since doped polycrystalline silicon has a high current transport capability, when the second doped semiconductor layer is a doped polycrystalline silicon layer, the carrier recombination rate can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the hybrid solar cell.

[0166] In the above embodiments, the method for fabricating the solar cell further includes the step of forming a dielectric layer 12 on the side of the second doped layer opposite to the silicon substrate 5, and electrically connecting the second electrode 9 through the dielectric layer 12 to the second doped layer. The dielectric layer 12 may have openings corresponding to the second doped layer, through which the second electrode 9 connects to the second doped layer. Alternatively, the second electrode 9 may connect to the second doped layer by burning through the dielectric layer 12.

[0167] Before forming the second doped layer, a second passivation layer 6 can be formed on the second surface first, and then a second doped layer can be formed on the side of the second passivation layer 6 facing away from the silicon substrate 5. The second passivation layer 6 can be a tunneling oxide layer.

[0168] In other embodiments, the second doped layer is a second amorphous doped layer. The method for fabricating this solar cell further includes the step of: crystallizing the second doped layer, such that a portion of the second doped layer is transformed into a second crystalline doped region, while the portion that does not undergo crystallization is a second amorphous doped region;

[0169] The projection of the second electrode on the silicon substrate 5 overlaps with the projection of the second crystal doped region on the silicon substrate 5, and the projection area of ​​the second electrode on the silicon substrate 5 is smaller than the projection area of ​​the second crystal doped region on the silicon substrate 5.

[0170] It is understood that the formation of the second doped layer on one side of the second surface can be performed either before or after the formation of the first doped layer.

[0171] In some embodiments, after crystallizing the first doped layer and before forming the first electrode 1 on the side of the first crystal doped region opposite to the silicon substrate 5, a first conductive layer is further formed on the side of the first doped layer opposite to the silicon substrate 5. The conductive layer has high conductivity, which can promptly export the collected charge carriers and reduce the charge carrier recombination rate.

[0172] In step one, the silicon wafer is cleaned and texturized to obtain a textured silicon substrate 5.

[0173] The silicon substrate 5 can be either a p-type doped silicon substrate 5 or an n-type doped silicon substrate 5.

[0174] In some embodiments, the front side of the silicon substrate 5 is textured, and the back side is flat.

[0175] In some implementations, both the front and back sides of the silicon substrate 5 are textured.

[0176] In some embodiments, the back side of the silicon substrate 5 is textured, and the front side is flat.

[0177] In some implementations, both the front and back sides of the silicon substrate 5 are planar.

[0178] In some embodiments, the back side of the silicon substrate 5 has a textured surface.

[0179] When the silicon substrate 5 has a textured structure, the actual contact area between the silicon substrate 5 and the amorphous film layer, the amorphous film layer and the TCO film layer, and the TCO film layer and the metal electrode grid line can be increased, thereby reducing the series resistance of the battery.

[0180] In step two, a first doped layer is formed on one side of the first surface, and the first doped layer is a first amorphous doped layer;

[0181] A second doped layer is formed on one side of the second surface. The second doped layer is a second amorphous doped layer.

[0182] In some implementations, such as Figure 2 As shown, a first passivation layer 4 and a first amorphous doped layer are sequentially formed on the first surface of the silicon substrate 5. The formation methods of the first passivation layer 4 and the first amorphous doped layer are not further limited. For example, the first passivation layer 4 can be prepared by plasma-enhanced CVD (PECVD) or hot-wire CVD (cat-CVD), and the first amorphous doped layer can be prepared by PECVD.

[0183] In some implementations, such as Figure 3 As shown, a second passivation layer 6 and a second amorphous doped layer are formed on one side of the second surface of the silicon substrate 5. The formation method of the second passivation layer 6 and the second amorphous doped layer is not further limited. For example, the second passivation layer 6 can be prepared by plasma-enhanced CVD (PECVD) or hot-wire CVD (cat-CVD), and the second amorphous doped layer can be prepared by PECVD.

[0184] In step three, such as Figure 4 As shown, the crystallization treatment of the first doped layer and the second doped layer is carried out by irradiating the first doped layer and the second doped layer with a laser. Under the thermal effect of the laser, the amorphous silicon crystallizes, so that a part of the first amorphous doped layer is transformed into the first crystal doped region 10, and the part that does not undergo crystallization is the first amorphous doped region 3. At the same time, a part of the second amorphous doped layer is transformed into the second crystal doped region 11, and the part that does not undergo crystallization is the second amorphous doped region 7. The doping concentration of the doped elements in the first crystal doped region 10 and the second crystal doped region 11 is increased.

[0185] In step four, as Figure 5 As shown, a first electrode 1 is formed on the side of the first doped layer opposite to the silicon substrate 5, and a second electrode 9 is formed on the side of the second doped layer opposite to the silicon substrate 5. Before forming the first electrode 1 and the second electrode 9, a first conductive layer 2 is formed on the surface of the first doped layer opposite to the first passivation layer 4; and a second conductive layer 8 is formed on the surface of the second doped layer opposite to the second passivation layer 6. The formation methods of the first conductive layer 2 and the second conductive layer 8 are not specifically limited. For example, the first conductive layer 2 and the second conductive layer 8 can be formed simultaneously, both by PVD (Physical Vapor Deposition), RPD (Reactive Plasma Diosition), etc., and both the first conductive layer 2 and the second conductive layer 8 can be ITO (Indium Tin Oxide), IWO (Indium Tungsten Oxide), AZO (Aluminum Doped Zinc Oxide), etc.

[0186] In step five, the formation methods of the first electrode 1 and the second electrode 9 are not specifically limited. For example, both the first electrode 1 and the second electrode 9 can be obtained by electroplating or screen printing.

[0187] The fabrication method of this application, through laser induction, enables the first doped layer to simultaneously possess a first crystalline doped region 10 and a first amorphous doped region 3, thereby providing good contact for the solar cell and effectively reducing contact resistance (and simultaneously reducing series resistance). Furthermore, the laser-induced transformation of amorphous silicon into microcrystalline silicon significantly increases production capacity. Additionally, the ends of the first and second doped layers are not crystallized, thus reducing the risk of leakage current in the cell.

[0188] The preparation method of this application produces a solar cell as described above. For each part of the solar cell, please refer to the foregoing description.

[0189] This application also provides a battery assembly including the aforementioned solar cell.

[0190] Example

[0191] Unless otherwise specified, the experimental methods used in the following examples are conventional methods.

[0192] Unless otherwise specified, all materials and reagents used in the following examples are commercially available.

[0193] Example 1.1

[0194] The method for preparing the solar cell in this embodiment includes the following steps:

[0195] Step 1: Polish and clean the silicon wafer, and perform texturing on the light-receiving surface.

[0196] Step 2: On one side of the silicon wafer, an intrinsic hydrogenated amorphous silicon passivation layer (first passivation layer) with a thickness of 6 nm and an amorphous silicon doped layer (first doped layer) with a thickness of 20 nm are deposited sequentially using PECVD. The doping type is boron. On the front side of the cell, an intrinsic hydrogenated amorphous silicon passivation layer (second passivation layer) with a thickness of 4 nm and a doped amorphous silicon doped layer (second doped layer) with a thickness of 11 nm are deposited sequentially using PECVD. The doping element is phosphorus.

[0197] Step 3: Using a 532nm green nano laser, scan the first and second doped layers of the entire solar cell. The scanning width is 30μm and the scanning length runs through the entire solar cell. In the first doped layer, laser-induced crystallization forms a microcrystalline silicon doped region (the total width of the first crystallized doped region is 2.5% of the width of the first doped layer). The uncrystallized portion is the first amorphous doped region. In the second doped layer, laser-induced crystallization forms a microcrystalline silicon doped region (the total width of the second crystallized doped region is 2.5% of the width of the second doped layer). The uncrystallized portion is the second amorphous doped region.

[0198] Step 4: Using a wet process, hydrofluoric acid is used to clean the silicon oxide generated on the surfaces of the first and second doped layers.

[0199] Step 5: A 65nm thick TCO film is deposited on the surface of both the first and second doped layers using PVD technology as a lateral conductive layer.

[0200] Step 6: Using laser transfer, metal gate lines (first electrode and second electrode) are printed on the conductive layers on both sides respectively. The projection of the gate line on the silicon substrate is located within the projection of the first crystal doped region and the second crystal doped layer on the silicon substrate, and their centers coincide. The projection area of ​​the gate line accounts for 2% of the projection area of ​​the first doped layer and the second doped layer, and the width of the gate line is 2% of the width of the first doped layer and the second doped layer.

[0201] Step 7: Cur the solar cells at 200℃ for 45 minutes and perform IV testing for screening. The parallel and series resistances of the solar cells are tested using an FCT650 instrument under standard testing conditions.

[0202] The performance parameters of the solar cells are shown in Table 1.

[0203] The difference between Examples 2 and 3 and Example 1 is that the total width of the first crystal doped region is different, while all other parameters are the same. See Table 1 for details.

[0204] The difference between Examples 4-7 and Example 1 is that the widths of the first amorphous doped regions 3 located at both ends of the first doped layer are different; all other parameters are the same. See Table 1 for details.

[0205] The difference between Comparative Example 1 and Example 1 is that there is no laser processing step in Comparative Example 1. All other parameters are the same as in Example 1. The first doped layer is entirely a first amorphous doped region 3, and the second doped layer is entirely a second amorphous doped region. The parameters of the solar cell of Comparative Example 1 are shown in Table 1.

[0206] The difference between Comparative Example 2 and Example 1 is that the projection of the first electrode on the silicon substrate completely coincides with the projection of the first crystal doped region on the silicon substrate, and the projection areas are the same; all other parameters are identical. See Table 1 for details.

[0207] The difference between Comparative Example 3 and Example 1 is that the total width of the first crystal doped region is different, while all other parameters are the same. See Table 1 for details.

[0208] The difference between Comparative Example 4 and Example 1 is that the first doped layer in Comparative Example 4 is a whole layer of first microcrystalline silicon doped region without amorphous silicon doped region, and the second doped layer is a whole layer of second microcrystalline silicon doped region without amorphous silicon doped region. The parameters of the solar cell of Comparative Example 4 are shown in Table 1.

[0209] The difference between Comparative Example 5 and Example 1 is that the projection of the first electrode on the silicon substrate and the projection of the first crystal doped region on the silicon substrate overlap by 20%, while all other parameters are the same. See Table 1 for details.

[0210] Table 1 shows the performance parameters of the solar cells in each embodiment and comparative example.

[0211]

[0212]

[0213] In summary, as shown in Table 1, the solar cell of this application has a smaller IV test series resistance and a larger IV test parallel resistance. The smaller the IV test series resistance, the smaller the contact resistance of the solar cell; the larger the IV test parallel resistance, the lower the risk of leakage current in the solar cell.

[0214] Although the embodiments of this application have been described above in conjunction with the accompanying drawings, this application is not limited to the specific embodiments and application fields described above. The specific embodiments described above are merely illustrative and instructive, not restrictive. Those skilled in the art can make many other forms based on the guidance of this specification and without departing from the scope of protection of the claims of this application, and these are all within the scope of protection of this application.

Claims

1. A solar cell, wherein, The device includes a silicon substrate having opposing first and second surfaces. A first doped layer and a first electrode are sequentially stacked on the first surface, and a first conductive layer is disposed between the first doped layer and the first electrode. The first doped layer includes a first crystalline doped region and a first amorphous doped region adjacent to each other along a first direction. A second doped layer and a second electrode are sequentially stacked on the second surface of the silicon substrate, and the doping types of the first doped layer and the second doped layer are opposite. The first direction is parallel to the first surface. The projection of the first electrode on the silicon substrate overlaps with the projection of the first crystal doped region on the silicon substrate, and the projected area of ​​the first electrode on the silicon substrate is smaller than the projected area of ​​the first crystal doped region on the silicon substrate.

2. The solar cell according to claim 1, wherein, The second doped layer includes a first region and a second region adjacent to each other along the first direction, the crystallinity of the second region is greater than that of the first region; the projection of the second electrode on the silicon substrate overlaps with the projection of the second region on the silicon substrate, and the projection area of ​​the second electrode on the silicon substrate is smaller than the projection area of ​​the second region on the silicon substrate.

3. The solar cell according to claim 2, wherein, The first region is a second amorphous doped region, and the second region is a second crystalline doped region.

4. The solar cell according to claim 1, wherein, The second doped layer comprises doped polycrystalline silicon.

5. The solar cell according to claim 4, wherein, The solar cell further includes a second passivation layer located on the side of the second doped layer near the silicon substrate; and / or, The solar cell also includes a dielectric layer that covers the side of the second doped layer away from the silicon substrate, and the second electrode passes through the dielectric layer and is electrically connected to the second doped layer.

6. The solar cell according to claim 1, wherein, Within the first crystal doped region, at least the portion on the side furthest from the silicon substrate has crystals.

7. The solar cell according to claim 3, wherein, The total width of the first crystal doped region is 0% to 100% of the width of the first doped layer, excluding 0% and 100%; and / or, The total width of the second crystal doped region is 0% to 100% of the width of the second doped layer, excluding 0% and 100%.

8. The solar cell according to claim 3, wherein, In the width direction, the first amorphous doped region includes a first amorphous doped region A located at both ends of the first doped layer, the width of the first amorphous doped region A being 0.05~6mm; and / or In the width direction, the second amorphous doped region includes a second amorphous doped region A located at both ends of the second doped layer, and the width of the second amorphous doped region A is 0.05~6mm.

9. The solar cell according to any one of claims 1-8, wherein, The first crystal doping region is a first microcrystalline doping region, a first nanocrystalline doping region, or a first polycrystalline doping region.

10. The solar cell according to any one of claims 1-8, wherein, The first amorphous doped region is selected from one of the following: a first amorphous silicon doped region, a first amorphous silicon carbide doped region, or a first amorphous silicon oxide doped region; and / or The first crystal doped region is selected from one of the first crystal silicon doped region, the first crystal silicon carbide doped region, or the first crystal silicon oxide doped region.

11. The solar cell according to any one of claims 3-8, wherein, The crystallinity of the first crystal doped region is 0.01-100%; and / or The crystallinity of the second crystal doped region is 0.01-100%.

12. A method for preparing a solar cell, wherein, Includes the following steps: A silicon substrate is provided, the silicon substrate having opposing first and second surfaces; A first doped layer is formed on one side of the first surface, wherein the first doped layer is a first amorphous doped layer; The first doped layer is subjected to crystallization treatment, so that a portion of the first amorphous doped layer is transformed into a first crystalline doped region, and the portion that does not undergo crystallization is the first amorphous doped region. A first conductive layer is formed on the side of the first doped layer that is away from the silicon substrate; A first electrode is formed on the side of the first crystal doped region away from the silicon substrate; A second doped layer is formed on one side of the second surface, wherein the doping type of the first doped layer is opposite to that of the second doped layer; A second electrode is formed on the side of the second doped layer opposite to the silicon substrate; The projection of the first electrode on the silicon substrate overlaps with the projection of the first crystal doped region on the silicon substrate, and the projected area of ​​the first electrode on the silicon substrate is smaller than the projected area of ​​the first crystal doped region on the silicon substrate.

13. The preparation method according to claim 12, wherein, The second doped layer is a polycrystalline silicon doped layer.

14. The preparation method according to claim 12, wherein, The second doped layer is a second amorphous doped layer; the method for fabricating the solar cell further includes the following steps: The second doped layer is subjected to crystallization treatment, so that a part of the second doped layer is transformed into a second crystalline doped region, and the part that does not undergo crystallization is a second amorphous doped region. The projection of the second electrode on the silicon substrate overlaps with the projection of the second crystal doped region on the silicon substrate, and the projection area of ​​the second electrode on the silicon substrate is smaller than the projection area of ​​the second crystal doped region on the silicon substrate.

15. The preparation method according to any one of claims 12-14, wherein, The crystallization process of the first doped layer is performed by irradiating the first doped layer with a laser.

16. A battery assembly, wherein, This includes the solar cell according to any one of claims 1-11 or the solar cell prepared by the preparation method according to any one of claims 12-15.

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