Display panel

Abstract

The application relates to a display panel, which comprises an array substrate, a first flat layer, a first electrode layer and a light-emitting functional layer. The first flat layer is arranged above the array substrate and comprises a plurality of first openings. The first electrode layer comprises a plurality of first electrodes, each of which comprises a main electrode and a gain electrode extending from the edge of the main electrode. The main electrode is located on the bottom side of the first opening, the gain electrode is located on the side of the first opening, and the position of the gain electrode in the first opening is higher than that of the main electrode. The light-emitting functional layer is arranged above the main electrode and the gain electrode. The application can effectively improve the viewing angle of the display panel and thus improve the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) display panels have properties such as self-illumination, low driving voltage, high luminous efficiency, short response time, high clarity and contrast, and can achieve flexible display.

[0003] However, the viewing angle limitation of existing OLED display panels has a significant impact on the display effect. Summary of the Invention

[0004] This application provides a display panel that can improve the viewing angle and enhance the display effect.

[0005] This application provides a display panel, the display panel comprising:

[0006] Array substrate;

[0007] A first planarization layer is disposed above the array substrate, and the first planarization layer includes a plurality of first openings;

[0008] A first electrode layer includes a plurality of first electrodes, each first electrode including a main electrode and a gain electrode extending from the edge of the main electrode. The main electrode is located on the bottom wall of the first opening, and the gain electrode is located on the side wall of the first opening, with the gain electrode positioned higher than the main electrode within the first opening.

[0009] A light-emitting functional layer is disposed on the main electrode and the gain electrode.

[0010] In some embodiments, the display panel further includes:

[0011] A pixel definition layer is disposed above the first flat layer, the pixel definition layer including a plurality of second openings, the second openings at least partially overlapping the first openings.

[0012] In some embodiments, the light-emitting functional layer is located within the pixel opening formed by the first opening and the second opening, and the light-emitting surface of the light-emitting functional layer is higher than the gain electrode and is connected to the pixel definition layer.

[0013] In some embodiments, the gain electrode extends to the end face of the first planarization layer, and the extended end of the gain electrode is located at the intersection of the pixel definition layer and the first planarization layer.

[0014] In some embodiments, the first planarization layer includes a plurality of first sub-planarization layers arranged in an array, each of the first sub-planarization layers having a first opening.

[0015] In some embodiments, the first planarization layer includes a plurality of first sub-planarization layers spaced apart along a first direction, each first sub-planarization layer having a plurality of first openings, and the plurality of first openings being arranged along a second direction, wherein the first direction intersects the second direction.

[0016] In some embodiments, the pixel definition layer includes a first sub-pixel definition layer, which is located within the second spacing slot and the first spacing slot, and is partially located above the first electrode.

[0017] In some embodiments, the first sub-pixel definition layer includes a first sub-part located above the first sub-flattening layer and a second sub-part located between adjacent first sub-flattening layers, wherein the first sub-part is connected to the second sub-part.

[0018] In a direction perpendicular to the array substrate, the thickness of the second sub-part is greater than the thickness of the first sub-part, the first sub-part is hydrophilic, and the second sub-part is hydrophobic.

[0019] In some embodiments, the pixel definition layer further includes a second sub-pixel definition layer, which is located within the first spacer and partially above the first electrode. The second sub-pixel definition layer is located above the first sub-planarization layer and contacts the surface of the first sub-planarization layer away from the array substrate. The second sub-pixel definition layer is hydrophilic.

[0020] This application provides a display panel. The display panel first forms a first planarization layer on an array substrate. The first planarization layer includes a plurality of first openings. Then, a first electrode layer is formed on the first planarization layer. The first electrode layer includes a plurality of first electrodes, including a main electrode and a gain electrode. The main electrode covers the bottom wall of the first opening, and the gain electrode is formed on the side wall of the first opening. A light-emitting functional layer is then formed on the first electrode layer. The light-emitting functional layer covers the main electrode located on the bottom wall of the first opening and the gain electrode located on the side wall of the first opening. Therefore, the light-emitting functional layer located on the side wall of the first opening can also emit light. The display panel of this application increases the emitted light from different angles of the light-emitting functional layer on the side wall of the first opening, and simultaneously increases the overall light-emitting area of ​​the light-emitting functional layer, thus effectively improving the viewing angle and enhancing the display effect of the display panel. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0023] Figure 1 This is a schematic diagram of the structure of a display panel provided by existing technology;

[0024] Figure 2 This is a schematic diagram of the light emission of a display panel provided in an embodiment of this application;

[0025] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0026] Figure 4 This is a cross-sectional view of one of the display panels provided in the embodiments of this application;

[0027] Figure 5 This is a top view of a display panel provided in an embodiment of this application;

[0028] Figure 6 yes Figure 5 A top view of a first planar layer and a first electrode layer of a display panel is provided;

[0029] Figure 7 This is a top view of another display panel provided in an embodiment of this application;

[0030] Figure 8 yes Figure 7 A top view of a first planar layer and a first electrode layer of a display panel is provided;

[0031] Figure 9 yes Figure 7 A BB cross-sectional view of a display panel is provided.

[0032] Explanation of reference numerals in the attached figures:

[0033] 100, Display panel; 101, Pixel opening; 110, Array substrate; 111, Substrate; 112, Driving circuit layer; 113, Second planarization layer; 120, First planarization layer; 121, First opening; 1211, Bottom wall; 1212, Side wall; 1213, End face; 122, First sub-planarization layer; 123, Second spacer; 130, First electrode layer; 131, First electrode; 1311, Main electrode; 1312, Gain electrode; 132, First spacer; 140, Light-emitting functional layer; 150, Pixel definition layer; 1501, First sub-pixel definition layer; 1502, Second sub-pixel definition layer; 151, Second opening; 152, First sub-section; 153, Second sub-section; 160, Second electrode layer. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0035] Please refer to Figure 1 , Figure 1 This is a cross-sectional view of a display panel in the prior art. The display panel includes an array substrate 110, a first electrode layer 130, a pixel definition layer 150, and a light-emitting functional layer 140. The pixel definition layer 150 is located on the side of the first electrode layer 130 away from the array substrate 110, and includes multiple pixel openings 101, each exposing a portion of the first electrode layer 130. The light-emitting functional layer 140 is located on the side of the first electrode layer 130 away from the array substrate 110 and is located within the pixel openings 101. In the prior art, only the bottom wall of the pixel opening 101 is covered by the first electrode layer 130; therefore, only the light-emitting functional layer 140 on the bottom wall of the pixel opening 101 emits light, and the direction of the emitted light from the light-emitting functional layer 140 is as follows: Figure 1 As indicated by the middle arrow, the viewing angle of the display panel is limited.

[0036] To address the aforementioned problems, this application provides a display panel 100. Please refer to... Figures 2-3This application provides a display panel 100, which includes an array substrate 110, a first planarization layer 120, a first electrode layer 130, and a light-emitting functional layer 140. The first planarization layer 120 is disposed above the array substrate 110 and includes a plurality of first openings 121. The first electrode layer 130 includes a plurality of first electrodes 131, which correspond one-to-one with the plurality of first openings 121. Each first electrode 131 includes a main electrode 1311 and a gain electrode 1312 extending from the edge of the main electrode 1311. The main electrode 1311 is located on the bottom wall 1211 of the first opening 121, and the gain electrode 1312 is located on the side wall 1212 of the first opening 121, with the gain electrode 1312 being higher than the position of the main electrode 1311 within the first opening 121. The light-emitting functional layer 140 is located above the main electrode 1311 and the gain electrode 1312, that is, the light-emitting functional layer 140 covers the first electrode 131.

[0037] Furthermore, the display panel 100 includes a second electrode layer 160, which is disposed on the side of the light-emitting functional layer 140 away from the first electrode layer 130.

[0038] In this application, a first electrode 131 is formed within a first opening 121 of a first planarization layer 120, including a main electrode 1311 and a gain electrode 1312. The main electrode 1311 covers the bottom wall 1211 of the first opening 121, and the gain electrode 1312 is located on the side wall 1212 of the first opening 121. A light-emitting functional layer 140 covers both the main electrode 1311 on the bottom wall 1211 and the gain electrode 1312 on the side wall 1212 of the first opening 121. Therefore, both the light-emitting functional layer 140 on the bottom wall 1211 and the side wall 1212 of the first opening 121 can emit light. However, the angle of the light emitted by the light-emitting functional layer 140 on the side wall 1212 of the first opening 121 is different from the angle of the light emitted by the light-emitting functional layer 140 on the bottom wall 1211 of the first opening 121. Compared with the prior art, the display panel 100 of this application increases the light emitted from the light-emitting functional layer 140 on the side wall 1212 of the first opening 121 at different angles, thereby improving the viewing angle. At the same time, since the light-emitting functional layer 140 on the side wall 1212 of the first opening 121 can also emit light, the overall light-emitting area of ​​the light-emitting functional layer 140 is increased, which can further improve the viewing angle and thus effectively improve the display effect of the display panel 100.

[0039] In some embodiments, please refer to Figures 3-4The display panel 100 also includes a pixel definition layer 150, which is disposed above the first planarization layer 120, i.e., on the side of the first planarization layer 120 away from the array substrate 110. The pixel definition layer 150 includes a plurality of second openings 151, which at least partially overlap with the first openings 121, i.e., the second openings 151 communicate with the first openings 121. For example, the orthographic projection of the first opening 121 on the array substrate 110 may be located within the range of the orthographic projection of the second opening 151 on the array substrate 110.

[0040] It is understood that in this application, the display panel 100 includes multiple pixel regions arranged in an array, each pixel region including one pixel. The first planarization layer 120 and the pixel definition layer 150 are stacked and jointly define the multiple pixel regions of the display panel 100. A first opening 121 and a second opening 151 connected together define a pixel region. The first electrode 131, the light-emitting functional layer 140 and the second electrode layer 160 located in a pixel region together constitute a pixel. Different pixels on the display panel 100 can emit light of different colors, such as red light, green light or blue light.

[0041] In some embodiments, please refer to Figures 3-4 The gain electrode 1312 extends to the end face 1213 of the first planarization layer 120, where the end face 1213 is the side surface of the first planarization layer 120 away from the array substrate 110. The extended end of the gain electrode 1312 is located at the overlap of the first planarization layer 120 and the pixel definition layer 150, where the extended end refers to the end of the gain electrode 1312 away from the main electrode 1311, so that the gain electrode 1312 covers the entire sidewall 1212 of the first opening 121. The light-emitting functional layer 140 is located within the pixel opening formed by the first opening 121 and the second opening 151, and covers the first electrode layer 130. The light-emitting surface of the light-emitting functional layer 140 is higher than the gain electrode 1312 and is in contact with the pixel definition layer 150, so that the light-emitting functional layer 140 completely covers the gain electrode 1312 located on the sidewall 1212 of the first opening 121.

[0042] For details, please refer to Figures 3-4The main electrode 1311 covers the entire bottom wall 1211 of the first opening 121, the gain electrode 1312 covers the entire side wall 1212 of the first opening 121, and the light-emitting functional layer 140 covers the main electrode 1311 located on the bottom wall 1211 of the first opening 121, and also covers the gain electrode 1312 located on the side wall 1212 of the first opening 121. Therefore, a portion of the light-emitting functional layer 140 is formed on the side wall of the second opening 151. In this embodiment, the first electrode layer 130 covers the entire side wall 1212 of the first opening 121, which can increase the light-emitting area of ​​the light-emitting functional layer 140 located on the side wall, thereby further improving the viewing angle. The pixel definition layer 150 is located above the first planarization layer 120 to separate the light-emitting functional layers 140 in adjacent pixel areas, avoiding problems such as color mixing.

[0043] In some embodiments, please refer to Figures 4-6 Multiple first electrodes 131 are spaced apart. For example, the multiple first electrodes 131 can be arranged in an array along a first direction X and a second direction Y, where the first direction X intersects the second direction Y. Further, the first direction X and the second direction Y can be perpendicular. Each of the multiple first electrodes 131 corresponds one-to-one with a multiple first opening 121, with the first electrode 131 covering the first opening 121. That is, the first electrode 131 and the pixel area have a one-to-one correspondence to achieve independent light emission for each pixel. Since the first electrodes 131 are spaced apart, a first spacing groove 132 is formed between adjacent first electrodes 131. At least a portion of the pixel definition layer 150 is located within the first spacing groove 132. For example, the pixel definition layer 150 fills the first spacing groove 132 to space and insulate adjacent first electrodes 131.

[0044] In some embodiments, please refer to Figure 4 At least a portion of the first electrode layer 130 is also formed on the end face 1213 of the first planarization layer 120, that is, at least a portion of the gain electrodes 1312 are located on the end face 1213 of the first planarization layer 120. During the formation of the first electrode layer 130, first electrode material is first deposited on the side of the first planarization layer 120 away from the array substrate 110, and then the first electrode material is patterned. To ensure that the first electrode layer 130 covers the entire sidewall 1212 of the first opening 121, and for ease of processing, a portion of the first electrodes 131 on the end face 1213 of the first planarization layer 120 is retained, that is, the first electrode layer 130 also covers at least a portion of the end face 1213 of the first planarization layer 120. To ensure that the light-emitting functional layer 140 is located within the first opening 121 and the second opening 151, the pixel definition layer 150 covers the portion of the first electrode layer 130 located on the end face 1213 of the first planarization layer 120.

[0045] In some embodiments, please refer to Figures 4-6 ,in Figure 4 for Figure 5 The cross-sectional view at point AA. The first planarization layer 120 includes a plurality of spaced first sub-planarization layers 122, each first sub-planarization layer 122 having a first opening 121. For example, the plurality of first sub-planarization layers 122 can be arranged in an array, that is, the plurality of first sub-planarization layers 122 of the display panel 100 correspond one-to-one with the plurality of pixels. Each first sub-planarization layer 122 includes a first opening 121, and a second spacing slot 123 is provided between adjacent first sub-planarization layers 122, the second spacing slot 123 communicating with the first spacing slot 132.

[0046] For further details, please refer to Figure 4 The pixel definition layer 150 includes a first sub-pixel definition layer 1501, which is located within the second spacing slot 123 and the first spacing slot 132, and partially located above the first electrode 131. The first sub-pixel definition layer 1501 fills the second spacing slot 123 and the first spacing slot 132, and covers the extension end of the gain electrode 1312 near the second spacing slot 123, so as to ensure the separation between two adjacent first sub-planarization layers 122 and the separation between adjacent first electrodes 131.

[0047] In this embodiment, each first sub-flattening layer 122 corresponds to a first opening 121, meaning there is a one-to-one correspondence between the first sub-flattening layer 122 and the pixel. In the display panel 100 structure of this embodiment, each first sub-flattening layer 122 is independently configured, and adjacent first sub-flattening layers 122 are separated by a first sub-pixel definition layer 1501. Ink from the light-emitting functional layer 140 is printed in each corresponding pixel area to avoid ink mixing between adjacent pixels.

[0048] In some embodiments, please refer to Figures 7-8 The first planarization layer 120 includes a plurality of first sub-planarization layers 122 arranged at intervals along a first direction X, and the first sub-planarization layers 122 extend along a second direction Y. Each first sub-planarization layer 122 has a plurality of first openings 121, and the plurality of first openings 121 are arranged along the second direction Y. In this embodiment, each first sub-planarization layer 122 includes a plurality of first openings 121, and a second spacing groove 123 is provided between adjacent first sub-planarization layers 122, and the second spacing groove 123 communicates with the first spacing groove 132.

[0049] Furthermore, the pixel definition layer 150 includes a first sub-pixel definition layer 1501, which is located within the second spacing slot 123 and the first spacing slot 132, and partially located above the first electrode layer 130. The first sub-pixel definition layer 1501 fills the second spacing slot 123 and the first spacing slot 132, and covers the extension end of the gain electrode 1312 near the second spacing slot 123, so as to ensure the separation between two adjacent first sub-planarization layers 122 and the separation between adjacent first electrodes 131.

[0050] In this embodiment, a first sub-planarization layer 122 is provided with a plurality of first openings 121. For example, the plurality of first openings 121 may be arranged at intervals along the second direction Y. In the display panel 100 structure of this embodiment, ink for one column of pixels can be printed at a time. For example, when the colors of multiple pixels arranged along the second direction are the same, ink for one column of pixels arranged along the second direction can be printed at once. Since the pixels in the second direction are the same color, there is no color mixing problem, and one column of pixels can be formed by printing at once, thereby simplifying the process.

[0051] In some embodiments, please refer to Figure 4 The first sub-pixel definition layer 1501 includes a first sub-part 152 located above the first sub-planarization layer 122 and a second sub-part 153 located between adjacent first sub-planarization layers 122. The first sub-part 152 and the second sub-part 153 are connected. In the direction perpendicular to the array substrate 110, the thickness of the second sub-part 153 is greater than the thickness of the first sub-part 152. The first sub-part 152 is hydrophilic, and the second sub-part 153 is hydrophobic. Specifically, the first sub-part 152 is located above the end face 1213 of the first sub-planarization layer 122, and the thickness of the first sub-part 152 is d1. The second sub-part 153 is located between adjacent first sub-planarization layers 122, including a portion filling the second spacer groove 123 (thickness d2), a portion filling the first spacer groove 132, and a portion located above the first spacer groove 132 (thickness d1). The thickness of the second sub-part 153 is d1+d2. Therefore, the thickness of the second sub-part 153 is greater than the thickness of the first sub-part 152. Since the material of the pixel definition layer 150 is a uniformly mixed slurry before coating, and the slurry contains hydrophobic components, the hydrophobic components in the slurry will migrate to the surface after the slurry is coated on the array substrate 110 and during the patterning process. The second sub-section 153 is a thick film region with a large thickness and a large amount of hydrophobic components, and its surface exhibits strong hydrophobicity. The first sub-section 152 is a thin film region with a small thickness and a small amount of hydrophobic components, and its surface exhibits hydrophilicity relative to the second sub-section 153.

[0052] Since the ink of the light-emitting functional layer 140 is formed by inkjet printing, the ink of the light-emitting functional layer 140 of adjacent pixels is prone to color mixing above the second sub-part 153. Therefore, this application sets the second sub-part 153 located between adjacent pixels to be hydrophobic and the first sub-part 152 near the second opening 151 to be hydrophilic, so that the ink of the light-emitting functional layer 140 of each pixel is formed in the corresponding second opening 151. Since the surface of the second sub-part 153 forms an ink-repellent interface, the ink of the light-emitting functional layer 140 of adjacent pixels can be prevented from mixing on the surface of the second sub-part 153.

[0053] In some embodiments, please refer to Figure 9 The pixel definition layer 150 further includes a second sub-pixel definition layer 1502. The second sub-pixel definition layer 1502 is located within the first spacing groove 132 and partially above the first electrode 131. The second sub-pixel definition layer 1502 fills the first spacing groove 132 and covers the extension end of the gain electrode 1312 to ensure the separation between adjacent first electrodes 131. The second sub-pixel definition layer 1502 is located above the first sub-planarization layer 122 and contacts the surface of the first sub-planarization layer 122 away from the array substrate 110. The second sub-pixel definition layer 1502 is hydrophilic. Please refer to... Figures 8-9 Since the first sub-planarization layer 122 of the display panel 100 includes multiple first openings 121 in the second direction Y, meaning that the first sub-planarization layer 122 between adjacent first openings 121 in the second direction Y is not separated, the second sub-pixel defining layer 1502 is located on the end face of the first sub-planarization layer 122 and fills the second spacing groove 123. The second sub-pixel defining layer 1502 is relatively thin, being a thin film region, and therefore exhibits hydrophilicity, similar to the first sub-part 152 described above. The hydrophilicity of the second sub-pixel defining layer 1502 is beneficial for the uniform spreading of ink.

[0054] for Figures 6-7 For an example, please refer to... Figure 4 and Figure 6 Since each pixel of the display panel 100 is independently inkjet printed, adjacent first sub-flattening layers 122 are separated by first sub-pixel definition layers 1501. The hydrophobic effect of the second sub-part 153 is used to prevent adjacent pixels from mixing colors during inkjet printing.

[0055] for Figures 7-8 For an example, please refer to... Figure 4 , Figure 7 and Figure 9 ,in Figure 4 for Figure 7 Sectional view at point AA, Figure 9 for Figure 7A cross-sectional view at point BB. Because the multiple pixels of the display panel 100 along the second direction Y are printed using a single inkjet print, therefore, as... Figure 9 As shown, there is no need to set a hydrophobic second sub-part 153 between adjacent pixels along the second direction Y. Instead, the hydrophilicity of the second sub-pixel definition layer 1502 allows the ink to spread evenly, ensuring uniform ink distribution in each pixel. Meanwhile, multiple pixels along the first direction X are independently printed using inkjet printing. Therefore, as... Figure 4 As shown, adjacent first sub-flattening layers 122 along the first direction X are separated by a first sub-pixel defining layer 1501. The hydrophobic effect of the second sub-part 153 is used to prevent adjacent pixels along the first direction X from mixing during inkjet printing.

[0056] Please refer to the following in this application: Figure 3 The array substrate 110 includes a substrate 111, a driving circuit layer 112, and a second planarization layer 113. The driving circuit layer 112 is disposed above the substrate 111 and includes a gate, a gate insulating layer, an active layer, and source and drain electrodes, wherein the source and drain electrodes are connected to the active layer. The structure of the driving circuit layer 112 can refer to the thin-film transistor structure in the prior art and is not limited thereto. The second planarization layer 113 is disposed on the side of the driving circuit layer 112 away from the substrate 111. Specifically, the second planarization layer 113 is located on the side of the source and drain electrodes away from the active layer, and vias are provided on the second planarization layer 113. A first planarization layer 120 is disposed on the side of the second planarization layer 113 away from the driving circuit layer 112; a first electrode layer 130 is connected to the source or drain electrode through vias.

[0057] Furthermore, the display panel 100 also includes an encapsulation layer (not shown in the figure), which covers the second electrode layer 160 to protect the display panel 100. The encapsulation layer may include one or more inorganic or organic films, and no specific limitations are imposed here.

[0058] In some embodiments, the material of the first planarization layer 120 is the same as that of the second planarization layer 113. The first planarization layer 120 and the second planarization layer 113 can be formed using the same process, for example, they can be patterned using a half-tone photomask process to form the patterns of the second planarization layer 113 and the first planarization layer 120 at the same time, so as to save photomask processes and simplify the process.

[0059] In other embodiments, the first planarization layer 120 and the second planarization layer 113 can also be patterned in two steps, that is, the second planarization layer 113 is patterned by one photomask process and the first planarization layer 120 is patterned by one photomask process, without limitation.

[0060] This application also provides a method for manufacturing a display panel 100, the method comprising:

[0061] S1. An initial first planarization layer is formed on the array substrate 110, and the initial first planarization layer is patterned to form a first planarization layer 120, the first planarization layer 120 including a plurality of first openings 121.

[0062] The first planarization layer 120 may include a plurality of first sub-planarization layers 122 spaced apart, each first sub-planarization layer 122 having one or at least two first openings 121. The material of the first planarization layer 120 may be an organic material, such as polyimide (PI), organic resin, etc., but is not limited thereto.

[0063] S2. An initial first electrode layer is formed on the side of the first planarization layer 120 away from the array substrate 110. The initial first electrode layer is patterned to form a first electrode layer 130. The first electrode layer 130 includes a plurality of first electrodes 131. The plurality of first electrodes 131 correspond one-to-one with a plurality of first openings 121. The first electrode 131 includes a main electrode 1311 and a gain electrode 1312 extending from the edge of the main electrode 1311. The main electrode 1311 is located on the bottom wall 1211 of the first opening 121, and the gain electrode 1312 is located on the side wall 1212 of the first opening 121. The gain electrode 1312 is higher than the position of the main electrode 1311 within the first opening 121.

[0064] The first electrode 131 is spaced apart, and a first gap 132 is formed between adjacent first electrodes 131. At least a portion of the pixel definition layer 150 is located within the first gap 132. The first electrode layer 130 can be an anode, and the material of the first electrode layer 130 includes at least one of metal oxide or metal. The metal oxide can be indium tin oxide (ITO), etc., and the metal can be Ag, Mg, Al, etc., but is not limited thereto.

[0065] S3. A light-emitting functional layer 140 is formed on the first electrode layer 130, and the light-emitting functional layer 140 is located on the main electrode 1311 and the gain electrode 1312.

[0066] The light-emitting functional layer 140 can be printed into the first opening 121 by inkjet printing to form the light-emitting functional layer 140. The light-emitting functional layer 140 includes at least an organic light-emitting layer, and may also include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL), etc., without limitation.

[0067] S4. A second electrode layer 160 is formed on the light-emitting functional layer 140.

[0068] The second electrode layer 160 covers the light-emitting functional layer 140 and the pixel definition layer 150. The second electrode layer 160 can be a cathode, and the material of the second electrode layer 160 includes metals, such as Al and Mg, but is not limited to these.

[0069] In some embodiments, the method further includes the following step before step S3:

[0070] An initial pixel definition layer is formed on the side of the first electrode layer 130 and the first planarization layer 120 away from the array substrate 110. The initial pixel definition layer is patterned to form a pixel definition layer 150. The pixel definition layer 150 includes a plurality of second openings 151. The second openings 151 at least partially overlap with the first openings 121. The gain electrode 1312 extends to the end face of the first planarization layer 120, and the extension end of the gain electrode 1312 is located at the intersection of the first planarization layer 120 and the pixel definition layer 150.

[0071] In this embodiment, the light-emitting functional layer 140 is located within the pixel opening formed by the first opening 121 and the second opening 151, and covers the first electrode layer 130. The light-emitting surface of the light-emitting functional layer 140 is higher than the gain electrode 1312 and is connected to the pixel definition layer 150.

[0072] The pixel definition layer 150 further fills the first spacer groove 132 between adjacent first electrodes 131 and the second spacer groove 123 between adjacent first sub-planarization layers 122. The material of the pixel definition layer 150 can be an organic material, such as polyimide (PI), organic resin, etc., but is not limited thereto.

[0073] In some embodiments, the step of forming a first planarization layer 120 on the array substrate 110 includes:

[0074] S11, Provide a substrate 111.

[0075] The substrate 111 can be a flexible substrate, such as polyimide (PI), or a rigid substrate, such as glass, but is not limited thereto.

[0076] S12. A driving circuit layer 112 is formed above the substrate 111.

[0077] The driving circuit layer 112 includes a gate, a gate insulating layer, an active layer, and a source and a drain. The source and drain are connected to the active layer. The fabrication method of the driving circuit layer 112 can refer to the fabrication method of thin film transistor structure in the prior art, and is not limited here.

[0078] S13. An initial planarization layer is formed on the side of the driving circuit layer 112 away from the substrate 111. The initial planarization layer is patterned to form a second planarization layer 113 and a first planarization layer 120. The second planarization layer 113 includes vias connecting the source and drain. The first planarization layer 120 is located on the side of the second planarization layer 113 away from the driving circuit layer 112, and the first planarization layer 120 includes a plurality of first openings 121.

[0079] In this embodiment, the material of the first planarization layer 120 is the same as that of the second planarization layer 113. The first planarization layer 120 and the second planarization layer 113 can be formed using the same process to save on photomask processes.

[0080] In other embodiments, the step of forming a first planarization layer 120 on the array substrate 110 includes:

[0081] S11, Provide a substrate 111;

[0082] S12. A driving circuit layer 112 is formed above the substrate 111;

[0083] S13. An initial second planarization layer is formed on the side of the driving circuit layer 112 away from the substrate 111. The initial second planarization layer is patterned to form a second planarization layer 113. The second planarization layer 113 includes vias connecting the source and the drain.

[0084] S14. An initial first flattening layer is formed on the side of the second flattening layer 113 away from the driving circuit layer 112. The initial first flattening layer is patterned to form a first flattening layer 120, which includes a plurality of first openings 121.

[0085] In this embodiment, the materials of the first planarization layer 120 and the second planarization layer 113 may be the same or different, and the first planarization layer 120 and the second planarization layer 113 may be patterned using a photomask process.

[0086] This application provides a display panel. The display panel first forms a first planarization layer on an array substrate. The first planarization layer includes a plurality of first openings. Then, a first electrode layer is formed on the first planarization layer. The first electrode layer includes a plurality of first electrodes, including a main electrode and a gain electrode. The main electrode covers the bottom wall of the first opening, and the gain electrode is formed on the side wall of the first opening. A light-emitting functional layer is then formed on the first electrode layer. The light-emitting functional layer covers the main electrode located on the bottom wall of the first opening and the gain electrode located on the side wall of the first opening. Therefore, the light-emitting functional layer located on the side wall of the first opening can also emit light. The display panel of this application increases the emitted light from different angles of the light-emitting functional layer on the side wall of the first opening, and simultaneously increases the overall light-emitting area of ​​the light-emitting functional layer, thus effectively improving the viewing angle and enhancing the display effect of the display panel.

[0087] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0088] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0089] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0090] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, include: Array substrate; A first planarization layer is disposed above the array substrate. The first planarization layer includes a plurality of first sub-planarization layers spaced apart along a first direction. A second spacing groove is provided between adjacent first sub-planarization layers. The first sub-planarization layer includes a plurality of first openings arranged along a second direction. The first direction intersects the second direction. The first electrode layer includes a plurality of first electrodes arranged in an array along the first direction and the second direction. A first spacing groove is provided between adjacent first electrodes, and the second spacing groove communicates with the first spacing groove. The first electrode includes a main electrode and a gain electrode extending from the edge of the main electrode. The main electrode is located on the bottom wall of the first opening, and the gain electrode is located on the side wall of the first opening. The gain electrode is higher than the position of the main electrode in the first opening. A light-emitting functional layer is disposed on the main electrode and the gain electrode; as well as The pixel definition layer includes a first sub-pixel definition layer and a second sub-pixel definition layer; The first sub-pixel definition layer is located between adjacent pixels along the first direction, and the first sub-pixel definition layer is located within the second spacing groove and the first spacing groove. The first sub-pixel definition layer includes a first sub-part located above the first sub-planarization layer and a second sub-part located between adjacent first sub-planarization layers. The first sub-part is connected to the second sub-part. In the direction perpendicular to the array substrate, the thickness of the second sub-part is greater than the thickness of the first sub-part. The first sub-part is hydrophilic, and the second sub-part is hydrophobic. The second subpixel definition layer is located between adjacent pixels along the second direction, and the second subpixel definition layer is located within the first spacing groove. The second subpixel definition layer is located above the first sub-planarization layer and is in contact with the side surface of the first sub-planarization layer away from the array substrate. The second subpixel definition layer is hydrophilic.

2. The display panel according to claim 1, characterized in that, The pixel definition layer is disposed above the first flat layer, and the pixel definition layer includes a plurality of second openings, the second openings at least partially overlapping the first openings.

3. The display panel according to claim 2, characterized in that, The light-emitting functional layer is located within the pixel opening formed by the first opening and the second opening. The light-emitting surface of the light-emitting functional layer is higher than the gain electrode and is connected to the pixel definition layer.

4. The display panel according to claim 2, characterized in that, The gain electrode extends to the end face of the first planarization layer, and the extended end of the gain electrode is located at the intersection of the pixel definition layer and the first planarization layer.

5. The display panel according to claim 4, characterized in that, The first sub-pixel definition layer is located above the first electrode.

6. The display panel according to claim 4, characterized in that, The second sub-pixel definition layer is located above the first electrode.

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