Managing three-dimensional semiconductor devices

Abstract

Systems, apparatuses, and methods for managing three-dimensional semiconductor devices are provided. In an aspect, a method includes forming a plurality of strings of memory cells in a first side of a semiconductor substrate having a semiconductor material, forming a plurality of alternating strips of the semiconductor material and an isolation material in a second, opposite side of the semiconductor substrate, and forming bit lines in the second side of the semiconductor substrate. The bit lines can be formed by depositing a layer of a metal material on the alternating strips of the semiconductor material and the isolation material, and by forming each of the bit lines in a corresponding strip of the semiconductor material of the alternating strips by forming a composite conductive material based on the metal material and the semiconductor material in the corresponding strip of the semiconductor material.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and manufacturing processes for semiconductor devices. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive because they can increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuitry to facilitate the operation of the memory array. Memory cells may include vertical transistors. Summary of the Invention

[0003] This disclosure describes methods, apparatus, systems, and techniques for managing three-dimensional (3D) semiconductor devices (e.g., vertical transistors and bit lines forming 3D memory devices).

[0004] A feature of this disclosure is a method comprising: forming a plurality of memory cell strings in a first side of a semiconductor substrate along a vertical direction, the semiconductor substrate comprising a semiconductor material; forming a plurality of alternating strips of semiconductor material and isolation material in a second side of the semiconductor substrate along a horizontal direction perpendicular to the vertical direction, the second side being opposite to the first side in the vertical direction; and forming a plurality of bit lines in the second side of the semiconductor substrate. Forming the plurality of bit lines comprises: depositing a metal material layer on the plurality of alternating strips of semiconductor material and isolation material; and forming each of the plurality of bit lines in the corresponding strips of semiconductor material by forming a composite conductive material based on the metal material and semiconductor material in the corresponding strips of semiconductor material of the plurality of alternating strips.

[0005] In some embodiments, forming a composite conductive material based on a metal and a semiconductor material in a corresponding strip of semiconductor material includes annealing the metal and semiconductor materials, causing the metal and semiconductor materials to react to form the composite conductive material. There may be no reaction between the insulating material and the metal material deposited on the insulating material.

[0006] In some embodiments, the semiconductor material includes silicon, the insulating material includes oxide, and the composite conductive material includes silicide. In some examples, the metallic material includes nickel (Ni).

[0007] In some embodiments, the method further includes removing metal material residues from the second side of the semiconductor substrate after forming multiple bit lines in the second side. In some embodiments, removing metal material residues from the second side includes wet etching of metal material residues.

[0008] In some embodiments, forming multiple alternating strips of semiconductor material and isolation material in a second side of a semiconductor substrate includes: thinning the semiconductor substrate from the second side to expose the multiple alternating strips of semiconductor material and isolation material. The method may further include: implanting ions into the second side of the semiconductor substrate. Forming a composite conductive material based on a metal and semiconductor material in corresponding strips of semiconductor material may include: using implanted ions to form the composite conductive material based on a metal and semiconductor material.

[0009] In some embodiments, ion implantation into the second side of a semiconductor substrate includes: implanting semiconductor ions into the second side of the semiconductor substrate; implanting N+ type ions into the second side of the semiconductor substrate; and activating the implanted N+ type ions with the implanted semiconductor ions at an activation temperature.

[0010] In some embodiments, the semiconductor material includes silicon, the semiconductor ion includes germanium (Ge) ions, and the N+ type ion includes arsenic (As) ions or phosphorus (P) ions.

[0011] In some implementations, the activation temperature is lower than the nominal temperature used to activate N+ ions without implanting semiconductor ions. In some examples, the nominal temperature is about 900°C, and the activation temperature is in the range of about 500°C to about 600°C.

[0012] In some embodiments, thinning the semiconductor substrate from a second side includes: etching semiconductor material in the second side of the semiconductor substrate; and polishing the top surface of the etched semiconductor material in the second side of the semiconductor substrate.

[0013] In some embodiments, each memory cell in a plurality of memory cell strings includes a vertical transistor along a vertical direction. Forming a plurality of memory cell strings includes: forming a gate terminal of the vertical transistor by depositing at least one metal layer along a vertical direction on the inner surface of a trench; forming a first terminal of the vertical transistor by implanting ions from a first side of a semiconductor substrate; and forming a second terminal of the vertical transistor by implanting ions into a second side of the semiconductor substrate. In some examples, the first terminal is a source terminal and the second terminal is a drain terminal.

[0014] In some implementations, each of the multiple bit lines is formed on and coupled to the second terminal of the vertical transistor.

[0015] In some implementations, each memory cell in a plurality of memory cell strings also includes a capacitor coupled to a vertical transistor. Forming a plurality of memory cell strings may include forming a capacitor prior to forming the vertical transistor, the capacitor being positioned above the vertical transistor along a vertical direction.

[0016] In some embodiments, forming multiple memory cell strings includes forming a pair of independent vertical transistor gate terminals in the same trench along a vertical direction, the gate terminals being separated by an insulating material along a third direction perpendicular to the vertical and horizontal directions.

[0017] In some implementations, the method further includes forming an isolation region between adjacent independent vertical transistor pairs along a third direction.

[0018] In some implementations, multiple memory cell strings and multiple bit lines are formed in the array die. The method further includes integrating the control die with the array die by bonding a first side of a semiconductor substrate to the front side of the control die and electrically coupling one or more conductive lines of the array die to control circuitry in the front side of the control die.

[0019] Another aspect of this disclosure features a semiconductor device comprising: a plurality of memory cell strings along a vertical direction on a first side of a semiconductor substrate, the semiconductor substrate comprising a semiconductor material; and a plurality of bit lines on a second side of the semiconductor substrate, the second side being in the opposite vertical direction to the first side, wherein adjacent bit lines among the plurality of bit lines are separated by an insulating material along a horizontal direction perpendicular to the vertical direction. The plurality of bit lines are made of a composite conductive material based on the semiconductor material, and the plurality of bit lines are located on a layer of semiconductor material having implanted ions.

[0020] In some embodiments, the implanted ions include semiconductor ions and N+ type ions. In some examples, the semiconductor material includes silicon, the semiconductor ions include germanium (Ge) ions, the N+ type ions include arsenic (As) ions or phosphorus (P) ions, and the composite conductive material includes silicides.

[0021] In some implementations, each memory cell in a plurality of memory cell strings includes a vertical transistor along a vertical direction, and a portion of a layer of semiconductor material with implanted ions is configured as a terminal of the vertical transistor and electrically coupled to the corresponding bit line.

[0022] In some implementations, the gate terminals of a pair of independent vertical transistors are located in the same trench along the vertical direction and separated by an insulating material along a third direction perpendicular to both the vertical and horizontal directions, with an isolation region along this third direction between adjacent pairs of independent vertical transistors. In some examples, the isolation region includes a cavity surrounded by an insulating material or a cavity filled with a metallic material.

[0023] Another aspect of this disclosure features a system comprising a memory device and a controller coupled to and configured to control the memory device. The memory device includes: an array structure comprising a plurality of memory cell strings along a vertical direction in a first side of a semiconductor substrate, the semiconductor substrate comprising a semiconductor material; and a plurality of bit lines located in a second side of the semiconductor substrate, the second side being in the opposite vertical direction to the first side, wherein adjacent bit lines among the plurality of bit lines are separated by an insulating material along a horizontal direction perpendicular to the vertical direction, wherein the plurality of bit lines are made of a composite conductive material based on the semiconductor material, and wherein the plurality of bit lines are located on a layer of semiconductor material having implanted ions.

[0024] Another aspect of this disclosure is a method comprising: forming a plurality of memory cell strings in a first side of a semiconductor substrate along a vertical direction, the semiconductor substrate comprising a semiconductor material; thinning the semiconductor substrate from a second side along a vertical direction, the second side being opposite to the first side of the semiconductor substrate; and implanting semiconductor ions into the second side of the semiconductor substrate.

[0025] In some embodiments, the method further includes: implanting N+ type ions into a second side of a semiconductor substrate, and activating the implanted N+ type ions at an activation temperature.

[0026] In some embodiments, the semiconductor material includes silicon, the semiconductor ion includes germanium (Ge) ions, and the N+ type ion includes arsenic (As) ions or phosphorus (P) ions.

[0027] In some implementations, the activation temperature is lower than the nominal temperature used to activate N+ ions without implanting semiconductor ions.

[0028] In some embodiments, thinning the semiconductor substrate along a vertical direction from a second side of the semiconductor substrate includes thinning the semiconductor substrate to expose multiple alternating strips of semiconductor material and insulating material. The method further includes forming multiple bit lines in the second side of the semiconductor substrate based on the multiple alternating strips of semiconductor material.

[0029] In some embodiments, forming multiple bit lines on a second side of a semiconductor substrate includes: depositing a metal material layer on multiple alternating strips of semiconductor material and insulating material; and forming each of the multiple bit lines in a corresponding strip by forming a composite conductive material based on the metal material and semiconductor material in a corresponding strip of the multiple strips of semiconductor material. The metal material may include nickel (Ni).

[0030] In some embodiments, forming a composite conductive material based on a metal and a semiconductor material in a corresponding strip includes annealing the metal and semiconductor materials to allow the metal and semiconductor materials to react and form the composite conductive material. There may be no reaction between the insulating material and the metal material deposited on the insulating material.

[0031] In some embodiments, forming a composite conductive material based on a metal and a semiconductor material in a corresponding strip includes: forming a composite conductive material based on a metal and a semiconductor material using activated implanted N+ ions.

[0032] In some embodiments, each memory cell in a plurality of memory cell strings includes a vertical transistor along a vertical direction. Forming a plurality of memory cell strings includes: forming a gate terminal of the vertical transistor by depositing at least one metal layer along a vertical direction on the inner surface of a trench; forming a first terminal of the vertical transistor by implanting N+ type ions from a first side of a semiconductor substrate; and forming a second terminal of the vertical transistor by implanting N+ type ions into a second side of the semiconductor substrate. In some examples, the first terminal is a source terminal and the second terminal is a drain terminal.

[0033] Embodiments of this disclosure may provide one or more of the following technical advantages and / or benefits. For example, the technology enables the formation of self-aligned bit lines on the back side of a semiconductor substrate via strips of semiconductor material, for example, by forming a composite conductive material (e.g., metal silicide) based on a metallic material (e.g., Ni) and a semiconductor material (e.g., Si). Furthermore, compared to the complex manufacturing processes for forming the metal used for the bit lines, forming self-aligned bit lines allows for an expanded process window and simplifies and / or minimizes process steps, such as omitting Si and polysilicon trench processes, oxide stamping, and several other processes, which can reduce manufacturing costs and increase manufacturing speed.

[0034] In some embodiments, the first and second terminals (e.g., source and drain terminals) of a vertical transistor are formed on opposite ends of the semiconductor body of the vertical transistor. The first terminal can be formed on the first end of the semiconductor body by implanting N+ ions from the front side of the semiconductor substrate and activating the N+ ions in the first end. The second terminal can be formed by implanting N+ ions from the back side of the semiconductor substrate and activating the N+ ions in the second end. In some cases, by germanium (Ge) pre-amorphization implantation (Ge PAI), the activation temperature of the N+ ions in the second end can be reduced, for example, from over 900°C to a low thermal temperature, such as 500°C to 600°C, which can reduce the thermal budget of the process. Furthermore, the second terminal of the vertical transistor can be formed by directly implanting N+ ions from the back side of the semiconductor substrate into the second end of the semiconductor body of the vertical transistor, which can expand the process window and reduce manufacturing costs.

[0035] This technology can also reduce the thickness requirements for performing chemical mechanical polishing (CMP) to thin the semiconductor substrate from the back side. Furthermore, composite conductive materials (e.g., silicides) can be formed using self-alignment for bit line metal connections, combined with forming a first terminal from the front side to reduce the cutoff current Ioff and increase the on-current Ion, and combined with forming a second terminal from the back side and using N+-doped silicides to form ohmic contacts to increase Ion. This can significantly improve the performance of vertical transistors, memory cells including vertical transistors, and / or 3D semiconductor devices including memory cells. This technology enables the simplification or optimization of the fabrication process for 3D semiconductor devices and reduces manufacturing costs.

[0036] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0037] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate various aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to implement and use this disclosure.

[0038] Figure 1 A cross-sectional view of an example 3D semiconductor device is shown.

[0039] Figure 2 A perspective view of an example 3D semiconductor device is shown.

[0040] Figure 3A A cross-sectional view of an example 3D semiconductor device including vertical transistors and bit lines is shown.

[0041] Figure 3BIt shows Figure 3A Example 3D top view of a semiconductor device.

[0042] Figure 4A An example structure is shown, illustrating the terminals of a vertical transistor formed by implanting N+ type ions from the front side of a semiconductor substrate.

[0043] Figure 4B Another example structure is shown, illustrating the terminals of a vertical transistor formed by implanting N+ type ions from the back side of a semiconductor substrate.

[0044] Figures 5A-5D Cross-sectional views of the structure of a 3D semiconductor device are shown at various stages of the manufacturing process.

[0045] Figure 6A A cross-sectional view of an example structure before the bit lines are formed is shown.

[0046] Figure 6B A cross-sectional view of an example structure after the bit lines are formed is shown.

[0047] Figure 7A This is a flowchart of an example process for forming a semiconductor device.

[0048] Figure 7B This is a flowchart of another example process for forming a semiconductor device according to one or more embodiments of the present disclosure.

[0049] Figure 8 A block diagram of an example system having one or more semiconductor devices is shown.

[0050] The same reference numerals and names in the various figures indicate the same elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0051] Figure 1 A side view of a cross-section of an example 3D semiconductor device 100 is shown. The 3D semiconductor device 100 may be a 3D dynamic random access memory (DRAM). It should be understood that... Figure 1 For illustrative purposes only and may not necessarily reflect the actual device structure (e.g., interconnects) in practice. In some embodiments, the 3D semiconductor device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of the first semiconductor structure 102. The first semiconductor structure 102 and the second semiconductor structure 104 may be bonded at a bonding interface 106 between them.

[0052] like Figure 1As shown, the first semiconductor structure 102 may include a substrate 110, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. The first semiconductor structure 102 may include peripheral circuitry 112 on and / or within the substrate 110. In some embodiments, the peripheral circuitry 112 includes a plurality of transistors 114 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of transistors 114) may also be formed on or within the substrate 110. In some examples, the peripheral circuitry 112 is formed using complementary metal-oxide-semiconductor (CMOS) technology, and the first semiconductor structure 102 may also be formed on a semiconductor die, which may be referred to as a control die or CMOS die 102.

[0053] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 116 above the peripheral circuitry 112 for transmitting electrical signals to and from the peripheral circuitry 112. The interconnect layer 116 may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and via contacts. The interconnect layer 116 may also include one or more interlayer dielectric (ILD) layers, in which interconnects and via contacts can be formed. That is, the interconnect layer 116 may include interconnects and via contacts in multiple ILD layers. In some embodiments, the peripheral circuitry 112 is coupled to each other through interconnects in the interconnect layer 116. The interconnects in the interconnect layer 116 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may be formed with dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0054] like Figure 1 As shown, the first semiconductor structure 102 has a front side and a back side, and the first semiconductor structure 102 may further include a bonding layer 118 on the back side at the bonding interface 106 and above the interconnect layer 116 and the peripheral circuitry 112. The bonding layer 118 may include a plurality of bonding contacts 119 and a dielectric for electrically isolating the bonding contacts 119. The bonding contacts 119 may include a conductive material, such as Cu. The remaining region of the bonding layer 118 may be formed using a dielectric material (e.g., silicon oxide). The bonding contacts 119 in the bonding layer 118 and the surrounding dielectric may be used for hybrid bonding. Similarly, as Figure 1As shown, the second semiconductor structure 104 may also include a bonding layer 120 at the bonding interface 106 and above the bonding layer 118 of the first semiconductor structure 102. The bonding layer 120 may include a plurality of bonding contacts 121 and a dielectric material for electrically isolating the bonding contacts 121. The bonding contacts 121 may include a conductive material, such as Cu. The remaining region of the bonding layer 120 may be formed using a dielectric material (e.g., silicon oxide). The bonding contacts 121 in the bonding layer 120 and the surrounding dielectric material may be used for hybrid bonding. The bonding contacts 121 may contact the bonding contacts 119 at the bonding interface 106. In some embodiments, the bonding layer 120 includes a dielectric layer opposite a memory cell (e.g., a DRAM cell) 124, wherein bit lines 123 are located between the dielectric layer and the memory cell 124, such as... Figure 1 As shown. The dielectric layer may include a bonding interface 106 having bonding contacts 121.

[0055] The second semiconductor structure 104 can be bonded face-to-face to the top of the first semiconductor structure 102 at the bonding interface 106. In some embodiments, as a result of hybrid bonding (also referred to as “metal / dielectric hybrid bonding”), the bonding interface 106 is disposed between the bonding layers 120 and 118. This hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer, such as solder or adhesive), and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 106 is where the bonding layers 120 and 118 meet and bond. In some examples, the bonding interface 106 can be a layer of a certain thickness, comprising the top surface of the bonding layer 118 of the first semiconductor structure 102 and the bottom surface of the bonding layer 120 of the second semiconductor structure 104.

[0056] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 122, which includes bit lines 123 above the bonding layer 120 for transmitting electrical signals. The interconnect layer 122 may include multiple interconnects, such as mid-stage (MEOL) interconnects and back-end stage (BEOL) interconnects. In some embodiments, the interconnects in the interconnect layer 122 also include local interconnects, such as bit lines 123 and word line contacts (not shown). The interconnect layer 122 may also include one or more ILD layers, in which interconnect lines and via contacts can be formed. The interconnects in the interconnect layer 122 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may be formed with dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0057] In some embodiments, peripheral circuitry 112 includes a word line driver / row decoder coupled to word line contacts in interconnect layer 122 via bonding contacts 121 and 119 in bonding layers 120 and 118, and interconnect layer 116. In some embodiments, peripheral circuitry 112 includes a bit line driver / column decoder coupled to bit lines 123 and bit line contacts in interconnect layer 122 via bonding contacts 121 and 119 in bonding layers 120 and 118, and interconnect layer 116. In some embodiments, bit line 123 is a metallic bit line, in contrast to semiconductor bit lines (e.g., doped silicon bit lines). For example, bit line 123 may comprise W, Co, Cu, Al, or any other suitable metal having a higher conductivity than doped silicon. In some embodiments, the bit line contacts are ohmic contacts instead of Schottky contacts.

[0058] In some embodiments, such as those discussed in further detail below, bit line 123 may be made of a composite conductive material that can be based on a metallic material (e.g., W, Co, Cu, Al) and a semiconductor material (e.g., Si). For example, the composite conductive material may include metal silicides such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon.

[0059] In some embodiments, the second semiconductor structure 104 includes a DRAM device, wherein memory cells are disposed above the interconnect layer 122 and the bonding layer 120 in the form of an array of DRAM cells 124. That is, the interconnect layer 122, including bit lines 123, may be disposed between the bonding layer 120 and the array of DRAM cells 124. The bit lines 123 in the interconnect layer 122 may be coupled to a string of DRAM cells 124. In some embodiments, the second semiconductor structure 104 is formed on a semiconductor die and may be referred to as an array die 104.

[0060] In some embodiments, the semiconductor device may include a plurality of array dies (e.g., array die 104) and CMOS dies (e.g., CMOS die 102). The array dies and CMOS dies may be stacked and bonded together. A CMOS die may be coupled to each of the array dies, and each of the array dies may be driven to operate in a manner similar to that of the semiconductor device. The semiconductor device may be any suitable device. In some examples, the semiconductor device includes at least a first wafer and a second wafer bonded face-to-face. Array dies may be disposed on the first wafer along with other array dies, and CMOS dies may be disposed on the second wafer along with other CMOS dies. The first and second wafers may be bonded together, so that an array die on the first wafer may be bonded to a corresponding CMOS die on the second wafer. In some examples, the semiconductor device is a chip having at least array dies and CMOS dies bonded together. In one example, the chip is diced from the bonded wafer. In another example, the semiconductor device is a semiconductor package comprising one or more semiconductor chips assembled on a packaging substrate.

[0061] Each DRAM cell 124 may include a vertical transistor 126 and a capacitor 128 coupled to the vertical transistor 126. The DRAM cell 124 may be a 1T1C cell consisting of one transistor and one capacitor. It should be understood that the DRAM cell 124 may have any suitable structure, such as a 2T1C cell, a 3T1C cell, etc. The vertical transistor 126 may be a MOSFET for switching the corresponding DRAM cell 124. In some embodiments, the vertical transistor 126 includes a vertically (in the z-direction) extending semiconductor body 130 (in which an active region may form a channel) and a gate structure 136 contacting one side of the semiconductor body 130. In a single-gate vertical transistor, the semiconductor body 130 may have a cuboid or cylindrical shape, and the gate structure 136 may be adjacent to one side of the semiconductor body 130 in a plan view, for example, as shown in the figure. Figure 1 As shown. In some embodiments, the vertical transistor 126 has a structure including two or more gates, such as a dual-gate structure, a tri-gate structure, or a gate all-around (GAA) structure. In some embodiments, the gate structure 136 includes a gate electrode 134 and a gate dielectric 132 laterally located between the gate electrode 134 and the semiconductor body 130 in the bit line direction (e.g., in the x-direction). In some embodiments, the gate dielectric 132 is adjacent to one side of the semiconductor body 130, and the gate electrode 134 is adjacent to the gate dielectric 132.

[0062] like Figure 1As shown, in some embodiments, the semiconductor body 130 has two ends in the vertical direction (z-direction). Figure 1 The semiconductor body 130 has an upper and lower end portion, and at least one end portion (e.g., the lower end portion) extends in the vertical direction (z-direction) beyond the gate dielectric 132 into the ILD layer. In some embodiments, one end portion (e.g., the upper end portion) of the semiconductor body 130 is flush with the corresponding end portion (e.g., the upper end portion) of the gate dielectric 132. In some embodiments, both ends portion (upper and lower) of the semiconductor body 130 extend in the vertical direction (z-direction) beyond the gate electrode 134 into the ILD layer. That is, the semiconductor body 130 may have a vertical dimension (e.g., depth) larger than the vertical dimension (e.g., depth) of the gate electrode 134, and neither the upper nor lower end portion of the semiconductor body 130 is flush with the corresponding end portion of the gate electrode 134. Therefore, short circuits between the bit line 123 and the word line / gate electrode 134 or between the word line / gate electrode 134 and the capacitor 128 can be avoided. The vertical transistor 126 may also include a source and a drain (both referred to as 138, as their positions can be interchanged) respectively disposed at two ends (upper and lower ends) of the semiconductor body 130 in the vertical direction (z-direction). In some embodiments, one of the source and drain 138 (e.g., in...) Figure 1 At the upper end of the middle) it is coupled to capacitor 128, and another of the source and drain 138 (e.g., in the upper end of the middle) ... Figure 1 At the lower end of the transistor, it is coupled to line 123. That is, the vertical transistor 126 may have a first terminal in the positive z-direction and a second terminal opposite to the first terminal in the negative z-direction, such as... Figure 1 As shown.

[0063] In some embodiments, the semiconductor body 130 comprises a semiconductor material, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 130 may comprise monocrystalline silicon. The source and drain 138 may be doped with an N+ type dopant (e.g., phosphorus (P) or arsenic (As)) or a P type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source / drain 138 of the vertical transistor 126 and the bit line 123 as a bit line contact, or formed between the source / drain 138 of the vertical transistor 126 and the first electrode of the capacitor 128 as a capacitor contact 142 to reduce contact resistance. In some embodiments, the gate dielectric 132 comprises a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode 134 comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode 134 comprises multiple conductive layers, such as a W layer over a TiN layer. In one example, the gate structure 136 may be a "gate oxide / gate polysilicon" gate, wherein the gate dielectric 132 comprises silicon oxide and the gate electrode 134 comprises doped polysilicon. In another example, the gate structure 136 may be an HKMG, wherein the gate dielectric 132 comprises a high-k dielectric and the gate electrode 134 comprises a metal.

[0064] As described above, since the gate electrode 134 can be part of a word line or extend as a word line in the word line direction (e.g., the y-direction), the second semiconductor structure 104 of the 3D semiconductor device 100 can also include multiple word lines, each extending in the word line direction (y-direction). Each word line 134 can be coupled to a row of DRAM cells 124. That is, the bit line 123 and the word line 134 can extend in two perpendicular lateral directions, and the semiconductor body 130 of the vertical transistor 126 can extend in a direction perpendicular to the two lateral directions in which the bit line 123 and the word line 134 extend. The word line 134 contacts a word line contact (not shown). In some embodiments, the word line 134 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the word line 134 includes multiple conductive layers, such as a W layer over a TiN layer, as... Figure 1 As shown.

[0065] In some implementations, such as Figure 1As shown, the vertical transistor 126 extends vertically through and contacts the word line 134, and the source or drain 138 of the vertical transistor 126 contacts the bit line 123 (or contacts the bit line contact, if any) at its lower end. Therefore, due to the vertical arrangement of the vertical transistor 126, the word line 134 and the bit line 123 can be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 134 and the bit line 123. In some embodiments, the bit line 123 is vertically disposed between the bonding layer 120 and the word line 134, and the word line 134 is vertically disposed between the bit line 123 and the capacitor 128. The word line 134 can be coupled to the peripheral circuitry 112 in the first semiconductor structure 102 via word line contacts (not shown) in the interconnect layer 122, bonding contacts 121 and 119 in the bonding layers 120 and 118, and interconnects in the interconnect layer 116. Similarly, bit lines 123 in interconnect layer 122 can be coupled to peripheral circuits 112 in the first semiconductor structure 102 via bonding contacts 121 and 119 in bonding layers 120 and 118 and interconnects in interconnect layer 116.

[0066] In some implementations, the vertical transistors 126 can be arranged in a mirror-symmetric manner to increase the density of DRAM cells 124 in the bit-line direction (x-direction). For example... Figure 1 As shown, two adjacent vertical transistors 126 in the bit line direction are mirror-symmetric to each other with respect to the trench isolation 160. That is, the second semiconductor structure 104 may include a plurality of trench isolations 160, each trench isolation 160 extending parallel to word line 134 in the word line direction (y-direction) and disposed between semiconductor bodies 130 of two adjacent rows of vertical transistors 126. In some embodiments, the rows of vertical transistors 126 separated by the trench isolations 160 are mirror-symmetric to each other with respect to the trench isolations 160. The trench isolations 160 may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. It should be understood that the trench isolations 160 may include air gaps, each air gap being laterally disposed between adjacent semiconductor bodies 130. Air gaps can be formed due to the relatively small spacing of the vertical transistors 126 in the bit line direction (e.g., the x-direction). On the other hand, the relatively large dielectric constant of air in the air gap (e.g., about 4 times that of silicon oxide) compared to some dielectrics (e.g., silicon oxide) can improve the insulation effect between the vertical transistors 126 (and the rows of DRAM cells 124). Similarly, in some embodiments, air gaps are also formed laterally between the word lines / gate electrodes 134 in the bit line direction, depending on the spacing of the word line / gate electrodes 134 in the bit line direction.

[0067] like Figure 1As shown, in some embodiments, capacitor 128 includes a first electrode 144 above the source or drain 138 of vertical transistor 126 (e.g., the upper end of semiconductor body 130) and coupled to the source or drain 138 of vertical transistor 126 via capacitor contact 142. In some embodiments, instead of Schottky contacts, capacitor contact 142 is an ohmic contact, such as a metal silicide contact. For example, capacitor contact 142 may include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon. Capacitor 128 may also include a capacitor dielectric above and in contact with the first electrode 144, and a second electrode above and in contact with the capacitor dielectric. That is, capacitor 128 may be a vertical capacitor, wherein the electrodes and capacitor dielectric are stacked vertically (in the z-direction), and the capacitor dielectric may be sandwiched between the electrodes. In some implementations, each first electrode is coupled to the source or drain 138 of a corresponding vertical transistor 126 in the same DRAM cell, while all second electrodes are coupled to a common plate 146, which is coupled to ground (e.g., common ground). The capacitor 128 may have a first end in the negative z-direction and a second end opposite to the first end in the positive z-direction, such as... Figure 1 As shown. In some embodiments, the first end of capacitor 128 is coupled to the first terminal of vertical transistor 126 via an ohmic contact (e.g., capacitor contact 142 made of metal silicide material). Figure 1 As shown, the second semiconductor structure 104 may further include capacitor contacts 147 (e.g., conductors) in contact with the common plate 146 for coupling the capacitor 128 to the peripheral circuit 112 or directly to ground. In some embodiments, the capacitor contacts 147 (e.g., conductors) extend in the z-direction from the dielectric layer of the bonding layer 120 to couple to a second end of the capacitor 128 via the common plate 146, such as... Figure 1 As shown. In some embodiments, the ILD layer forming capacitor 128 has the same dielectric material, such as silicon oxide, as the two ILD layers into which semiconductor body 130 extends.

[0068] It should be understood that the structure and configuration of capacitor 128 are not limited to Figure 1Examples are provided, and any suitable structure and configuration may be included, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-substrate capacitors. In some embodiments, the capacitor dielectric comprises a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al₂O₃, HfO₂, Ta₂O₅, ZrO₂, TiO₂, or any combination thereof. It should be understood that in some examples, capacitor 128 may be a ferroelectric capacitor for use in an FRAM cell, and the capacitor dielectric may be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, the electrodes comprise conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0069] like Figure 1 As shown, a vertical transistor 126 extends vertically through and contacts word line 134. The source or drain 138 of the vertical transistor 126 contacts bit line 123 at its lower end, and the source or drain 138 of the vertical transistor 126 is coupled to capacitor 128 at its upper end. That is, due to the vertical arrangement of the vertical transistor 126, bit line 123 and capacitor 128 can be arranged in different planes in the vertical direction and coupled vertically to opposite ends of the vertical transistor 126 of the DRAM cell 124. In some embodiments, bit line 123 and capacitor 128 are arranged on opposite sides of the vertical transistor 126 in the vertical direction. Compared to DRAM cells where the bit line and capacitor are arranged on the same side of a planar transistor, this simplifies the wiring of bit line 123 and reduces the coupling capacitance between bit line 123 and capacitor 128.

[0070] like Figure 1 As shown, in some embodiments, the vertical transistor 126 is vertically disposed between the capacitor 128 and the bonding interface 106. That is, the vertical transistor 126 can be arranged closer to the peripheral circuitry 112 and the bonding interface 106 of the first semiconductor structure 102 than the capacitor 128. Since the bit line 123 and the capacitor 128 are coupled to opposite ends of the vertical transistor 126, the bit line 123 (as part of the interconnect layer 122) is vertically disposed between the vertical transistor 126 and the bonding interface 106. As a result, the interconnect layer 122, including the bit line 123, can be arranged close to the bonding interface 106 to reduce interconnect wiring distance and complexity.

[0071] In some embodiments, the second semiconductor structure 104 further includes a substrate 148 disposed above the DRAM cell 124. As described below with respect to the manufacturing process, the substrate 148 may be a portion of a carrier wafer. It should be understood that in some examples, the substrate 148 may not be included in the second semiconductor structure 104.

[0072] like Figure 1 As shown, the second semiconductor structure 104 may further include a pad output interconnect layer 150 above the substrate 148 and the DRAM cell 124. The pad output interconnect layer 150 may include interconnects in one or more ILD layers, such as contact pads 154. The pad output interconnect layer 150 and the interconnect layer 122 may be formed on opposite sides of the DRAM cell 124. A capacitor 128 may be vertically disposed between the vertical transistor 126 and the pad output interconnect layer 150. In some embodiments, the interconnects in the pad output interconnect layer 150 may transmit electrical signals between the 3D semiconductor device 100 and external circuitry, for example, for pad output purposes.

[0073] In some embodiments, the second semiconductor structure 104 further includes one or more contacts 152 extending through portions of the substrate 148 and the pad output interconnect layer 150 to couple the pad output interconnect layer 150 to the DRAM cell 124 and the interconnect layer 122. As a result, peripheral circuitry 112 can be coupled to the DRAM cell 124 via interconnect layers 116 and 122 and bonding layers 120 and 118, and peripheral circuitry 112 and the DRAM cell 124 can be coupled to external circuitry via the contacts 152 and the pad output interconnect layer 150. The contact pads 154 and contacts 152 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, the contact pad 154 may include Al, and the contact 152 may include W. In some embodiments, the contact 152 includes a via surrounded by a dielectric spacer (e.g., having silicon oxide) to electrically isolate the via from the substrate 148. Depending on the thickness of the substrate 148, the contact 152 can be an ILV with a submicron depth (e.g., between 10 nm and 1 μm) or a TSV with a micron or tens of micron depth (e.g., between 1 μm and 100 μm).

[0074] Although not shown, it should be understood that the pad outputs of 3D memory devices are not limited to those from sources such as... Figure 1 The second semiconductor structure 104 shown has DRAM cells 124 and may be derived from a first semiconductor structure 102 having peripheral circuitry 112. Although not shown, it should be understood that the air gaps between word lines 134 and / or between semiconductor bodies 130 may be partially or completely filled with dielectric. Although not shown, it should be understood that arrays of more than one DRAM cell 124 may be stacked vertically to proportionally increase the number of DRAM cells 124.

[0075] Figure 2A perspective view of an example 3D semiconductor device 200 is shown. The 3D semiconductor device 200 can be... Figure 1 3D semiconductor devices 100 or Figure 1 The structure of the intermediate manufacturing process of the 3D semiconductor device 100.

[0076] like Figure 2 As shown, the 3D semiconductor device 200 has a front side 201 and a back side 203 along the vertical direction (Z direction). The 3D semiconductor device 200 includes multiple bit lines 202 separated by an insulating material 204 (e.g., oxide) on the back side 203. The bit lines 202 can be connected to... Figure 1 Bit lines 123 are similar or identical. Bit line 202 may be separated along the Y direction and extend along the X direction. For example... Figure 2 As shown, bit line 202 has a depth along the vertical direction (Z direction). As discussed in further detail below, for example, in... Figures 5A-5D In 6A-6B, bit lines 202 can be formed by depositing metal material (e.g., Ni) layers on multiple alternating strips of semiconductor material (e.g., Si) and insulating material 204 (e.g., oxide), and forming a composite conductive material based on the metal and semiconductor materials (e.g., silicide such as NiSi) in the corresponding strips of semiconductor material. Therefore, bit lines 202 can be self-aligned.

[0077] The 3D semiconductor device 200 may include strings of memory cells on its front side 201. Each string of memory cells may be coupled to a corresponding bit line 202. The memory cells may be... Figure 1 The DRAM cell 124 is similar to or the same as the DRAM cell 124. The memory cell may include a vertical transistor (e.g., Figure 1 The vertical transistor 126) and the capacitor coupled to the vertical transistor (e.g., Figure 1 (Capacitor 128). In some embodiments, the gate structure of the two vertical transistors 212, 214 (e.g., Figure 1 The gate structure 136 can be formed in the trench structure 210 and separated by an isolation material 216 (e.g., oxide) in the trench structure 210. Adjacent trench structures 210 (or adjacent vertical transistors in adjacent trench structures 210) can be separated along the X direction by an isolation region 220 (e.g., Figure 1 The trench is separated (160).

[0078] Figure 3A A cross-sectional view (e.g., in the XZ plane) of an example 3D semiconductor device 300 including vertical transistors and bit lines is shown. Figure 3B It shows Figure 3A A top view (e.g., in the XY plane) of an example 3D semiconductor device 300. The 3D semiconductor device 300 can be... Figure 2 3D semiconductor devices 200 or Figure 1 3D semiconductor devices 100 or Figure 1 The structure of the 3D semiconductor device 100 during the intermediate manufacturing process. The 3D semiconductor device 300 can be manufactured through... Figures 4A-4B The methods and / or processes described in further detail in 5A-5D, 6A-6B and / or 7A-7B are formed.

[0079] like Figure 3B As shown, the 3D semiconductor device 300 includes multiple bit lines 302 extending along the X direction and multiple word lines (WL1, W2, ..., WL8, ...) 304 extending along the Y direction. Adjacent bit lines 302 are separated along the Y direction by an insulating material (e.g., such as...). Figure 2 The 204 oxide is separated, and adjacent word lines 304 are separated along the X direction by isolation region 306. Bit line 302 can be with Figure 1 bit line 123 or Figure 2 Bit line 202 is similar to or the same as bit line 202. Isolation region 306 can be with... Figure 1 trench isolation 160 or Figure 2 The isolation region 220 is similar to or the same as the isolation region 306. The isolation region 306 may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. It should be understood that the isolation region 306 may include air gaps laterally disposed between adjacent semiconductor bodies 314 (e.g., along the X direction).

[0080] The 3D semiconductor device 300 has a semiconductor substrate 301 comprising a semiconductor material (e.g., silicon). Memory cells (e.g., Figure 1 An array of memory cells 124 can be formed in a semiconductor substrate 301. Each memory cell may include a vertical transistor 310 (e.g., Figure 1 Vertical transistor 126 or Figure 2 (vertical transistor 212 or 214) and capacitors coupled to vertical transistor 310 (e.g., Figure 1 A DRAM memory cell (capacitor 128). The vertical transistor 310 may include a gate electrode (or gate terminal) 312, a semiconductor body 314, and a first terminal 315 and a second terminal 316 formed along a vertical direction (e.g., the Z direction) on opposite ends of the semiconductor body 314. One of the first terminal 315 and the second terminal 316 may be a source terminal, and the other of the first terminal 315 and the second terminal 316 may be a drain terminal. The first terminal 315 and the second terminal 316 may be connected to... Figure 1 Terminal 138 is similar to or the same as 138.

[0081] Semiconductor body 314 can be with Figure 1 The semiconductor body 130 is similar to or identical to the semiconductor body 314. The semiconductor body 314 may include a semiconductor material such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 314 may include monocrystalline silicon. As discussed in further detail below, each of the first terminal 315 and the second terminal 316 can be formed by implanting N+ type ions (e.g., P or As) or P type ions (e.g., B or Ga) into the end of the semiconductor body 314 at a desired doping level. In one example, the first terminal 315 represents a drain terminal (e.g., lightly doped drain-LDD), and the second terminal 316 represents a source terminal. In another example, the first terminal 315 represents a source terminal, and the second terminal 316 represents a drain terminal.

[0082] The gate electrode 312 may include one or more conductive layers, such as a W layer 312a above the TiN layer 312b, for example... Figure 3A As shown. The insulating material 311 can be formed as the gate dielectric between the semiconductor body 314 and the gate electrode 312 (e.g., Figure 1 The gate electrode 312 may be a portion of the word line 304 or may extend as the word line 304 in the word line direction (e.g., the Y direction). The gate electrode 312 and the gate dielectric may form a gate structure (e.g., Figure 1 (Gate structure 136).

[0083] In some embodiments, the 3D semiconductor device 300 includes a trench structure 308 separated by isolation regions 306 (e.g., Figure 2 The trench structure 210). Gate electrodes 312 of a pair of vertical transistors 310 can be formed in the trench structure 308 and separated by an insulating material 311. The bottom ends of the gate electrodes 312 of the vertical transistors 310 in the trench structure 308 can be separated by one or more insulating layers 307 (e.g., oxide), 317 (e.g., SiN), and 318 (e.g., oxide). The gate electrodes 312 can be separated and isolated from the first terminal 315 and the second terminal 316, for example, by the insulating material 311. For example, as... Figure 3A As shown, along the Z direction, the bottom of the gate electrode 312 is higher than the top surface of the second terminal 316, and the bottom of the second terminal 316 may be higher than the bottom of the trench structure 308.

[0084] The first terminal 315 of the vertical transistor 310 can be connected to the capacitor contact 322 (e.g., Figure 1 The capacitor contact 142) is coupled to the first electrode 324 of the capacitor (e.g., Figure 1The first electrode 324 may include a via contact comprising a conductive material (e.g., polysilicon). The first electrode 324 may include one or more conductive layers, such as a metal silicide 324a, an intermediate layer 324b (e.g., a TiN layer), and a metal layer 324c (e.g., a W layer) in contact with the capacitor contact 322. A dielectric layer 320 (e.g., comprising SiN) may be formed on top of the semiconductor substrate 301. The capacitor contact 322 may be at least partially formed in the dielectric layer 320 and may extend into the trench structure 308 to contact the first terminal 315 of the vertical transistor 310.

[0085] In some embodiments, the second terminal 316 of the vertical transistor 310 is coupled to the bit line 302, for example, through an intermediate region 313. The intermediate region 313 may be located between the bottom of the second terminal 316 of the vertical transistor 310 and the bit line 302. The intermediate region 313 may also be located between the bottom of the trench structure 308 and the bit line 302. As discussed in further detail below, for example… Figures 5B-5C The intermediate region 313 can be formed by implanting N+ type ions (e.g., P or As) into the back side of the semiconductor substrate 301. The ions implanted into the semiconductor substrate 301 can be referred to as dopants. The intermediate region 313 can have a higher dopant concentration than the second terminal 316 of the vertical transistor 310.

[0086] As discussed in further detail below, for example Figure 5D and 6B Bit lines 302 can be formed by depositing a metal material (e.g., Ni) layer on an intermediate region 313 (e.g., alternating strips of semiconductor material (e.g., Si) with implanted dopants and an isolation material (e.g., oxide), and then forming a composite conductive material (e.g., NiSi) based on the metal material and the semiconductor material with implanted dopants in the corresponding strips of semiconductor material. Conversely, the metal material does not react with the isolation material (e.g., oxide). Therefore, the metal material can be readily removed from the surface of the isolation material strips during an etching process (e.g., wet etching), and the composite conductive material in the corresponding strips of semiconductor material can remain unchanged during the etching process, allowing for the formation of self-aligned bit lines. The composite conductive material can be a silicide, such as a metal silicide.

[0087] Figure 4A An example structure 400 is shown, illustrating the terminals of a vertical transistor formed by implanting N+ type ions from the front side of a semiconductor substrate 401. The vertical transistor can be coupled with... Figure 1 Vertical transistor 126 Figure 2 Vertical transistors 212, 214 or Figure 3A The vertical transistor 310 is similar to or the same as that of the vertical transistor.

[0088] Structure 400 includes a trench 420 for forming a gate structure of a vertical transistor. The gate structure can be... Figure 1 The gate structure 136 is similar to or the same as the gate structure. The gate structure includes a gate electrode (e.g., Figure 1 Gate electrode 134 or Figure 3A The gate electrode 312) and the gate electrode and the semiconductor body 402 of the vertical transistor (e.g., Figure 1 Semiconductor body 130 or Figure 3A The gate dielectric (e.g., between the semiconductor body 314) and the semiconductor body 314 Figure 1 The gate dielectric 132). Structure 400 includes a dielectric layer 405 (e.g., oxide) on the inner surface of trench 420, which can be used to form the gate dielectric of the gate structure of a vertical transistor. Furthermore, the dielectric layer 405 can protect the semiconductor body 402 from N+ ions in a later process step where N+ ions are implanted from the opening of trench 420 to the bottom of trench 420.

[0089] Structure 400 may include an isolation region 410 between adjacent trenches 420 or adjacent semiconductor bodies 402 of a vertical transistor. The isolation region 410 may be... Figure 1 trench isolation 160, Figure 2 Quarantine area 220 or Figure 3A The isolation region 306 is similar to or the same as the isolation region 410. The isolation region 410 may be formed of a dielectric material 412, which surrounds an air gap 414 laterally disposed between adjacent semiconductor bodies 402 (e.g., along the X direction).

[0090] In structure 400, the first terminal 404 of the vertical transistor (e.g., Figure 3A The first terminal 315 is formed, for example, on the first end (e.g., the top) of the semiconductor body 402 of the vertical transistor at the front side of the semiconductor substrate 401 by implanting N+ type ions from the front side of the semiconductor substrate 401 into the region of the first terminal 404. The first terminal 404 may be an LDD.

[0091] In order to form a second terminal 406 (e.g., bottom end) on the second end (e.g., bottom end) of the semiconductor body 402 of the vertical transistor Figure 3A The second terminal 316), for example, as Figure 4AAs shown, N+ ions can be implanted from the opening of a trench 420 on the front side of a semiconductor substrate 401 to the bottom of the trench 420. The implanted ions can diffuse to the region of the second terminal 406 to form the second terminal 406 of a vertical transistor. One of the first terminal 404 and the second terminal 406 is a source terminal, and the other of the first terminal 404 and the second terminal 406 is a drain terminal. In one example, the width of the opening of the trench 420 is approximately tens of nm, for example, 40 nm to 50 nm.

[0092] Figure 4B Another example structure 430 is shown, illustrating the terminals of a vertical transistor formed by implanting N+ type ions from the back side of a semiconductor substrate 401. The vertical transistor can be coupled with... Figure 1 Vertical transistor 126 Figure 2 Vertical transistors 212, 214 or Figure 3A The vertical transistor 310 is similar to or the same as that of the vertical transistor.

[0093] At the second terminal 436 forming the vertical transistor (e.g., Figure 3A Before the second terminal 316), the first terminal 404 of the vertical transistor can be formed first (e.g., Figure 3A The first terminal 315) and / or gate structure 432 (e.g., Figure 1 The gate structure 432 may include a gate electrode 433 and a gate electrode 433 coupled to the gate electrode 433 (e.g., gate structure 136). Figure 1 Gate electrode 134 or Figure 3A The gate dielectric 434 (e.g., between the gate electrode 312) and the semiconductor body 402 Figure 1 The gate dielectric 132). Adjacent gate structures 432 in the same trench can be made of an insulating material 431 (e.g., Figure 2 216 or the isolation material Figure 3A The gate structures 432 in the same trench are isolated by an isolation material 311, and the gate structures 432 in the same trench can be covered by an isolation material 431. The gate structures 432 in the same trench can be separated by one or more isolation layers (e.g., SiN layer 437 and oxide layer 438) on the bottom of the trench.

[0094] and Figure 4A The difference in the structure is to form the second terminal 436 of the vertical transistor (e.g., Figure 3A The second terminal 316), in Figure 4BIn this process, N+ type ions (e.g., P) are implanted from the back side of the semiconductor substrate 401. The structure 430 can be flipped, and the semiconductor substrate 401 can be thinned from the back side (e.g., by chemical mechanical polishing - CMP) to a thickness of, for example, about 100 nm. Then, N+ type ions can be directly implanted into the back side of the semiconductor substrate 401 to form a second terminal 436 at the bottom end of the semiconductor body 402, which can be achieved compared to forming... Figure 4A The second terminal 406 is formed faster and easier. Furthermore, since the second terminal 436 is formed through direct injection rather than diffusion, the second terminal 436 can have a higher density than... Figure 4A The second terminal 406 in the semiconductor substrate has a more uniform dopant concentration. Furthermore, the process window is much larger than that of implanting N+ ions across the entire back surface of the semiconductor substrate 401. Figure 4A The opening of the trench 420 for injection from the front side of the semiconductor substrate 401.

[0095] In some implementations, germanium (Ge) pre-amorphization implantation (Ge PAI) is performed for low-thermal activation prior to the implantation of N+ ions. In some examples, semiconductor ions (e.g., Ge ions) are implanted to a certain depth (e.g., in the range of 20 nm to 40 nm), followed by the implantation of N+ ions (e.g., P ions), and the structure is activated at a low temperature (e.g., 500 °C to 600 °C) below the nominal temperature (e.g., 900 °C).

[0096] Figures 5A-5D Cross-sectional views (in the XZ plane) of the structure of a 3D semiconductor device are shown at various stages of the manufacturing process. Figures 6A-6B Cross-sectional views (in the YZ plane) of some structures of 3D semiconductor devices are shown to further illustrate the manufacturing process. 3D semiconductor devices can be... Figures 3A-3B 3D semiconductor devices 300, Figure 2 3D semiconductor devices 200 Figure 1 3D semiconductor devices 100 or Figure 1 The structure of the intermediate manufacturing process of the 3D semiconductor device 100.

[0097] 3D semiconductor devices include vertical transistors 510 formed in a semiconductor substrate 501 (e.g., Figure 1 Vertical transistor 126 Figure 2 Vertical transistors 212, 214 or Figure 3A Vertical transistor 510. Vertical transistor 510 extends along a vertical direction (e.g., the Z direction). As described above, vertical transistor 510 may include semiconductor body 512 (e.g., Figure 1 Semiconductor body 130, Figure 3A Semiconductor body 314 or Figure 4A Or the semiconductor body 402 of 4B), and the first terminal 514 on the opposite end of the semiconductor body 512 (e.g., Figure 3A First terminal 315 or Figure 4A Or the first terminal 404 of 4B) and the second terminal 516 (e.g., Figure 3A The second terminal 316 or Figure 4B The second terminal 436), coupled to the gate structure 518 of the semiconductor body 512 (e.g., Figure 1 Gate structure 136 or Figure 4B (Gate structure 432). For illustrative purposes, in Figures 5A-5D The components in the structure are simplified, and only one vertical transistor 510 is shown in detail.

[0098] In some implementations, the 3D semiconductor device includes a trench structure 520 (e.g., Figure 2 The groove structure 210 or Figure 3A The trench structure 520 (308) is separated by an isolation region 530 in a transverse direction (e.g., the X direction). In some embodiments, the isolation region 530 includes an air gap, for example, Figure 1 160 isolation areas Figure 2 Quarantine area 220 Figure 3A The isolation area 306 or Figure 4A Alternatively, an isolation region 410 of 4B. In some embodiments, the isolation region 530 includes a conductive structure (e.g., a metallic material such as W). The conductive structure may be coupled to a low voltage (e.g., a negative voltage), which can reduce or eliminate back-coupled effects or row hammer effects. In some cases, the conductive structure may contact at least one of the adjacent semiconductor bodies 512, which can reduce or eliminate floating body effects. The gate structures 518 of a pair of vertical transistors 510 may be formed in a trench structure 520 and separated by an insulating material 502 (e.g., oxide).

[0099] Figure 5A It shows the relationship with Figure 4B The structure 500a is similar to or the same as the structure 430. Structure 500a may include, for example, a first terminal 514 and a gate structure 518 formed from the front side of the semiconductor substrate 501. Figure 5A As shown, the back side of structure 500a faces upward for subsequent ion implantation, for example, to form the second terminal 516 of vertical transistor 510. Therefore, structure 500a may include an unfinished vertical transistor 510. Structure 500a may have a thinned semiconductor substrate on its back side, for example, with a thickness of about 100 nm.

[0100] Figure 6AA cross-sectional view of the rear side of structure 500a is shown. (See diagram.) Figure 6A As shown, alternating strips of semiconductor material (e.g., Si) 602 and isolation material (e.g., oxide) 604 are formed along the Y direction. In some embodiments, strips of isolation material 604 are formed by etching semiconductor substrate 501 to form trenches and filling the trenches with isolation material 604 from the front side of semiconductor substrate 501. Semiconductor substrate 501 can be thinned from the back side (e.g., by CMP) to expose the strips of semiconductor material 602 and isolation material 604. The strips of semiconductor material 602 and isolation material 604 can extend into semiconductor substrate 501 with a thickness of, for example, about 100 nm.

[0101] Figure 5B Structure 500b is shown after N+ type ions (e.g., P ions) have been implanted from the back side of structure 500a into semiconductor substrate 501. Region 540 of the semiconductor substrate with implanted ions can be... Figure 3A The intermediate region 313 is similar to or the same as the intermediate region 512. In some embodiments, region 540 may extend to the end of the semiconductor body 512, for example, as shown in the figure. Figure 3A As shown. The second terminal 516 can be formed at the end of the semiconductor body 512. Note that, as Figure 6A As shown, the back side of structure 500a includes alternating strips of semiconductor material 602 and insulating material 604. N+ type ions can be implanted into the strips of semiconductor material 602, but not into the strips of insulating material 604.

[0102] In some implementations, semiconductor ions are implanted first, for example using Ge pre-amorphization implantation (Ge PAI), before implanting N+ ions for low-thermal activation. In some examples, Ge ions are implanted to a certain depth (e.g., in the range of 20 nm to 40 nm), followed by implantation of N+ ions (e.g., P ions), allowing the structure 500b to be activated at a low temperature (e.g., in the range of 500 °C to 600 °C). This temperature can be lower than the nominal temperature (e.g., about 900 °C) used to activate N+ ions without Ge ion implantation.

[0103] Figure 5C Structure 500c is shown after a metal layer 550 has been formed on the back surface of structure 500b. The metal layer 500 may cover both a strip of semiconductor material 602 (e.g., region 540) and a strip of insulating material 604. The metal layer 550 may comprise a metallic material, such as Ni.

[0104] Figure 5DThe diagram shows structure 500d after an annealing process has been performed on structure 500c. The metallic material of metal layer 550 and the semiconductor material of semiconductor substrate 501 (e.g., a strip of semiconductor material 602) can react during the annealing process to form a composite conductive material 560, such as a silicide. In some examples, the metallic material includes Ni, the semiconductor material includes Si, and the composite conductive material includes NiSi.

[0105] After the annealing process, any remaining metal material of the metal layer 550 can be removed from the back side of the semiconductor substrate 501, for example, by etching (e.g., wet etching). Since the metal material of the metal layer 550 does not react with the strips of the insulating material 604, the metal material on the strips of the insulating material 604 can be removed, for example, as... Figure 6B As shown. Conversely, layer 608 of the composite conductive material 560 is formed as a bit line on top of the strip of semiconductor material 602 (e.g., Figure 1 The bit line 123, Figure 2 bit line 202 or Figures 3A-3B (Bit line 302). A layer 608 of the composite conductive material 560 can be formed on top of a layer 606 of the semiconductor material 602, wherein an N+ type dopant is implanted in region 540. In this way, a self-aligned bit line is formed on the back side of the semiconductor substrate 501.

[0106] Figure 7A This is a flowchart of an example process 700 for forming a semiconductor device. A semiconductor device can be... Figures 3A-3B 3D semiconductor devices 300, Figure 2 3D semiconductor devices 200 Figure 1 3D semiconductor devices 100 Figure 1 The structure of the intermediate manufacturing process of the 3D semiconductor device 100, or Figure 5D The structure is 500d. It can be based on... Figures 5A-5D and Figures 6A-6B Describe process 700. Process 700 includes operations (or steps) that can be performed in any suitable order and / or any combination.

[0107] In operation 710, a plurality of memory cell strings are formed along a vertical direction in a first side of a semiconductor substrate. The semiconductor substrate comprises a semiconductor material (e.g., Si). The semiconductor substrate can be used with materials for forming... Figure 1 First semiconductor substrate 104 Figures 3A-3B Semiconductor substrate 301, Figures 4A-4B Semiconductor substrate 401 or Figure 5A The semiconductor substrate 501 is similar to or the same as the semiconductor substrate. The vertical direction can be the Z direction. The first side of the semiconductor substrate can be the front side of the semiconductor substrate. The memory cell can be... Figure 1 The memory cell 124, for example, is a DRAM memory cell.

[0108] Memory cells may include vertical transistors (e.g., Figure 1 Vertical transistor 126 Figure 2 Vertical transistors 212, 214 Figure 3A Vertical transistor 310 or Figures 5A-5D (Vertical transistor 510). In some embodiments, for example, such as Figure 1 , 3A As shown in 4B or 5A-5D, a vertical transistor includes a semiconductor body (e.g., Figure 1 Semiconductor body 130, Figure 3A Semiconductor body 314, Figure 4B Semiconductor body 402 or Figures 5A-5D The semiconductor body 512), and the first and second terminals at opposite ends of the semiconductor body (e.g., Figure 1 Terminal 138, terminals 315 and 316 in Figure 3 Figure 4B Terminals 404 and 436 or Figures 5B-5D Terminals 514, 516), and gate structures coupled to the semiconductor body (e.g., Figure 1 Gate structure 136 Figure 4B Gate structure 432 or Figures 5A-5D The gate structure 518). The gate structure may include a vertical gate electrode ( Figure 1 Gate electrode 134 Figure 3A The gate electrode 312 or Figure 4B The gate electrode 433) and the gate dielectric coupled between the vertical gate electrode and the semiconductor body (e.g., Figure 1 Gate dielectric 132, Figure 3A Gate dielectric 311 or Figure 4B Gate dielectric 434).

[0109] In some implementations, forming multiple strings of memory cells includes: along a vertical direction in the same trench (e.g., Figure 4A A pair of independent vertical transistor gate terminals (e.g., vertical gate electrodes) are formed in a trench 420. The gate terminals may be separated by an insulating material (e.g., oxide) along a lateral direction perpendicular to the vertical direction (e.g., the X direction). In some embodiments, process 700 further includes forming an isolation region between adjacent pairs of independent vertical transistors along the lateral direction. The isolation region may be... Figure 1 trench isolation 160, Figure 2 Quarantine area 220 Figure 3A Isolation area 306 Figure 4AOr isolation zone 410 of 4B or Figures 5A-5D The isolation region 530 is similar to or the same as the isolation region. In some examples, the isolation region includes an air cavity surrounded by an isolation material or a cavity filled with a metallic material.

[0110] In operation 720, a semiconductor material and an insulating material are formed in a horizontal direction (e.g., the Y direction) perpendicular to the vertical direction on a second side (e.g., the back side) of the semiconductor substrate. Figures 6A-6B Multiple alternating stripes of 602 and 604, with the second side being opposite to the first side along the vertical direction.

[0111] In some embodiments, forming multiple alternating strips of semiconductor material and isolation material in a second side of the semiconductor substrate includes: thinning the semiconductor substrate from the second side of the semiconductor substrate to expose the multiple alternating strips of semiconductor material and isolation material, for example, as... Figure 6A As shown.

[0112] In operation 730, multiple bit lines are formed on the second side of the semiconductor substrate. The bit lines can be, for example... Figure 1 The bit line 123, Figure 2 bit line 202 or Figures 3A-3B Bit lines 302. In some embodiments, the operation 730 of forming multiple bit lines includes: depositing a metal material layer (e.g., on multiple alternating strips of semiconductor material and isolation material). Figure 5C The metal layer 550)(732), for example, such as Figure 5C As shown, and by forming a composite conductive material based on metal and semiconductor materials in corresponding strips of semiconductor materials with multiple alternating strips, each bit line (734) of multiple bit lines is formed in the corresponding strips of said semiconductor material, for example, as Figure 5D Or as shown in 6B.

[0113] In some embodiments, forming a composite conductive material based on a metal and a semiconductor material in a corresponding strip of semiconductor material includes annealing the metal and semiconductor materials, causing the metal to react with the semiconductor material to form the composite conductive material. No reaction may occur between the insulating material and the metal material deposited on the insulating material. In some embodiments, the semiconductor material includes silicon, the insulating material includes an oxide, and the composite conductive material includes a silicide. In some examples, the metal material includes nickel (Ni).

[0114] In some embodiments, after forming multiple bit lines in the second side of the semiconductor substrate, process 700 further includes removing metal material residues from the second side of the semiconductor substrate, for example by wet etching. The metal material residues may include metal material on strips of insulating material and residual metal material on the bit lines.

[0115] In some implementations, for example, such as Figure 5B As shown, process 700 includes implanting ions (e.g., N+ type ions such as P ions) into a second side of a semiconductor substrate. The composite conductive material can be formed based on a metallic material and a semiconductor material with implanted ions.

[0116] In some embodiments, ion implantation into the second side of a semiconductor substrate includes: implanting semiconductor ions (e.g., Ge ions) into the second side of the semiconductor substrate using, for example, Ge PAI technology; implanting N+ type ions into the second side of the semiconductor substrate; and activating the implanted N+ type ions with the implanted semiconductor ions at an activation temperature. In some examples, the semiconductor material includes silicon, the semiconductor ions include germanium (Ge) ions, and the N+ type ions include arsenic (As) ions or phosphorus (P) ions. The activation temperature may be lower than the nominal temperature used to activate N+ type ions without implanting semiconductor ions. In some examples, the nominal temperature is about 900°C, and the activation temperature is in the range of about 500°C to about 600°C.

[0117] In some embodiments, thinning the semiconductor substrate from the second side of the semiconductor substrate includes: etching the semiconductor material in the second side of the semiconductor substrate, and polishing, for example, the top surface of the etched semiconductor material in the second side of the semiconductor substrate by CMP.

[0118] In some embodiments, forming a plurality of memory cell strings includes: forming a first terminal of a vertical transistor by implanting ions from a first side of a semiconductor substrate, and forming a second terminal of a vertical transistor by implanting ions into a second side of the semiconductor substrate (e.g., as shown in the figure). Figure 4B (or as shown in 5B). In some examples, one of the first and second terminals is a source terminal, and the other of the first and second terminals is a drain terminal. In some implementations, each of the multiple bit lines is formed on and coupled to the second terminal of the vertical transistor, for example, as shown in 5B. Figure 1 Or as shown in 3A.

[0119] In some implementations, each memory cell in a plurality of memory cell strings further includes, for example, a capacitor coupled to a vertical transistor via capacitor contacts and / or via contacts (e.g., Figure 1 (Capacitor 128). The capacitor can be formed before the vertical transistor is formed, and the capacitor can be located above the vertical transistor along the vertical direction (e.g., the Z direction).

[0120] In some implementations, multiple memory cell strings and multiple bit lines are formed on an array die (e.g., Figure 1In the second semiconductor substrate or array die 104). Process 700 may further include: bonding a first side of the semiconductor substrate to the front side of the control die and electrically coupling one or more conductive lines of the array die to a control circuit in the front side of the control die, thereby connecting the control die (e.g., Figure 1 The first semiconductor structure or control die 102 is integrated with the array die.

[0121] In some implementations, for example, such as Figure 3A As shown, multiple bit lines are located on a semiconductor material layer with implanted ions. The implanted ions can include semiconductor ions and N+ type ions. In some examples, the semiconductor material includes silicon, the semiconductor ions include germanium (Ge) ions, the N+ type ions include arsenic (As) ions or phosphorus (P) ions, and the composite conductive material includes silicides.

[0122] In some implementations, for example, such as Figure 3A As shown, a portion of the semiconductor material layer with implanted ions is configured as a terminal of a vertical transistor (e.g., Figure 3A The second terminal 316, Figure 4B The second terminal 436 or Figures 5B-5D The second terminal 516) is electrically coupled to the corresponding bit line.

[0123] Figure 7B This is a flowchart of another example process 750 for forming a semiconductor device. A semiconductor device can be... Figure 7A Semiconductor devices. Process 750 includes processes that can be used with... Figure 7A The operations in process 700 are similar to or the same as those in process 700. These operations can be performed in any suitable order and / or in any combination.

[0124] In operation 752, and Figure 7A Operation 710 is similar to or the same as forming a plurality of memory cell strings in a first side (e.g., front side) of a semiconductor substrate along a vertical direction (e.g., the Z direction). The semiconductor substrate may include a semiconductor material (e.g., Si).

[0125] In operation 754, the semiconductor substrate is thinned along a vertical direction from a second side (e.g., the back side). The second side is opposite to the first side of the semiconductor substrate. For example, as... Figure 4B or Figure 5A As shown, a first terminal is formed in a first side of the semiconductor substrate (e.g., Figure 3A First terminal 315, Figure 4B First terminal 404, Figure 5A The first terminal 514) and / or the gate structure (e.g., Figure 4B Gate structure 432 or Figure 5AAfter the gate structure 518 is formed, the structure is flipped, and the semiconductor substrate can be thinned from the second side, for example, by CMP. In some embodiments, the semiconductor substrate is thinned to expose multiple alternating strips of semiconductor material and insulating material, for example, as... Figure 6A As shown.

[0126] In operation 756, semiconductor ions are implanted into a second side of the semiconductor substrate. Process 750 may further include: implanting N+ type ions into the second side of the semiconductor substrate and activating the implanted N+ type ions at an activation temperature. In some examples, the semiconductor material includes silicon, the semiconductor ions include germanium (Ge) ions, and the N+ type ions include arsenic (As) ions or phosphorus (P) ions. Prior to implanting the N+ type ions, Ge pre-amorphization implantation (Ge PAI) is performed by implanting Ge ions into the second side of the semiconductor substrate for low-thermal activation. Therefore, the activation temperature can be lower than the nominal temperature used to activate N+ type ions without implanting semiconductor ions.

[0127] In some embodiments, process 750 further includes: forming multiple bit lines in a second side of a semiconductor substrate by multiple strips of semiconductor material in alternating strips of semiconductor material and insulating material (e.g., oxide), for example, Figure 7A Operation 730. A bit line can be formed by depositing a metal material layer on multiple alternating strips of semiconductor material and insulating material, and by forming each of multiple bit lines in the corresponding strips of the multiple strips of semiconductor material using a composite conductive material based on the metal material and semiconductor material. The metal material may include nickel (Ni).

[0128] Composite conductive materials can be formed by annealing a metallic material and a semiconductor material, causing the metallic material to react with the semiconductor material to form the composite conductive material. There may be no reaction between the insulating material and the metallic material deposited on the insulating material. In some embodiments, the composite conductive material is formed based on a metallic material and a semiconductor material with activated implanted N+ ions.

[0129] In some embodiments, each memory cell in a plurality of memory cell strings includes a vertical transistor along a vertical direction. Forming a plurality of memory cell strings includes: forming a gate terminal of the vertical transistor by depositing at least one metal layer along a vertical direction on the inner surface of a trench; forming a first terminal of the vertical transistor by implanting N+ type ions from a first side of a semiconductor substrate; and forming a second terminal of the vertical transistor by implanting N+ type ions into a second side of the semiconductor substrate. In some examples, the first terminal is a source terminal and the second terminal is a drain terminal.

[0130] Figure 8A block diagram of a system 800 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure is shown. System 800 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 8 As shown, system 800 may include a host device 808 and a memory system 802 having one or more 3D memory devices 804 and a memory controller 806. The host device 808 may include a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host device 808 may be configured to send data to or receive data from one or more 3D memory devices 804.

[0131] 3D memory device 804 can be any 3D memory device disclosed herein, such as Figure 1-7B The 3D memory device 804 is shown. In some embodiments, the 3D memory device 804 includes NAND flash memory. A memory controller 806 (also referred to as controller circuitry) is coupled to the 3D memory device 804 and the host device 808. Consistent with embodiments of this disclosure, the 3D memory device 804 may include a plurality of conductive interconnects that pass through a cover layer and contact conductive pads in a conductive pad layer, and the memory controller 806 may be coupled to the 3D memory device 804 through at least one of the plurality of conductive interconnects. The memory controller 806 is configured to control the 3D memory device 804. For example, the memory controller 806 may be configured to operate a plurality of channel structures via word lines. The memory controller 806 may manage data stored in the 3D memory device 804 and communicate with the host device 808.

[0132] In some embodiments, the memory controller 806 is designed / configured to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 806 is designed / configured to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which can be used as a data storage device for mobile devices such as smartphones, tablets, and laptops, and for enterprise storage arrays. The memory controller 806 can be configured to control the operation of the 3D memory device 804, such as read, erase, and program operations. The memory controller 806 can also be configured to manage various functions regarding data stored or to be stored in the 3D memory device 804, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 806 is also configured to process error correction codes (ECC) regarding data read from or written to the 3D memory device 804. Any other appropriate function may also be performed by the memory controller 806, such as formatting the 3D memory device 804.

[0133] The memory controller 806 can communicate with external devices (e.g., host 808) according to a specific communication protocol. For example, the memory controller 806 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0134] The memory controller 806 and one or more 3D memory devices 804 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 802 can be implemented and packaged into different types of end electronic products. Figure 8In one example shown, the memory controller 806 and a single 3D memory device 804 can be integrated into the memory card 802. The memory card 802 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0135] The subject matter and embodiments of action and operation described in this disclosure can be implemented in digital electronic circuits, in tangibly embodied computer software or firmware, or in computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or combinations thereof. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, such as one or more modules of computer program instructions encoded on a computer program carrier, for execution by a data processing apparatus or for controlling the operation of a data processing apparatus. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a suitable receiver device for execution by the data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof, or a part of a combination thereof. The computer storage medium is not a propagation signal.

[0136] Note that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," "some implementations," etc., in this disclosure indicate that the described implementation may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other implementations is within the knowledge of those skilled in the art.

[0137] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a," "an," or "the" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least partly on the context.

[0138] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on something,” but also includes “on something” with an intermediate feature or layer therebetween. Furthermore, “above” or “on top of” not only means “above something” or “on top of something,” but can also include the meaning of being “above something” or “on top of something” without an intermediate feature or layer therebetween (i.e., directly on something).

[0139] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another (or more) as shown in the accompanying drawings. In addition to the orientations shown in the drawings, the spatially relative terms are intended to also cover different orientations of the device during use or process steps. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein may be interpreted accordingly.

[0140] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed; therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0141] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes thereon. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vertical interconnect vias are formed) and one or more dielectric layers.

[0142] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a specific technology node associated with the semiconductor device involved. Based on a specific technology node, the term "about" may indicate a value of a given quantity that varies, for example, within 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0143] In this disclosure, the terms "horizontal / horizontally / laterally" refer to a lateral surface that is parallel to the substrate, and the terms "vertical" or "perpendicularly" refer to a surface that is perpendicular to the lateral surface of the substrate. The terms "operation" and "step" may be used interchangeably to describe a process.

[0144] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in the vertical direction relative to the substrate.

[0145] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features can be in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0146] The foregoing description of a particular implementation can be readily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of equivalents of the disclosed implementations.

[0147] While this disclosure contains numerous details of specific embodiments, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features that may be specific to particular embodiments. Certain features described in the context of different embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claims may be directed to sub-combinations or variations thereof.

[0148] Similarly, although operations are illustrated in the accompanying drawings and recited in a specific order in the claims, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or to perform all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0149] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired result. As an example, the processes shown in the figures do not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0150] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A method comprising: A plurality of memory cell strings are formed along a vertical direction in a first side of a semiconductor substrate, the semiconductor substrate comprising a semiconductor material; Multiple alternating strips of the semiconductor material and the insulating material are formed on a second side of the semiconductor substrate along a horizontal direction perpendicular to the vertical direction, the second side being opposite to the first side along the vertical direction; as well as Multiple bit lines are formed on the second side of the semiconductor substrate, wherein forming the multiple bit lines includes: A metal material layer is deposited on the plurality of alternating strips of the semiconductor material and the insulating material; By forming a composite conductive material based on the metal material and the semiconductor material in corresponding strips of the plurality of alternating strips of the semiconductor material, each of the plurality of bit lines is formed in the corresponding strips of the semiconductor material, and Ion implantation into the second side of the semiconductor substrate, wherein ion implantation into the second side of the semiconductor substrate includes: implanting semiconductor ions into the second side of the semiconductor substrate.

2. The method according to claim 1, wherein, Forming the composite conductive material based on the metal material and the semiconductor material in the corresponding strip of the semiconductor material includes: The metal material and the semiconductor material are annealed, causing the metal material and the semiconductor material to react to form the composite conductive material.

3. The method according to claim 1 or 2, wherein, The semiconductor material includes silicon, the insulating material includes oxide, and the composite conductive material includes silicide.

4. The method according to any one of claims 1 to 3, further comprising: After the plurality of bit lines are formed in the second side of the semiconductor substrate, the residue of the metal material is removed from the second side of the semiconductor substrate.

5. The method according to any one of claims 1 to 4, wherein, The plurality of alternating strips of the semiconductor material and the insulating material formed in the second side of the semiconductor substrate include: Thinning the semiconductor substrate from the second side to expose the plurality of alternating strips of the semiconductor material and the insulating material, and Wherein, forming the composite conductive material based on the metal material and the semiconductor material in the corresponding strip of the semiconductor material includes: The composite conductive material based on the metal material and the semiconductor material is formed by ion implantation.

6. The method according to claim 5, wherein, Implanting the ions into the second side of the semiconductor substrate further includes: N+ type ions are implanted into the second side of the semiconductor substrate; and The implanted N+ type ions are activated with the implanted semiconductor ions at the activation temperature.

7. The method according to claim 6, wherein, The semiconductor material includes silicon, the semiconductor ion includes germanium (Ge) ions, and the N+ type ion includes arsenic (As) ions or phosphorus (P) ions.

8. The method according to claim 6 or 7, wherein, The activation temperature is lower than the nominal temperature used to activate the N+ type ions without implanting the semiconductor ions.

9. The method according to any one of claims 5 to 8, wherein, Thinning the semiconductor substrate from the second side of the semiconductor substrate includes: Etching the semiconductor material in the second side of the semiconductor substrate; and Polish the top surface of the etched semiconductor material in the second side of the semiconductor substrate.

10. The method according to any one of claims 5 to 9, wherein, Each memory cell in the plurality of memory cell strings includes a vertical transistor along the vertical direction, and The formation of the plurality of memory cell strings includes: The gate terminal of the vertical transistor is formed by depositing at least one metal layer on the inner surface of the trench along the vertical direction. The first terminal of the vertical transistor is formed by implanting the ions from the first side of the semiconductor substrate; and The second terminal of the vertical transistor is formed by implanting the ions into the second side of the semiconductor substrate.

11. The method according to claim 10, wherein, Each of the plurality of bit lines is formed on and coupled to the second terminal of the vertical transistor.

12. The method according to claim 10 or 11, wherein, Each memory cell in the plurality of memory cell strings also includes a capacitor coupled to the vertical transistor, and The formation of the plurality of memory cell strings includes: The capacitor is formed prior to the formation of the vertical transistor, and the capacitor is positioned above the vertical transistor along the vertical direction.

13. The method according to any one of claims 10 to 12, wherein, Forming the plurality of memory cell strings includes: A pair of independent vertical transistor gate terminals are formed in the same trench along the vertical direction, the gate terminals being separated by an insulating material along a third direction perpendicular to the vertical and horizontal directions.

14. The method of claim 13, further comprising: An isolation region is formed between adjacent independent vertical transistor pairs along the third direction.

15. The method according to any one of claims 1 to 14, wherein, The plurality of memory cell strings and the plurality of bit lines are formed in the array die, and The method further includes: The control die is integrated with the array die by bonding the first side of the semiconductor substrate to the front side of the control die and electrically coupling one or more conductive lines of the array die to the control circuitry in the front side of the control die.

16. A semiconductor device, comprising: A plurality of memory cell strings along a vertical direction on a first side of a semiconductor substrate, the semiconductor substrate comprising a semiconductor material; as well as Multiple bit lines are located on a second side of the semiconductor substrate, the second side being opposite to the first side along the vertical direction, wherein adjacent bit lines are separated by an insulating material along a horizontal direction perpendicular to the vertical direction. The plurality of bit lines are made of a composite conductive material based on the semiconductor material, wherein the plurality of bit lines are located on a layer of the semiconductor material having implanted ions, and wherein the implanted ions include semiconductor ions.

17. The semiconductor device according to claim 16, wherein, The implanted ions also include N+ type ions.

18. The semiconductor device according to claim 16 or 17, wherein, Each memory cell in the plurality of memory cell strings includes a vertical transistor along the vertical direction, and A portion of the layer of the semiconductor material having the implanted ions is configured as a terminal of the vertical transistor and is conductively coupled to the corresponding bit line.

19. The semiconductor device according to claim 18, wherein, The gate terminals of a pair of independent vertical transistors are in the same trench along the vertical direction and are separated by an insulating material along a third direction perpendicular to both the vertical and horizontal directions. The isolation region extends along the third direction between adjacent independent vertical transistor pairs.

20. A system comprising: Memory device, the memory device comprising: An array structure comprising a plurality of memory cell strings along a vertical direction on a first side of a semiconductor substrate, the semiconductor substrate comprising a semiconductor material; and Multiple bit lines are located on a second side of the semiconductor substrate, the second side being opposite to the first side along the vertical direction, wherein adjacent bit lines are separated by an insulating material along a horizontal direction perpendicular to the vertical direction, wherein the multiple bit lines are made of a composite conductive material based on the semiconductor material, wherein the multiple bit lines are located on a layer of the semiconductor material having implanted ions, and wherein the implanted ions include semiconductor ions; and A controller coupled to the memory device and configured to control the memory device.

21. A method comprising: A plurality of memory cell strings are formed along a vertical direction in a first side of a semiconductor substrate, the semiconductor substrate comprising a semiconductor material; The semiconductor substrate is thinned from a second side along the vertical direction, the second side being opposite to the first side of the semiconductor substrate; as well as Semiconductor ions are implanted into the second side of the semiconductor substrate.

22. The method of claim 21, further comprising: N+ type ions are implanted into the second side of the semiconductor substrate; as well as The injected N+ ions are activated at the activation temperature.

23. The method according to claim 22, wherein, The semiconductor material includes silicon, the semiconductor ion includes germanium (Ge) ions, and the N+ type ion includes arsenic (As) ions or phosphorus (P) ions.

24. The method according to claim 22 or 23, wherein, The activation temperature is lower than the nominal temperature used to activate the N+ type ions without implanting the semiconductor ions.

25. The method according to any one of claims 22 to 24, wherein, Thinning the semiconductor substrate from the second side along the vertical direction includes: The semiconductor substrate is thinned to expose multiple alternating strips of the semiconductor material and the insulating material, and The method further includes: Multiple stripes of the semiconductor material based on the multiple alternating stripes form multiple bit lines on the second side of the semiconductor substrate.

26. The method of claim 25, wherein, Forming the plurality of bit lines in the second side of the semiconductor substrate includes: Depositing a metal material layer on the plurality of alternating strips of the semiconductor material and the insulating material; and Each bit line is formed in the plurality of bit lines by forming a composite conductive material based on the metal material and the semiconductor material in a corresponding strip among the plurality of strips of the semiconductor material.

27. The method according to claim 26, wherein, Forming the composite conductive material based on the metallic material and the semiconductor material in the corresponding strips includes: The metal material and the semiconductor material are annealed to react the metal material and the semiconductor material to form the composite conductive material.

28. The method according to claim 27, wherein, There is no reaction between the insulating material and the metallic material deposited on the insulating material.

29. The method according to any one of claims 26 to 28, wherein, Forming the composite conductive material based on the metallic material and the semiconductor material in the corresponding strips includes: The composite conductive material based on the metal material and the semiconductor material is formed by utilizing activated implanted N+ ions.

30. The method according to any one of claims 21 to 29, wherein, Each memory cell in the plurality of memory cell strings includes a vertical transistor along the vertical direction, and The formation of the plurality of memory cell strings includes: The gate terminal of the vertical transistor is formed by depositing at least one metal layer on the inner surface of the trench along the vertical direction. The first terminal of the vertical transistor is formed by implanting N+ type ions from the first side of the semiconductor substrate; and The second terminal of the vertical transistor is formed by implanting the N+ type ions into the second side of the semiconductor substrate.

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