Fault detection method and system, electronic device and storage medium

Abstract

The application discloses a fault detection method and system, an electronic device and a storage medium, relates to the technical field of computers, is executed by a fault detection device, a pin of the fault detection device is connected to a pin hole installed on a server mainboard, a management controller of the server mainboard is connected to at least one bus between a sub-device, the pin hole is connected to the at least one bus, and wherein the method comprises: connecting to a bus to be tested in the at least one bus through the pin hole; according to the period identifier of the bus signal of the bus to be tested, whether the period data of the bus signal is complete is judged; if it is detected that the period data is incomplete, the period data is determined as fault data, and the fault type of the bus to be tested is detected according to the fault data. Compared with the prior art, the application does not need manual fault data grabbing, effectively improves the fault data grabbing efficiency, and further improves the fault detection efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a fault detection method and system, electronic device and storage medium. Background Technology

[0002] Peripheral Component Interconnect Express (PCIe) devices connect to the Baseboard Management Controller (BMC) in the server via a bus to achieve out-of-band management. Due to the large number of types and manufacturers of PCIe devices and the occasional firmware upgrades, problems such as bus hangs of PCIe devices frequently occur.

[0003] Currently, the relevant technologies typically involve soldering test points onto the bus corresponding to the faulty PCIe device, requiring manual monitoring of the logic analyzer to capture error data, resulting in low fault detection efficiency. Summary of the Invention

[0004] This disclosure provides a fault detection method and system, electronic device, and storage medium. Its main objective is to address the problems of low testing efficiency and poor testing accuracy in fault detection, as well as the high wear and tear on the interfaces of component devices.

[0005] In view of this, this application provides a fault detection method, system, storage medium, and electronic device. The main purpose is to improve the technical problem that current related technologies typically involve soldering test points on the bus corresponding to the faulty PCIe device, requiring manual monitoring of the logic analyzer to capture error data, resulting in low fault detection efficiency.

[0006] In a first aspect, this application provides a fault detection method, executed by a fault detection device, wherein pins of the fault detection device are connected to pinholes mounted on a server motherboard, and the server motherboard's management controller and sub-devices have at least one bus, and the pinholes are connected to the at least one bus, comprising:

[0007] The pin is connected to the bus to be tested in at least one of the buses through the pin hole;

[0008] Based on the period identifier of the bus signal of the bus under test, determine whether the period data of the bus signal is complete;

[0009] If the periodic data is found to be incomplete, the periodic data is determined to be fault data, and the fault type of the bus under test is detected based on the fault data.

[0010] In some embodiments, detecting the fault type of the bus under test based on the fault data includes:

[0011] Based on the fault data, the status of the bus under test is detected;

[0012] If the bus under test is detected to be in an idle state, the fault type is determined to be the first fault, which includes task interruption caused by master device switching;

[0013] If the bus under test is detected to be not in an idle state, then a low-level bus signal is detected.

[0014] If a low-level bus signal is detected as a data signal, a bus switch is used to reset the bus and the preceding circuitry of the bus switch is checked to see if it has recovered.

[0015] If the upstream line is detected to have recovered, the fault type is determined to be a second fault, which includes sub-device faults;

[0016] If the upstream line is not restored, the fault type is determined to be a third fault, which includes a management controller fault.

[0017] In some embodiments, detecting the fault type of the bus under test based on the fault data further includes:

[0018] If a low-level bus signal is detected as a clock signal, a bus switch is used to reset the bus and the preceding circuitry of the bus switch is checked to see if it has recovered.

[0019] If the front-end line is detected to have recovered, the fault type is determined to be the fourth fault, which includes the sub-device failing to properly release the bus;

[0020] If the preceding line is not restored, the fault type is determined to be the fifth fault, which includes the management controller failing to properly release the bus.

[0021] In some embodiments, after determining the fault type as a second fault if the upstream line is detected to have recovered, the method further includes:

[0022] Reset signals are sent sequentially to the sub-devices connected to the bus switch. Sub-devices that fail to recover are identified as target fault devices, and the target fault devices are recorded.

[0023] In some embodiments, before resetting using a bus switch and detecting whether the preceding circuitry of the bus switch has recovered, the method further includes:

[0024] Detect whether a bus switch exists on the bus under test;

[0025] If it is detected that there is no bus switch on the bus under test, a reset signal is sent directly to the sub-device corresponding to the bus under test.

[0026] In some embodiments, after determining that the periodic data is fault data, the method further includes:

[0027] Save the fault data.

[0028] In some embodiments, after determining whether the period data of the bus signal is complete based on the period identifier of the bus signal of the bus under test, the method further includes:

[0029] If the periodic data is detected to be complete, then the periodic data is determined to be normal data and is discarded.

[0030] Secondly, this application provides a fault detection system, including: a pinhole and a fault detection device;

[0031] The pinhole is mounted on the server motherboard, and there is at least one bus between the server motherboard's management controller and the sub-device, with the pinhole connected to the at least one bus;

[0032] The pin hole is used to connect the pin of the fault detection device;

[0033] The fault detection device is used to connect to the bus under test in at least one bus through the pin hole; to determine whether the period data of the bus signal is complete according to the period identifier of the bus signal of the bus under test; if the period data is detected to be incomplete, the period data is determined to be fault data, and the fault type of the bus under test is detected according to the fault data.

[0034] According to a third aspect of this disclosure, an electronic device is provided, comprising:

[0035] At least one processor; and

[0036] A memory communicatively connected to the at least one processor; wherein,

[0037] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in the first aspect above.

[0038] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are configured to cause the computer to perform the method described in the first aspect above.

[0039] According to a fifth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the method described in the first aspect above.

[0040] The fault detection method, system, electronic device, and storage medium disclosed herein are executed by a fault detection device. The pins of the fault detection device are connected to pinholes mounted on a server motherboard. At least one bus exists between the server motherboard's management controller and a sub-device. The pinhole is connected to the at least one bus. The method includes: connecting to a bus under test in the at least one bus via the pinhole; determining whether the periodic data of the bus signal under test is complete based on the periodic identifier of the bus signal under test; if the periodic data is detected to be incomplete, determining the periodic data as fault data, and detecting the fault type of the bus under test based on the fault data. Compared with existing technologies, this application uses a fault detection device to connect the bus under test between the management controller and the sub-device via a pinhole mounted on a server motherboard. Then, based on the periodic identifier of the bus signal under test, incomplete periodic data is determined as fault data, and the fault type of the bus under test is determined based on the fault data. This eliminates the need for manual collection of fault data from the bus under test, effectively improving the efficiency of fault data collection. Simultaneously, it achieves automatic classification of fault types, shortening manual detection and analysis time, thereby improving the efficiency of fault detection.

[0041] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0042] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0043] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0044] Figure 1 A schematic diagram illustrating an example provided in an embodiment of this application is shown;

[0045] Figure 2 A schematic diagram illustrating an example provided in an embodiment of this application is shown;

[0046] Figure 3A flowchart illustrating a fault detection method provided in an embodiment of this application is shown;

[0047] Figure 4 A schematic diagram illustrating an example provided in an embodiment of this application is shown;

[0048] Figure 5 A schematic diagram of the structure of a fault detection system provided in an embodiment of this application is shown. Detailed Implementation

[0049] The embodiments of this application will now be described in more detail with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0050] Currently, in related technologies, the BMC in the server motherboard and various sub-devices can be connected using a two-wire serial bus (Inter-Integrated Circuit, I2C), such as... Figure 1 As shown, the BMC can connect to multiple buses, such as I2C0, I2C1, and I2Cn. A Complex Programming Logic Device (FPGA) can receive data from each bus and issue a reset signal to reset the connected sub-devices on the bus. If a particular I2C bus has few connected devices with different addresses, an I2C switch is not needed to control them. If there are many connected devices with the same address, an I2C switch can be used to control them. The I2C switch chip (such as the PCA9548 chip) can be used to attempt to restore the corresponding sub-device using a reset signal.

[0051] In specific application scenarios, if the server architecture experiences I2C hangs or other failures, the following methods are typically used: Figure 2 The fault detection method involves soldering test points onto the faulty I2C bus and connecting them to a logic analyzer for fault detection. However, due to the limited storage space of the logic analyzer, it is impossible to store large amounts of bus data (such as waveform data). This necessitates manual monitoring of the bus data using the logic analyzer to capture error data during bus transmission. The problem is then reproduced and analyzed based on this error data, resulting in low efficiency in error data capture, which in turn affects the efficiency of fault reproduction and analysis, while also incurring significant labor costs.

[0052] To address the current technical issue of low fault detection efficiency, which typically involves soldering test points onto the bus of a faulty PCIe device and requiring manual monitoring of a logic analyzer to capture erroneous data, this embodiment provides a fault detection method. Figure 3 As shown, the method includes:

[0053] Step 101: Connect to the bus to be tested in at least one bus through the pinhole.

[0054] In specific application scenarios, the execution entity of this embodiment can be a fault detection device. The pins of the fault detection device are connected to the pin holes installed on the server motherboard. There is at least one bus between the management controller of the server motherboard and the sub-device, and the pin holes are connected to at least one bus.

[0055] In some examples, the pin headers can be installed near the management controller on the server motherboard, which may include, but is not limited to, the BMC. Minimize cable length and avoid unnecessary bends and excessively long paths to reduce signal attenuation and interference. Specifically, the pin headers can be used to route bus signals for connection to fault detection devices. When a fault occurs, the cable can be directly connected to the pin header and then routed outside the chassis to connect to the fault detection device, eliminating the need for soldering and improving bus connection efficiency.

[0056] In some examples, servers, as core devices of information systems, are characterized by high storage performance and strong input / output (I / O) expansion capabilities. When a fault is found in a sub-device of the server architecture, the bus to be tested corresponding to the faulty sub-device can be obtained first, and then the pins of the fault detection device can be connected to the corresponding pin holes of the bus to be tested. In this way, the fault detection device can be used to connect to the bus to be tested, obtain the data of the bus to be tested, and capture the fault data, thereby improving the efficiency of the fault detection device connecting to the bus to be tested.

[0057] In some examples, if multiple sub-devices fail and correspond to different buses, the multiple buses to be tested corresponding to the multiple sub-devices can be obtained first. The multiple pins of the fault detection device can be connected to the pin holes corresponding to each bus to be tested. In this way, the fault detection device can be used to connect multiple buses to be tested at the same time to perform fault detection on multiple buses to be tested, which effectively improves the fault detection efficiency and reduces the cost of manual testing.

[0058] Among them, sub-devices may include, but are not limited to, PCIe devices, such as: Non-Volatile Memory Host Controller Interface Specification (NVME) hard disk devices, Serial Attached SCSI (SAS) interface devices, Redundant Arrays of Independent Disks (RAID) cards, PCI Express network interface cards, Graphics Processing Unit (GPU) cards, GPU modules, etc., which can be used to implement the main functions of server storage, computing, communication, etc. The PCIe bus of the PCIe device can be connected to the Central Processing Unit (CPU) to enable fast data exchange between the two.

[0059] In some examples, to ensure the stable and reliable operation of PCIe devices, the BMC, as a server-specific independent system with monitoring, control and management functions, typically establishes a connection with devices that support the MCTP protocol (MCTP devices) by transmitting MCTP messages over I2C via the I2C bus. This allows the user end to manage and monitor the MCTP devices through the BMC.

[0060] Step 102: Determine whether the period data of the bus signal is complete based on the period identifier of the bus signal under test.

[0061] In some examples, a fault detection device can be used to read the bus signals of the bus under test in real time. Then, based on the period identifiers defined by the bus protocol (such as start bit, stop bit, synchronization character, etc.), the boundary of each period can be determined, the period data can be parsed, and the integrity of each period's data can be determined. For example, the integrity of each period's data can also be determined by comparing the expected period data length, checksum, data format, and other information.

[0062] Correspondingly, different bus protocols have different cycle identification methods. For the I2C bus, the start bit (Start) of the cycle data is when the serial clock line (SCL) is high, and the serial data line (SDA) changes from high to low. The stop bit (Stop) is when SCL is high, and SDA changes from low to high. The cycle identifier can be identified based on the corresponding signal level changes. When a complete start bit and stop bit are detected, it can be determined as a complete cycle data.

[0063] Step 103: If incomplete periodic data is detected, the periodic data is determined to be faulty data, and the fault type of the bus under test is detected based on the faulty data.

[0064] In some examples, if the start bit, stop bit, or other periodic markers of the bus signal do not appear correctly, or if there are abnormalities in the bus signal, it can be determined that the periodic data is incomplete. For example, if the start bit of the bus signal is detected, but the corresponding stop bit is not detected, it can be determined that the periodic data is incomplete. The periodic data can be identified as fault data, and then the fault type of the bus under test can be analyzed based on the fault data. This achieves automatic classification of fault types, shortens the manual inspection and analysis time of the bus under test, and improves the fault detection efficiency of the bus under test.

[0065] Compared with existing technologies, this embodiment can be performed by a fault detection device. The pins of the fault detection device are connected to pinholes mounted on a server motherboard. The server motherboard's management controller and sub-devices have at least one bus, and the pinholes are connected to at least one bus. The method includes: connecting to the bus under test through the pinhole; determining whether the periodic data of the bus signal is complete based on the periodicity identifier of the bus signal under test; if incomplete periodic data is detected, determining the periodic data as fault data, and detecting the fault type of the bus under test based on the fault data. Compared with existing technologies, this embodiment uses a fault detection device to connect the bus under test between the management controller and the sub-device through pinholes mounted on the server motherboard. Then, based on the periodicity identifier of the bus signal under test, incomplete periodic data is determined as fault data, and the fault type of the bus under test is determined based on the fault data. This eliminates the need for manual collection of fault data from the bus under test, effectively improving the efficiency of fault data collection. Simultaneously, it achieves automatic classification of fault types, shortening manual detection and analysis time, thereby improving the efficiency of fault detection.

[0066] In some embodiments, detecting the fault type of the bus under test based on fault data may specifically include: detecting the state of the bus under test based on the fault data; if the bus under test is detected to be in an idle state, then determining the fault type as a first fault, the first fault including task interruption caused by master device switching; if the bus under test is detected to be not in an idle state, then detecting a low-level bus signal; if the low-level bus signal is detected to be a data signal, then resetting it using a bus switch and detecting whether the preceding line of the bus switch is restored; if the preceding line is detected to be restored, then determining the fault type as a second fault; if the preceding line is detected to be not restored, then determining the fault type as a third fault.

[0067] The first fault may include, but is not limited to, task interruption caused by master device switching; the second fault may include, but is not limited to, slave device faults; and the third fault may include, but is not limited to, manager faults. Correspondingly, bus switches can be used to control signal paths, extend or isolate different bus segments, and dynamically select different channels, enabling the master device to communicate with multiple slave devices without conflict. These switches may include, but are not limited to, I2C switches, SPI switches, and GPIO expanders.

[0068] Optionally, a reset signal can be sent to the sub-device corresponding to the bus under test through the logic device in the fault detection device or the logic device in the server, so as to restore bus communication in various ways.

[0069] For example, such as Figure 4 The diagram illustrates the fault type detection process, which combines the status of the bus under test and bus signals to classify and record fault types. Specifically, if a complete cycle is detected to have ended normally, but the next cycle does not occur completely, and the bus under test is in an idle state, the incomplete cycle data can be saved, and the fault type can be identified and recorded as the first fault, such as recording error type 1.

[0070] For the first fault, R&D personnel can intervene to analyze the master device of the last cycle data. For example, if the BMC is the master device and the slave device is the master device, after identifying the master device, analyze the fault reason why the bus is idle but no data is sent. If the fault reason is that the device that switched to master did not complete the transmission in one clock cycle, the specific reason for the interruption of the I2C task of the device that switched to master can be analyzed in conjunction with the device log.

[0071] Correspondingly, if the bus under test is detected to be not in an idle state, the bus signal is further detected to determine whether SDA is pulled low, and to distinguish whether the clock signal or the data signal is pulled low; if the data signal is detected to be pulled low, and there is an I2C SWITCH link in the entire I2C link of the bus under test, the data can be saved and the I2C SWITCH reset command can be executed. Then, by detecting whether the BMC side can restore normal access, it is determined whether the I2CSWITCH front-end line has been restored.

[0072] Correspondingly, if the I2C SWITCH front-end line is detected to be restored and the BMC can resume normal access, the BMC can reread each device. If there are devices that cannot be read successfully, it can be determined that the device is hanging, and the fault type is recorded as the second fault, such as error type 2. If the I2C SWITCH front-end line is detected to be not restored and the BMC rereads each device but still cannot read successfully, it can be determined that the BMC is hanging, and the fault type is recorded as the third fault, such as error type 3. When the R&D personnel receive this fault type mark, they can try to reset the I2C controller module in the BMC to see if it can be restored.

[0073] In some embodiments, detecting the fault type of the bus under test based on fault data may further include: if the bus signal at a low level is detected to be a clock signal, then resetting it using a bus switch and detecting whether the preceding circuit of the bus switch is restored; if the preceding circuit is detected to be restored, then determining the fault type as a fourth fault; if the preceding circuit is detected not to be restored, then determining the fault type as a fifth fault.

[0074] The fourth fault may include, but is not limited to, the sub-device failing to release the bus properly, and the fifth fault may include, but is not limited to, the management controller failing to release the bus properly.

[0075] For example, if the clock signal is pulled low and there is an I2C SWITCH link fast location module in the bus under test, the data needs to be saved and the I2C SWITCH reset command needs to be executed. The BMC will then reread the other devices except the problematic device. If the other devices can be read successfully but the problematic device cannot, it is determined that the problematic device is hanging because it did not release the bus properly (e.g., bus preemption failed but the bus was not released). The fault type is recorded as the fourth fault, such as error type 4. If the BMC still cannot read the other devices after rereading, it is determined that the BMC is hanging because it did not release the bus properly. The fault type is recorded as the fifth fault, such as error type 5.

[0076] In this way, the fault types of the bus under test can be simply classified according to the fault data, so as to notify the R&D personnel corresponding to the fault type to perform fault analysis and reproduction, and provide the R&D personnel with fault analysis directions, thereby improving the efficiency of fault reproduction and ultimately improving the efficiency of fault resolution.

[0077] In some embodiments, after determining the fault type as a second fault if the preceding line is detected to have recovered, the method of this embodiment may further include: sequentially sending reset signals to the sub-devices connected to the bus switch, identifying the sub-devices that have not recovered successfully as target fault devices, and recording the target fault devices.

[0078] The target faulty device may include at least one sub-device that has failed.

[0079] Specifically, when the current-level line is restored, a reset signal can be sent to multiple sub-devices sequentially via the bus switch to check whether the sub-devices can resume normal communication. If there is a sub-device that cannot be restored, it can be identified as the target fault device, thereby pointing out the specific target fault device and notifying the relevant personnel of the target fault device to handle the fault.

[0080] In some embodiments, before resetting using a bus switch and detecting whether the preceding circuitry of the bus switch has been restored, the method of this embodiment may further include: detecting whether a bus switch exists on the bus to be tested; if a bus switch is detected not to exist on the bus to be tested, then directly sending a reset signal to the sub-device corresponding to the bus to be tested.

[0081] For example, the addresses of each sub-device connected to the bus under test can be obtained first, and it can be determined whether a bus switch is needed to control multiple sub-devices with the same address. If there is no bus switch on the bus under test, a reset signal can be sent directly to the sub-device corresponding to the bus under test through the FPGA in the fault detection device or the FPGA in the server to restore bus communication.

[0082] In some embodiments, after determining that the periodic data is fault data, the method of this embodiment may further include: saving the fault data.

[0083] For example, when the fault detection device detects that the periodic data is fault data, it can save the fault data into memory. If the relevant personnel do not have time to collect the fault data in time, the fault data in the memory can be read later to reproduce and analyze the fault, thus providing convenience for the relevant personnel.

[0084] In this way, this embodiment can automatically identify and save fault data without the need for personnel to manually capture fault data. This makes it easier for relevant R&D personnel to more effectively and quickly reproduce the debug version, thereby quickly reproducing the problem and resolving it promptly.

[0085] In some embodiments, after determining whether the periodic data of the bus signal is complete based on the periodic identifier of the bus signal of the bus to be tested, the method of this embodiment may further include: if the periodic data is detected to be complete, then determining that the periodic data is normal data and discarding the normal data.

[0086] For example, the fault detection device can determine whether to save the periodic data based on whether the periodic data is complete. When accessing the data normally, the periodic data can be identified as normal data and does not need to be saved to the memory of the fault detection device, thereby saving the storage space of the fault detection device and reducing the impact of memory limitations on fault data retrieval.

[0087] In specific application scenarios, after the fault detection device starts reading data, it can first determine whether there are complete START and STOP bits. When a cycle data with complete START and STOP bits can be captured, another clock cycle can be captured. If a cycle data corresponding to a complete clock cycle can still be captured, the previous cycle data can be discarded until abnormal data (fault data) appears. When the fault data appears, the fault data is saved to the memory. In this way, by judging the complete data cycle, the loss of abnormal data can be avoided, and memory consumption can be reduced by not saving normal data.

[0088] Compared to existing technologies, this embodiment uses a fault detection device to connect the management controller and the sub-device to the bus under test via the pinhole of the server motherboard. Then, based on the periodicity of the bus signal, incomplete periodic data is identified as fault data. The fault type of the bus under test is then determined based on the fault data, eliminating the need for manual data retrieval and significantly improving the efficiency of fault data retrieval. Simultaneously, automatic fault type classification shortens manual detection and analysis time, further improving fault detection efficiency. Furthermore, it can automatically identify the fault type of the bus under test based on conditions such as whether the bus is idle, whether the bus signal is at a low level, and whether the preceding circuitry of the bus switch has recovered. Fault data is saved while normal data is discarded, facilitating notification to the corresponding R&D personnel for fault analysis and reproduction. This provides R&D personnel with analytical guidance, eliminating the need for on-site data retrieval and improving the efficiency of fault reproduction, thus enhancing fault resolution efficiency. Simultaneously, it saves storage space on the fault detection device, reducing the impact of memory limitations on fault data retrieval.

[0089] To further illustrate the specific implementation process of the method in this embodiment, this embodiment provides the following: Figure 5 The system shown includes: a pinhole 11 and a fault detection device 21;

[0090] The pinhole 11 is mounted on the server motherboard, and there is at least one bus between the server motherboard's management controller and the sub-device, with the pinhole 11 connected to at least one bus;

[0091] The pin hole 11 is used to connect the pins of the fault detection device 21;

[0092] The fault detection device 21 is used to connect to at least one bus under test through the pin hole 11; it determines whether the period data of the bus signal is complete according to the period identifier of the bus signal under test; if the period data is not complete, it determines that the period data is fault data and detects the fault type of the bus under test according to the fault data.

[0093] The pinhole 11 (pin) can be installed near the management controller (such as BMC) of the server motherboard to minimize the trace length and reduce signal attenuation and interference. The pinhole 11 can be used to connect the fault detection device 21 (quick location module) to perform fault detection on the bus under test, receive the bus signal, determine whether the period data is complete according to the period identifier of the bus signal, identify incomplete data as fault data, and then perform fault type detection based on the fault data, thereby improving the convenience of connecting the bus and improving the efficiency of fault detection.

[0094] Accordingly, the bus may include buses with standard frame formats, such as I2C, UART, RS485, etc., and the bus under test may include one or more buses that have failed. When multiple buses are involved, the pin 11 may include multiple independent pin 11s, each pin 11 corresponding to a different bus line or signal line. The appropriate pin 11 type can be selected according to the bus requirements, such as single-row pin 11, double-row pin 11, etc., and independent pins are assigned to each bus during the printed circuit board (PCB) layout stage for routing, ensuring sufficient spacing between the bus signal lines to avoid signal interference.

[0095] Compared with existing technologies, this embodiment can use a fault detection device 21 to connect the management controller and the sub-device to the bus under test through the pinhole 11 of the server motherboard. Then, based on the periodicity of the bus signal of the bus under test, incomplete periodic data is identified as fault data. The fault type of the bus under test is then determined based on the fault data. This eliminates the need for manual collection of fault data from the bus under test, effectively improving the efficiency of fault data collection. At the same time, it realizes automatic classification of fault types, shortens the time for manual detection and analysis, and thus improves the efficiency of fault detection.

[0096] Based on the above, Figure 3Accordingly, this embodiment also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method. Figure 3 The method shown.

[0097] Based on this understanding, the technical solution of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as CD-ROM, USB flash drive, mobile hard drive, etc.) and includes several instructions to cause a computer device (such as personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of this application.

[0098] Based on the above, Figure 3 To achieve the above objectives, embodiments of this application also provide an electronic device, such as a personal computer or a server, comprising a storage medium and a processor; the storage medium for storing a computer program; and the processor for executing the computer program to implement the above-described... Figure 3 The method shown.

[0099] In some embodiments, the aforementioned physical device may further include a user interface, a network interface, a camera, radio frequency (RF) circuitry, sensors, audio circuitry, a Wi-Fi module, etc. The user interface may include a display screen, an input unit such as a keyboard, etc., and optionally, a USB interface, a card reader interface, etc. In some embodiments, the network interface may include a standard wired interface, a wireless interface (such as a Wi-Fi interface), etc.

[0100] Those skilled in the art will understand that the physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or combine certain components, or have different component arrangements.

[0101] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the aforementioned physical device, supporting the operation of information processing programs and other software and / or programs. The network communication module is used to enable communication between the various components within the storage medium, as well as communication with other hardware and software in the information processing physical device.

[0102] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms, or it can be implemented by hardware. By applying the solution of this embodiment, compared with the prior art, this embodiment can use a fault detection device to connect the management controller and the sub-device to the bus under test through the pinhole of the server motherboard. Then, based on the periodicity of the bus signal of the bus under test, incomplete periodic data is identified as fault data, and the fault type of the bus under test is determined based on the fault data. Therefore, there is no need to manually capture the fault data of the bus under test, which effectively improves the efficiency of fault data capture. At the same time, it realizes automatic classification of fault types, shortens the manual detection and analysis time, and thus improves the efficiency of fault detection. Furthermore, it can automatically identify the fault type of the bus under test based on conditions such as whether the bus under test is idle, whether the bus signal is at a low level, and whether the pre-stage circuit of the bus switch has recovered. It saves the fault data and discards normal data, so as to notify the R&D personnel corresponding to the fault type to perform fault analysis and reproduction. It also provides R&D personnel with fault analysis directions. Fault data is captured without the need for personnel to be on duty, which improves the efficiency of fault reproduction by R&D personnel and thus improves the efficiency of fault resolution. At the same time, it saves the storage space of the fault detection device, thereby reducing the impact of memory limitations on fault data capture.

[0103] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0104] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A fault detection method, characterized in that, Performed by a fault detection device, wherein the pins of the fault detection device are connected to pin headers mounted on a server motherboard, and the server motherboard's management controller and sub-devices have at least one bus connection, the pin headers being connected to the at least one bus, the method comprising: The pin is connected to the bus to be tested in at least one of the buses through the pin hole; Based on the period identifier of the bus signal of the bus under test, determine whether the period data of the bus signal is complete; If the periodic data is found to be incomplete, the periodic data is determined to be faulty data, and the fault type of the bus under test is detected based on the faulty data. The step of detecting the fault type of the bus under test based on the fault data includes: Based on the fault data, the status of the bus under test is detected; If the bus under test is detected to be in an idle state, the fault type is determined to be the first fault, which includes task interruption caused by master device switching; If the bus under test is detected to be not in an idle state, then a low-level bus signal is detected. If a low-level bus signal is detected as a data signal, a bus switch is used to reset the bus and the preceding circuitry of the bus switch is checked to see if it has recovered. If the upstream line is detected to have recovered, the fault type is determined to be a second fault, which includes sub-device faults; If the upstream line is not restored, the fault type is determined to be a third fault, which includes a management controller fault. The step of detecting the fault type of the bus under test based on the fault data further includes: If a low-level bus signal is detected as a clock signal, a bus switch is used to reset the bus and the preceding circuitry of the bus switch is checked to see if it has recovered. If the front-end line is detected to have recovered, the fault type is determined to be the fourth fault, which includes the sub-device failing to properly release the bus; If the preceding line is not restored, the fault type is determined to be the fifth fault, which includes the management controller failing to properly release the bus.

2. The method according to claim 1, characterized in that, After determining the fault type as a second fault if the upstream line is detected to have recovered, the method further includes: Reset signals are sent sequentially to the sub-devices connected to the bus switch. Sub-devices that fail to recover are identified as target fault devices, and the target fault devices are recorded.

3. The method according to claim 1, characterized in that, Before resetting using a bus switch and detecting whether the preceding circuitry of the bus switch has recovered, the method further includes: Detect whether a bus switch exists on the bus under test; If it is detected that there is no bus switch on the bus under test, a reset signal is sent directly to the sub-device corresponding to the bus under test.

4. The method according to claim 1, characterized in that, After determining that the periodic data is fault data, the method further includes: Save the fault data.

5. The method according to claim 1, characterized in that, After determining whether the period data of the bus signal is complete based on the period identifier of the bus signal under test, the method further includes: If the periodic data is detected to be complete, then the periodic data is determined to be normal data and is discarded.

6. A fault detection system, characterized in that, include: Pinholes and fault detection devices; The pinhole is mounted on the server motherboard, and there is at least one bus between the server motherboard's management controller and the sub-device, with the pinhole connected to the at least one bus; The pin hole is used to connect the pin of the fault detection device; The fault detection device is used to connect to the bus under test in at least one bus through the pin hole; to determine whether the period data of the bus signal is complete according to the period identifier of the bus signal of the bus under test; if the period data is detected to be incomplete, the period data is determined to be fault data, and the fault type of the bus under test is detected according to the fault data. The step of detecting the fault type of the bus under test based on the fault data includes: Based on the fault data, the status of the bus under test is detected; If the bus under test is detected to be in an idle state, the fault type is determined to be the first fault, which includes task interruption caused by master device switching; If the bus under test is detected to be not in an idle state, then a low-level bus signal is detected. If a low-level bus signal is detected as a data signal, a bus switch is used to reset the bus and the preceding circuitry of the bus switch is checked to see if it has recovered. If the upstream line is detected to have recovered, the fault type is determined to be a second fault, which includes sub-device faults; If the upstream line is not restored, the fault type is determined to be a third fault, which includes a management controller fault. The step of detecting the fault type of the bus under test based on the fault data further includes: If a low-level bus signal is detected as a clock signal, a bus switch is used to reset the bus and the preceding circuitry of the bus switch is checked to see if it has recovered. If the front-end line is detected to have recovered, the fault type is determined to be the fourth fault, which includes the sub-device failing to properly release the bus; If the preceding line is not restored, the fault type is determined to be the fifth fault, which includes the management controller failing to properly release the bus.

7. An electronic device, characterized in that, include: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.

8. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-5.

Images