Input signal adjusting circuit, method and device

Abstract

The invention relates to an input signal adjusting circuit, method and device. The method comprises the following steps: acquiring the signal intensity of a target signal in real time; if it is detected that the size relation between the signal strength and a set threshold value changes at the current moment, a target gain link is selected from a gain link set according to the pre-associated size relation and gain links, each gain link in the gain link set synchronously executes gain adjustment of different degrees, and the target gain link is obtained. The set threshold value is the maximum input amplitude of the analog-to-digital converter; and controlling a change-over switch to switch to the target gain link, so that the target gain link inputs the adjustment signal at the current moment to the analog-to-digital converter. The signal precision can be improved.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to an input signal adjustment circuit, method and device. Background Art

[0002] The size of the signal collected in the imaging system is generally not fixed, so it is necessary to adjust the dynamic range of the collected signal. The dynamic range is a common performance indicator of ADC (Analog-to-Digital Converter), which refers to the ratio between the maximum and minimum values ​​that the ADC can reliably measure. For the ADC, the dynamic range must match the maximum input amplitude of the input signal to ensure that the signal accuracy is high enough.

[0003] If the collected signal is a small signal, the input signal does not reach the maximum input amplitude of the ADC and cannot fully utilize the dynamic range of the ADC. Therefore, a digital variable gain amplifier (DVGA) and a fixed gain (GA) are required to amplify the signal. However, it is easy for the input signal to exceed the maximum input amplitude of the ADC, resulting in signal overflow. The overflowed signal cannot be collected by the ADC, and the overflowed part cannot utilize the dynamic range of the ADC, resulting in a mismatch between the dynamic range of the ADC and the maximum input amplitude of the signal, and reduced signal accuracy. Summary of the invention

[0004] The present application provides an input signal adjustment circuit, method and device to solve the problem of low signal accuracy.

[0005] In a first aspect, the present application provides an input signal adjustment circuit, the circuit comprising: a first gain link, a second gain link, a conversion switch, an analog-to-digital converter, and an FPGA;

[0006] The input ends of the first gain link and the second gain link are both connected to the signal input port, and the first gain link and the second gain link are used to synchronously perform gain adjustment of different degrees;

[0007] The input end of the conversion switch is connected to the output end of the first gain link and the output end of the second gain link respectively, and the conversion switch is used to switch to the first gain link or the second gain link according to the control instruction, wherein the adjustment signal output by the switched gain link is close to and lower than the maximum input amplitude of the analog-to-digital converter compared with the adjustment signal output by other gain links;

[0008] The input end of the analog-to-digital converter is connected to the output end of the conversion switch, and the analog-to-digital converter is used to output the processed target signal;

[0009] The input end of the FPGA is connected to the output end of the analog-to-digital converter, and the output end of the FPGA is connected to the input end of the conversion switch. The FPGA is used to send the control instruction to the conversion switch when it detects that the size relationship between the signal strength of the target signal and the set threshold at the current moment changes.

[0010] Optionally, the FPGA includes a signal comparison module, a calibration module and a digital down converter;

[0011] The input end of the signal comparison module is connected to the output end of the analog-to-digital converter, the output end of the signal comparison module is connected to the input end of the conversion switch, and the signal comparison module is used to compare the signal strength of the target signal with the set threshold and issue a control instruction;

[0012] The input end of the calibration module is connected to the output end of the signal comparison module, and the calibration module is used to perform delay and gain calibration on the signal adjusted by the second gain link and the signal adjusted by the first gain link;

[0013] The input end of the digital down converter is connected to the output end of the signal comparison module and the output end of the calibration module respectively, and the digital down converter is used to downsample the signal after delay and gain calibration.

[0014] Optionally, the first gain link and the second gain link both include an amplifier and a filter;

[0015] The input end of the amplifier is connected to the signal input port, and the amplifier is used to perform gain adjustment on the initial signal;

[0016] The input end of the filter is connected to the output end of the amplifier, the output end of the filter is connected to the input end of the conversion switch, and the filter is used to filter the initial signal after gain adjustment.

[0017] In a second aspect, the present application provides an input signal adjustment method, the method comprising:

[0018] Acquire the signal strength of the target signal in real time, wherein the target signal is a signal processed by an analog-to-digital converter;

[0019] If it is detected that the magnitude relationship between the signal strength and the set threshold value at the current moment changes, a target gain link is selected from the gain link set according to the pre-associated magnitude relationship and the gain link, wherein each gain link in the gain link set synchronously performs gain adjustment to a different degree, and the adjustment signal output by the target gain link is close to and lower than the set threshold value compared to the adjustment signals output by other gain links in the gain link set, and the set threshold value is the maximum input amplitude of the analog-to-digital converter;

[0020] The conversion switch is controlled to switch to the target gain link, so that the target gain link inputs the adjustment signal at the current moment into the analog-to-digital converter.

[0021] Optionally, if it is detected that the magnitude relationship between the signal strength and the set threshold at the current moment changes, selecting a target gain link from the gain link set according to the pre-associated magnitude relationship and gain link includes:

[0022] At the current moment, if it is detected that the signal strength changes from being greater than or equal to the set threshold to being less than the set threshold, a first gain link is selected from the gain link set according to the pre-associated size relationship and gain link, wherein the first gain link is used to amplify the signal strength of the initial signal by using a first gain;

[0023] At the current moment, if it is detected that the signal strength changes from less than the set threshold to greater than or equal to the set threshold, a second gain link is selected from the gain link set based on the pre-associated size relationship and gain link, wherein the second gain link is used to amplify the signal strength of the initial signal using a second gain, and the first gain is greater than the second gain.

[0024] Optionally, controlling the conversion switch to switch to the target gain link so that the target gain link inputs the adjustment signal at the current moment into the analog-to-digital converter comprises:

[0025] After sending a control instruction to the conversion switch so that the conversion switch switches to the target gain link, the target gain link inputs the adjustment signal at the current moment into the analog-to-digital converter, wherein the first gain link and the second gain link independently and synchronously perform gain adjustment on the initial signal.

[0026] Optionally, after acquiring the signal strength of the target signal in real time, the method further includes:

[0027] If it is detected that the magnitude relationship between the signal strength and the set threshold at the current moment has not changed, and the signal strength is greater than or equal to the set threshold, delay and gain calibration is performed on the digitized signal processed by the analog-to-digital converter based on a preset reference signal, wherein the preset reference signal is the signal mediated by the first gain link;

[0028] A digital down-converter is used to downsample the delay and gain calibrated signal.

[0029] In a third aspect, the present application provides an input signal adjustment device, the device comprising:

[0030] An acquisition module, used for acquiring the signal strength of a target signal in real time, wherein the target signal is a signal processed by an analog-to-digital converter;

[0031] A selection module, configured to select a target gain link from a gain link set according to a pre-associated size relationship and a gain link if it is detected that a size relationship between the signal strength and a set threshold value at the current moment changes, wherein each gain link in the gain link set synchronously performs gain adjustment to a different degree, and an adjustment signal output by the target gain link is close to and lower than the set threshold value compared to adjustment signals output by other gain links in the gain link set, and the set threshold value is the maximum input amplitude of the analog-to-digital converter;

[0032] The control module is used to control the conversion switch to switch to the target gain link, so that the target gain link inputs the adjustment signal at the current moment into the analog-to-digital converter.

[0033] In a fourth aspect, the present application provides an electronic device comprising: at least one communication interface; at least one bus connected to the at least one communication interface; at least one processor connected to the at least one bus; and at least one memory connected to the at least one bus.

[0034] In a fifth aspect, the present application further provides a computer storage medium storing computer executable instructions, wherein the computer executable instructions are used to execute the input signal adjustment method described in any one of the above items of the present application.

[0035] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art: each gain link synchronously performs gain adjustment to varying degrees. When the size relationship between the signal strength and the set threshold changes, it indicates that the current gain link can no longer meet the maximum input amplitude of the analog-to-digital converter. At this time, based on the pre-associated size relationship and gain link, a target gain link that can adjust the signal strength to be closer to and lower than the set threshold is selected. The present application makes a real-time decision before the signal enters the analog-to-digital converter, so that the signal input to the analog-to-digital converter is as close to and lower than the maximum input amplitude as possible, thereby improving the matching degree between the dynamic range of the ADC and the signal input amplitude, thereby improving the signal accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0038] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0039] Figure 1 A schematic diagram of a circuit for adjusting the dynamic range of a received signal in a spectrometer receiver in the prior art;

[0040] Figure 2 An overall circuit diagram provided for an embodiment of the present application;

[0041] Figure 3 A schematic diagram of the internal circuit of the FPGA provided in the embodiment of the present application;

[0042] Figure 4 A flow chart of an input signal adjustment method provided in an embodiment of the present application;

[0043] Figure 5 An internal control schematic diagram of the FPGA provided in the embodiment of the present application;

[0044] Figure 6 A schematic diagram of an initial signal flowing through multiple gain channels provided in an embodiment of the present application;

[0045] Figure 7A schematic diagram of calculating the maximum input amplitude of an ADC provided in an embodiment of the present application;

[0046] Figure 8 A schematic diagram of the structure of an input signal adjustment device provided in an embodiment of the present application;

[0047] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0049] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0050] In MRI (Magnetic Resonance Imaging) systems, the area of ​​the excited object, the thickness of the layer and other parameters vary according to different applications, which leads to significant differences in the size of the magnetic resonance signal generated. In order to ensure high-quality image acquisition, the receiver of the MRI system must be able to cover all possible signal dynamic ranges. This means that the magnetic resonance spectrometer receiver needs to have sufficient dynamic range to adapt to various situations from weak small signals to strong large signals.

[0051] Existing MRI receivers usually use DVGA to adjust the dynamic range of the acquired signal. Figure 1 As shown, assuming that the fixed gain of the receiver is GA and the gain range of the DVGA is (GB, GC), the total gain dynamic range of the receiver is GA+GB to GA+GC.

[0052] Figure 1In the figure, MR signal (Magnetic Resonance signal) is the magnetic resonance signal, AmP (Amplifier) ​​is the amplifier, VGA (Variable Gain Amplifier) ​​is the variable gain amplifier, and Filter is the filter.

[0053] Dynamic range (DR) is a key performance indicator of ADC, which is defined as the ratio between the maximum and minimum values ​​that the ADC can reliably measure. For an ideal N-bit ADC, its dynamic range can be expressed as: Dynamic range = 6.02*N□(dB), where N is the number of bits of the ADC. The signal amplitude that the ADC can resolve ranges from the minimum value (least significant bit, LSB) to the maximum value (LSB*(2^N-1)). When expressed in decibels, the dynamic range of the ADC is: A to A*10^(6.02*N / 20), where A is the minimum signal amplitude that the ADC can detect.

[0054] In order to obtain the best ADC conversion accuracy, the dynamic range of the ADC should match the amplitude of the maximum initial signal. If the dynamic range of the ADC does not match the maximum input amplitude, the signal accuracy will be reduced. The SNR (Signal-to-Noise Ratio) of the ADC can be calculated by the following formula:

[0055] SNR=ENOB*6.02+1.76□, where ENOB ((Effective Number of Bits)) is the effective number of bits of ADC.

[0056] The higher the conversion accuracy of the ADC, the higher its effective number of bits, and thus the SNR will be improved accordingly. For MRI images, a high signal-to-noise ratio is crucial, so it is necessary to make full use of the dynamic range of the ADC and make the signal amplitude of the input ADC match the maximum accuracy of the ADC as much as possible to obtain a high signal-to-noise ratio.

[0057] Although most MRI signals are weak and small signals that require sufficient gain amplification to meet the dynamic range of the ADC, the gain dynamic range of the DVGA is limited. In order to meet the requirements of a high signal-to-noise ratio, a fixed gain GAGA is usually required. However, when performing full excitation or 3D imaging, the signal intensity generated is much greater than the small signal generated by the conventional sequence method. Even if the fixed gain GA of the receiver and the minimum gain GB of the DVGA are combined, the signal amplitude of the input ADC may still exceed the dynamic range of the ADC, resulting in signal overflow. The overflowed signal cannot be collected by the ADC, resulting in a decrease in signal accuracy, which ultimately affects the signal-to-noise ratio of the image.

[0058] In order to solve the above-mentioned problems, according to one aspect of an embodiment of the present application, a schematic diagram of an input signal adjustment circuit is provided, such as Figure 2 As shown, the circuit includes a first gain link, a second gain link, a conversion switch ( Figure 2 The first gain link and the second gain link are both connected to the signal input port, the output end of the first gain link and the output end of the second gain link are respectively connected to the input end of the conversion switch, the output end of the conversion switch is connected to the input end of the analog-to-digital converter, the input end of the FPGA is connected to the output end of the analog-to-digital converter, and the output end of the FPGA is connected to the input end of the conversion switch.

[0059] After the initial signal enters the circuit through the signal input port, it will flow through the first gain link and the second gain link at the same time. The first gain link and the second gain link respectively increase the signal of the initial signal with different gains, so that the two gain links respectively output gain-adjusted signals. When the initial signal is adjusted for the first time, the conversion switch turns on the first gain link, and the amplified signal is input to the analog-to-digital converter for digital processing by default, so that the FPGA obtains the digitally processed signal, that is, the target signal. The FPGA determines the signal strength of the target signal based on the set threshold. If the signal strength is less than the set threshold, the FPGA will control the conversion switch to turn on the first gain link, so that the signal amplified by the first gain link is input to the analog-to-digital converter; if the signal strength is greater than or equal to the set threshold, the FPGA will control the conversion switch to turn on the second gain link, so that the signal amplified by the second gain link is input to the analog-to-digital converter, wherein the signal amplified by the second gain is smaller than the original signal to prevent the input signal of the analog-to-digital converter from exceeding its maximum input amplitude. This process is continuous and real-time, ensuring that the circuit can respond to any changes in signal strength immediately.

[0060] To put it another way, according to the judgment result of FPGA, the target signal is divided into two sub-signals, one is a first sub-signal whose signal strength is less than a set threshold, and the other is a second sub-signal whose signal strength is greater than or equal to the set threshold. FPGA sends different control instructions to the conversion switch according to the sub-signals, and the conversion switch switches to the selected target gain path, thereby obtaining a gain-adjusted signal from the output end of the target gain path. The signal strength output by the target gain path is closer to the maximum input amplitude of the analog-to-digital converter than the signal strength output by other gain links, so that the input signal of the analog-to-digital converter is more in line with the dynamic range.

[0061] If the target signal is small as a whole and all signals do not exceed the set threshold, then it is necessary to obtain the output signal amplified by the first gain channel; if the target signal is large as a whole and contains signals both greater than the set threshold and less than the set threshold, the FPGA splits the signal into two parts: the first sub-signal (small amplitude part): obtain this part of the signal from the first gain channel (GmaxChannel) to ensure that these signal components can be fully amplified; the second signal (large amplitude part): obtain this part of the signal from the second gain channel (Gmin Channel) to determine that these signals are amplified by small gains to avoid overflowing the maximum input amplitude of the analog-to-digital converter.

[0062] In the present application, each gain link synchronously performs gain adjustment to varying degrees. When the magnitude relationship between the signal strength and the set threshold changes, it indicates that the current gain link can no longer meet the maximum input amplitude of the analog-to-digital converter. At this time, based on the pre-associated magnitude relationship and gain link, a target gain link that can adjust the signal strength to be closer to and lower than the set threshold is selected. The present application makes a real-time decision before the signal enters the analog-to-digital converter, so that the signal input to the analog-to-digital converter is as close to and lower than the maximum input amplitude as possible, thereby improving the matching degree between the dynamic range of the ADC and the signal input amplitude, thereby improving the signal accuracy.

[0063] Alternatively, if Figure 3 As shown, the FPGA includes a signal comparison module, the input end of the signal comparison module is connected to the output end of the analog-to-digital converter, and the output end of the signal comparison module is respectively connected to the input end of the conversion switch and the input end of the digital down converter. The signal comparison module is used to compare the signal strength output by the analog-to-digital converter with the set threshold in real time, determine the relationship between the signal strength and the set threshold, and output a corresponding control instruction to the conversion switch. The control instruction is used to instruct the conversion switch which gain link to turn on, so as to obtain the signal of the gain link after gain adjustment.

[0064] The FPGA also includes a calibration module and a digital down converter (DDC). The input of the calibration module is connected to the output of the signal comparison module, the output of the calibration module is connected to the input of the digital down converter, and the input of the digital down converter is also connected to the output of the signal comparison module. When the signal comparison module determines that the second gain link needs to be used, the flag of the second gain link will be sent to the calibration module. The calibration module is responsible for delaying and gain calibration of the signal flowing through the second gain link to ensure that the data of different gain paths (the first gain link and the second gain link) are consistent in time and amplitude. The digital down converter performs downsampling and other necessary digital processing, such as filtering, on the calibrated signal to provide high-quality digital signals for subsequent data analysis; when the signal comparison module determines that the first gain link needs to be used, the flag of the first gain link will be sent to the digital down converter.

[0065] Alternatively, if Figure 2 As shown, the first gain link and the second gain link both include an amplifier and a filter; the input end of the amplifier is connected to the output end of the signal input port; the input end of the filter is connected to the output end of the amplifier, and the output end of the filter is connected to the input end of the conversion switch.

[0066] The first gain link (Gmax Channel) and the second gain link (Gmin Channel) both include amplifiers and filters to ensure that the signal is properly amplified and filtered before entering the analog-to-digital converter. Among them, the amplifier is responsible for making necessary gain adjustments to the initial signal. For the first gain link that amplifies the signal, the amplifier provides a larger gain to ensure that the small signal can be fully amplified; and for the second gain link, the amplifier provides a smaller gain to prevent the large signal from exceeding the maximum input amplitude of the analog-to-digital converter. The filter is used to eliminate noise and other unnecessary frequency components in the signal to ensure that only signals within the target frequency band enter the subsequent processing stage, which not only improves the quality of the signal, but also reduces the complexity of subsequent processing.

[0067] The circuit composition and working principle in this application are shown below.

[0068] 1. Signal input port ( Figure 2 (not shown schematically) : serves as the entrance for all external analog signals to enter the system and is connected to the input ends of the first gain link and the second gain link.

[0069] 2. The first gain link (Gmax Channel) and the second gain link (Gmin Channel).

[0070] The input ends of the two gain links are connected to the output end of the signal input port to receive the monitored signal. The two gain links are used to provide gain amplified signals of different sizes to adapt to the maximum input amplitude limit of the analog-to-digital converter.

[0071] First gain link (Gmax Channel): Designed for small-amplitude signals (first signals), it provides higher gain so that these signal components can be fully amplified.

[0072] The second gain link (Gmin Channel): is designed specifically for large-amplitude signals (second signals) and provides lower gain to prevent the signal from exceeding the maximum input amplitude of the analog-to-digital converter.

[0073] 3.Conversion switch.

[0074] The input end of the conversion switch is connected to the output end of the first gain link and the output end of the second gain link respectively, and the output end is directly connected to the input end of the analog-to-digital converter. The conversion switch is the core component of signal path switching. It selectively directs the signal to different gain links according to the control instructions issued by the FPGA.

[0075] 4. Analog-to-digital converter.

[0076] The input end of the analog-to-digital converter is connected to the output end of the conversion switch to receive signals from different gain links. The analog-to-digital converter is responsible for converting the analog signal into a digital signal for use by the subsequent digital processing module.

[0077] 5. Field Programmable Gate Array (FPGA).

[0078] The input end of the FPGA is connected to the output end of the analog-to-digital converter to obtain real-time signal strength, and its output end is connected to the conversion switch to send control instructions for path selection.

[0079] FPGA decides which gain link to output the signal based on the relationship between the signal strength and the set threshold. If the overall signal is less than the set threshold, the entire signal output by the first gain link (Gmax Channel) is selected; if the signal has both parts greater than and less than the set threshold, the signal is split into two parts: the part less than the set threshold selects the output of the first gain link (Gmax Channel), and the part greater than or equal to the set threshold selects the output of the second gain link (Gmin Channel).

[0080] FPGA is the control center of the entire system. It obtains the signal strength of the target signal in real time and makes path selection decisions based on it. FPGA controls the conversion switch to ensure that the signal is obtained from the output of the correct gain link, so that the strength of the obtained signal can reach or approach the maximum input amplitude of the analog-to-digital converter.

[0081] The embodiment of the present application also provides an input signal adjustment method, which can be executed by an FPGA. The input signal adjustment method provided by the embodiment of the present application will be described in detail below in conjunction with a specific implementation method. Figure 4 As shown, the specific steps are as follows:

[0082] Step 401: acquiring the signal strength of a target signal in real time, wherein the target signal is a signal processed by an analog-to-digital converter;

[0083] Step 402: if it is detected that the magnitude relationship between the signal strength at the current moment and the set threshold value changes, a target gain link is selected from a gain link set according to the pre-associated magnitude relationship and the gain link, wherein each gain link in the gain link set synchronously performs gain adjustment to a different degree, and the set threshold value is the maximum input amplitude of the analog-to-digital converter;

[0084] Step 403: Control the conversion switch to switch to the target gain link, so that the target gain link inputs the adjustment signal at the current moment into the analog-to-digital converter.

[0085] When the initial signal (analog signal) enters the circuit from an external source through the signal input port, it will be simultaneously assigned to the first gain link and the second gain link. The two gain links respectively amplify the initial signal with different gains. When the initial signal is processed for the first time, the default conversion switch turns on the first gain link, and the fully amplified signal enters the analog-to-digital converter for analog-to-digital conversion and obtains the target signal. At this time, the FPGA will acquire the digital signal provided by the analog-to-digital converter, that is, the target signal, in real time, and calculate its actual signal strength. Optionally, the initial signal can be a magnetic resonance signal, a radio frequency signal, or an acoustic signal. The embodiment of the present application does not specifically limit the type of the initial signal.

[0086] A threshold value is preset inside the FPGA, which represents the maximum input amplitude of the analog-to-digital converter and is the maximum signal strength that the analog-to-digital converter can process without distortion under ideal conditions. Optionally, the threshold value is lower than the maximum input amplitude of the analog-to-digital converter and the difference between the threshold value and the maximum input amplitude is less than the preset difference, that is, the threshold value is less than and close to the maximum input amplitude, that is, the FPGA determines whether the signal strength is close to the maximum input amplitude of the analog-to-digital converter based on the threshold value.

[0087] The FPGA will compare the signal strength at the current moment acquired in real time with the set threshold. When the size relationship between the detected signal strength and the set threshold changes, the FPGA will automatically execute the pre-configured selection algorithm, which maps to the corresponding gain link selection strategy based on the relationship between the signal strength and the threshold. Specifically, based on the comparison results and the size relationship, and the mapping table between the gain links, the FPGA determines the gain link that best suits the current signal conditions as the target gain link. For example, when the signal strength is detected to be greater than the set threshold, it switches to the second gain link, and when the signal strength is detected to be less than the set threshold, it switches to the first gain link. If the signal strength and the set threshold have not changed, then continue to use the original gain link.

[0088] Once the target gain link is determined, the FPGA will immediately send a control instruction to the conversion switch to turn on the newly selected target gain link. This process is very fast, usually completed within a few microseconds, and will hardly affect the continuity and integrity of the signal. The target gain link sends the current adjustment signal to the analog-to-digital converter through the conversion switch for analog-to-digital conversion. Since the signal strength is close to or reaches the set threshold at this time, the analog-to-digital converter can obtain high-quality input signals.

[0089] Exemplarily, when the initial signal enters the circuit through the signal input port, it will be simultaneously distributed to the first gain link and the second gain link. At this time, the default conversion switch turns on the first gain link, and the initial signal is amplified and enters the analog-to-digital converter to obtain a digitized target signal. If the FPGA determines that the target signal at the first moment is greater than the set threshold, it controls the conversion switch to switch to the second gain link. At this time, the adjustment signal at the first moment in the second gain link is input to the analog-to-digital converter. If the FPGA finds that the target signal becomes less than the set threshold at the nth moment, it controls the conversion switch to switch to the first gain link again, and the first gain link inputs the adjustment signal at the nth moment to the analog-to-digital converter.

[0090] In the present application, the size relationship between the signal strength and the set threshold is detected in real time. When a change in the size relationship is detected, it indicates that the current gain link is no longer applicable. Then, based on the pre-associated size relationship and gain link, the target gain link that best suits the current signal strength is dynamically switched to ensure that the regulated signal output by the switched target gain link can reach and be lower than the maximum input amplitude of the analog-to-digital converter as much as possible. The present application dynamically switches the gain link according to the signal strength, so that the input amplitude of the analog-to-digital converter always matches its dynamic range, thereby improving the signal accuracy.

[0091] As an optional implementation, in step 402, if it is detected that the magnitude relationship between the signal strength at the current moment and the set threshold value changes, then selecting a target gain link from the gain link set according to the pre-associated magnitude relationship and gain link includes:

[0092] Step S11: at the current moment, if it is detected that the signal strength changes from being greater than or equal to the set threshold to being less than the set threshold, a first gain link is selected from the gain link set according to the pre-associated magnitude relationship and the gain link, wherein the first gain link is used to amplify the signal strength of the initial signal by using a first gain;

[0093] Step S12: At the current moment, if it is detected that the signal strength changes from less than the set threshold to greater than or equal to the set threshold, a second gain link is selected from the gain link set based on the pre-associated size relationship and gain link, wherein the second gain link is used to amplify the signal strength of the initial signal using a second gain, and the first gain is greater than the second gain.

[0094] A mapping table between size relationships and gain links is pre-set in the FPGA, which specifies that the first gain link is used when the signal strength is less than a set threshold, and the second gain link is used when the signal strength is greater than or equal to the set threshold. The FPGA compares the real-time acquired signal strength with the preset maximum input amplitude of the analog-to-digital converter (set threshold), determines whether to switch the gain link based on the comparison result and the mapping table, and then selects the most suitable target gain link from the gain link set to adjust the strength of the initial signal to the set threshold.

[0095] If the signal strength at the previous moment is equal to or greater than the set threshold, and the signal strength at the current moment is less than the set threshold, indicating that the gain link needs to be switched, the FPGA selects the first gain link from the gain link set, where the first gain link is used to amplify the signal strength of the initial signal using the first gain. This means that when the signal strength is insufficient, the system will select a link with a higher gain to ensure that the signal strength can be increased to the optimal level and fully utilize the dynamic range of the analog-to-digital converter.

[0096] If the signal strength at the previous moment is less than the set threshold, and the signal strength at the current moment is equal to or greater than the set threshold, indicating that the gain link needs to be switched, the FPGA will select a second gain link from the gain link set, where the second gain link is used to amplify the signal strength of the initial signal using a second gain, and the second gain is less than the first gain. This means that when the signal strength is too high, the system will select a link with a lower gain to avoid signal overflow and ensure that the analog-to-digital converter operates within a safe range.

[0097] In the present application, the FPGA compares the real-time acquired signal strength with the set threshold value to determine whether the signal strength is close to or exceeds the threshold value. If the entire signal strength is lower than the set threshold value, the first gain link is selected to be turned on, so that the acquired signal is the signal amplified by the first gain link using the first gain, which can meet the maximum input amplitude of the analog-to-digital converter; if the signal contains a part exceeding the threshold value, it can be considered that the signal is split into two parts during the real-time signal processing process. First sub-signal: all components with amplitudes less than the set threshold value; second sub-signal: all components with amplitudes greater than or equal to the set threshold value. FPGA generates corresponding control instructions based on the relationship between the signal strength and the set threshold value, specifying which gain link's output signal should be input to the analog-to-digital converter. Specifically, the first gain link is selected for the first sub-signal less than the set threshold value, and the second gain link is selected for the second sub-signal greater than or equal to the set threshold value. The gain adjustment degree of different gain links is different, so that the signal strength finally output by each gain link is as close as possible and does not exceed the set threshold value.

[0098] Optionally, after the initial signal has been subjected to gain adjustment, digitization, downsampling and other processing operations, the split signals can be accurately spliced ​​together to ensure the continuity and consistency of the final output signal.

[0099] As an optional implementation, in step 403, the FPGA controls the conversion switch to switch to the target gain link so that the target gain link inputs the adjustment signal at the current moment into the analog-to-digital converter, including: sending a control instruction to the conversion switch so that after the conversion switch switches to the target gain link, the target gain link inputs the adjustment signal at the current moment into the analog-to-digital converter, wherein the first gain link and the second gain link independently and synchronously perform gain adjustment on the initial signal.

[0100] When the FPGA determines that the link needs to be switched, it sends a control instruction to the switch, which instructs the switch to switch to the first gain link or the second gain link. After the switch successfully switches to the specified target gain link, the target gain link inputs the signal that has just completed gain adjustment to the analog-to-digital converter.

[0101] Among them, after the initial signal enters the circuit through the signal input port, it will be input into the first gain link and the second gain link respectively. The first gain link and the second gain link independently and synchronously adjust the gain of the initial signal, and the previous adjustment result will not be retained. Exemplarily, after the initial signal enters the two gain links, the two gain links synchronously process the initial signal. If the first gain link is turned on from 1 to 3 seconds, the adjustment signal from 1 to 3 seconds enters the analog-to-digital converter via the first gain link, and the adjustment signal from 1 to 3 seconds in the second gain link is discarded. If the second gain link is turned on from 4 to 7 seconds, the adjustment signal from 4 to 7 seconds enters the analog-to-digital converter via the second gain link, and the adjustment signal from 4 to 7 seconds in the first gain link is discarded. The above operation is performed until all signal processing is completed.

[0102] As an optional implementation manner, after acquiring the signal strength of the target signal in real time, the method further includes:

[0103] Step S21: If it is detected that the magnitude relationship between the signal strength and the set threshold at the current moment has not changed, and the signal strength is greater than or equal to the set threshold, delay and gain calibration is performed on the digitized signal processed by the analog-to-digital converter based on a preset reference signal, wherein the preset reference signal is a signal mediated by the first gain link;

[0104] Step S22: down-sampling the delay and gain calibrated signal using a digital down-converter.

[0105] If the FPGA detects that the relationship between the signal strength and the set threshold at the current moment has not changed, it indicates that the current gain link does not need to be changed, then subsequent operations can be continued. At this time, it is necessary to determine whether the current gain link is the first gain link or the second gain link based on the relationship between the signal strength and the set threshold.

[0106] If the first gain link is currently used, the signal digitally processed by the analog-to-digital converter can be directly input into the digital down-converter, and then the digital down-converter is used to down-sample the digitally processed signal. The down-sampling process includes operations such as filtering, mixing, and extraction, which are used to reduce the sampling rate of the signal, reduce the amount of data, and improve the efficiency of subsequent processing.

[0107] If the current link is the second gain link, the calibration module in the FPGA needs to calibrate the target signal so that the signal obtained from the second gain link and the signal obtained from the first gain link are consistent in time and amplitude. Among them, the present application advances a signal through the first gain link and the second gain link at the same time, and then uses the output of the first gain link as a preset reference signal to compare the outputs of the two links, thereby determining the calibration coefficient in the calibration module, which can calibrate the output of the second gain link so that it is consistent with the output of the first gain link in time and amplitude.

[0108] Specifically, on the one hand, the calibration module performs delay calibration on the initial signal to ensure that it is synchronized in time with the reference signal of the first gain link. This step compensates for the time difference caused by factors such as the switching of the conversion switch and the response time of the amplifier, thereby ensuring the temporal consistency of the signals of the two paths. On the other hand, the calibration module performs gain calibration on the target signal to restore it to the amplitude of the initial signal so that its signal amplitude is consistent with the preset reference signal. Specifically, the appropriate gain ratio is calculated and applied so that the data of the second gain link matches the data of the first gain link in amplitude.

[0109] This application ensures the consistency of signals output by different gain links in time and amplitude, avoids data deviation caused by gain differences, makes the data input to the digital down-converter by the two gain links consistent, and also facilitates data alignment when subsequently splicing signals.

[0110] Figure 5 FIG. 1 is a schematic diagram of the internal control flow of FPGA. It can be seen that after the target signal ADC_DATA output by the analog-to-digital converter enters, the FPGA compares the signal strength of the target signal with the set threshold, and then sends a control instruction to the conversion switch according to the comparison result, so that the conversion switch decides to switch to the first gain link or the second gain link. Figure 5 It includes link selection 1 and link selection 2. The switching of these two link selections and the switching of the conversion switch are synchronized. When the two link selections are switched to the first gain link, the conversion switch switches and turns on the first gain link. When the two link selections are switched to the second gain link, the conversion switch switches and turns on the second gain link.

[0111] At the same time, the preset reference signal Gmax ADC_DATA of the first gain link is pre-specified inside the FPGA. If the first gain link is currently turned on, there is no need to process the signal, and the target signal can be directly input into the digital down-converter for down-sampling; if the second gain link is currently turned on, it is necessary to perform delay and gain calibration on the signal in the second gain link to obtain the signal Gmin ADC_DATA after delay and gain calibration. In this way, the same initial signal passes through two links with different gains and the analog-to-digital converter, and the data sent to the digital down-converter after verification is consistent.

[0112] Figure 6 This is a schematic diagram of selecting a gain link according to a set threshold. It can be seen that for a signal less than or equal to the set threshold Amplitude threshold, the fully amplified signal output by the first gain link (Gmax Channel) is obtained; for a signal greater than the set threshold, the signal amplified by a small gain output by the second gain link (Gmin Channel) is obtained.

[0113] In this application, the FPGA generates precise control instructions to guide the conversion switch to select a path, and dynamically selects the gain link according to the characteristics of different signal amplitudes, which not only ensures that the signal reaches the maximum input amplitude of the analog-to-digital converter, but also prevents the signal overflow of the analog-to-digital converter.

[0114] The present application can make initial signals of different sizes fit the dynamic range of the analog-to-digital converter, that is, fully utilize the number of bits of the analog-to-digital converter, improve the conversion effective bit ENOB of the analog-to-digital converter, and thus improve the signal-to-noise ratio.

[0115] Taking an ideal N-bit ADC as an example, in the existing magnetic resonance receiver solution, once the signal input amplitude of the ADC exceeds the dynamic range, the dynamic range of the ADC will not match the maximum input amplitude, thereby reducing the accuracy of the signal. Therefore, the maximum dynamic range of the existing magnetic resonance receiver can only be 6.02*N decibels, and the signal amplitude range that the ADC can resolve is from A to approximately A*10^(6.02*N / 20), where A is the minimum input amplitude that the ADC can detect.

[0116] In the present application, the threshold is set to be close to the maximum input amplitude of the ADC A*10^(6.02*N / 20). If the magnetic resonance signal is a small signal (the overall signal is less than the set threshold), the gain can be amplified through the first gain link to make full use of the conversion accuracy of the ADC, improve the ADC conversion effective bit, and improve the signal-to-noise ratio of the magnetic resonance small signal; if the magnetic resonance signal is a large signal (the signal has both parts greater than and less than the set threshold), such as Figure 7As shown, the part of the signal below the set threshold has reached the maximum input amplitude of the ADC A*10^(6.02*N / 20), and also reached the maximum dynamic range of the ADC 6.02*N decibels. At this time, the part of the signal above the set threshold is switched to the second gain link, and on the second gain link, its maximum input amplitude of the ADC can also reach 10^(6.02*N / 20)*A, and can also reach the maximum dynamic range of the ADC 6.02*N decibels.

[0117] If only one gain link is used in the related art, only signals below 10^(6.02*N / 20)*A can be collected by the ADC. However, the present application uses two gain links, so even signals with larger amplitudes can be collected by the ADC. Therefore, the actual maximum input amplitude of the ADC in the present application can reach 2*A*10^(6.02*N / 20), which is equivalent to doubling the dynamic range of the ADC. The corresponding conversion accuracy of the ADC is also expanded, that is, the number of bits of the ADC is expanded. Assuming that the number of bits of the ADC after expansion is M, according to the ADC dynamic range calculation formula,

[0118]

[0119] Can get Where N is the number of ADC bits before expansion.

[0120] According to calculations, this application can achieve an expansion of the ADC bit number by 1 bit, that is, the ADC conversion accuracy is improved by 1 bit, its ENOB effective bit will also increase, and the SNR will also increase accordingly.

[0121] The present application realizes ADC bit expansion without increasing the number of ADCs; and realizes ADC accuracy improvement and improves signal-to-noise ratio without replacing the ADC.

[0122] The present application provides a complete process of input signal adjustment, including the following steps:

[0123] 1. Preliminary monitoring and preliminary processing.

[0124] After the initial signal enters the circuit through the signal input port, it enters the first gain link and the second gain link respectively. The first gain link uses a larger gain to amplify the initial signal, and the second gain link uses a smaller gain to amplify the initial signal. At this time, the first gain link is turned on, and the signal mediated by the first gain link is input to the analog-to-digital converter for digital processing to obtain the target signal.

[0125] 2.FPGA judgment and control.

[0126] FPGA compares the signal strength of the target signal with the set threshold. If the signal strength is less than the set threshold, it decides to turn on the first gain link (Gmax Channel). If the signal strength is greater than or equal to the set threshold, it decides to turn on the second gain link (Gmin Channel). FPGA sends a control instruction to the conversion switch, instructing the conversion switch to switch to the appropriate gain path.

[0127] 3.ADC sampling.

[0128] The conversion switch guides the signal to the selected gain path. The gain-adjusted signal enters the analog-to-digital converter through the conversion switch for digital processing. The analog-to-digital converter generates digital data based on the received analog signal, providing high-quality input for subsequent processing.

[0129] 4. Calibration and synchronization.

[0130] For the signal flowing through the second gain link (Gmin Channel), the calibration module inside the FPGA performs delay and gain calibration to restore it to the size of the initial signal, ensuring that the data of different gain paths are consistent in time and amplitude.

[0131] 5. Digital down-conversion processing.

[0132] The calibrated digital data enters the digital down converter for further processing, such as downsampling and filtering, to provide high-quality digital signals for subsequent data analysis.

[0133] Based on the same technical concept, the present application provides an input signal adjustment device, such as Figure 8 As shown, the device comprises:

[0134] An acquisition module 801 is used to acquire the signal strength of a target signal in real time, wherein the target signal is a signal processed by an analog-to-digital converter;

[0135] A selection module 802 is used to select a target gain link from a gain link set according to a pre-associated size relationship and a gain link if it is detected that the size relationship between the signal strength at the current moment and the set threshold value changes, wherein each gain link in the gain link set synchronously performs gain adjustment to a different degree, and an adjustment signal output by the target gain link is close to and lower than the set threshold value compared to adjustment signals output by other gain links in the gain link set, and the set threshold value is the maximum input amplitude of the analog-to-digital converter;

[0136] The control module 803 is used to control the conversion switch to switch to the target gain link, so that the target gain link inputs the adjustment signal at the current moment into the analog-to-digital converter.

[0137] Optionally, the selection module 802 is used to:

[0138] At the current moment, if it is detected that the signal strength changes from being greater than or equal to the set threshold to being less than the set threshold, a first gain link is selected from the gain link set according to the pre-associated size relationship and the gain link, wherein the first gain link is used to amplify the signal strength of the initial signal by using a first gain;

[0139] At the current moment, if it is detected that the signal strength changes from less than the set threshold to greater than or equal to the set threshold, a second gain link is selected from the gain link set based on the pre-associated size relationship and gain link, wherein the second gain link is used to amplify the signal strength of the initial signal using a second gain, and the first gain is greater than the second gain.

[0140] Optionally, the control module 803 is used to:

[0141] After sending a control instruction to the conversion switch so that the conversion switch switches to the target gain link, the target gain link inputs the adjustment signal at the current moment into the analog-to-digital converter, wherein the first gain link and the second gain link independently and synchronously perform gain adjustment on the initial signal.

[0142] Optionally, the device is also used for:

[0143] If it is detected that the magnitude relationship between the signal strength at the current moment and the set threshold value has not changed, and the signal strength is greater than or equal to the set threshold value, delay and gain calibration is performed on the digitized signal processed by the analog-to-digital converter based on a preset reference signal, wherein the preset reference signal is a signal mediated by the first gain link;

[0144] A digital down-converter is used to downsample the delay and gain calibrated signal.

[0145] like Fig. 9 As shown, an embodiment of the present application provides an electronic device, including a processor 901, a communication interface 902, a memory 903 and a communication bus 904, wherein the processor 901, the communication interface 902, and the memory 903 communicate with each other through the communication bus 904.

[0146] The memory 903 is used to store computer programs.

[0147] In one embodiment of the present application, the processor 901 is used to implement the input signal adjustment method provided by any one of the aforementioned method embodiments when executing the program stored in the memory 903.

[0148] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the input signal adjustment method provided in any of the aforementioned method embodiments are implemented.

[0149] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0150] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0151] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0152] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

Claims

1. An input signal adjustment circuit, characterized in that: The circuit comprises: a first gain link, a second gain link, a conversion switch, an analog-to-digital converter and an FPGA; The input ends of the first gain link and the second gain link are both connected to the signal input port, and the first gain link and the second gain link are used to synchronously perform gain adjustment of different degrees; The input end of the conversion switch is connected to the output end of the first gain link and the output end of the second gain link respectively, and the conversion switch is used to switch to the first gain link or the second gain link according to the control instruction, wherein the adjustment signal output by the switched gain link is close to and lower than the maximum input amplitude of the analog-to-digital converter compared with the adjustment signal output by other gain links; The input end of the analog-to-digital converter is connected to the output end of the conversion switch, and the analog-to-digital converter is used to output the processed target signal; The input end of the FPGA is connected to the output end of the analog-to-digital converter, and the output end of the FPGA is connected to the input end of the conversion switch. The FPGA is used to send the control instruction to the conversion switch when it detects that the size relationship between the signal strength of the target signal and the set threshold at the current moment changes.

2. The circuit according to claim 1, characterized in that The FPGA includes a signal comparison module, a calibration module and a digital down converter; The input end of the signal comparison module is connected to the output end of the analog-to-digital converter, the output end of the signal comparison module is connected to the input end of the conversion switch, and the signal comparison module is used to compare the signal strength of the target signal with the set threshold and issue a control instruction; The input end of the calibration module is connected to the output end of the signal comparison module, and the calibration module is used to perform delay and gain calibration on the signal adjusted by the second gain link and the signal adjusted by the first gain link; The input end of the digital down converter is connected to the output end of the signal comparison module and the output end of the calibration module respectively, and the digital down converter is used to downsample the signal after delay and gain calibration.

3. The circuit according to claim 2, characterized in that The first gain link and the second gain link both include an amplifier and a filter; The input end of the amplifier is connected to the signal input port, and the amplifier is used to perform gain adjustment on the initial signal; The input end of the filter is connected to the output end of the amplifier, the output end of the filter is connected to the input end of the conversion switch, and the filter is used to filter the initial signal after gain adjustment.

4. A method for adjusting an input signal, characterized in that: The method comprises: Acquire the signal strength of the target signal in real time, wherein the target signal is a signal processed by an analog-to-digital converter; If it is detected that the magnitude relationship between the signal strength and the set threshold value at the current moment changes, a target gain link is selected from the gain link set according to the pre-associated magnitude relationship and the gain link, wherein each gain link in the gain link set synchronously performs gain adjustment to a different degree, and the adjustment signal output by the target gain link is close to and lower than the set threshold value compared to the adjustment signals output by other gain links in the gain link set, and the set threshold value is the maximum input amplitude of the analog-to-digital converter; The conversion switch is controlled to switch to the target gain link, so that the target gain link inputs the adjustment signal at the current moment into the analog-to-digital converter.

5. The method according to claim 4, characterized in that If it is detected that the magnitude relationship between the signal strength and the set threshold at the current moment changes, then selecting a target gain link from the gain link set according to the pre-associated magnitude relationship and gain link includes: At the current moment, if it is detected that the signal strength changes from being greater than or equal to the set threshold to being less than the set threshold, a first gain link is selected from the gain link set according to the pre-associated size relationship and gain link, wherein the first gain link is used to amplify the signal strength of the initial signal by using a first gain; At the current moment, if it is detected that the signal strength changes from less than the set threshold to greater than or equal to the set threshold, a second gain link is selected from the gain link set based on the pre-associated size relationship and gain link, wherein the second gain link is used to amplify the signal strength of the initial signal using a second gain, and the first gain is greater than the second gain.

6. The method according to claim 5, characterized in that Controlling the conversion switch to switch to the target gain link so that the target gain link inputs the adjustment signal at the current moment into the analog-to-digital converter comprises: After sending a control instruction to the conversion switch so that the conversion switch switches to the target gain link, the target gain link inputs the adjustment signal at the current moment into the analog-to-digital converter, wherein the first gain link and the second gain link independently and synchronously perform gain adjustment on the initial signal.

7. The method according to claim 5, characterized in that After acquiring the signal strength of the target signal in real time, the method further includes: If it is detected that the magnitude relationship between the signal strength and the set threshold at the current moment has not changed, and the signal strength is greater than or equal to the set threshold, delay and gain calibration is performed on the digitized signal processed by the analog-to-digital converter based on a preset reference signal, wherein the preset reference signal is the signal mediated by the first gain link; A digital down-converter is used to downsample the delay and gain calibrated signal.

8. An input signal adjustment device, characterized in that: The device comprises: An acquisition module, used for acquiring the signal strength of a target signal in real time, wherein the target signal is a signal processed by an analog-to-digital converter; A selection module, configured to select a target gain link from a gain link set according to a pre-associated size relationship and a gain link if it is detected that a size relationship between the signal strength and a set threshold value at the current moment changes, wherein each gain link in the gain link set synchronously performs gain adjustment to a different degree, and an adjustment signal output by the target gain link is close to and lower than the set threshold value compared to adjustment signals output by other gain links in the gain link set, and the set threshold value is the maximum input amplitude of the analog-to-digital converter; The control module is used to control the conversion switch to switch to the target gain link, so that the target gain link inputs the adjustment signal at the current moment into the analog-to-digital converter.

9. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing any of the methods described in claims 4-7 when executing a program stored in a memory.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 4 to 7 is implemented.

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