Imaging device and electronic apparatus

Abstract

The invention relates to an imaging device and an electronic apparatus. Provided is an imaging device that generates a potential higher than a potential supplied to a pixel in the pixel. One embodiment of the present invention is an imaging device including a pixel having a first circuit and a second circuit, the second circuit including a photoelectric conversion device, the first circuit being electrically connected to the second circuit, the first circuit having a function of adding a first potential and a second potential to generate a third potential, and the second circuit having a function of adding the third potential to the first potential. The second circuit has a function of generating data in the photoelectric conversion device to which the third potential is applied and a function of outputting data.

Description

[0001] This divisional application is a divisional application based on the Chinese patent application with application number 201980046607.4, application date July 18, 2019, and invention name “Camera device and electronic device”. Technical Field

[0002] One embodiment of the present invention relates to an imaging device.

[0003] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification, etc., relates to an object, method or manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product or a composition of matter. Therefore, more specifically, as an example of the technical field of one embodiment of the present invention disclosed in this specification, a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, a camera device, a driving method of these devices or a manufacturing method of these devices can be cited.

[0004] Note that in this specification and the like, a semiconductor device refers to any device that can operate by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one form of a semiconductor device. In addition, a storage device, a display device, a camera device, and an electronic device may include a semiconductor device. Background Art

[0005] A technique for forming a transistor using an oxide semiconductor thin film formed on a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device using a transistor including an oxide semiconductor and having an extremely low off-state current for a pixel circuit.

[0006] In addition, Patent Document 2 discloses a memory device having a structure in which a transistor with extremely low off-state current is used for a memory cell.

[0007] [Prior technical literature]

[0008] [Patent Document]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2011-119711

[0010] [Patent Document 2] Japanese Patent Application Publication No. 2011-119674 Summary of the invention

[0011] Technical problem to be solved by the invention

[0012] In order to achieve a higher resolution of the image sensor, it is necessary to reduce the area of ​​each pixel and increase the pixel density. As the pixel area is reduced, the area of ​​the light receiving part of the photoelectric conversion device is also reduced, so the photosensitivity is reduced. In particular, when shooting under low illumination, the S / N ratio of the shooting data is sometimes greatly reduced. That is, the image sensor with the existing structure has the problem of a trade-off between resolution and photosensitivity.

[0013] One solution to the above problem is to use a photoelectric conversion device that utilizes the avalanche multiplication effect with high photosensitivity. Note that when utilizing the avalanche multiplication effect, a high voltage needs to be applied to the photoelectric conversion device, and a dedicated power supply circuit or the like needs to be used.

[0014] Therefore, one of the purposes of one embodiment of the present invention is to provide an imaging device capable of generating a voltage higher than a voltage supplied to a pixel. In addition, one of the purposes of one embodiment of the present invention is to provide an imaging device capable of adding two potentials supplied to a pixel. In addition, one of the purposes of one embodiment of the present invention is to provide an imaging device capable of generating a reset potential in a pixel.

[0015] One of the purposes of one embodiment of the present invention is to provide a low-power camera device. One of the purposes of one embodiment of the present invention is to provide a camera device capable of high-speed camera imaging. One of the purposes of one embodiment of the present invention is to provide a camera device with high reliability. One of the purposes of one embodiment of the present invention is to provide a novel camera device. One of the purposes of one embodiment of the present invention is to provide an operating method of the above-mentioned camera device. One of the purposes of one embodiment of the present invention is to provide a novel semiconductor device, etc.

[0016] Note that the recording of the above-mentioned purpose does not prevent the existence of other purposes. In addition, one mode of the present invention does not need to achieve all of the above-mentioned purposes. In addition, purposes other than the above-mentioned purposes can be naturally known and derived from the records of the specification, drawings, claims, etc.

[0017] Solutions to technical problems

[0018] One embodiment of the present invention relates to an imaging device that generates, in a pixel, a potential higher than a potential supplied to the pixel.

[0019] One embodiment of the present invention is a camera device including pixels having a first circuit and a second circuit, wherein the second circuit includes a photoelectric conversion device, the first circuit is electrically connected to the second circuit, the first circuit has a function of adding a first potential and a second potential to generate a third potential, and the second circuit has a function of generating data in the photoelectric conversion device to which the third potential is applied and a function of outputting data.

[0020] The first circuit includes a first transistor, a second transistor, and a first capacitor, one of the source and the drain of the first transistor is electrically connected to an electrode of the first capacitor, the other electrode of the first capacitor is electrically connected to one of the source and the drain of the second transistor, and one of the source and the drain of the first transistor is connected to the second circuit.

[0021] The second circuit also includes a third transistor, a fourth transistor, a fifth transistor, and a second capacitor, one electrode of the photoelectric conversion device is electrically connected to one of the source and the drain of the third transistor, the other of the source and the drain of the third transistor is electrically connected to one electrode of the second capacitor, one electrode of the second capacitor is electrically connected to the gate of the fourth transistor, and one of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor.

[0022] One of the source and the drain of the third transistor of the second circuit may be connected to the first circuit. In addition, the other of the source and the drain of the third transistor of the second circuit may be connected to the first circuit.

[0023] As a structure different from the above structure, the second circuit also includes a third transistor, a fourth transistor, a fifth transistor, and a second capacitor, one electrode of the photoelectric conversion device is electrically connected to one electrode of the second capacitor, the other electrode of the second capacitor is electrically connected to the gate of the fourth transistor, one of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor, the other electrode of the photoelectric conversion device is electrically connected to one of the source and the drain of the third transistor, and one electrode of the photoelectric conversion device is connected to the first circuit.

[0024] Preferably, at least one of the transistors included in the camera device contains a metal oxide in a channel formation region, and the metal oxide contains In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0025] The photoelectric conversion device is preferably an avalanche photodiode.

[0026] Effects of the Invention

[0027] By using one embodiment of the present invention, an imaging device capable of generating a voltage higher than a voltage supplied to a pixel can be provided. In addition, by using one embodiment of the present invention, an imaging device capable of adding two potentials supplied to a pixel can be provided. In addition, by using one embodiment of the present invention, an imaging device capable of generating a reset potential in a pixel can be provided.

[0028] By using one embodiment of the present invention, a low-power camera device can be provided. By using one embodiment of the present invention, a camera device capable of high-speed camera can be provided. By using one embodiment of the present invention, a camera device with high reliability can be provided. By using one embodiment of the present invention, a novel camera device can be provided. By using one embodiment of the present invention, an operating method of the above-mentioned camera device can be provided. By using one embodiment of the present invention, a novel semiconductor device, etc. can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] [ Figure 1 ] Figure 1 A diagram illustrating a pixel circuit.

[0031] [ Figure 2 ] Figure 2 A diagram illustrating a pixel circuit.

[0032] [ Figure 3 ] Figure 3 A diagram illustrating a pixel circuit.

[0033] [Figure 4] Figure 4A and Figure 4B A diagram illustrating a pixel circuit.

[0034] [Figure 5] Figure 5A and Figure 5B is a timing diagram illustrating the operation of the pixel circuit.

[0035] [Figure 6] Fig. 6A and Figure 6B A diagram illustrating a pixel circuit.

[0036] [Figure 7] Fig. 7A and Figure 7B A diagram illustrating a pixel circuit.

[0037] [ Figure 8 ] Figure 8 A diagram illustrating a pixel circuit.

[0038] [ Fig. 9 ] Fig. 9 is a timing diagram illustrating the operation of the pixel circuit.

[0039] [ Fig.10 ] Fig.10 A diagram illustrating a pixel circuit.

[0040] [ Fig.11 ] Fig.11 A diagram illustrating a pixel circuit.

[0041] [ Fig.12 ] Fig.12 is a timing diagram illustrating the operation of the pixel circuit.

[0042] [ Fig.13 ] Fig.13 It is a block diagram for explaining an imaging device.

[0043] [Figure 14] Fig.14A , Fig. 14B is a diagram illustrating simulation results.

[0044] [Figure 15] FIG. 15A to FIG. 15E This is a diagram for explaining the structure of a pixel of an imaging device.

[0045] [Figure 16] Fig.16A , Fig. 16B This is a diagram for explaining the structure of a pixel of an imaging device.

[0046] [Figure 17] FIG. 17A to FIG. 17C A diagram illustrating a transistor.

[0047] [Figure 18] Fig.18A and Fig.18B This is a diagram for explaining the structure of a pixel of an imaging device.

[0048] [Figure 19] FIG. 19A to FIG. 19D A diagram illustrating a transistor.

[0049] [Figure 20] FIG. 20A to FIG. 20C This is a diagram for explaining the structure of a pixel of an imaging device.

[0050] [Figure 21] FIG. 21A1 to FIG. 21B3 This is a perspective view of a package or module that houses a camera device.

[0051] [Figure 22] FIG. 22A to FIG. 22F It is a diagram for explaining an electronic device.

[0052] Modes for Carrying Out the Invention

[0053] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person of ordinary skill in the art can easily understand the fact that its methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below. In addition, in the structure of the invention described below, the same figure marks are used in different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In addition, the shading of the same constituent elements is sometimes appropriately omitted or changed in different drawings.

[0054] In addition, even if there is one element in the circuit diagram, the element may be composed of multiple elements if there is no problem in terms of function. For example, sometimes multiple transistors used as switches may be connected in series or in parallel. Also, sometimes a capacitor is divided and arranged in multiple locations.

[0055] In addition, sometimes a conductor has multiple functions such as wiring, electrode and terminal, and in this specification, multiple names are sometimes used for the same element. In addition, even if the circuit diagram shows that the elements are directly connected, sometimes the elements are actually connected through multiple conductors, and this structure is also included in the category of direct connection in this specification.

[0056] (Implementation Method 1)

[0057] In this embodiment, an imaging device according to one embodiment of the present invention is described with reference to the drawings.

[0058] One embodiment of the present invention is an imaging device capable of performing a voltage boosting operation in a pixel. By generating a high voltage in the pixel, an avalanche photodiode can be operated without using a high voltage power supply. Therefore, a low power consumption and high sensitivity imaging device can be provided.

[0059] <Structural Example 1>

[0060] Figure 1 1 is a diagram for explaining a pixel 10 a that can be used in an imaging device according to one embodiment of the present invention. The pixel 10 a can have a structure including a circuit 11 and a circuit 12 .

[0061] The circuit 11 is a circuit for generating a reset potential, and can generate a high voltage by adding two supplied potentials.

[0062] The circuit 12 includes a photoelectric conversion device, and can generate and hold image data by operating the photoelectric conversion device using the reset potential generated by the circuit 11.

[0063] As the photoelectric conversion device, an avalanche photodiode is preferably used. Since a high voltage (reset potential) can be generated by the circuit 11, the avalanche photodiode can be operated without using a high voltage power supply.

[0064] Circuit 11 may include transistor 102, transistor 103, and capacitor 107. One of the source and drain of transistor 102 is electrically connected to one electrode of capacitor 107. The other electrode of capacitor 107 is electrically connected to one of the source and drain of transistor 103. One of the source and drain of transistor 102 is connected to circuit 12.

[0065] The circuit 12 includes a photoelectric conversion device 101, a transistor 104, a transistor 105, a transistor 106, and a capacitor 108. Note that the capacitor 108 may not be provided.

[0066] One electrode (cathode) of the photoelectric conversion device 101 is electrically connected to one of the source and drain of the transistor 104. The other of the source and drain of the transistor 104 is electrically connected to one electrode of the capacitor 108. One electrode of the capacitor 108 is electrically connected to the gate of the transistor 105. One of the source and drain of the transistor 105 is electrically connected to one of the source and drain of the transistor 106. One of the source and drain of the transistor 104 may be electrically connected to the circuit 11.

[0067] Here, a wiring connecting the other of the source and the drain of the transistor 104, one electrode of the capacitor 108, and the gate of the transistor 105 is referred to as a node FD. The node FD can be used as a charge accumulation portion.

[0068] The other electrode (anode) of the photoelectric conversion device 101 is electrically connected to the wiring 122. The gate of the transistor 102 is electrically connected to the wiring 125. The other of the source and the drain of the transistor 102 is electrically connected to the wiring 123. The gate of the transistor 103 is electrically connected to the wiring 126. The other of the source and the drain of the transistor 103 is electrically connected to the wiring 124. The gate of the transistor 104 is electrically connected to the wiring 127. The other electrode of the capacitor 108 is electrically connected to a reference potential line such as a GND wiring. The other of the source and the drain of the transistor 105 is electrically connected to the wiring 121. The gate of the transistor 106 is electrically connected to the wiring 128. The other of the source and the drain of the transistor 106 is electrically connected to the wiring 129.

[0069] The wirings 121 and 122 may be used as power supply lines. The wirings 123 and 124 may have a function of supplying a potential for generating a reset potential. The potentials of the wirings 123 and 124 differ depending on the connection direction of the photoelectric conversion device 101 . Figure 1 The structure shown is a structure in which the cathode side of the photoelectric conversion device 101 is electrically connected to the transistor 102 and the node FD is reset to a high potential, so the wirings 123 and 124 are at a high potential (higher than the potential of the wiring 122). Figure 1 On the contrary, the potentials of the wirings 123 and 124 may be low (lower than the potential of the wiring 122 ).

[0070] The wirings 125, 126, 127, and 128 can be used as signal lines for controlling conduction of the respective transistors. The wiring 129 can be used as an output line.

[0071] A photodiode can be used as the photoelectric conversion device 101. In one embodiment of the present invention, an avalanche photodiode is preferably used.

[0072] Transistors 102 and 103 have a function of generating a reset potential. Transistor 104 has a function of controlling the potential of node FD. Transistor 105 is used as a source follower circuit and can output the potential of node FD as image data to wiring 129. Transistor 106 has a function of selecting a pixel to output image data.

[0073] When an avalanche photodiode is used as the photoelectric conversion device 101, a high withstand voltage transistor is preferably used as a transistor connected to the photoelectric conversion device 101 so that a higher voltage can be applied. As the high withstand voltage transistor, for example, a transistor (hereinafter referred to as an OS transistor) using a metal oxide for a channel formation region can be used. Specifically, OS transistors are preferably used as transistors 102, 104, etc. In addition, OS transistors can also be used as transistors 103, 105, and 106.

[0074] In addition, the OS transistor also has the characteristic of extremely low off-state current. By using the OS transistor as the transistors 102 and 104, the node FD can be made to hold the charge for an extremely long period of time. Therefore, a global shutter method that performs charge accumulation in all pixels simultaneously can be adopted without adopting a complicated circuit structure or operation method.

[0075] Note that the present invention is not limited to the above structure, and an OS transistor and a transistor using Si in the channel formation region (hereinafter referred to as a Si transistor) may be used in any combination. In addition, all transistors may be OS transistors or Si transistors. Examples of Si transistors include transistors containing amorphous silicon, transistors containing crystalline silicon (typically low-temperature polysilicon, single crystal silicon, etc.), and the like.

[0076] <Structure Example 2>

[0077] The imaging device according to one embodiment of the present invention may also adopt Figure 2 The structure of the pixel 10b shown in FIG. 1 is different from the pixel 10a in the connection position of the circuit 11 and the circuit 12, that is, the circuit 11 is connected to the node FD. In this structure, the wiring connecting the other of the source and the drain of the transistor 104, an electrode of the capacitor 108, the gate of the transistor 105, one of the source and the drain of the transistor 102, and an electrode of the capacitor 107 is recorded as the node FD. The circuit 11, the circuit 12, and the wiring structure connected thereto are the same as those of the pixel 10a.

[0078] <Structural Example 3>

[0079] The imaging device according to one embodiment of the present invention may also adopt Figure 3 The structure of the pixel 10c shown in FIG. Figure 1 The pixel 10a shown is different in the connection position of the transistor 104 in the circuit 12. One of the source and the drain of the transistor 104 is electrically connected to the other electrode (anode) of the photoelectric conversion device 101, and the other of the source and the drain of the transistor 104 is electrically connected to the wiring 122. The other structures are the same as the pixel 10a.

[0080] In this structure, the node FD is a wiring that connects one of the source and the drain of the transistor 102, one electrode of the capacitor 107, one electrode of the capacitor 108, the gate of the transistor 105, and one electrode (cathode) of the photoelectric conversion device 101. Note that the potential of the node FD is determined in consideration of the potential allocated to the other electrode (anode) of the photoelectric conversion device 101.

[0081] The transistor 104 has a function of controlling the potential of the node FD. Specifically, the transistor 104 is used to initialize and maintain the potential of the node FD. In the pixel 10a, the following operation is performed: by making the transistor 104 non-conductive, the conduction between the photoelectric conversion device 101 and the node FD is cut off, and the potential of the node FD is determined.

[0082] In the pixel 10c, by making the transistor 104 non-conductive, the conduction between the other electrode (anode) of the photoelectric conversion device 101 and the wiring 122 is cut off. When the transistor 104 is non-conductive, the potential of the anode of the photoelectric conversion device 101 rises and the potential difference between the cathode and the anode is close to the forward voltage (Vf), and the operation of the photoelectric conversion device 101 stops. Therefore, the potential of the node FD can be determined.

[0083] <Modification Example of Circuit 12>

[0084] The pixels 10a, 10b, and 10c have a structure in which the reset potential of the node FD is set to a voltage higher than the anode voltage of the photoelectric conversion device 101, and the photoelectric conversion device 101 is connected in a direction in which a reverse bias is applied.

[0085] As other structures, it is also possible to adopt Figure 4A , Figure 4B In the modified example of the circuit 12 shown, the reset potential of the node FD is set to a voltage lower than the cathode voltage of the photoelectric conversion device 101, and the photoelectric conversion device 101 is connected in a direction in which a reverse bias is applied. Figure 4A The circuit 12 shown can be used as a modified example of the pixel 10a, 10b, and Figure 4B The circuit 12 shown can be used as a modified example of the pixel 10c.

[0086] Notice, Figure 4A , Figure 4B The structure shown is preferably operated so that the node FD has a negative potential. Therefore, it is preferable to use a p-ch type transistor as at least the transistor 105.

[0087] <Operation of Circuit 11>

[0088] by Figure 2 Taking the connection structure of the circuit 11 and the circuit 12 shown in FIG. 1 as an example, the voltage addition operation in the circuit 11 is described. First, the transistor 102 is turned on, and the potential "V RS1 ” (reset potential 1). In addition, the transistor 103 is turned on, and the potential “V REF ” (reference potential). At this time, the potential “V RS1 -V REF Next, the node FD is placed in a floating state, and the potential “V RS2 ” (Reset potential 2).

[0089] At this time, the capacitance value of capacitor 107 is recorded as C 107 And the capacitance value of node FD is recorded as C FD When the potential of node FD is "V RS1 +(C 107 / (C 107 +C FD ))×(V RS2 -V REF )". Here, if C 107 The value is sufficiently greater than C FD and can ignore C FD The potential of node FD is "V RS1 +V RS2 -V REF ”.

[0090] Therefore, in “V RS1 ”=“V RS2 ”, “V REF ”=0V and C 107 Sufficiently greater than C FD When the potential of node FD is close to "2V RS1 That is, a voltage approximately twice the voltage that can be supplied to the pixel can be supplied to the node FD as a reset potential.

[0091] The reset potential of the high voltage supplied to the node FD can be supplied to the photoelectric conversion device 101. RS1 ”, “V RS2"Supplying the appropriate voltage allows the avalanche photodiode to operate without the use of a dedicated high voltage power supply.

[0092] <Operation of Structural Example 1>

[0093] Next, refer to Figure 5A The timing diagram of the present specification illustrates an example of the operation of the pixel 10a. Note that in the description of the timing diagram in this specification, a high potential is represented by "HH" or "H" ("HH"> "H"), a low potential is represented by "L", and a reset potential is represented by "V RS1 ” or “V RS2 ”, the reference potential is expressed as “V REF " ". "H" is always supplied to the wiring 121, and "L" is always supplied to the wiring 122.

[0094] Note that detailed changes due to circuit structure, operation timing, etc. are not considered in the potential distribution, coupling, or loss here. In addition, the potential change caused by the capacitive coupling of the capacitor depends on the capacitance ratio of the capacitor and the element connected to it, but for the sake of convenience, the capacitance value of the element is assumed to be sufficiently small.

[0095] During the period T1, the potential of the wiring 123 is set to “V RS1 ”, and set the potential of wiring 124 to “V REF ”, the potential of wiring 125 is set to “H”, the potential of wiring 126 is set to “H”, the potential of wiring 127 is set to “H”, and the potential of wiring 128 is set to “L”, thereby turning on transistors 102 and 104, and supplying the potential “V” of wiring 123 to node FD. RS1 In addition, the transistor 103 is turned on, and the potential “V REF In the above operation, the capacitor 107 holds “V RS1 -V REF ”.

[0096] During period T2, the potential of wiring 123 is set to “V RS1 ”, and set the potential of wiring 124 to “V RS2 ”, the potential of wiring 125 is set to “L”, the potential of wiring 126 is set to “H”, the potential of wiring 127 is set to “H”, and the potential of wiring 128 is set to “L”, thereby supplying the potential “V” of wiring 124 to the other electrode of capacitor 107. RS2 At this time, the potential of the node FD becomes "V RS1 +V RS2 '" (reset operation).

[0097] As explained in the operation of circuit 11, if C 107 The value is sufficiently greater than C FD The value of C can be ignored FD The potential of node FD becomes "V RS1 +V RS2 -V REF Here, it is assumed that “V REF ” is 0V, and in fact C FD is a non-negligible value, the potential of node FD can be expressed as “V RS1 +V RS2 '".

[0098] “V RS1 ” and “V RS2 "V RS1 +V RS2 '" is set in a manner such that the voltage at which the photoelectric conversion device 101 exhibits avalanche multiplication characteristics is reached. For example, "V RS1 ” and “V RS2 ” is set to a voltage higher than 1 / 2 of the voltage at which the photoelectric conversion device 101 exhibits avalanche multiplication characteristics.

[0099] During the period T2, the potential of the node FD decreases according to the operation of the photoelectric conversion device 101 (accumulation operation).

[0100] During period T3, the potential of wiring 123 is set to “V RS1 ”, and set the potential of wiring 124 to “V RS2 ", sets the potential of wiring 125 to "L", sets the potential of wiring 126 to "L", sets the potential of wiring 127 to "L", and sets the potential of wiring 128 to "L", thereby determining and maintaining the potential of node FD (maintaining operation).

[0101] During period T4, the potential of the wiring 123 is set to “V RS1 ”, and set the potential of wiring 124 to “V RS2 ", sets the potential of wiring 125 to "L", sets the potential of wiring 126 to "L", sets the potential of wiring 127 to "L", sets the potential of wiring 128 to "H", thereby turning on transistor 106, and the potential of node FD is read to wiring 129 through the source follower action of transistor 105 (reading action).

[0102] The above is Figure 1 An example of the operation of the pixel 10a is shown. Note that when using Figure 4A The circuit shown in 12, as "V RS1 ” and “V RS2 "Just use a negative potential.

[0103] <Operation of Structural Examples 2 and 3>

[0104] Next, refer to Figure 5B An example of the operation of the pixels 10b and 10c is described with reference to the timing diagram of FIG. 1. Note that although the circuit components of the pixels 10b and 10c are connected in different ways, they can operate according to the same timing diagram.

[0105] During the period T1, the potential of the wiring 123 is set to “V RS1 ”, and set the potential of wiring 124 to “V REF ”, the potential of wiring 125 is set to “H”, the potential of wiring 126 is set to “H”, the potential of wiring 127 is set to “L”, and the potential of wiring 128 is set to “L”, thereby turning on transistor 102 and supplying the potential “V” of wiring 123 to node FD. RS1 In addition, the transistor 103 is turned on, and the potential “V REF In the above operation, the capacitor 107 holds “V RS1 -V REF ”.

[0106] During period T2, the potential of wiring 123 is set to “V RS1 ”, and set the potential of wiring 124 to “V RS2 ”, the potential of wiring 125 is set to “L”, the potential of wiring 126 is set to “H”, the potential of wiring 127 is set to “L”, and the potential of wiring 128 is set to “L”, thereby supplying the potential “V” of wiring 124 to the other electrode of capacitor 107. RS2 At this time, the potential of the node FD becomes "V RS1 +V RS2 '" (reset operation).

[0107] As explained in the operation of circuit 11, if C 107 The value is sufficiently greater than C FD The value of C can be ignored FD The potential of node FD becomes "V RS1 +V RS2 -V REF Here, it is assumed that “V REF ” is 0V, and in fact C FD is a non-negligible value, the potential of node FD can be expressed as “V RS1 +V RS2 '".

[0108] During period T3, the potential of wiring 123 is set to “V RS1 ”, and set the potential of wiring 124 to “V RS2 ", sets the potential of wiring 125 to "L", sets the potential of wiring 126 to "L", sets the potential of wiring 127 to "H", and sets the potential of wiring 128 to "L", thereby decreasing the potential of the working node FD according to the photoelectric conversion device 101 (accumulation operation).

[0109] During period T4, the potential of the wiring 123 is set to “V RS1 ”, and set the potential of wiring 124 to “V RS2 ", sets the potential of wiring 125 to "L", sets the potential of wiring 126 to "L", sets the potential of wiring 127 to "L", and sets the potential of wiring 128 to "L", thereby determining and maintaining the potential of node FD (maintaining operation).

[0110] During period T5, the potential of the wiring 123 is set to “V RS1 ”, and set the potential of wiring 124 to “V RS2 ", sets the potential of wiring 125 to "L", sets the potential of wiring 126 to "L", sets the potential of wiring 127 to "L", sets the potential of wiring 128 to "H", thereby turning on transistor 106, and the potential of node FD is read to wiring 129 through the source follower action of transistor 105 (reading action).

[0111] The above is Figure 2 The pixel 10b shown and Figure 3 An example of the operation of pixel 10c is shown. Note that in pixel 10b, Figure 4A The circuit 12 shown and the pixel 10c use Figure 4B The circuit shown in 12, as "V RS1 ” and “V RS2 "Just use a negative potential.

[0112] <Modification Examples of Structural Examples 1, 2, and 3>

[0113] In one embodiment of the present invention, Fig. 6A , Figure 6B As shown, the transistor may also have a structure with a back gate. Fig. 6A The structure in which the back gate is electrically connected to the front gate is shown, which has the effect of increasing the on-state current. Figure 6B A structure in which a back gate is electrically connected to a wiring capable of supplying a constant potential is shown, and this structure can control the threshold voltage of the transistor.

[0114] Alternatively, a structure may be adopted in which each transistor can perform appropriate operations, such as combining Fig. 6A , Figure 6B In addition, the pixel circuit may include a transistor that is not provided with a back gate. Note that the structure in which a back gate is provided in the transistor can be used for all pixels 10a to 10c.

[0115] As a modified example of the pixels 10a and 10b, the circuit 11 is as follows: Fig. 7A , Figure 7B As shown, a structure may be provided in which one of the source and the drain of the transistor 102 is electrically connected to one electrode of the capacitor 107 through the transistor 104 .

[0116] The deformation of the pixels 10a, 10b, and 10c can realize a structure in which a plurality of pixels share a source follower circuit. Figure 8 The structure shown. Figure 8 The structure is formed by adding appropriate components to the pixel 10a as the basic structure, and can also be used for a global shutter method. By using a source follower circuit in common for a plurality of pixels, the number of transistors per pixel can be reduced.

[0117] Figure 8 The structure of a shared pixel circuit is shown in which four pixels in the vertical direction share a reset circuit (transistor 111) and a source follower circuit (transistor 105). Pixel 10a' (pixels 10a' [1] to [4]) includes a capacitor 109 and a transistor 110 in addition to the components included in pixel 10a.

[0118] One electrode of the capacitor 109 is electrically connected to the other of the source and the drain of the transistor 104. The other of the source and the drain of the transistor 104 is electrically connected to one of the source and the drain of the transistor 110. The other of the source and the drain of the transistor 110 is electrically connected to one of the source and the drain of the transistor 111. One of the source and the drain of the transistor 111 is electrically connected to the gate of the transistor 105.

[0119] The other electrode of the capacitor 109 and the other of the source and the drain of the transistor 111 are electrically connected to a reference potential line such as a GND wiring. The gate of the transistor 110 is electrically connected to the wiring 130. The gate of the transistor 111 is electrically connected to the wiring 131. The wiring 130 (wiring 130 [1] to [4]) and the wiring 131 can be used as a signal line for controlling conduction of each transistor.

[0120] A wiring connecting the other of the source and drain of the transistor 110 of each pixel 10a' [1] to [4], one of the source and drain of the transistor 111, and the gate of the transistor 105 is referred to as a node FD. In addition, a wiring connecting the other of the source and drain of the transistor 104, one electrode of the capacitor 109, and one of the source and drain of the transistor 110 is referred to as a node AD. The node AD has a function of storing data captured in each pixel.

[0121] Reference Fig. 9 Timing diagram of Figure 8 The operation of the shared pixel circuit shown in FIG. 1 is a global shutter method in which accumulation is performed simultaneously in all pixels.

[0122] The operations during the period T1 to the period T3 can refer to the description of the operation of the pixel 10a. Note that the data acquired in the accumulation operation is held in the nodes AD [1] to [4].

[0123] In the period T4, when the potential of the wiring 131 is set to "H", the transistor 111 is turned on, and the potential of the node FD is reset. The reset potential may be, for example, GND or 0 V.

[0124] In period T5, when the potential of wiring 131 is set to "L", the potential of wiring 130[1] is set to "H", and the potential of wiring 128 is set to "H", transistor 110 is turned on, and the potential of node AD[1] is distributed to node FD. In addition, due to the source follower operation of transistor 105 and the conduction of transistor 106, the potential according to the potential of node FD is read to wiring 129.

[0125] Since data is held in nodes AD [2] to [4], data can be read from pixels 10a' [1] to [4] by repeating the above operation during periods T6 to T12.

[0126] As described above, the pixel 10 b and the pixel 10 c may also adopt a structure of a shared pixel circuit. Fig.10 A structure using the pixel 10 b (pixels 10 b ′ [ 1 ] to [ 4 ]) in a shared pixel circuit including four pixels in the vertical direction is shown. Fig.11 The structure of using the pixel 10c in a shared pixel circuit including four pixels in the vertical direction (pixels 10c' [1] to [4]) is shown. Each shared pixel circuit can be Fig.12 The timing diagram shown is used for operation.

[0127] Fig.131 is an example of a block diagram for explaining a circuit structure of an imaging device according to one embodiment of the present invention. The imaging device includes a pixel array 21 having pixels 10 arranged in a matrix, a circuit 22 (row driver) having a function of selecting a row of the pixel array 21, a circuit 23 having a function of reading data from the pixels 10, and a circuit 28 for supplying a power supply potential. The pixels 10 may be any of the pixels 10a, 10b, 10c, and their modified examples.

[0128] The circuit 23 includes a circuit 24 (column driver) having a function of selecting a column of the pixel array 21, a circuit 25 (CDS circuit) for performing correlated double sampling processing on the output data of the pixel 10, and a circuit 26 (A / D conversion circuit, etc.) having a function of converting the analog data output from the circuit 25 into digital data.

[0129] The circuit 23 is electrically connected to the wiring 129, and can convert the data output from the pixel 10 into digital data and output the data to the outside. For example, the output destination may also be a neural network, a storage device, a display device, a communication device, or the like.

[0130] Next, the simulation results of the pixel circuit operation are described. Figure 1 The pixel 10a and Figure 2 The pixel 10b shown calculates the potential of the node FD.

[0131] The parameters used for the simulation are as follows: transistor size L / W = 3 μm / 10 μm (transistors 102, 103, 104), L / W = 3 μm / 50 μm (transistors 105, 106), the capacitance value of capacitor 107 is 200 fF, the capacitance value of capacitor 108 is 100 fF (not set for pixel 10a), the capacitance value of photoelectric conversion device 101 is 20 fF, and the reset potential is 1 (V RS1 ) is 20V, reset potential 2(V RS2 ) is 26 V. In addition, the voltage applied to the gate of the transistor is set to +26 V or +46 V as "H" and to 0 V as "L". Note that the circuit simulation software uses SPICE.

[0132] Fig.14A is based on Figure 5A The timing diagram of the simulation results when the pixel 10a is operated. The horizontal axis represents time, the vertical axis (left side) represents the voltage supplied to the gate wiring (GL1, GL2), and the vertical axis (right side) represents the voltage of the node FD. Note that GL1 corresponds to the wiring 125, and GL2 corresponds to the wiring 126.

[0133] Confirmed: When writing V to node FD RS1 After that, V is applied according to the capacitance ratio RS2, can generate high voltage (V RS1 +V RS2 ').

[0134] Fig. 14B is based on Figure 5B The simulation results when the pixel 10b is operated are shown in the timing diagram. It is confirmed that, similarly to the pixel 10a, when V is written to the node FD, RS1 After that, V is applied according to the capacitance ratio RS2 , can generate high voltage (V RS1 +V RS2 ').

[0135] As can be seen from the above simulation results, by using one embodiment of the present invention, a high voltage can be generated in a pixel without using a high voltage power supply circuit, and an avalanche photodiode can be operated.

[0136] This embodiment mode can be combined with the description of other embodiment modes as appropriate.

[0137] (Implementation Method 2)

[0138] In this embodiment, a configuration example of an imaging device according to one embodiment of the present invention will be described.

[0139] Fig.15A and Fig. 15B The structure of a pixel included in an imaging device is exemplified. Fig.15A An example in which a pixel has a stacked-layer structure including a layer 561 and a layer 562 is shown.

[0140] Layer 561 includes the photoelectric conversion device 101. Fig. 15C As shown, the photoelectric conversion device 101 may be a stack of layers 565a, 565b, and 565c.

[0141] Fig. 15C The photoelectric conversion device 101 shown is a pn junction type photodiode. For example, a p + type semiconductor, an n-type semiconductor can be used as layer 565b, and an n-type semiconductor can be used as layer 565c. + Alternatively, n-type semiconductor may be used as layer 565a. + type semiconductor, a p-type semiconductor may be used as layer 565b, and a p-type semiconductor may be used as layer 565c. + Alternatively, the photoelectric conversion device 101 may be a pin junction photodiode using an i-type semiconductor as the layer 565b.

[0142] The pn junction photodiode or the pin junction photodiode can be formed using single crystal silicon. Alternatively, the pin junction photodiode can be formed using a thin film of amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like.

[0143] In addition, the photoelectric conversion device 101 in the layer 561 may be Fig.15D As shown, a stack of layer 566a, layer 566b, layer 566c, and layer 566d is used. Fig.15D The photoelectric conversion device 101 shown is an example of an avalanche photodiode, in which the layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to photoelectric conversion units.

[0144] The layer 566a is preferably made of a low-resistance metal layer or the like. For example, aluminum, titanium, tungsten, tantalum, silver, or a stacked layer thereof can be used.

[0145] The layer 566d is preferably a conductive layer having high light transmittance to visible light, and for example, indium oxide, tin oxide, zinc oxide, indium tin oxide, gallium zinc oxide, indium gallium zinc oxide, or graphene can be used. Alternatively, the layer 566d may be omitted.

[0146] The layers 566b and 566c of the photoelectric conversion unit may have a pn junction photodiode structure using a selenium-based material as the photoelectric conversion layer. Preferably, a p-type semiconductor selenium-based material is used as the layer 566b, and an n-type semiconductor such as gallium oxide is used as the layer 566c.

[0147] Photoelectric conversion devices using selenium materials have high external quantum efficiency for visible light. The photoelectric conversion device can increase the amount of electron amplification relative to the amount of incident light by using avalanche multiplication. In addition, selenium materials have high light absorption coefficients, so they have advantages in production, such as being able to manufacture photoelectric conversion layers with thin films. Thin films of selenium materials can be formed by vacuum evaporation or sputtering.

[0148] As the selenium-based material, crystalline selenium such as single crystal selenium or polycrystalline selenium, amorphous selenium, a compound of copper, indium, and selenium (CIS), or a compound of copper, indium, gallium, and selenium (CIGS) can be used.

[0149] The n-type semiconductor is preferably formed of a material with a wide band gap and translucency to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or oxides mixed with the above substances can be used. In addition, these materials also have the function of a hole injection blocking layer, which can reduce dark current.

[0150] In addition, the photoelectric conversion device 101 in the layer 561 may be Fig.15E As shown, a stack of layer 567a, layer 567b, layer 567c, layer 567d and layer 567e is used. Fig.15E The photoelectric conversion device 101 shown is an example of an organic photoconductive film, the layers 567a and 567e correspond to electrodes, and the layers 567b, 567c, and 567d correspond to photoelectric conversion sections.

[0151] Either one of the layer 567b and the layer 567d of the photoelectric conversion unit may be a hole-transport layer, and the other may be an electron-transport layer. Alternatively, the layer 567c may be a photoelectric conversion layer.

[0152] As the hole transport layer, for example, molybdenum oxide or the like can be used. As the electron transport layer, for example, fullerene such as C60 or C70 or its derivatives or the like can be used.

[0153] As the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.

[0154] Fig.15A The layer 562 shown may use a silicon substrate, for example. The silicon substrate includes Si transistors, etc. By using the Si transistors, in addition to forming a pixel circuit, a circuit for driving the pixel circuit, a readout circuit for image signals, an image processing circuit, etc. may be formed. Specifically, a part or all of the transistors included in the pixel circuit and the peripheral circuit (pixel 10, circuits 22, 23, 28, etc.) described in Embodiment 1 may be set in layer 562.

[0155] Alternatively, pixels can be Fig. 15B As shown, a stacked structure of layer 561, layer 563 and layer 562 is used.

[0156] The layer 563 may include OS transistors (e.g., transistors 102, 103, 104, etc. of the pixel 10a). In this case, the layer 562 preferably includes Si transistors (e.g., transistors 105, 106, etc. of the pixel 10a). In addition, a part of the transistors included in the peripheral circuit described in Embodiment 1 may be provided in the layer 563.

[0157] By adopting this structure, the components and peripheral circuits constituting the pixel circuit can be dispersed into multiple layers, and the components can be overlapped with each other or with the peripheral circuits, so that the area of ​​the camera device can be reduced. Fig. 15B In the structure, layer 562 can also be used as a supporting substrate and pixels 10 and peripheral circuits can be set on layers 561 and 563.

[0158] As a semiconductor material for OS transistors, metal oxides with an energy gap of 2eV or more, preferably 2.5eV or more, and more preferably 3eV or more can be used. Typical examples include oxide semiconductors containing indium, such as CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) or CAC (Cloud-Aligned Composite)-OS mentioned later. The atoms that make up the crystal in CAAC-OS are stable, and it is suitable for transistors that value reliability. CAC-OS exhibits high mobility characteristics and is suitable for transistors that are driven at high speeds.

[0159] Since the semiconductor layer of the OS transistor has a large energy gap, it exhibits an extremely low off-state current characteristic of only a few yA / μm (current value per channel width of 1μm). Unlike Si transistors, OS transistors do not experience impact ionization, avalanche breakdown, short channel effects, etc., so they can form circuits with high voltage resistance and high reliability. In addition, the electrical characteristic unevenness caused by the uneven crystallinity of Si transistors is not easily generated in OS transistors.

[0160] As the semiconductor layer in the OS transistor, for example, a film represented by an "In-M-Zn-based oxide" containing indium, zinc and M (selected from metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium) can be used.

[0161] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, the atomic ratio of the metal element of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≥M and Zn≥M. The atomic ratio of the metal element of such a sputtering target is preferably In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. Note that the atomic ratio of the semiconductor layer formed may vary within the range of ±40% of the atomic ratio of the metal element in the above-mentioned sputtering target.

[0162] As the semiconductor layer, an oxide semiconductor with a low carrier density is used. For example, an oxide semiconductor with a carrier density of 1×10 17 / cm 3 Below, preferably 1×10 15 / cm 3 Below, more preferably 1×10 13 / cm 3 Below, more preferably 1×1011 / cm 3 Below, more preferably less than 1×10 10 / cm 3 , 1×10 -9 / cm 3 The above oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. Since the defect state density of the oxide semiconductor is low, it can be said that the oxide semiconductor has stable characteristics.

[0163] Note that the present invention is not limited to the above description, and a material having an appropriate composition can be used according to the desired semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. In addition, it is preferred to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. of the semiconductor layer to obtain the desired semiconductor characteristics of the transistor.

[0164] When the oxide semiconductor constituting the semiconductor layer contains silicon or carbon, which is one of the Group 14 elements, oxygen vacancies increase, which causes the semiconductor layer to become n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0165] In addition, when an alkali metal or alkaline earth metal is bonded to an oxide semiconductor, carriers are generated, which increases the off-state current of the transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0166] In addition, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, electrons are generated as carriers, the carrier density increases, and it is easy to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to have normally-on characteristics. Therefore, the nitrogen concentration of the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is preferably 5×10 18 atoms / cm 3 the following.

[0167] In addition, when the oxide semiconductor constituting the semiconductor layer contains hydrogen, hydrogen reacts with oxygen bonded to metal atoms to generate water, and thus oxygen vacancies are sometimes formed in the oxide semiconductor. In the case where the channel formation region in the oxide semiconductor contains oxygen vacancies, the transistor may have a normally-on characteristic. Furthermore, sometimes defects formed by hydrogen entering oxygen vacancies are used as donors to generate electrons as carriers. In addition, a portion of the hydrogen is bonded to oxygen bonded to metal atoms to generate electrons as carriers. Therefore, transistors using oxide semiconductors containing more hydrogen tend to have normally-on characteristics.

[0168] Defects formed by hydrogen entering oxygen vacancies are used as donors for oxide semiconductors. However, it is difficult to quantitatively evaluate this defect. Therefore, in oxide semiconductors, evaluation is sometimes performed based on carrier concentration rather than donor concentration. Therefore, in this specification, etc., sometimes as a parameter of an oxide semiconductor, instead of using donor concentration, carrier concentration assumed to be in a state where no electric field is applied is used. That is, the "carrier concentration" described in this specification, etc. may sometimes be referred to as "donor concentration".

[0169] Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration measured by secondary ion mass spectrometry (SIMS) is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 By using an oxide semiconductor in which impurities such as hydrogen have been sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be imparted.

[0170] In addition, the semiconductor layer may also have a non-single-crystal structure, for example. The non-single-crystal structure includes, for example, a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) with a c-axis orientation, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single-crystal structures, the amorphous structure has the highest defect state density, while the CAAC-OS has the lowest defect state density.

[0171] The oxide semiconductor film with an amorphous structure has, for example, a disordered atomic arrangement and no crystalline component. Alternatively, the oxide semiconductor film with an amorphous structure has, for example, a completely amorphous structure and no crystalline part.

[0172] In addition, the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a single layer structure or a stacked layer structure including two or more of the above regions.

[0173] Next, the structure of CAC (Cloud-Aligned Composite)-OS, which is one embodiment of a non-single-crystal semiconductor layer, will be described.

[0174] CAC-OS refers to, for example, a configuration in which elements contained in an oxide semiconductor are unevenly distributed, wherein the size of the material containing the unevenly distributed elements is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, or a similar size. Note that in the following, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed in a size of greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, is also referred to as a mosaic or patch shape.

[0175] The oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition, it may also contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium.

[0176] For example, CAC-OS in In-Ga-Zn oxide (in CAC-OS, In-Ga-Zn oxide can be referred to as CAC-IGZO in particular) refers to a material divided into indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0)) or indium zinc oxide (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2 and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4 and Z4 are real numbers greater than 0)) etc. to form a mosaic shape, and the mosaic-shaped InO X1 or In X2 Zn Y2 O Z2 A structure uniformly distributed in the film (hereinafter also referred to as a cloud shape).

[0177] In other words, CAC-OS is a GaO X3The area with In as the main component X2 Zn Y2 O Z2 or InO X1 In this specification, for example, when the atomic ratio of In to element M in the first region is greater than that in the second region, the In concentration in the first region is higher than that in the second region.

[0178] Note that IGZO is a general term and sometimes refers to a compound containing In, Ga, Zn, and O. As a typical example, InGaO3(ZnO) m1 (m1 is a natural number) or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≤x0≤1, m0 is an arbitrary number).

[0179] The crystalline compound has a single crystal structure, a polycrystalline structure or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected in a non-oriented manner on the ab plane.

[0180] On the other hand, CAC-OS is related to the material composition of oxide semiconductors. CAC-OS refers to a composition in which, in a material composition containing In, Ga, Zn, and O, a nanoparticle-like region with Ga as the main component is observed in one part, and a nanoparticle-like region with In as the main component is observed in another part, and these regions are irregularly dispersed in a mosaic shape. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0181] CAC-OS does not include a stacked-layer structure of two or more films having different compositions, for example, a structure consisting of two layers of a film having In as a main component and a film having Ga as a main component.

[0182] Note that sometimes no GaO X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 There are clear boundaries between the regions of the main components.

[0183] In the case where CAC-OS includes one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium instead of gallium, CAC-OS refers to a structure in which nanoparticle-like regions with the metal element as the main component are observed in a part and nanoparticle-like regions with In as the main component are observed in a part and are irregularly dispersed in a mosaic manner.

[0184] CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. When CAC-OS is formed by sputtering, one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas can be used as a deposition gas. In addition, the lower the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during film formation, the better. For example, the flow rate ratio of the oxygen gas is set to be greater than 0% and less than 30%, preferably greater than 0% and less than 10%.

[0185] CAC-OS has the following characteristics: when measured by the Out-of-plane method using θ / 2θ scanning, which is one of the X-ray diffraction (XRD) measurement methods, no clear peak is observed. In other words, according to the X-ray diffraction measurement, it is known that there is no orientation in the ab plane direction and the c-axis direction in the measurement area.

[0186] In addition, in the electron diffraction pattern of CAC-OS obtained by irradiating an electron beam with a beam diameter of 1 nm (also called a nanobeam), a ring-shaped area with high brightness (ring-shaped area) and multiple bright spots in the ring-shaped area were observed. Therefore, according to the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure that is not oriented in the plane direction and the cross-sectional direction.

[0187] In addition, for example, in CAC-OS of In-Ga-Zn oxide, it can be confirmed from the EDX-mapping image obtained by energy dispersive X-ray spectroscopy (EDX) that there is GaO X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 A composition in which the main components are unevenly distributed in the area.

[0188] The structure of CAC-OS is different from that of IGZO compounds in which metal elements are evenly distributed, and it has different properties from IGZO compounds.X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 The regions where the main components are present are separated from each other, and the regions where the main components are present are in a mosaic-like structure.

[0189] Here, In X2 Zn Y2 O Z2 or InO X1 The conductivity of the area with GaO as the main component is higher than that of the area with GaO as the main component. X3 In other words, when the carrier flows through the region with In X2 Zn Y2 O Z2 or InO X1 When In is the main component of the region, it exhibits the conductivity of an oxide semiconductor. X2 Zn Y2 O Z2 or InO X1 When the region as the main component is distributed in a cloud shape in the oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0190] On the other hand, GaO X3 The insulation of the area with In as the main component is higher than that of the area with In X2 Zn Y2 O Z2 or InO X1 In other words, when GaO X3 When regions with the main components of , etc. are distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0191] Therefore, when CAC-OS is used in semiconductor devices, the X3 The insulation properties of etc. and the causes of In X2 Zn Y2 O Z2 or InO X1 The complementary effect of conductivity can achieve high on-state current (I on ) and high field effect mobility (μ).

[0192] In addition, semiconductor elements using CAC-OS have high reliability. Therefore, CAC-OS is suitable for use as a constituent material of various semiconductor devices.

[0193] Fig.16A Yes Description Fig.15AFIG. 5 shows an example of a cross section of a pixel. As the photoelectric conversion device 101, layer 561 includes a pn junction type photodiode using silicon as a photoelectric conversion layer. Layer 562 includes a Si transistor, Fig.16A The transistors 102 and 104 constituting the pixel circuit are shown by taking the pixel 10 b as an example.

[0194] In the photoelectric conversion device 101, the layer 565a may be p + type region, layer 565b is an n-type region and layer 565c is an n-type region. + In addition, layer 565b is provided with region 536 for connecting the power line to layer 565c. For example, region 536 may be p + Type area.

[0195] Fig.16A The Si transistor shown is a fin-type transistor having a channel formation region in a silicon substrate 540. Fig.17A The cross section along the channel width is shown. Si transistors can also be Fig. 17B A planar transistor is shown.

[0196] In addition, if Fig. 17C The Si transistor shown may also be a transistor including a semiconductor layer 545 of a silicon thin film. For example, the semiconductor layer 545 may use single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on a silicon substrate 540.

[0197] Fig.16A An example is shown in which the components of the layer 561 and the components of the layer 562 are electrically connected by the bonding technology.

[0198] An insulating layer 542, a conductive layer 533, and a conductive layer 534 are provided on the layer 561. The conductive layer 533 and the conductive layer 534 have a region buried in the insulating layer 542. The conductive layer 533 is electrically connected to the layer 565a. The conductive layer 534 is electrically connected to the region 536. In addition, the surfaces of the insulating layer 542, the conductive layer 533, and the conductive layer 534 are flattened so that their heights are uniform.

[0199] An insulating layer 541, a conductive layer 531, and a conductive layer 532 are provided over the layer 562. The conductive layer 531 and the conductive layer 532 have a region buried in the insulating layer 541. The conductive layer 532 is electrically connected to a power supply line. The conductive layer 531 is electrically connected to a source or a drain of the transistor 104. In addition, the surfaces of the insulating layer 541, the conductive layer 531, and the conductive layer 532 are flattened so that their heights are uniform.

[0200] Here, the conductive layer 531 and the conductive layer 533 preferably have the same metal element as their main component. The conductive layer 532 and the conductive layer 534 preferably have the same metal element as their main component. Insulating layer 541 and insulating layer 542 preferably have the same component.

[0201] For example, Cu, Al, Sn, Zn, W, Ag, Pt, Au, or the like can be used as the conductive layers 531, 532, 533, and 534. From the viewpoint of ease of bonding, Cu, Al, W, or Au is preferably used. In addition, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used as the insulating layers 541 and 542.

[0202] In other words, it is preferable that the same metal material as the above metal material is used as the combination of the conductive layer 531 and the conductive layer 533 and the combination of the conductive layer 532 and the conductive layer 534. In addition, it is preferable that the same insulating material as the above insulating material is used as the insulating layer 541 and the insulating layer 542. With the above structure, bonding can be performed with the boundary between the layer 561 and the layer 562 as the bonding position.

[0203] Through the above-described bonding step, electrical connection can be obtained between the combination of the conductive layer 531 and the conductive layer 533 and between the combination of the conductive layer 532 and the conductive layer 534. In addition, connection between the insulating layer 541 and the insulating layer 542 having mechanical strength can be obtained.

[0204] When joining metal layers, a surface activation bonding method can be used. In this method, the oxide film and impurity adsorption layer on the surface are removed by sputtering treatment, etc., and the cleaned and activated surfaces are brought into contact for bonding. Alternatively, a diffusion bonding method that uses temperature and pressure to bond the surfaces can be used. The above methods can all produce atomic-level bonding, so excellent bonding can be obtained both electrically and mechanically.

[0205] In addition, when bonding the insulating layer, a hydrophilic bonding method can be used. In this method, after obtaining high flatness by polishing, etc., the surfaces that have been hydrophilized by oxygen plasma, etc. are brought into contact for temporary bonding, and dehydration is performed by heat treatment to perform formal bonding. The hydrophilic bonding method also produces bonding at the atomic level, so mechanically excellent bonding can be obtained.

[0206] In the case of the bonding layer 561 and the layer 562, since the insulating layer and the metal layer are mixed at each bonding surface, for example, a surface activation bonding method and a hydrophilic bonding method may be combined.

[0207] For example, a method of bonding can be adopted in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed. Alternatively, a difficultly oxidizable metal such as Au can be used as the surface of the metal layer and a hydrophilic treatment can be performed. Alternatively, bonding methods other than the above methods can be used.

[0208] Fig. 16B As Fig.15A The layer 561 of the pixel shown is a cross-sectional view when a pn junction type photodiode using a selenium-based material as a photoelectric conversion layer is used. A layer 566a is included as one electrode, layers 566b and 566c are included as photoelectric conversion layers, and a layer 566d is included as another electrode.

[0209] In this case, the layer 561 can be directly provided on the layer 562. The layer 566a is electrically connected to the source or drain of the transistor 104. The layer 566d is electrically connected to the power supply line through the conductive layer 537. In the case where an organic photoconductive film is used for the layer 561, the connection method with the transistor is the same as the above method.

[0210] Fig.18A Yes Description Fig. 15B 1 is a diagram showing an example of a cross section of a pixel. Layer 561 includes a pn junction type photodiode using silicon as a photoelectric conversion layer as the photoelectric conversion device 101. Layer 562 includes a Si transistor, Fig.18A The transistors 105 and 106 constituting the pixel circuit are shown by taking the pixel 10b as an example. The layer 563 includes an OS transistor, Fig.18A Transistors 102 and 104 constituting the pixel circuit are shown. Also shown is a structural example in which a layer 561 and a layer 563 are electrically connected by a bonding step.

[0211] Fig.19A The OS transistor is shown in detail. Fig.19A The OS transistor shown has a self-aligned structure in which a source electrode 205 and a drain electrode 206 are formed by providing an insulating layer over a stack of an oxide semiconductor layer and a conductive layer and providing a groove reaching the oxide semiconductor layer.

[0212] In addition to the channel formation region, source region 203 and drain region 204 formed in the oxide semiconductor layer, the OS transistor may further include a gate electrode 201 and a gate insulating film 202. At least the gate insulating film 202 and the gate electrode 201 are provided in the groove. An oxide semiconductor layer 207 may also be provided in the groove.

[0213] like Fig.19B As shown, the OS transistor may also have a self-aligned structure in which a source region and a drain region are formed in an oxide semiconductor layer using the gate electrode 201 as a mask.

[0214] Or, if Fig.19C As shown, a non-self-aligned top gate transistor having a region where the source electrode 205 or the drain electrode 206 overlaps with the gate electrode 201 can be used.

[0215] The transistors 102 and 104 include a back gate 535, but may not include a back gate. Fig.19D As shown in the cross-sectional view of the transistor in the channel width direction, the back gate 535 can also be electrically connected to the front gate of the opposite transistor. As an example, Fig.19D China-Israel Fig.18A The transistor shown is used as an example, and the same applies to transistors of other structures. In addition, a structure in which a fixed potential different from that of the front gate can be supplied to the back gate 535 may be adopted.

[0216] An insulating layer 543 having a function of preventing diffusion of hydrogen is provided between a region where the OS transistor is formed and a region where the Si transistor is formed. Hydrogen in the insulating layer provided near the channel formation region of the transistors 105 and 106 terminates dangling bonds of silicon. On the other hand, hydrogen in the insulating layer provided near the channel formation region of the transistors 102 and 104 may be one of the causes of generation of carriers in the oxide semiconductor layer.

[0217] Since hydrogen is confined in one layer by the insulating layer 543, reliability of the transistors 105 and 106 can be improved. At the same time, since diffusion of hydrogen from one layer to another layer is suppressed, reliability of the transistors 102 and 104 can be improved.

[0218] The insulating layer 543 can be made of, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like.

[0219] Fig.18B It is described as Fig. 15B The cross-sectional view of the case where the layer 561 of the pixel shown uses a pn junction type photodiode using a selenium-based material as a photoelectric conversion layer. The layer 561 can be directly provided on the layer 563. The details of the layers 561, 562, and 563 can refer to the above description. Note that when an organic photoconductive film is used for the layer 561, the connection method with the transistor is the same as the above method.

[0220] Fig. 20A1 is a stereogram showing an example of adding a color filter or the like to a pixel of an imaging device of one embodiment of the present invention. The stereogram also shows a cross section of a plurality of pixels. An insulating layer 580 is formed on the layer 561 forming the photoelectric conversion device 101. The insulating layer 580 can use a silicon oxide film or the like having high light transmittance to visible light. In addition, a silicon nitride film can also be stacked as a passivation film. In addition, a dielectric film such as hafnium oxide can also be stacked as an anti-reflection film.

[0221] A light shielding layer 581 may also be formed on the insulating layer 580. The light shielding layer 581 has a function of preventing mixing of light passing through the upper color filter. A metal layer such as aluminum or tungsten may be used as the light shielding layer 581. In addition, the metal layer and a dielectric film having the function of an anti-reflection film may be stacked.

[0222] An organic resin layer 582 used as a planarization film may be provided on the insulating layer 580 and the light shielding layer 581. In addition, a color filter 583 (color filters 583a, 583b, 583c) is formed in each pixel. For example, the color filters 583a, 583b, and 583c are provided with colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta), thereby obtaining a color image.

[0223] An insulating layer 586 or the like which is light-transmissive to visible light may be provided on the color filter 583 .

[0224] In addition, if Fig. 20B As shown, an optical conversion layer 585 may be used instead of the color filter 583. By adopting such a structure, an imaging device capable of obtaining images in various wavelength regions can be formed.

[0225] For example, when a filter that blocks light with a wavelength below the visible light is used as the optical conversion layer 585, an infrared camera device can be obtained. When a color filter that blocks light with a wavelength below the near infrared light is used as the optical conversion layer 585, a far infrared camera device can be obtained. In addition, when a filter that blocks light with a wavelength above the visible light is used as the optical conversion layer 585, an ultraviolet camera device can be obtained.

[0226] In addition, by using a scintillator for the optical conversion layer 585, an imaging device for obtaining an image that visualizes the radiation intensity, such as an X-ray imaging device, can be formed. When radiation such as X-rays that pass through the object to be photographed enters the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light due to the photoluminescence phenomenon. Image data is obtained by detecting this light with the photoelectric conversion device 101. In addition, the imaging device of this structure can also be used for radiation detectors, etc.

[0227] The scintillator contains a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible light or ultraviolet light when the scintillator is irradiated with radiation such as X-rays or gamma rays. For example, a material obtained by dispersing Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc. in a resin or ceramic can be used.

[0228] In addition, in the photoelectric conversion device 101 using a selenium-based material, since radiation such as X-rays can be directly converted into electric charges, a scintillator does not need to be used.

[0229] In addition, if Fig. 20C As shown in FIG. 5 , a microlens array 584 may be provided on the color filter 583. Light passing through each lens of the microlens array 584 is irradiated to the photoelectric conversion device 101 via the color filter 583 provided thereunder. Fig. 20B The optical conversion layer 585 is shown with a microlens array 584 disposed thereon.

[0230] An example of a package and a camera module that accommodate an image sensor chip will be described below. The image sensor chip may be the one having the structure of the above-mentioned imaging device.

[0231] Fig.21A1 4 is a perspective view of the top surface of a package that contains an image sensor chip. Fig.21A3 ) fixed packaging substrate 410, glass cover 420 and adhesive 430 bonding them, etc.

[0232] Fig.21A2 This is a three-dimensional view of the bottom side of the package. The bottom side of the package includes a BGA (Ball grid array) with solder balls as bumps 440. Note that it is not limited to BGA, and can also include LGA (Land grid array), PGA (Pin Grid Array), etc.

[0233] Fig.21A3 The package is shown in a perspective view with a portion of the cover glass 420 and the adhesive 430 omitted. The electrode pads 460 are formed on the package substrate 410 and are electrically connected to the bumps 440 through the through holes. The electrode pads 460 are electrically connected to the image sensor chip 450 through the wires 470 .

[0234] in addition, Fig.21B14 is a perspective view of the top surface of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 411 for fixing an image sensor chip 451, a lens cover 421, and a lens 435. Figure 21B3 ) is provided between the IC chip 490 (refer to Figure 21B3 ) and has a structure as a SiP (System in package).

[0235] Fig.21B2 This is a perspective view of the bottom side of the camera module. The bottom and side surfaces of the package substrate 411 have a QFN (Quad flat no-lead package) structure with a storage connection pad 441. Note that this structure is an example, and a QFP (Quad flat package) or the above-mentioned BGA can also be provided.

[0236] Figure 21B3 It is a perspective view of the module in which a part of the lens cover 421 and the lens 435 are omitted. The connection pad 441 is electrically connected to the electrode pad 461 , and the electrode pad 461 is electrically connected to the image sensor chip 451 or the IC chip 490 through the wire 471 .

[0237] By housing the image sensor chip in a package of the above type, it can be easily mounted on a printed circuit board or the like, and thus the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0238] This embodiment mode can be combined with the description of other embodiment modes as appropriate.

[0239] (Implementation 3)

[0240] Electronic devices that can use the camera device according to one embodiment of the present invention include display devices, personal computers, image storage devices or image reproduction devices with recording media, mobile phones, including portable game consoles, portable data terminals, e-book readers, imaging devices such as video cameras or digital cameras, goggle-type displays (head-mounted displays), navigation systems, audio reproduction devices (car audio systems, digital audio players, etc.), copiers, fax machines, printers, multifunction printers, automatic teller machines (ATMs), and vending machines. FIG. 22A to FIG. 22F Specific examples of these electronic devices are shown.

[0241] Fig.22AThe mobile phone is an example of a mobile phone, which includes a housing 981, a display portion 982, an operation button 983, an external connection interface 984, a speaker 985, a microphone 986, a camera 987, etc. The mobile phone has a touch sensor on the display portion 982. By touching the display portion 982 with a finger or a stylus pen, various operations such as making a call or inputting text can be performed. The camera device of one embodiment of the present invention can be applied to the element for acquiring an image in the mobile phone.

[0242] Fig. 22B The portable data terminal includes a housing 911, a display unit 912, a speaker 913, a camera 919, etc. Information can be input and output through the touch panel function of the display unit 912. In addition, text and the like can be recognized from the image acquired by the camera 919, and the text can be output in the form of voice using the speaker 913. The camera device of one embodiment of the present invention can be applied to the element for acquiring an image in the portable data terminal.

[0243] Fig. 22C The surveillance camera includes a bracket 951, a camera unit 952, a protective cover 953, etc. The camera unit 952 is provided with a rotating mechanism, etc., and can capture the surroundings by being installed on the ceiling. The camera device of one embodiment of the present invention can be applied to an element used to obtain an image in the camera unit. Note that "surveillance camera" is a general name and is not limited to its use. For example, a device having a function as a surveillance camera is called a video camera or a video camera.

[0244] Fig.22D The present invention is a video camera, which includes a first housing 971, a second housing 972, a display unit 973, an operation key 974, a lens 975, a connection unit 976, a speaker 977, a microphone 978, and the like. The operation key 974 and the lens 975 are provided in the first housing 971, and the display unit 973 is provided in the second housing 972. The imaging device according to one embodiment of the present invention can be applied to a component for acquiring an image in the video camera.

[0245] Fig.22E The digital camera includes a housing 961, a shutter button 962, a microphone 963, a light emitting unit 967, a lens 965, and the like. The imaging device according to one embodiment of the present invention can be applied to components for acquiring images in the digital camera.

[0246] Fig.22FThe present invention is a watch-type information terminal, which includes a display unit 932, a housing and wristband 933, and a camera 939. The display unit 932 may also include a touch panel for operating the information terminal. The display unit 932 and the housing and wristband 933 are flexible and suitable for being worn on the body. The camera device of one embodiment of the present invention can be applied to the constituent elements used to obtain images in the information terminal.

[0247] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0248] [Explanation of symbols]

[0249] 10: pixel, 10a: pixel, 10b: pixel, 10c: pixel, 11: circuit, 12: circuit, 21: pixel array, 22: circuit, 23: circuit, 24: circuit, 25: circuit, 26: circuit, 28: circuit, 101: photoelectric conversion device, 102: transistor, 103: transistor, 104: transistor, 105: transistor, 106: transistor, 107: capacitor, 108: capacitor, 109: capacitor, 110: transistor, 111: transistor, 121: wiring, 122: wiring, 123: wiring, 124: wiring, 125: wiring, 126: wiring, 127: wiring, 128: wiring, 129: wiring, 130: wiring, 131: wiring, 201: gate electrode, 202: gate insulating film, 203: source region, 204: drain region, 205: source electrode, 206: drain electrode, 207: oxide semiconductor layer, 410: package substrate, 411: package substrate, 420: glass cover, 421: lens cover, 430: adhesive, 435: lens, 440: bump, 441: connection pad, 450: image sensor chip, 451: image sensor chip, 460: electrode pad, 461: electrode pad, 470: lead, 471: lead, 490: IC chip, 531: conductive layer, 532: conductive layer, 533: conductive layer, 534: conductive layer, 535: back gate, 536: region domain, 537: conductive layer, 540: silicon substrate, 541: insulating layer, 542: insulating layer, 543: insulating layer, 545: semiconductor layer, 546: insulating layer, 561: layer, 562: layer, 563: layer, 565a: layer, 565b: layer, 565c: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 580: insulating layer, 581: light shielding layer, 582: organic resin layer, 583: color filter, 583a: color filter, 583b: color filter, 583c: color filter, 584: microlens array, 585: optical conversion layer, 58 6: Insulation layer, 911: Housing, 912: Display, 913: Speaker, 919: Camera, 932: Display, 933: Housing and wristband, 939: Camera, 951: Bracket, 952: Camera unit, 953: Protective cover, 961: Housing, 962: Shutter button, 963: Microphone, 965: Lens, 967: Light emitting unit, 971: Housing, 972: Housing, 973: Display, 974: Operation key, 975: Lens, 976: Connecting part, 977: Speaker, 978: Microphone, 981: Housing, 982: Display, 983: Operation button, 984: External connection port, 985: Speaker, 986: Microphone, 987: Camera

Claims

1. A camera device, comprising: A pixel, the pixel comprising: Photoelectric conversion devices; a first transistor; a second transistor; a third transistor; and Capacitors, wherein one electrode of the photoelectric conversion device is electrically connected to one of the source and drain of the first transistor and one of the source and drain of the second transistor, The other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, And, the other electrode of the capacitor is electrically connected to one of the source and the drain of the third transistor.

2. A camera device, comprising: A pixel, the pixel comprising: Photoelectric conversion devices; a first transistor; a second transistor; a third transistor; and Capacitors, wherein one electrode of the photoelectric conversion device is electrically connected to one of the source and the drain of the third transistor and one electrode of the capacitor, The other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the first transistor, And, the other electrode of the capacitor is electrically connected to one of a source and a drain of the second transistor.

3. The imaging device according to claim 1 or 2, in, The pixel is configured to add the first potential and the second potential to generate a third potential, And, the pixel is configured to generate data in the photoelectric conversion device to which the third potential is applied and output the data.

4. A camera device, comprising: A first pixel and a second pixel, each pixel comprising: Photoelectric conversion devices; a first transistor; a second transistor; and Capacitors, wherein one of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor, The other electrode of the capacitor is electrically connected to one of the source and the drain of the second transistor, The photoelectric conversion device is electrically connected to the one of the source and the drain of the first transistor, The one of the source and the drain of the first transistor of the first pixel is electrically connected to the gate of the third transistor, Furthermore, the one of the source and the drain of the first transistor of the second pixel is electrically connected to the gate of the third transistor.

5. The imaging device according to claim 4, in, The one of the source and the drain of the first transistor of the first pixel is electrically connected to the gate of the third transistor through a fourth transistor.

6. The imaging device according to claim 4, in, The photoelectric conversion device in the first pixel is electrically connected to the one of the source and the drain of the first transistor through a fifth transistor.

Images