Multilayer circuit board and method for manufacturing the same
By laminating a copper layer onto the carrier copper layer and then onto both sides of the core board, the problem of easily damaged copper foil on thin circuit boards is solved, achieving a thinner and lighter circuit board with lower loss, and improving the stability of signal transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- AVARY HLDG (SHENZHEN) CO LTD
- Filing Date
- 2023-10-26
- Publication Date
- 2026-07-14
AI Technical Summary
In the manufacturing of thin circuit boards, existing technologies are prone to quality problems such as creases, indentations, and wrinkles in the copper foil, and the copper foil thickness is uneven, making it difficult to meet the requirements of both thinness and low loss.
The method involves setting a copper layer on a carrier copper layer, then pressing the copper layer onto both sides of the core board through lamination, and finally removing the carrier copper layer. This achieves a uniform distribution of copper layers with a thickness of 2 to 6 micrometers on both sides of the core board, reducing problems such as pressure points, dents, and wrinkles.
This improved the flatness of the copper layer, reduced signal transmission loss, enhanced signal transmission stability, and met the requirements for thinner and lighter circuit boards.
Smart Images
Figure CN119947005B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit board manufacturing, and more particularly to a multilayer circuit board and a method for manufacturing the same. Background Technology
[0002] As consumer electronics become increasingly thinner and lighter, the circuit boards inside these products also need to be correspondingly thinner to meet the structural requirements of the overall device. On the other hand, the commercialization of 5G bands requires circuit boards to have low loss, while the usual effective way to reduce loss is to increase the thickness of the dielectric material. Therefore, there is a contradiction between the requirements for thinness and lightness and low loss.
[0003] During high-frequency signal transmission, the return signal is mainly concentrated on the ground plane and propagates closer to the signal line. Furthermore, as the frequency increases, the current distribution becomes more concentrated on the surface; for example, at 10GHz, the current distribution is limited to within 0.3µm of the surface. Therefore, appropriately reducing the thickness of the return ground plane will not affect signal transmission loss and can reduce the overall thickness of the circuit board. However, if conventional printed circuit board processes are used to produce excessively thin copper foil substrates, quality problems such as creases, indentations, and wrinkles are likely to occur. Conversely, using methods to thin the copper foil may lead to uneven copper foil thickness. Summary of the Invention
[0004] In view of this, it is necessary to provide a method for manufacturing multilayer circuit boards to solve the problem of processing excessively thin copper foil.
[0005] Additionally, this application also provides a multilayer circuit board.
[0006] A method for manufacturing a multilayer circuit board includes the following steps:
[0007] A core board is provided, the core board including an inner insulating layer and an inner circuit layer disposed on one side of the inner insulating layer;
[0008] A first outer carrier plate is provided on one side of the core board. The first outer carrier plate includes a first outer insulating layer, a first copper layer and a first peelable layer. The first outer insulating layer is disposed between the first copper layer and the inner circuit layer. The first peelable layer is disposed on the side of the first copper layer away from the first outer insulating layer.
[0009] A second outer carrier plate is disposed on the other side of the core board. The second outer carrier plate includes a second outer insulating layer, a second copper layer, and a second peelable layer. The second outer insulating layer is disposed between the second copper layer and the inner insulating layer. The second peelable layer is disposed on the side of the second copper layer opposite to the second outer insulating layer.
[0010] Remove the first peelable layer and the second peelable layer to obtain the multilayer circuit board.
[0011] In some possible embodiments, the steps further include:
[0012] Etch the first copper layer to form the first outer circuit layer, and
[0013] The second copper layer is etched to form the second outer circuit layer.
[0014] In some possible embodiments, the steps further include:
[0015] A portion of the first outer circuit layer and a portion of the first outer insulation layer are removed to form a gap, and a portion of the inner circuit layer is exposed in the gap.
[0016] In some possible embodiments, the steps further include:
[0017] A first protective film is provided on the first outer circuit layer, and
[0018] A second protective film is provided on the second outer circuit layer.
[0019] In some possible embodiments, the core board further includes a first adhesive layer and a plurality of inner conductors, the first adhesive layer being disposed on the side of the inner insulating layer opposite to the inner circuit layer, and the inner conductors passing through the first adhesive layer and the inner insulating layer and connecting to the inner circuit layer.
[0020] In some possible embodiments, the first outer carrier plate further includes a second adhesive layer and a plurality of first outer conductors, the second adhesive layer being disposed on the side of the first outer insulating layer opposite to the first copper layer, and the first outer conductors passing through the second adhesive layer and the first outer insulating layer and connecting to the first copper layer.
[0021] In some possible embodiments, the second outer carrier plate further includes a plurality of second outer conductors that pass through the second outer insulating layer and connect to the second copper layer.
[0022] A multilayer circuit board, comprising:
[0023] A core board, the core board including an inner insulating layer and an inner circuit layer disposed on one side of the inner insulating layer;
[0024] A first outer side plate is disposed on one side of the core plate. The first outer side plate includes a first outer insulating layer and a first outer circuit layer. The first outer insulating layer is disposed between the first outer circuit layer and the inner circuit layer. The thickness of the first outer circuit layer is 2 to 6 micrometers.
[0025] The second outer side plate is disposed on the other side of the core plate. The second outer side plate includes a second outer insulating layer and a second outer circuit layer. The second outer insulating layer is disposed between the second outer circuit layer and the inner insulating layer. The thickness of the second outer circuit layer is 2 to 6 micrometers.
[0026] In some possible embodiments, the system further includes a plurality of inner conductors, a plurality of first outer conductors, and a plurality of second outer conductors. The inner conductors are disposed on the inner insulating layer, the first outer conductors are disposed on the first outer insulating layer, and the second outer conductors are disposed on the second outer insulating layer. The inner conductors connect the inner circuit layer and the second outer conductors, and the first outer conductors connect the inner circuit layer and the first outer circuit layer.
[0027] In some possible embodiments, a first protective film and a second protective film are also included, wherein the first protective film is disposed on the first outer circuit layer and the second protective film is disposed on the second outer circuit layer.
[0028] Compared to existing technologies, the manufacturing method of the multilayer circuit board provided in this application sets a copper layer on a carrier copper layer, then presses the copper layer to both sides of the core board by lamination, and finally removes the carrier copper layer. This method can set a copper layer with a thickness of 2 to 6 micrometers on both sides of the core board. During the lamination process, due to the protection of the carrier copper layer, the copper layer can reduce the problems of pressure points, folds and wrinkles. Furthermore, the uniform pressure applied to the carrier copper layer helps to improve the flatness of the copper layer. Attached Figure Description
[0029] Figure 1 This is a cross-sectional schematic diagram of a first substrate provided in an embodiment of this application.
[0030] Figure 2 for Figure 1 The diagram shows a cross-sectional view of the first substrate after the inner adhesive layer has been applied.
[0031] Figure 3 for Figure 2 The diagram shows a cross-sectional view of the inner adhesive layer and the inner insulating layer after the first groove is made.
[0032] Figure 4 for Figure 3 The diagram shows a cross-sectional view of the core plate obtained after setting an inner conductor in the first slot.
[0033] Figure 5 This is a cross-sectional schematic diagram of a second substrate provided in an embodiment of this application.
[0034] Figure 6 for Figure 5The diagram shows a cross-sectional view of the second substrate after the outer adhesive layer is applied.
[0035] Figure 7 for Figure 6 The diagram shows a cross-sectional view of the outer adhesive layer and the first outer insulating layer after the second groove is provided.
[0036] Figure 8 for Figure 7 The diagram shows a cross-section of the first outer conductor after the first outer carrier plate is obtained by setting the first outer conductor in the second slot.
[0037] Figure 9 This is a cross-sectional schematic diagram of a third substrate provided in an embodiment of this application.
[0038] Figure 10 for Figure 9 The diagram shows a cross-sectional view of the third substrate after the third slot is provided.
[0039] Figure 11 for Figure 10 The diagram shows a cross-sectional view of the second outer carrier plate obtained after the third slot is set with the second outer conductor.
[0040] Figure 12 For pressing Figure 4 The core board shown Figure 8 The first outer carrier plate shown and Figure 11 The diagram shows a cross-section behind the second outer carrier plate.
[0041] Figure 13 for Figure 12 The first outer carrier plate shown has its first carrier copper layer removed and Figure 12 The diagram shows a cross-section of the second outer carrier plate after the second carrier copper layer has been removed.
[0042] Figure 14 For etching Figure 13 The diagram shows a cross-section of the first copper layer and the second copper layer.
[0043] Figure 15 A cross-sectional schematic diagram showing the gap formed after removing part of the first outer circuit layer and part of the first outer insulation layer.
[0044] Figure 16 This is a cross-sectional schematic diagram of a multilayer circuit board provided in an embodiment of this application.
[0045] Explanation of main component symbols
[0046] Multilayer circuit board 100
[0047] Core board 10
[0048] Inner insulation layer 11
[0049] Inner adhesive layer 12
[0050] Inner circuit layer 13
[0051] Inner conductor 14
[0052] First substrate 15
[0053] First slot 16
[0054] First outer carrier plate 20
[0055] First carrier copper layer 21
[0056] First peelable layer 22
[0057] First copper layer 23
[0058] First outer circuit layer 231
[0059] First outer insulating layer 24
[0060] outer adhesive layer 25
[0061] First outer conductor 26
[0062] Second substrate 27
[0063] Second slot 28
[0064] Second outer carrier plate 30
[0065] Second carrier copper layer 31
[0066] Second peelable layer 32
[0067] Second copper layer 33
[0068] Second outer circuit layer 331
[0069] Second outer insulating layer 34
[0070] Second outer conductor 35
[0071] Third slot 36
[0072] Third substrate 37
[0073] Gap 40
[0074] First protective film 42
[0075] Second protective film 43
[0076] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation
[0077] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0078] It should be noted that when a component is considered to be "set on" another component, it can be set directly on the other component or there may be a middle component present at the same time.
[0079] Please see Figures 1 to 16 One embodiment of this application provides a method for manufacturing a multilayer circuit board 100, including the following steps:
[0080] S1: Please see Figure 4 A core board 10 is provided, the core board 10 including an inner insulating layer 11, an inner adhesive layer 12, an inner wiring layer 13, and a plurality of inner conductors 14. The inner insulating layer 11 is disposed between the inner adhesive layer 12 and the inner wiring layer 13. The inner conductors 14 pass through the inner insulating layer 11 and the inner adhesive layer 12. One end of the inner conductor 14 is connected to the inner wiring layer 13, and the other end is exposed outside the inner adhesive layer 12.
[0081] In this embodiment, please refer to Figures 1 to 4 In step S1, the specific manufacturing method of the core board 10 includes the following steps:
[0082] S11: Please refer to Figure 1 A first substrate 15 is provided, the first substrate 15 including the inner insulating layer 11 and an inner circuit layer 13 disposed on the inner insulating layer 11. The inner circuit layer 13 includes signal lines and isolation lines, the signal lines being used to transmit high-frequency signals (e.g., 10 GHz radio frequency signals), and the isolation lines being used for grounding. Specifically, the thickness of the inner circuit layer 13 is greater than 12 micrometers. The inner insulating layer 11 is made of polyimide.
[0083] S12: Please refer to Figure 2 An inner adhesive layer 12 is provided on the side of the inner insulating layer 11 opposite to the inner circuit layer 13. The inner adhesive layer 12 is made of epoxy resin and is used to connect other components.
[0084] S13: Please see Figure 3 A first groove 16 is provided in the inner adhesive layer 12 and the inner insulating layer 11, and the first groove 16 penetrates the inner adhesive layer 12 and the inner insulating layer 11. The cross-section of the first groove 16 is approximately trapezoidal.
[0085] S14: Please see Figure 4The inner conductive body 14 is disposed within the first slot 16 to obtain the core board 10. The inner conductive body 14 is printed copper paste. The copper paste includes copper powder and an adhesive. It is understood that in other embodiments of this application, the inner conductive body 14 may also be silver paste, solder paste, etc.
[0086] S2: Please see Figures 5 to 8 A first outer carrier plate 20 is provided. The first outer carrier plate 20 includes a first carrier copper layer 21, a first peelable layer 22, a first copper layer 23, a first outer insulating layer 24, and an outer adhesive layer 25 stacked sequentially. In addition, the first outer carrier plate 20 also includes a plurality of first outer conductors 26, which pass through the outer adhesive layer 25 and the first outer insulating layer 24 and are connected to the first copper layer 23.
[0087] In this embodiment, step S2, the specific manufacturing method of the first outer carrier plate 20 includes the following steps:
[0088] S21: Please see Figure 5 A second substrate 27 is provided, the second substrate 27 including a first carrier copper layer 21, a first peelable layer 22, a first copper layer 23 and a first outer insulating layer 24 stacked sequentially. The first peelable layer 22 is a release film, and the first carrier copper layer 21 and the first copper layer 23 can be separated by removing the first peelable layer 22.
[0089] S22: Please see Figure 6 An outer adhesive layer 25 is provided on the side of the first outer insulating layer 24 opposite to the first copper layer 23. One end of the first outer insulating layer 24 is flush with one end of the outer adhesive layer 25, and the width of the outer adhesive layer 25 is smaller than the width of the first outer insulating layer 24, so that a portion of the first outer insulating layer 24 is not covered by the outer adhesive layer 25.
[0090] S23: Please see Figure 7 A second groove 28 is provided between the outer adhesive layer 25 and the first outer insulating layer 24, and the second groove 28 penetrates through the second outer adhesive layer 25 and the first outer insulating layer 24. The cross-sectional shape of the second groove 28 is approximately trapezoidal.
[0091] S24: Please see Figure 8 A first outer conductor 26 is provided within the second slot 28 to obtain the first outer carrier plate 20. The first outer conductor 26 is printed copper paste.
[0092] S3: Please see Figures 9 to 11A second outer carrier plate 30 is provided. The second outer carrier plate 30 includes a second carrier copper layer 31, a second peelable layer 32, a second copper layer 33, and a second outer insulating layer 34 stacked sequentially. Additionally, the second outer carrier plate 30 also includes a plurality of second outer conductors 35. The second outer conductors 35 pass through the second outer insulating layer 34 and are connected to the second copper layer 33.
[0093] In this embodiment, step S3, the specific manufacturing method of the second outer carrier plate 30 includes the following steps:
[0094] S31: Please see Figure 9 A third substrate 37 is provided. The third substrate 37 includes a second carrier copper layer 31, a second peelable layer 32, a second copper layer 33 and a second outer insulating layer 34 stacked in sequence.
[0095] S32: Please refer to Figure 10 A third slot 36 is provided on the second outer insulating layer 34, and a portion of the second copper layer 33 is exposed at the bottom of the third slot 36.
[0096] S33: Please see Figure 11 The second outer conductor 35 is disposed within the third slot 36 to obtain the second outer carrier plate 30. The second outer conductor 35 is printed copper paste.
[0097] S4: Please see Figure 12 The first outer carrier plate 20 and the second outer carrier plate 30 are respectively attached to opposite sides of the core board 10. The inner adhesive layer 12 connects the inner insulating layer 11 and the second outer insulating layer 34. The outer adhesive layer 25 connects the first outer insulating layer 24 and the inner circuit layer 13. The first outer conductor 26 connects to the inner circuit layer 13, and the inner conductor 14 connects to the second outer conductor 35.
[0098] S5: Please see Figure 13 Remove the first peelable layer 22 and the second peelable layer 32, so that the first carrier copper layer 21 is separated from the first copper layer 23, and the second carrier copper layer 31 is separated from the second copper layer 33.
[0099] In this embodiment, the manufacturing method of the multilayer circuit board 100 further includes the step of:
[0100] S6: Please see Figure 14The first copper layer 23 is etched to form a first outer circuit layer 231, and the second copper layer 33 is etched to form a second outer circuit layer 331. The first outer circuit layer 231 includes a plurality of first ground lines (not shown) arranged side-by-side at intervals. A portion of these first ground lines are connected to the isolation lines of the inner circuit layer 13 via the first outer conductor 26. The second outer circuit layer 331 also includes a plurality of second ground lines (not shown) arranged side-by-side at intervals. These second ground lines are connected to the isolation lines and signal lines of the inner circuit layer 13 via the inner conductor 14 and the second outer conductor 35. The first and second ground lines are used to connect to a reference zero potential point.
[0101] S7: Please see Figure 15 A portion of the first outer insulating layer 24 and a portion of the first outer circuit layer 231 are removed to form a gap 40, through which a portion of the inner circuit layer 13 is exposed.
[0102] S8: Please see Figure 16 A first protective film 42 is provided on the first outer circuit layer 231, and a second protective film 43 is provided on the second outer circuit layer 331 to obtain the multilayer circuit board 100.
[0103] Compared with the prior art, the manufacturing method of the multilayer circuit board 100 provided in this application has the following advantages:
[0104] (i) By setting copper layers (first copper layer 23, second copper layer 33) on the carrier copper layer (first carrier copper layer 21, second carrier copper layer 31), and then pressing the copper layers to both sides of the core board by pressing, and finally removing the carrier copper layer, it is possible to set copper layers with a thickness of 2 to 6 micrometers on both sides of the core board 10. During the pressing process, due to the protection of the carrier copper layer, the copper layer can reduce the problems of pressure points, folds and wrinkles. Furthermore, due to the uniform pressure applied to the carrier copper layer, it is beneficial to improve the flatness of the copper layer.
[0105] (ii) By setting thinner copper layers on both sides of the core board 10, the thickness of the insulation layer (first outer insulation layer and second outer insulation layer) can be increased without changing the total thickness, thereby reducing signal transmission loss and improving signal transmission stability.
[0106] Also see Figure 16This application also provides a multilayer circuit board 100, which includes a core board 10, a first outer side plate (not shown), and a second outer side plate (not shown). The core board 10 includes an inner insulating layer 11 and an inner circuit layer 13 disposed on one side of the inner insulating layer 11. The first outer side plate is disposed on one side of the core board 10, and includes a first outer insulating layer 24 and a first outer circuit layer 231. The first outer insulating layer 24 is disposed between the first outer circuit layer 231 and the inner circuit layer 13. The thickness of the first outer circuit layer 231 is 2 to 6 micrometers. The second outer side plate is disposed on the other side of the core board 10, and includes a second outer insulating layer 34 and a second outer circuit layer 331. The second outer insulating layer 34 is disposed between the second outer circuit layer 331 and the inner insulating layer 11. The thickness of the second outer circuit layer 331 is 2 to 6 micrometers. The total thickness of the multilayer circuit board 100 is 280 to 300 micrometers. The distance between the inner circuit layer 13 and the first outer circuit layer 231 is 120 micrometers.
[0107] In this embodiment, the second outer plate is provided with a notch 40, which penetrates the second outer insulating layer 34 and the second outer circuit layer 331, so that a portion of the inner circuit layer 13 is exposed in the notch 40. The notch 40 can be used to accommodate other electronic components (e.g., chips).
[0108] In this embodiment, the multilayer circuit board 100 further includes a plurality of inner conductors 14, a plurality of first outer conductors 26, and a plurality of second outer conductors 35. The inner conductors 14 are disposed on the inner insulating layer 11, and the first outer conductors 26 are disposed on the first outer insulating layer 24. The second outer conductors 35 are disposed on the second outer insulating layer 34. The inner conductors 14 connect the inner circuit layer 13 and the second outer conductors 35, and the first outer conductors 26 connect the inner circuit layer 13 and the first outer circuit layer 231.
[0109] In this embodiment, the multilayer circuit board 100 further includes a first protective film 42 and a second protective film 43. The first protective film 42 is disposed on the first outer circuit layer 231, and the second protective film 43 is disposed on the second outer circuit layer 331.
[0110] Those skilled in the art should recognize that the above embodiments are merely illustrative of this application and are not intended to limit this application. Any appropriate changes and variations made to the above embodiments within the spirit and essence of this application fall within the scope of this application's disclosure.
Claims
1. A method for manufacturing a multilayer circuit board, characterized in that, Including the following steps: A core board is provided, the core board including an inner insulating layer and an inner circuit layer disposed on one side of the inner insulating layer; A first outer carrier plate is disposed on one side of the core board. The first outer carrier plate includes a first outer insulating layer, a first copper layer, a first peelable layer, and an outer adhesive layer. The first outer insulating layer is disposed between the first copper layer and the inner circuit layer. The first peelable layer is disposed on the side of the first copper layer opposite to the first outer insulating layer. The outer adhesive layer is disposed between the first outer insulating layer and the inner circuit layer. One end of the outer adhesive layer is flush with one end of the first outer insulating layer, and the width of the outer adhesive layer is smaller than the width of the first outer insulating layer. The outer adhesive layer does not completely cover the inner circuit layer, and there is a gap between the inner circuit layer and the first outer insulating layer. A second outer carrier plate is disposed on the other side of the core board. The second outer carrier plate includes a second outer insulating layer, a second copper layer, and a second peelable layer. The second outer insulating layer is disposed between the second copper layer and the inner insulating layer. The second peelable layer is disposed on the side of the second copper layer opposite to the second outer insulating layer. Remove the first peelable layer and the second peelable layer to obtain the multilayer circuit board; A portion of the first copper layer and a portion of the first outer insulating layer corresponding to the gap are removed to form a notch, and a portion of the inner circuit layer is exposed in the notch.
2. The manufacturing method as described in claim 1, characterized in that, It also includes the following steps: Etch the first copper layer to form the first outer circuit layer, and The second copper layer is etched to form the second outer circuit layer.
3. The manufacturing method as described in claim 2, characterized in that, It also includes the following steps: A first protective film is provided on the first outer circuit layer, and A second protective film is provided on the second outer circuit layer.
4. The manufacturing method as described in claim 1, characterized in that, The core board further includes a first adhesive layer and a plurality of inner conductors. The first adhesive layer is disposed on the side of the inner insulating layer away from the inner circuit layer. The inner conductors pass through the first adhesive layer and the inner insulating layer and are connected to the inner circuit layer.
5. The manufacturing method as described in claim 1, characterized in that, The first outer carrier plate also includes a plurality of first outer conductors, which pass through the outer adhesive layer and the first outer insulating layer and are connected to the first copper layer.
6. The manufacturing method as described in claim 1, characterized in that, The second outer carrier plate also includes a plurality of second outer conductors, which pass through the second outer insulating layer and are connected to the second copper layer.