Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the semiconductor device comprises a plurality of transistors which are distributed in different layers and are stacked in a direction perpendicular to a substrate; the word lines penetrate through the transistors of the different layers and extend in the direction perpendicular to the substrate; the back gate electrode penetrates through the different layers and extends along the direction vertical to the substrate; the transistor comprises a semiconductor layer surrounding the side wall of the word line, and a first gate insulating layer arranged between the semiconductor layer and the word line; and the back gate electrode is distributed on the outer side wall of the semiconductor layer and is insulated from the semiconductor layer through a second gate insulating layer. According to the scheme provided by the embodiment of the invention, the vertically stacked semiconductor device with the double-gate structure is provided, and the channel control capability is improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present application provides a semiconductor device and a manufacturing method thereof, and an electronic device.

[0006] The present disclosure provides a semiconductor device, including:

[0007] Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate;

[0008] A word line, passing through the transistors of different layers and extending in a direction perpendicular to the substrate;

[0009] A back gate electrode, penetrating through the different layers and extending in a direction perpendicular to the substrate;

[0010] The transistor includes a semiconductor layer surrounding the side wall of the word line, and a first gate insulating layer arranged between the semiconductor layer and the word line; the back gate electrode is distributed on the outer side walls of the multiple semiconductor layers of the multiple transistors and is insulated from the multiple semiconductor layers by a second gate insulating layer.

[0011] In some embodiments, the transistor also includes a first electrode and a second electrode, the first electrode and the second electrode are distributed on the outer wall of the semiconductor layer and are spaced apart along a first direction parallel to the substrate, and the back gate electrode is distributed in the area between the first electrode and the second electrode on the outer wall of the semiconductor layer.

[0012] In some embodiments, the semiconductor device includes a plurality of the back gate electrodes, and the area between the first electrode and the second electrode on the outer wall of the semiconductor layer includes a first sub-channel region and a second sub-channel region spaced apart along a second direction parallel to the substrate, and one of the back gate electrodes is distributed on the outer wall of the first sub-channel region, and one of the back gate electrodes is distributed on the outer wall of the second sub-channel region.

[0013] In some embodiments, the semiconductor device includes a plurality of the back-gate electrodes, and two of the back-gate electrodes adjacent to the same transistor are distributed on both sides of the transistor and spaced apart along a second direction parallel to the substrate.

[0014] In some embodiments, transistors on the same layer are arrayed along the first direction and the second direction, a back gate electrode is arranged between two adjacent transistors along the second direction, and the back gate electrode is insulated from the semiconductor layers of the two adjacent transistors by a second gate insulation layer connected into an integrated structure.

[0015] In some embodiments, the semiconductor device further includes: a plurality of bit lines distributed in different layers and extending along the second direction, each of the bit lines connecting the second electrodes of transistors in the same layer and in the same column distributed along the second direction; the second gate insulation layer of the integrated structure having a groove with an opening facing away from the bit line, the groove being connected to the side wall of the bit line near the bottom wall of the bit line.

[0016] In some embodiments, a second insulating layer covering the bottom wall of the groove close to the bit line and the back gate electrode is disposed between the bottom wall, and a third insulating layer is disposed between the second insulating layer and the back gate electrode.

[0017] In some embodiments, multiple semiconductor layers of multiple transistors distributed at the same position in different layers are arranged alternately.

[0018] In some embodiments, the semiconductor device further comprises:

[0019] A first insulating layer and a conductive layer are alternately distributed in sequence along a direction vertical to the substrate, and the first electrode and the second electrode are arranged on the conductive layer;

[0020] A hole is formed through each of the first insulating layer and the conductive layer, wherein the semiconductor layer, the first gate insulating layer, and the word line are sequentially distributed in the hole from outside to inside.

[0021] In some embodiments, a diameter of a first sub-hole of the hole corresponding to the conductive layer is larger than a diameter of a second sub-hole corresponding to the first insulating layer.

[0022] In some embodiments, the word line includes a second portion extending along the hole, and a first portion located on a sidewall of each of the first gate insulating layers.

[0023] In some embodiments, a recessed region is formed in a contact region between the semiconductor layer and the first insulating layer, and an isolation layer is disposed in the recessed region. The isolation layer is distributed on a surface of the semiconductor layer and a surface of the first gate insulating layer.

[0024] The present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0025] Providing a substrate, on which a first insulating film and a conductive layer film are alternately deposited in sequence to form a stacked structure including alternately arranged first insulating layers and conductive layers;

[0026] The stacked structure is patterned to form first trenches penetrating each layer, and the conductive layer is configured to form a bit line extending along a second direction, wherein the first trenches extend along the first direction and transistor regions are included between the first trenches;

[0027] forming a second gate insulating layer covering the sidewalls of the first trench;

[0028] A first hole is formed in the transistor region between adjacent first trenches, penetrating the stacked structure in a direction perpendicular to the substrate, the second gate insulating layer is exposed along the sidewall of the first hole in the second direction, a semiconductor layer, a first gate insulating layer, and a word line are sequentially formed in the first hole, and the semiconductor layer is connected to the exposed second gate insulating layer;

[0029] A second hole is formed in the first trench and penetrates the stack structure in a direction perpendicular to the substrate, the second hole exposes the second gate insulating layer, and a back gate electrode filling the second hole is formed in the second hole.

[0030] In some embodiments, forming a second gate insulating layer covering a sidewall of the first trench includes forming a second gate insulating layer covering a sidewall of the first trench and a sidewall of the bit line.

[0031] In some embodiments, the second hole exposing the second gate insulating layer comprises: the second hole exposing the second gate insulating layer on two sidewalls of the first trench oppositely disposed along the second direction, and not exposing the second gate insulating layer covering the sidewalls of the bit line.

[0032] An embodiment of the present disclosure provides an electronic device, comprising the semiconductor device described in any of the above embodiments, or a semiconductor device manufactured according to the semiconductor device manufacturing method described in any of the above embodiments.

[0033] The present application includes a semiconductor device and a manufacturing method thereof, and an electronic device, wherein the semiconductor device includes: a plurality of transistors distributed in different layers and stacked in a direction perpendicular to the substrate; a word line, which penetrates the transistors in different layers and extends in a direction perpendicular to the substrate; a back gate electrode, which penetrates the different layers and extends in a direction perpendicular to the substrate; the transistor includes a semiconductor layer surrounding the sidewall of the word line, and a first gate insulating layer arranged between the semiconductor layer and the word line; the back gate electrode is distributed on the outer sidewall of the semiconductor layer and is insulated from the semiconductor layer by a second gate insulating layer. The solution provided in this embodiment provides a vertically stacked semiconductor device with a dual-gate structure to improve the control capability of the channel. Other features and advantages of the present application will be described in the subsequent description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the description and the drawings.

[0034] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0036] Figure 1A A schematic diagram of a semiconductor device provided for an exemplary embodiment is shown. Figure 1B For along Figure 1A The cross-sectional view along the aa' direction, Figure 1C For along Figure 1A Cross-sectional view along the bb' direction, Figure 1D For along Figure 1A Cross-sectional view along the cc' direction, Figure 1E For along Figure 1A Cross-sectional view along the dd' direction;

[0037] Figure 2 A cross-sectional view along the aa' direction after a stacked structure is formed provided by an exemplary embodiment;

[0038] Figure 3A A cross-sectional view along the aa' direction after forming the first trench provided for an exemplary embodiment, Figure 3B is the cross-sectional view along the bb' direction, Figure 3C is the cross-sectional view along the cc' direction, Figure 3D is the cross-sectional view along the dd' direction, Figure 3E A schematic diagram of a preset electrode pattern of a first conductive layer;

[0039] Figure 4AA cross-sectional view along the aa' direction after forming a second gate insulating layer, a second insulating layer, and a third insulating layer is provided for an exemplary embodiment. Figure 4B is the cross-sectional view along the bb' direction, Figure 4C is the cross-sectional view along the cc' direction, Figure 4D is a cross-sectional view along the dd' direction;

[0040] Figure 5A A cross-sectional view along the aa' direction after the second trench is exposed is provided for an exemplary embodiment. Figure 5B is a cross-sectional view along the bb' direction;

[0041] Fig. 6A A cross-sectional view along the aa' direction after forming a support layer provided by an exemplary embodiment. Figure 6B is the cross-sectional view along the bb' direction, Figure 6C is the cross-sectional view along the cc' direction, Fig.6D is a cross-sectional view along the dd' direction;

[0042] Fig. 7A A cross-sectional view along the aa' direction after forming the third trench provided in an exemplary embodiment, Figure 7B is the cross-sectional view along the bb' direction, Figure 7C is the cross-sectional view along the cc' direction, Fig.7D is a cross-sectional view along the dd' direction;

[0043] Fig. 8A A cross-sectional view along the aa' direction after exposing the first conductive portion located in the capacitor region provided by an exemplary embodiment, Figure 8B is the cross-sectional view along the bb' direction, Figure 8C is the cross-sectional view along the cc' direction, Fig.8D is a cross-sectional view along the dd' direction;

[0044] Fig. 9A A cross-sectional view along the aa' direction after forming a dielectric layer and a second pole according to an exemplary embodiment is provided. Fig. 9B is the cross-sectional view along the bb' direction, Fig. 9C is the cross-sectional view along the cc' direction, Fig.9D is a cross-sectional view along the dd' direction;

[0045] Fig. 10A A cross-sectional view along the aa' direction after forming the fourth trench provided in an exemplary embodiment, Fig. 10B is the cross-sectional view along the bb' direction, Fig. 10C is a cross-sectional view along the cc' direction;

[0046] Fig.11A A cross-sectional view along the aa' direction after forming the first hole provided by an exemplary embodiment, Fig. 11Bis the cross-sectional view along the bb' direction, Fig. 11C is the cross-sectional view along the cc' direction, Fig.11D is a cross-sectional view along the dd' direction;

[0047] Fig. 12A A cross-sectional view along the aa' direction after the first conductive layer is laterally etched according to an exemplary embodiment. Fig. 12B is the cross-sectional view along the bb' direction, Fig. 12C is a cross-sectional view along the cc' direction;

[0048] Fig.13A A cross-sectional view along the aa' direction after forming a semiconductor layer provided by an exemplary embodiment, Fig. 13B is a cross-sectional view along the cc' direction;

[0049] Fig.14A A cross-sectional view along the aa' direction after forming an isolation layer provided by an exemplary embodiment, Fig. 14B is a cross-sectional view along the cc' direction;

[0050] Fig.15A A cross-sectional view along the aa' direction after forming the second part of the word line provided for an exemplary embodiment, Fig. 15B is a cross-sectional view along the cc' direction;

[0051] Fig.16A A cross-sectional view along the bb' direction after forming the second hole provided by an exemplary embodiment, Fig. 16B is a cross-sectional view along the cc' direction;

[0052] Fig.17A A cross-sectional view along the bb' direction after forming a back gate electrode provided by an exemplary embodiment, Fig. 17B It is a cross-sectional view along the cc' direction. DETAILED DESCRIPTION

[0053] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0054] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0055] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0056] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0057] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0058] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0059] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0060] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0061] In the present disclosure, "connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0062] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0063] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0064] In the embodiments of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0065] Figure 1A A schematic diagram of a semiconductor device provided for an exemplary embodiment is shown. Figure 1B For along Figure 1A The cross-sectional view along the aa' direction, Figure 1C For along Figure 1A Cross-sectional view along the bb' direction, Figure 1D For along Figure 1A Cross-sectional view along the cc' direction, Figure 1E For along Figure 1A The cross-sectional view along the dd' direction. Figures 1A to 1E As shown, an embodiment of the present disclosure provides a semiconductor device, which may include a multi-layer memory cell array vertically stacked on a substrate 1, a plurality of word lines 40, and a plurality of back gate electrodes 46. Each layer of the memory cell array may include a plurality of memory cells and a plurality of bit lines 30, and the plurality of memory cells may be distributed in an array along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1.

[0066] The bit lines 30 may be conductive lines extending along the second direction Y, and a plurality of bit lines 30 of the same layer of memory cell arrays may be spaced apart from each other, and the plurality of bit lines 30 may be spaced apart from each other along the first direction X. The bit lines 30 of memory cell arrays of different layers may be stacked on the substrate 1, and the bit lines 30 at the same position of different layers may be spaced apart from each other.

[0067] The word line 40 may extend in a direction perpendicular to the substrate 1. Memory cells at the same position in different layers share one word line 40.

[0068] In some embodiments, the back gate electrode 46 extends in a direction perpendicular to the substrate 1 and may be a linear electrode. However, the embodiments of the present disclosure are not limited thereto, and the back gate electrode 46 may extend in a direction perpendicular to the substrate 1 as a whole, and the local morphology is not limited.

[0069] The memory cell may be applicable to a 1T or 2T memory cell (such as a 2T0C or 2T1C memory cell) or other multi-transistor memory cells.

[0070] Taking a 1T1C memory cell as an example, the memory cell includes a transistor and a capacitor connected to the transistor, and the transistor may include a gate electrode 26, a first electrode 51, and a second electrode 52. The gate electrode 26 may be a part of a word line 40, and the gate electrodes 26 of transistors at the same position in different layers may be different regions of the same word line 40. The capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42. The first electrode 51 may be connected to the first capacitor electrode 41 of the capacitor, and the first electrode 51 and the first capacitor electrode 41 may share one electrode.

[0071] The second electrode 52 may be connected to the bit line 30. The second electrode 52 may be a part of the bit line 30. The second electrodes 52 of the transistors of the memory cells in the same column of the same memory cell array may be connected to the same bit line 30. That is, the second electrodes 52 of the transistors in the same column distributed along the second direction Y are connected to form the bit line 30 extending along the second direction Y.

[0072] The transistor and the capacitor of the same memory cell may be distributed along a first direction X.

[0073] The following description is made by taking a semiconductor device including a plurality of vertically stacked transistors at the same position as an example, and taking a memory cell of 1T1C as an example.

[0074] like Figures 1A to 1E As shown, the present disclosure provides a semiconductor device, including:

[0075] A plurality of transistors are distributed in different layers and stacked in a direction perpendicular to the substrate 1; it can be understood that the plurality of transistors are stacked in a direction perpendicular to the substrate 1 to form a vertical memory cell column, and are insulated from each other in the direction perpendicular to the substrate 1; a word line 40 runs through the transistors in different layers and extends in a direction perpendicular to the substrate 1; a word line 40 is connected to the plurality of transistors;

[0076] A back gate electrode 46, penetrating through the different layers and extending in a direction perpendicular to the substrate 1;

[0077] The transistor includes a semiconductor layer 23 surrounding the side wall of the word line 40, and a first gate insulating layer 24 arranged between the semiconductor layer 23 and the word line 40; the back gate electrode 46 is distributed on the outer side walls of the multiple semiconductor layers 23 of the multiple transistors and is insulated from the multiple semiconductor layers 23 by the second gate insulating layer 27.

[0078] The solution provided in this embodiment can realize a dual-gate transistor by providing a back-gate electrode, thereby improving the control capability of the channel and facilitating the adjustment of the threshold voltage of the transistor.

[0079] In some embodiments, the semiconductor layer 23 may be a full surround type, fully surrounding the sidewall of the word line 40 , that is, a cross section of the semiconductor layer 23 along a direction parallel to the substrate 1 is a closed loop.

[0080] In some embodiments, Figure 1A As shown, the first electrode 51 and the second electrode 52 are distributed on the outer wall of the semiconductor layer 23 and are spaced apart along the first direction X, and the back gate electrode 46 is distributed in the area between the first electrode 51 and the second electrode 52 on the outer wall of the semiconductor layer 23. That is, a part of the outer wall of the semiconductor layer 23 is in contact with the first electrode 51, which is called the first source / drain contact area, and another part of the outer wall is in contact with the second electrode 52, which is called the second source / drain contact area. The area between the first source / drain contact area and the second source / drain area is the channel area, and the back gate electrode 46 can be distributed on the outer wall of the channel area. The channel area can include two parts: a first sub-channel area 231 and a second sub-channel area 232. The first sub-channel area 231 and the second sub-channel area 232 can be spaced apart along the second direction Y, and the back gate electrode 46 can be distributed on the outer wall of the first sub-channel area 231, or the outer wall of the second sub-channel area 232, or the outer wall of the first sub-channel area 231 and the outer wall of the second sub-channel area 232.

[0081] In some embodiments, the semiconductor device includes a plurality of the back-gate electrodes 46, and two of the back-gate electrodes 46 adjacent to the same transistor are distributed on both sides of the transistor and spaced apart along a second direction Y parallel to the substrate. A transistor may be provided with two back-gate electrodes 46, a back-gate electrode 46 is distributed on the outer sidewall of the first sub-channel region 231 of the transistor, and a back-gate electrode 46 is distributed on the outer sidewall of the second sub-channel region 232 of the transistor, and the two back-gate electrodes 46 may be electrically connected to each other. However, the embodiments of the present disclosure are not limited thereto, and a back-gate electrode 46 may be provided only on the outer sidewall of the first sub-channel region 231 or the second sub-channel region 232 of the transistor.

[0082] In some embodiments, a plurality of the back gate electrodes 46 may be connected, may be connected in the peripheral circuit of the memory cell array, or may be connected on the side of the memory cell array facing the substrate 1 (i.e., connected at the bottom of the memory cell array), or may be connected on the side of the memory cell array facing away from the substrate 1 (i.e., connected at the top of the memory cell array).

[0083] In some embodiments, transistors in the same layer are arranged in an array along the first direction X and the second direction Y, and a back gate electrode 46 is disposed between two adjacent transistors along the second direction Y, and the back gate electrode 46 is insulated from the semiconductor layers 23 of the two adjacent transistors by a second gate insulating layer 27 connected to form an integrated structure. Figure 1A As shown, only one back gate electrode 46 is arranged between two adjacent transistors in the same column, that is, the back gate electrode 46 can control the two adjacent transistors, and the back gate electrode 46 and the semiconductor layer 23 of the two adjacent transistors are insulated by the second gate insulation layer 27 of an integrated structure, but the embodiments of the present disclosure are not limited to this, and the second gate insulation layers 27 of two adjacent transistors along the second direction can be manufactured separately. The solution provided in this embodiment can control two transistors by one back gate electrode 46, and the second gate insulation layers of multiple transistors can be manufactured at one time, thereby simplifying the process.

[0084] In some embodiments, two back-gate electrodes 46 may be disposed between two adjacent transistors in the same column, that is, one back-gate electrode 46 may be disposed for each transistor between two adjacent transistors in the same column.

[0085] In some embodiments, the semiconductor device further comprises: a plurality of bit lines 30 distributed in different layers and extending along the second direction Y, each of the bit lines 30 connecting the second electrodes 52 of transistors in the same layer and in the same column distributed along the second direction Y; the second gate insulating layer 27 of the integrated structure has a groove with an opening facing away from the bit line 30, the groove is close to the bottom wall of the bit line 30 and connected to the side wall of the bit line 30. Figure 1A As shown, the second gate insulating layer 27 may form a groove with an opening facing away from the bit line 30, and the bottom wall of the groove is connected to the side wall of the bit line 30. In the solution provided in this embodiment, during the manufacturing process of the semiconductor device, the bit line 30 is usually completed in an earlier step of the manufacturing process of the semiconductor device, and the second gate insulating layer 27 can protect the manufactured bit line 30.

[0086] In some embodiments, a second insulating layer 12 covering the bottom wall is further provided between the bottom wall of the groove and the back gate electrode 46, and a third insulating layer 13 is provided between the second insulating layer 12 and the back gate electrode 46. Low-k insulating materials can be used for the second insulating layer 12 and the third insulating layer 13. The solution provided in this embodiment isolates the bit line and the back gate electrode through the second insulating layer, the third insulating layer and the second gate insulating layer, thereby reducing the parasitic capacitance between the back gate electrode and the bit line.

[0087] In some embodiments, multiple semiconductor layers 23 of multiple transistors distributed at the same position in different layers are arranged at intervals, for example, physically disconnected. The solution provided by this embodiment can eliminate parasitic MOS between layers and reduce leakage.

[0088] In some embodiments, the semiconductor device may further include:

[0089] A first insulating layer and a conductive layer are alternately distributed in sequence along a direction vertical to the substrate 1, and the first electrode 51 and the second electrode 52 are arranged on the conductive layer;

[0090] A hole is formed through each of the first insulating layer and the conductive layer, wherein the semiconductor layer 23, the first gate insulating layer 24, and the word line 40 are sequentially distributed in the hole from the outside to the inside. The solution provided in this embodiment can form the semiconductor layer 23, the gate insulating layer 24, and the word line 40 of multiple transistors in one process, thereby simplifying the process.

[0091] In some embodiments, the aperture of the first sub-aperture of the hole corresponding to the conductive layer is larger than the aperture of the second sub-aperture of the first insulating layer. By setting different apertures in the conductive layer and the first insulating layer, it is convenient to remove the semiconductor layer between the layers inside the hole.

[0092] In some embodiments, Figure 1B As shown, the word line 40 may include a second portion 402 extending along the hole, and a first portion 401 located at the sidewall of each first gate insulating layer 24. That is, the word line 40 includes two portions formed by two manufacturing processes.

[0093] In some embodiments, a recessed area is formed in the contact area between the semiconductor layer 23 and the first insulating layer, and an isolation layer 19 is provided in the recessed area. The isolation layer 19 is distributed on the surface of the semiconductor layer 23 and the surface of the first gate insulating layer 24. The isolation layer 19 can isolate the word line 40 from the semiconductor layer 23 to prevent leakage between the word line 40 and the semiconductor layer 23.

[0094] In some embodiments, along a direction perpendicular to the substrate 1, the first electrode 51 and the second electrode 52 may be located in the same conductive film layer. It can be understood that the first electrode 51 and the second electrode 52 are formed by patterning the same conductive film layer. In some embodiments, the conductive film layer is approximately parallel to the upper surface of the substrate 1. However, the embodiments of the present disclosure are not limited thereto, and the first electrode 51 and the second electrode 52 may be located in different conductive film layers.

[0095] In some embodiments, the second electrode 52 of the transistor may be a part of the bit line 30 connected to the second electrode 52. For example, the bit line 30 is a straight line, and the sidewall of the straight line is connected to the semiconductor layer 23, or the bit line 30 has an integrally designed branch, and the branch is connected to the semiconductor layer 23, wherein the extension direction of the branch intersects with the extension direction of the bit line 30, such as being approximately perpendicular. The branch may be a plurality of branches on one sidewall of the bit line 30, or a plurality of branches on both sidewalls at the same time, and each branch will form a transistor or a storage unit.

[0096] In some embodiments, two adjacent columns of transistors in the same layer may share a bit line 30 .

[0097] In some embodiments, the first electrode 51 may include a first end face facing the word line 40 and a second end face away from the word line 40, as well as a side surface connecting the first end face and the second end face, the first electrode 51 shares the same electrode with the first capacitor electrode 41 of the capacitor, and the second capacitor electrode 42 surrounds the side surface of the first electrode 51.

[0098] In some embodiments, a dielectric layer 43 may be further disposed between the first capacitor electrode 41 and the second capacitor electrode 42 .

[0099] In some embodiments, the semiconductor device may further include: a support layer 45 extending in a direction perpendicular to the substrate 1, the support layer 45 wrapping the second end surface of each first electrode 51, and wrapping the area of ​​the side surface of the first electrode 51 close to the second end surface. The support layer 45 forms a plate-shaped film layer extending in a direction perpendicular to the substrate 1, which can be formed before manufacturing the capacitor to provide support for the subsequent manufacturing process of forming the capacitor. The support layer 45 wraps part of the side surface of the first electrode 51, which can enhance the support performance of the support layer 45.

[0100] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0101] In an exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0102] 1) A first insulating film and a first conductive film are sequentially deposited on a substrate 1 to form a stacked structure, wherein the stacked structure comprises a first insulating layer 9 and a first conductive layer 10 sequentially arranged. Figure 2 As shown, Figure 2 This is a cross-sectional view along the aa' direction after the stacking structure is formed. The cross-sectional views along the bb' direction, the cc' direction and the dd' direction are similar to those along the aa' direction and are omitted here.

[0103] The orthographic projections of the first insulating layer 9 and the first conductive layer 10 in a direction parallel to the substrate 1 overlap.

[0104] In some embodiments, the first insulating film may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K<3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0105] In some embodiments, the first conductive film may be a conductive material as follows:

[0106] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0107] Alternatively, it may be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, conductive metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0108] Alternatively, it may be polysilicon, silicon, germanium, silicon germanium, etc. which are conductive after being doped.

[0109] Figure 2 The stacked structure shown in FIG. 1 includes four first insulating layers 9 and three first conductive layers 10 , which is only an example. In other embodiments, the stacked structure may include more or fewer film layers.

[0110] 2) forming a first trench T1;

[0111] Depositing a first sacrificial layer film to form a first sacrificial layer 11; the first sacrificial layer 11 covers the stacked structure;

[0112] The stacked structure is etched from the top layer to the bottom layer by a dry etching method to form a plurality of first trenches T1 and second trenches T2, wherein the first trenches T1 extend along a first direction X, and the second trenches T2 extend along a second direction Y. Adjacent first trenches T1 include transistor regions 100, and the second trenches T2 space two adjacent groups of memory cells (each two columns of memory cells as a group). The plurality of first trenches T1 and second trenches T2 enable the first conductive layer 10 to form a preset electrode pattern, and the preset electrode pattern may include a first conductive portion 121 and a second conductive portion 122, wherein the first conductive portion 121 may extend along the first direction X, and the second conductive portion 122 may extend along the second direction Y, as shown in FIG. Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E As shown, Figure 3A is a cross-sectional view along the aa' direction after the first trench T1 is formed. Figure 3B It is a cross-sectional view along the bb' direction after the first trench T1 is formed. Figure 3C This is a cross-sectional view along the cc' direction after the first trench T1 is formed. Figure 3D is a cross-sectional view along the dd' direction after the first trench T1 is formed. Figure 3E Schematic diagram of a preset electrode pattern of the first conductive layer 10. The preset electrode pattern is complementary to the pattern of the plurality of first trenches T1, that is, the combination of the preset electrode pattern and the pattern of the first trenches T1 is the shape of the first conductive layer 10 in step 1).

[0113] The first conductive portion 121 may subsequently form a first electrode 51 of a transistor, and the second conductive portion 122 may form a second electrode 52 of a transistor, and further, form a bit line 30 .

[0114] Alternatively, the first conductive portion 121 may subsequently form the first electrode 51 and the second electrode 52 of the transistor, and the second conductive portion 122 may form the bit line 30 .

[0115] Figure 3E The preset electrode pattern shown is only an example, and the preset electrode pattern may be other shapes.

[0116] The first sacrificial film layer may be an insulating film layer different from the first insulating film, including but not limited to silicon nitride (SiN).

[0117] 3) forming a second gate insulating layer 27, a second insulating layer 12, and a third insulating layer 13;

[0118] A second gate insulating film, a second insulating film, and a third insulating film are sequentially deposited on the substrate 1 having the aforementioned structure, and are polished to form a second gate insulating layer 27, a second insulating layer 12, and a third insulating layer 13. Figure 4A , Figure 4B , Figure 4C ,and Figure 4D As shown, Figure 4A is the cross-sectional view along the aa' direction, Figure 4B is the cross-sectional view along the bb' direction, Figure 4C is the cross-sectional view along the cc' direction, Figure 4D is a cross-sectional view along the dd' direction. The third insulating layer 13 fills the first trench T1; the second gate insulating layer 27 covers the bottom wall and side wall of the first trench T1 and the second trench T2, and the second insulating layer covers the second gate insulating layer 27. The second conductive layer 122 forms part of the side wall of the first trench T1, so the second insulating layer 27 and the third insulating layer 13 cover the side wall of the second conductive layer 122, so that the second conductive layer 122 can be protected in the subsequent process, that is, the bit line 30 can be protected. For example, when depositing the third insulating film, a spin coating (SOD) process can be used for deposition, which is a high-temperature process. The second gate insulating layer 27 and the second insulating layer 12 can protect the second conductive portion 122 in this process. In some embodiments, the third insulating layer 13 can be annealed, and the annealing process can make the coated third insulating film dense. When flattening, the second insulating layer 12 is used as a stop layer.

[0119] In some embodiments, the second gate insulating film includes one or more layers of High-K dielectric material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials. The subsequent first gate insulating film is similar and will not be repeated.

[0120] In some embodiments, the third gate insulating film may be a low-K dielectric layer, such as silicon dioxide (SiO 2 ) or the like.

[0121] In some embodiments, the second insulating film may be an insulating material having an etching selectivity ratio with the third insulating film, such as silicon nitride (SiN).

[0122] 4) exposing the second trench T2;

[0123] After forming the third insulating layer 13, dry etching is performed from the top layer to the bottom layer of the stacked structure to remove the second gate insulating layer 27, the second insulating layer 12 and the third insulating layer 13 in the second trench T2;

[0124] The first insulating layer 9 is laterally etched in the second trench T2 to a first preset length to form a plurality of transverse grooves A1, exposing the end surface of the first conductive portion 121 and the sidewall adjacent to the end surface. Figure 5A , Figure 5B As shown, Figure 5A is a cross-sectional view along the aa' direction after the second trench T2 is exposed. Figure 5B It is a cross-sectional view along the bb' direction after the second trench T2 is exposed. The cross-sectional views along the cc' direction and the dd' direction are the same as the previous step and are omitted here. The purpose of the lateral etching is to enhance the supporting performance of the supporting layer 45 formed subsequently. In the bb' direction, the lateral groove A1 forms a hole that penetrates the stacked structure in a direction perpendicular to the substrate, and the hole is connected to the second trench T2;

[0125] In some embodiments, the lateral etching may be performed using vapor phase etching.

[0126] In some embodiments, the ratio of the first preset length to the length of the first conductive layer 10 along the aa′ direction may be less than or equal to 5%.

[0127] 5) forming a support layer 45;

[0128] The forming of the support layer 45 may include: depositing a support layer film in the second trench T2 and the transverse groove A1 to form the support layer 45, wherein the support layer 45 fills the second trench T2 and the transverse groove A1 and wraps the exposed end surface and side wall of the first conductive portion 121;

[0129] The support layer 45 is ground flat so that the support layer 45 is flush with the topmost first insulating layer 9. Fig. 6A , Figure 6B As shown, Fig. 6A is a cross-sectional view along the aa' direction after the support layer 45 is formed. Figure 6B It is a cross-sectional view along the bb' direction after forming the support layer 45. When the support layer 45 is polished, the surface of the topmost first insulating layer 9 away from the substrate 1 is exposed, that is, the first sacrificial layer 11, the second gate insulating layer 27 and the second insulating layer 12 covering the surface of the first insulating layer 9 away from the substrate 1 are removed, and the third insulating layer 13 is flush with the topmost first insulating layer 9.

[0130] In an exemplary embodiment, the support layer film may be an insulating material having an etching selectivity ratio with the third insulating film, such as SiN.

[0131] The support layer 45 can provide support when a capacitor is subsequently formed.

[0132] 6) forming a third trench T3;

[0133] Depositing a fourth insulating film on the substrate 1 forming the above structure to form a fourth insulating layer 14; for example, the fourth insulating film may be deposited by ALD;

[0134] Depositing a first hard mask film to form a first hard mask layer 61;

[0135] The third insulating layer 13 located in the capacitor region 200 is removed by dry etching from the top layer (here, the first hard mask layer 61) of the stacked structure to the bottom layer to form a third trench T3. At this time, there is no third insulating layer 14 between the first conductive portions 121 located in the same layer of the capacitor region 200. Fig. 7A , Figure 7B , Figure 7C and Fig.7D As shown, Fig. 7A is a cross-sectional view along the aa' direction after the third trench T3 is formed. Figure 7B is a cross-sectional view along the bb' direction after the third trench T3 is formed. Figure 7C This is a cross-sectional view along the cc' direction after the third trench T3 is formed. Fig.7DThis is a cross-sectional view along the dd' direction after the third trench T3 is formed. For example, the first hard mask film may be deposited by low pressure chemical vapor deposition (LPCVD).

[0136] In some embodiments, the fourth insulating film may be an insulating film layer different from the first insulating film, such as including but not limited to SiN.

[0137] In some embodiments, the first hard mask layer 61 may include, for example, but is not limited to, polysilicon.

[0138] 7) exposing the first conductive portion 121 located in the capacitor region 200;

[0139] The second gate insulating layer 27 on the side wall of the third trench T3 is removed by etching to expose the first insulating layer 9 covered by the second gate insulating layer 27 ; in some embodiments, the second gate insulating layer 27 may be removed by vapor phase etching;

[0140] The first insulating layer 9 located in the capacitor region 200 is removed by wet lateral etching through the third trench T3 to expose the first conductive portion 121 located in the capacitor region 200 and covered by the first insulating layer 9;

[0141] The first hard mask layer 61 is removed by etching. Fig. 8A , Figure 8B , Figure 8C and Fig.8D As shown, Fig. 8A It is a cross-sectional view along the aa' direction after the first conductive portion 121 located in the capacitor region 200 is exposed. Figure 8B It is a cross-sectional view along the bb' direction after the first conductive portion 121 located in the capacitor region 200 is exposed. Figure 8C It is a cross-sectional view along the cc' direction after the first conductive portion 121 located in the capacitor region 200 is exposed. Fig.8D The cross-sectional view along the dd' direction after exposing the first conductive part 121 located in the capacitor region 200. The exposed portion of the first conductive part 121 can be used as the first electrode 41 of the capacitor, and the dielectric layer 43 and the second electrode 42 can be formed in sequence on the exposed region of the first electrode 41 to complete the manufacturing of the capacitor.

[0142] In some embodiments, the first hard mask layer 61 may be removed by wet etching.

[0143] 8) forming a dielectric layer 43, a second electrode 42, a second conductive layer 7, and a fifth insulating layer 16;

[0144] A dielectric film and a conductor material are sequentially deposited on the substrate 1 forming the above structure to form a dielectric layer 43 and a second electrode 42 respectively, wherein the dielectric layer 43 covers the exposed area of ​​the first conductive layer 10;

[0145] A second conductive film is deposited to form a second conductive layer 7 covering the second electrode 42 and filling the third groove; the second conductive layer 7 is connected to the second electrode 42, and the second conductive layer 7 can be grounded, thereby realizing capacitor grounding.

[0146] The second conductive layer 7 is ground flat, and a fifth insulating film is deposited to form a fifth insulating layer 15, wherein the fifth insulating layer 15 covers the second conductive layer 7. Fig. 9A , Fig. 9B , Fig. 9C and Fig.9D As shown, Fig. 9A It is a cross-sectional view along the aa' direction after the dielectric layer 43 and the second electrode 42 are formed. Fig. 9B is the cross-sectional view along the bb' direction, Fig. 9C is the cross-sectional view along the cc' direction, Fig.9D The fifth insulating layer 15 can be used as a stop layer for subsequently grinding the sixth insulating layer 16 flat.

[0147] The dielectric layer 43 serves as a medium between the capacitor electrodes, and the second electrode 42 serves as an electrode of the capacitor.

[0148] In some embodiments, the dielectric film and the conductor material may be deposited by atomic layer deposition (ALD).

[0149] In some embodiments, the dielectric film may be a High-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0150] In some embodiments, the conductor material includes but is not limited to at least one of the following or a combination thereof:

[0151] Metals or alloys, for example, metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc., and metal alloys containing the aforementioned metals;

[0152] Alternatively, it can be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other metal oxide conductive materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.

[0153] In some embodiments, the second conductive film includes but is not limited to metal, metal alloy, polysilicon, silicon-doped conductive layer, metal oxide conductive layer, such as Poly-GiSe, etc.

[0154] In some embodiments, the fifth insulating film includes but is not limited to SiN.

[0155] The second pole 42 may surround a sidewall of the first conductive portion 121 , and the second pole 42 is insulated from the first conductive portion 121 by the dielectric layer 43 .

[0156] 9) forming a fourth trench T4;

[0157] By using dry etching, the fifth insulating layer 15, the second conductive layer 7, the second electrode 42, the dielectric layer 43 and the fourth insulating layer 14 are etched away in sequence starting from the fifth insulating layer 15 in the area where the transistor area 100 and the second conductive part 122 are located, to form a fourth trench T4; since the word line 40, the gate electrode 26, etc. are to be formed in this area later, the second conductive layer 7 and the second electrode 42 in this area are removed by forming the fourth trench T4 to avoid affecting the transistor.

[0158] A sixth insulating film is deposited on the substrate 1 having the above structure and then ground flat to form a sixth insulating layer 16 filling the fourth trench T4; the sixth insulating layer 16 is flush with the fifth insulating layer 15. Fig. 10A , Fig. 10B , Fig. 10C As shown, Fig. 10A is a cross-sectional view along the aa' direction after the fourth trench T4 is formed. Fig. 10B is the cross-sectional view along the bb' direction, Fig. 10C The cross-sectional view along the cc' direction is the same as the previous step and is omitted here.

[0159] 10) forming a seventh insulating layer 17 and a first hole K1;

[0160] A seventh insulating film is deposited on the substrate having the above structure to form a seventh insulating layer 17 , and the seventh insulating layer 17 covers the fifth insulating layer 15 and the sixth insulating layer 16 ; the seventh insulating layer 17 serves as a stop layer when the word line 40 is subsequently polished.

[0161] The stacked structure is etched by dry etching in the transistor region 100 to form a plurality of first holes K1 penetrating the stacked structure, wherein the sidewalls of the first holes K1 expose each of the first conductive layers 10, and the apertures of the first holes K1 in different layers are substantially consistent, and the first holes K1 do not disconnect the first conductive layer 10, and all regions of the first conductive layer 10 remain connected, such as Fig.11A , Fig. 11B , Fig. 11C and Fig.11D As shown, Fig.11A This is a cross-sectional view along the aa' direction after the first hole K1 is formed. Fig. 11B is the cross-sectional view along the bb' direction, Fig. 11C is the cross-sectional view along the cc' direction, Fig.11D It is a cross-sectional view along the dd' direction. In the subsequent steps, since the capacitor region 200 is not involved, the cross-sectional view along the dd' direction is omitted.

[0162] The first hole K1 may extend in a direction perpendicular to the substrate 1. In some embodiments, the orthographic projection of the first hole K1 on a plane parallel to the substrate 1 may be circular or elliptical, but is not limited thereto, and may be square, hexagonal, or the like.

[0163] In some embodiments, the seventh insulating film includes but is not limited to SiN.

[0164] 11) Laterally etching the first conductive layer 10;

[0165] The lateral etching of the first conductive layer 10 may include: lateral etching of the first conductive layer 10 through the first hole K1 to form a lateral groove A2, that is, at this time, the first hole K1 includes a hole extending in a direction perpendicular to the substrate and the lateral groove A2, and the first insulating layer 9 is almost not affected by the etching, so that on a plane parallel to the substrate 1, the orthographic projection of a first sub-hole K11 of the first hole K1 located in the first insulating layer 9 falls within the orthographic projection of a second sub-hole K12 of the first hole K1 located in the first conductive layer 10, and the first conductive layer 10 forms a first electrode 51 and a second electrode 52 separated from each other, and the first hole K1 exposes the side wall of the second gate insulating layer 27; Fig. 12A , Fig. 12B , Fig. 12C As shown, Fig. 12A is a cross-sectional view along the aa' direction after the first conductive layer 10 is laterally etched. Fig. 12Bis the cross-sectional view along the bb' direction, Fig. 12C It is a cross-sectional view along the cc' direction.

[0166] The plurality of first sub-holes K11 and the plurality of second sub-holes K12 constitute a first hole K1.

[0167] In some embodiments, wet etching can be used to select an acid solution with a high etching selectivity ratio between the first insulating layer 9 and the first conductive layer 10, and the first conductive layer 10 can be laterally etched to a first preset thickness L1 in a direction away from the initial through hole K0. Due to the high etching selectivity, the first insulating layer 9 is almost not etched.

[0168] 12) forming a semiconductor layer 23, a first gate insulating layer 24 and a first portion 401 of a word line 40;

[0169] A semiconductor film and a first gate insulating film are sequentially deposited on the side wall of the first hole K1 to form a semiconductor layer 23 and a first gate insulating layer 24;

[0170] A protective layer film is deposited on the first hole K1 to form a protective layer. The protective layer is used as a protective layer for the semiconductor layer 23 located on the side wall of the first hole K1 in the first conductive layer 10 when the semiconductor layer 23 and the first gate insulating layer 24 located on the side wall of the first hole K1 in the first insulating layer 9 and the seventh insulating layer 17 are subsequently etched;

[0171] The protective layer distributed on the side wall of the first hole K1 located in the first insulating layer 8, the sixth insulating layer 16, and the seventh insulating layer 17, as well as the protective layer located on the surface of the first gate insulating layer 24 away from the substrate, is removed by wet etching. At this time, the protective layer is only distributed on the side wall of the first hole K1 located in the first conductive layer 10;

[0172] The semiconductor layer 23 and the first gate insulating layer 24 distributed on the side walls of the first hole K1 located in the first insulating layer 9, the sixth insulating layer 16, and the seventh insulating layer 17 are removed by wet etching. At this time, the side walls of the first hole K1 located in the first insulating layer 9, the sixth insulating layer 16, and the seventh insulating layer 17 have no semiconductor layer 23 and the first gate insulating layer 24, and the semiconductor layer 23 and the gate insulating layer 24 on the side walls of the first hole K1 located in the first conductive layer 10 are partially etched away to form a lateral recessed area A3. The protective layer is partially etched away in the process, and a part of the protective layer is still retained to cover the first gate insulating layer 24. The retained protective layer serves as the first part 401 of the word line 40, as shown in FIG. Fig.13A and Fig. 13B As shown, Fig.13A is a cross-sectional view along the aa' direction after the semiconductor layer 23 is formed. Fig. 13B This is a cross-sectional view along the cc' direction. For the cross-sectional view along the bb' direction, refer to Fig. 12BIn this embodiment, the semiconductor layer 23 between the layers is removed, thereby eliminating the parasitic MOS tubes between the layers and improving the stability of the device.

[0173] In an exemplary embodiment, the material of the protective layer film may be a conductive material, for example, consistent with the material of the subsequent gate electrode film, so that after etching away the semiconductor layer 23 and the first gate insulating layer 24 on the side wall of the first hole K1 located in the first insulating layer 9 and the seventh insulating layer 17, the protective layer 25 does not need to be removed before depositing the gate electrode film, and the gate electrode film can be directly deposited, and the protective layer and the deposited gate electrode film together serve as the gate electrode of the final device. However, the embodiments of the present disclosure are not limited thereto, and the material of the protective layer film may be inconsistent with the gate electrode film.

[0174] In an exemplary embodiment, the semiconductor film, the gate insulating film and the protective layer film may be deposited by ALD.

[0175] In an exemplary embodiment of the present disclosure, the material of the semiconductor layer 23 may be silicon or polysilicon with a band gap less than 2 eV, or may be a wide band gap material, such as a metal oxide material with a band gap greater than 2 eV.

[0176] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may contain compounds of other elements, such as N, Si, etc., and may contain other small amounts of doping elements.

[0177] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.

[0178] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0179] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0180] In an exemplary embodiment, the protective layer film may be one or more of the following different types of materials:

[0181] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0182] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO), etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0183] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0184] 13) forming an isolation layer 19;

[0185] The forming of the isolation layer 19 may include: depositing an isolation layer film in the first hole K1 to form the isolation layer 19, wherein the isolation layer 19 fills the recessed area A3 to avoid exposing the semiconductor layer 23;

[0186] The isolation layer 19 covering the first portion 401 of the word line facing the first hole K1 is removed by etching. The first portion 401 and the gate electrode film deposited subsequently serve as the word line 40. Therefore, the isolation layer 19 covering the surface of the first portion 401 is removed to avoid affecting the resistance of the word line 40. Fig.14A , Fig. 14B As shown, Fig.14A is a cross-sectional view along the aa' direction after the isolation layer 19 is formed. Fig. 14Bis a cross-sectional view along the cc' direction. The isolation layer 19 can be removed by dry etching. In this embodiment, the isolation layer 19 can isolate the semiconductor layer 23 and the second portion 402 of the word line 40 obtained by subsequent deposition.

[0187] In an exemplary embodiment, the isolation layer film may be deposited by ALD.

[0188] In an exemplary embodiment, the isolation layer film may include but is not limited to silicon oxide, such as SiO2.

[0189] 14) The second portion 402 of the word line 40 is formed.

[0190] The forming of the second portion 402 of the word line 40 may include: depositing a gate electrode film filling the first hole K1 in the first hole K1, grinding to form the second portion 402 of the word line 40, such as Fig.15A , Fig. 15B As shown, Fig.15A is a cross-sectional view along the aa' direction after the second portion 402 of the word line 40 is formed. Fig. 15B is a cross-sectional view along the cc' direction. The second portion 402 of the word line 40 fills the first hole K1. The seventh insulating layer 17 is used as a stop layer during grinding, that is, the surface of the second portion 402 of the word line 40 away from the substrate 1 is flush with the surface of the seventh insulating layer 17 away from the substrate 1. The second portion 402 of the word line 40 and the first portion 401 of the word line 40 (that is, the previously retained protection layer) together form the word line 40.

[0191] In one exemplary embodiment, the gate electrode thin film may be deposited by ALD.

[0192] In an exemplary embodiment, the gate electrode film may be one or more of the following different types of materials:

[0193] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0194] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO), etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0195] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0196] The subsequent back gate electrode film is similar to the gate electrode film and will not be described in detail.

[0197] 15) forming a second hole K2;

[0198] The stacked structure is etched by dry etching in the first trench T1 to form a plurality of second holes K2 penetrating the stacked structure. The second holes K2 are adjacent to the sidewalls of the transistor region 100 to expose the second gate insulating layer 27 (see Fig. 16B , that is, the second hole K2 has two side walls parallel to the first direction X, respectively exposing the second gate insulating layer 27 on the outer side walls of the semiconductor layer 23 of two adjacent transistors in the same column), so that the second gate insulating layer 27 is in contact with the back gate electrode 46, and the side wall of the second hole K2 adjacent to the bit line 30 does not expose the second gate insulating layer 27 (and does not expose the second insulating layer 12, so as to reduce the parasitic capacitance between the bit line 30 and the back gate electrode 46), and the aperture sizes of the second hole K2 in different layers are basically consistent, such as Fig.16A and Fig. 16B As shown, Fig.16A This is a cross-sectional view along the bb' direction after the second hole K2 is formed. Fig. 16B This is a cross-sectional view along the cc' direction. Please refer to the previous step for the cross-sectional view along the aa' direction.

[0199] In some embodiments, the orthographic projection of the second hole K2 on a plane parallel to the substrate 1 is, for example, a square, but the embodiments of the present disclosure are not limited thereto and may be other shapes.

[0200] 16) forming a back gate electrode 46;

[0201] A back gate electrode film is deposited in the second hole K2 to form a back gate electrode 46 filling the second hole K2. Fig.17A and Fig. 17B As shown, Fig.17A is a cross-sectional view along the bb' direction after the back gate electrode 46 is formed. Fig. 17B This is a cross-sectional view along the cc' direction. For the cross-sectional view along the aa' direction, please refer to step 14).

[0202] The present disclosure also provides an electronic device, including the semiconductor device described in any of the above embodiments, or the semiconductor device manufactured by the semiconductor device manufacturing method described in any of the embodiments. The electronic device may be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0203] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: include: Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate; A word line, passing through the transistors of different layers and extending in a direction perpendicular to the substrate; A back gate electrode, penetrating through the different layers and extending in a direction perpendicular to the substrate; The transistor includes a semiconductor layer surrounding a sidewall of the word line, and a first gate insulating layer disposed between the semiconductor layer and the word line; The back gate electrodes are distributed on outer side walls of the semiconductor layers of the transistors and are insulated from the semiconductor layers by a second gate insulating layer.

2. The semiconductor device according to claim 1, wherein: The transistor also includes a first electrode and a second electrode, which are distributed on the outer wall of the semiconductor layer and spaced apart along a first direction parallel to the substrate, and the back gate electrode is distributed in the area between the first electrode and the second electrode on the outer wall of the semiconductor layer.

3. The semiconductor device according to claim 2, characterized in that The semiconductor device includes a plurality of back-gate electrodes, and an area between the first electrode and the second electrode on the outer wall of the semiconductor layer includes a first sub-channel area and a second sub-channel area spaced apart along a second direction parallel to the substrate, and one back-gate electrode is distributed on the outer wall of the first sub-channel area, and one back-gate electrode is distributed on the outer wall of the second sub-channel area.

4. The semiconductor device according to claim 3, characterized in that The transistors in the same layer are arrayed along the first direction and the second direction. A back gate electrode is arranged between two adjacent transistors along the second direction, and the back gate electrode is insulated from the semiconductor layers of the two adjacent transistors by a second gate insulating layer connected into an integrated structure.

5. The semiconductor device according to claim 4, characterized in that The semiconductor device also includes: a plurality of bit lines distributed in different layers and extending along the second direction, each of the bit lines connecting the second electrodes of transistors in the same layer and in the same column distributed along the second direction; the second gate insulating layer of the integrated structure has a groove with an opening facing away from the bit line, and the groove is connected to the side wall of the bit line near the bottom wall of the bit line.

6. The semiconductor device according to claim 5, characterized in that A second insulating layer covering the bottom wall of the groove close to the bit line and the back gate electrode is also arranged between the bottom wall, and a third insulating layer is arranged between the second insulating layer and the back gate electrode.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that: A plurality of semiconductor layers of a plurality of transistors distributed at the same position in different layers are arranged at intervals.

8. The semiconductor device according to any one of claims 2 to 6, characterized in that: The semiconductor device further comprises: A first insulating layer and a conductive layer are alternately distributed in sequence along a direction vertical to the substrate, and the first electrode and the second electrode are arranged on the conductive layer; A hole is formed through each of the first insulating layer and the conductive layer, wherein the semiconductor layer, the first gate insulating layer, and the word line are sequentially distributed in the hole from outside to inside.

9. The semiconductor device according to claim 8, characterized in that The diameter of the first sub-hole of the hole corresponding to the conductive layer is larger than the diameter of the second sub-hole corresponding to the first insulating layer.

10. The semiconductor device according to claim 8, characterized in that The word line includes a second portion extending along the hole, and a first portion located at a sidewall of each of the first gate insulating layers.

11. The semiconductor device according to claim 8, characterized in that A recessed region is formed in a contact region between the semiconductor layer and the first insulating layer. An isolation layer is disposed in the recessed region. The isolation layer is distributed on a surface of the semiconductor layer and a surface of the first gate insulating layer.

12. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, on which a first insulating film and a conductive layer film are alternately deposited in sequence to form a stacked structure including alternately arranged first insulating layers and conductive layers; The stacked structure is patterned to form first trenches penetrating each layer, and the conductive layer is formed into a bit line extending along a second direction, wherein the first trenches extend along the first direction, and transistor regions are included between adjacent first trenches; forming a second gate insulating layer covering the sidewalls of the first trench; A first hole is formed in the transistor region between adjacent first trenches, penetrating the stacked structure in a direction perpendicular to the substrate, the second gate insulating layer is exposed along the sidewall of the first hole in the second direction, a semiconductor layer, a first gate insulating layer, and a word line are sequentially formed in the first hole, and the semiconductor layer is connected to the exposed second gate insulating layer; A second hole is formed in the first trench and penetrates the stack structure in a direction perpendicular to the substrate, the second hole exposes the second gate insulating layer, and a back gate electrode filling the second hole is formed in the second hole.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The forming of the second gate insulating layer covering the sidewall of the first trench includes: forming the second gate insulating layer covering the sidewall of the first trench and the sidewall of the bit line.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The second hole exposing the second gate insulating layer includes: the second hole exposing the second gate insulating layer on two side walls of the first trench opposite to each other along the second direction, and not exposing the second gate insulating layer covering the side wall of the bit line.

15. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device according to any one of claims 1 to 11, or a semiconductor device manufactured according to the semiconductor device manufacturing method according to any one of claims 12 to 14.

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