A semiconductor device and its manufacturing method, and an electronic device.

Abstract

A semiconductor device and its manufacturing method, and an electronic device, are disclosed. The semiconductor device includes: a plurality of transistors stacked in different layers along a direction perpendicular to a substrate; word lines extending through the transistors in the different layers along a direction perpendicular to the substrate; and a back gate electrode extending through the different layers along a direction perpendicular to the substrate. Each transistor includes a semiconductor layer surrounding the sidewalls of the word lines, and a first gate insulating layer disposed between the semiconductor layers and the word lines. The back gate electrode is distributed on the outer sidewalls of the semiconductor layers and insulated from the semiconductor layers by a second gate insulating layer. This embodiment provides a vertically stacked semiconductor device with a dual-gate structure, improving channel control.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a semiconductor device, a method for manufacturing the same, and an electronic device.

[0006] This disclosure provides a semiconductor device, including:

[0007] Multiple transistors are stacked in different layers along the direction perpendicular to the substrate;

[0008] Word lines, which extend through the transistors in the different layers, along a direction perpendicular to the substrate;

[0009] The back gate electrode extends through the different layers along a direction perpendicular to the substrate.

[0010] The transistor includes a semiconductor layer surrounding the word line sidewall, and a first gate insulating layer disposed between the semiconductor layer and the word line; the back gate electrode is distributed on the outer sidewalls of the plurality of semiconductor layers of the plurality of transistors and is insulated from the plurality of semiconductor layers by a second gate insulating layer.

[0011] In some embodiments, the transistor further includes a first electrode and a second electrode, the first electrode and the second electrode being distributed on the outer wall of the semiconductor layer and spaced apart along a first direction parallel to the substrate, and the back gate electrode being distributed on the outer wall of the semiconductor layer in the region between the first electrode and the second electrode.

[0012] In some embodiments, the semiconductor device includes a plurality of back gate electrodes, and the region between the first electrode and the second electrode on the outer wall of the semiconductor layer includes a first sub-channel region and a second sub-channel region spaced apart along a second direction parallel to the substrate, and a back gate electrode is distributed on the outer wall of the first sub-channel region and a back gate electrode is distributed on the outer wall of the second sub-channel region.

[0013] In some embodiments, the semiconductor device includes a plurality of back gate electrodes, with two back gate electrodes adjacent to the same transistor distributed on both sides of the transistor at intervals along a second direction parallel to the substrate.

[0014] In some embodiments, transistors in the same layer are arrayed along a first direction and a second direction, and a back gate electrode is disposed between two adjacent transistors along the second direction. The back gate electrode is insulated from the semiconductor layers of the two adjacent transistors by a second gate insulating layer that is connected to form an integral structure.

[0015] In some embodiments, the semiconductor device further includes: a plurality of bit lines distributed in different layers extending along the second direction, each bit line being connected to a second electrode of a transistor in the same column distributed along the second direction in the same layer; the second gate insulating layer of the integral structure having a groove with an opening opposite to the bit line, the groove being connected to the sidewall of the bit line near the bottom wall of the bit line.

[0016] In some embodiments, a second insulating layer covering the bottom wall is further provided between the groove near the bottom wall of the bit line and the back gate electrode, and a third insulating layer is provided between the second insulating layer and the back gate electrode.

[0017] In some embodiments, multiple semiconductor layers of multiple transistors distributed at the same location on different layers are spaced apart.

[0018] In some embodiments, the semiconductor device further includes:

[0019] A first insulating layer and a conductive layer are alternately distributed along a direction perpendicular to the substrate, and the first electrode and the second electrode are disposed on the conductive layer;

[0020] A hole penetrating each of the first insulating layer and the conductive layer, wherein the semiconductor layer, the first gate insulating layer, and the word line are distributed sequentially from the outside to the inside of the hole.

[0021] In some embodiments, the diameter of the first sub-hole corresponding to the conductive layer is larger than the diameter of the second sub-hole corresponding to the first insulating layer.

[0022] In some embodiments, the word line includes a second portion extending along the hole and a first portion located on the sidewall of each of the first gate insulating layers.

[0023] In some embodiments, a recessed region is formed at the contact area between the semiconductor layer and the first insulating layer, and an isolation layer is disposed in the recessed region. The isolation layer is distributed on the surface of the semiconductor layer and the surface of the first gate insulating layer.

[0024] This disclosure provides a method for manufacturing a semiconductor device, including:

[0025] A substrate is provided, and a first insulating film and a conductive layer film are sequentially and alternately deposited on the substrate to form a stacked structure including the alternating first insulating layer and conductive layer;

[0026] The stacked structure is patterned to form a first trench penetrating each layer, and the conductive layer forms a bit line extending along a second direction, wherein the first trench extends along a first direction and includes a transistor region between the first trenches.

[0027] A second gate insulating layer is formed covering the sidewall of the first trench;

[0028] A first hole is formed in the transistor region between adjacent first trenches, penetrating the stacked structure in a direction perpendicular to the substrate. The first hole exposes the second gate insulating layer along the sidewall of the second direction. A semiconductor layer, a first gate insulating layer, and a word line are sequentially formed in the first hole. The semiconductor layer is connected to the exposed second gate insulating layer.

[0029] A second hole is formed in the first trench, penetrating the stacked structure in a direction perpendicular to the substrate. The second hole exposes the second gate insulating layer, and a back gate electrode is formed in the second hole to fill the second hole.

[0030] In some embodiments, forming a second gate insulating layer covering the sidewalls of the first trench includes: forming a second gate insulating layer covering the sidewalls of the first trench and the sidewalls of the bit line.

[0031] In some embodiments, the second hole exposing the second gate insulating layer includes: the second hole exposing the second gate insulating layer on two sidewalls of the first trench disposed opposite each other in a second direction, and not exposing the second gate insulating layer covering the sidewalls of the bit line.

[0032] This disclosure provides an electronic device, including the semiconductor device described in any of the above embodiments, or a semiconductor device manufactured according to the semiconductor device manufacturing method described in any of the above embodiments.

[0033] This application includes a semiconductor device and a method for manufacturing the same, as well as an electronic device. The semiconductor device includes: a plurality of transistors stacked in different layers along a direction perpendicular to a substrate; word lines extending through the transistors in the different layers along a direction perpendicular to the substrate; and a back gate electrode extending through the different layers along a direction perpendicular to the substrate. Each transistor includes a semiconductor layer surrounding the sidewalls of the word lines, and a first gate insulating layer disposed between the semiconductor layers and the word lines. The back gate electrode is distributed on the outer sidewalls of the semiconductor layers and insulated from the semiconductor layers by a second gate insulating layer. The solution provided in this embodiment offers a vertically stacked semiconductor device with a dual-gate structure, improving channel control. Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the methods described in the description and drawings.

[0034] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0035] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0036] Figure 1A A schematic diagram of a semiconductor device is provided as an exemplary embodiment. Figure 1B For along Figure 1A Cross-sectional view along the aa' direction. Figure 1C For along Figure 1A Cross-sectional view in the bb' direction. Figure 1D For along Figure 1A Cross-sectional view in the cc' direction. Figure 1E For along Figure 1A Cross-sectional view in the dd' direction;

[0037] Figure 2 A cross-sectional view along the aa' direction after forming a stacked structure, provided as an exemplary embodiment;

[0038] Figure 3A A cross-sectional view along the aa' direction after the formation of the first trench, provided as an exemplary embodiment. Figure 3B This is a cross-sectional view along the bb' direction. Figure 3C This is a cross-sectional view along the cc' direction. Figure 3D This is a cross-sectional view along the dd' direction. Figure 3E A schematic diagram of the preset electrode pattern for the first conductive layer;

[0039] Figure 4AA cross-sectional view along the aa' direction after the formation of the second gate insulating layer, the second insulating layer, and the third insulating layer, provided as an exemplary embodiment. Figure 4B This is a cross-sectional view along the bb' direction. Figure 4C This is a cross-sectional view along the cc' direction. Figure 4D This is a cross-sectional view along the dd' direction;

[0040] Figure 5A A cross-sectional view along the aa' direction after exposing the second trench, provided as an exemplary embodiment. Figure 5B This is a cross-sectional view along the bb' direction;

[0041] Figure 6A A cross-sectional view along the aa' direction after the support layer has been formed, provided as an exemplary embodiment. Figure 6B This is a cross-sectional view along the bb' direction. Figure 6C This is a cross-sectional view along the cc' direction. Figure 6D This is a cross-sectional view along the dd' direction;

[0042] Figure 7A A cross-sectional view along the aa' direction after the formation of the third trench, provided as an exemplary embodiment. Figure 7B This is a cross-sectional view along the bb' direction. Figure 7C This is a cross-sectional view along the cc' direction. Figure 7D This is a cross-sectional view along the dd' direction;

[0043] Figure 8A A cross-sectional view along the aa' direction after exposing the first conductive portion located in the capacitor region, provided as an exemplary embodiment. Figure 8B This is a cross-sectional view along the bb' direction. Figure 8C This is a cross-sectional view along the cc' direction. Figure 8D This is a cross-sectional view along the dd' direction;

[0044] Figure 9A A cross-sectional view along the aa' direction after the formation of the dielectric layer and the second electrode, provided as an exemplary embodiment. Figure 9B This is a cross-sectional view along the bb' direction. Figure 9C This is a cross-sectional view along the cc' direction. Figure 9D This is a cross-sectional view along the dd' direction;

[0045] Figure 10A A cross-sectional view along the aa' direction after the formation of the fourth trench, provided as an exemplary embodiment. Figure 10B This is a cross-sectional view along the bb' direction. Figure 10C This is a cross-sectional view along the cc' direction;

[0046] Figure 11A A cross-sectional view along the aa' direction after the formation of the first hole is provided as an exemplary embodiment. Figure 11BThis is a cross-sectional view along the bb' direction. Figure 11C This is a cross-sectional view along the cc' direction. Figure 11D This is a cross-sectional view along the dd' direction;

[0047] Figure 12A A cross-sectional view along the aa' direction after lateral etching of the first conductive layer, provided as an exemplary embodiment. Figure 12B This is a cross-sectional view along the bb' direction. Figure 12C This is a cross-sectional view along the cc' direction;

[0048] Figure 13A A cross-sectional view along the aa' direction after the formation of a semiconductor layer is provided as an exemplary embodiment. Figure 13B This is a cross-sectional view along the cc' direction;

[0049] Figure 14A A cross-sectional view along the aa' direction after the formation of the isolation layer is provided as an exemplary embodiment. Figure 14B This is a cross-sectional view along the cc' direction;

[0050] Figure 15A A cross-sectional view along the aa' direction after the second portion of the formed word line is provided as an exemplary embodiment. Figure 15B This is a cross-sectional view along the cc' direction;

[0051] Figure 16A A cross-sectional view along the bb' direction after the formation of the second hole is provided as an exemplary embodiment. Figure 16B This is a cross-sectional view along the cc' direction;

[0052] Figure 17A A cross-sectional view along the bb' direction after the back gate electrode has been formed, provided as an exemplary embodiment. Figure 17B This is a cross-sectional view along the cc' direction. Detailed Implementation

[0053] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0054] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0055] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0056] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0057] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0058] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0059] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0060] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0061] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0062] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0063] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0064] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0065] Figure 1A A schematic diagram of a semiconductor device is provided as an exemplary embodiment. Figure 1B For along Figure 1A Cross-sectional view along the aa' direction. Figure 1C For along Figure 1A Cross-sectional view in the bb' direction. Figure 1D For along Figure 1A Cross-sectional view in the cc' direction. Figure 1E For along Figure 1A A cross-sectional view along the dd' direction. (e.g.) Figures 1A to 1E As shown, this disclosure provides a semiconductor device, which may include a multilayer memory cell array vertically stacked on a substrate 1, multiple word lines 40, and multiple back gate electrodes 46. Each layer of the memory cell array may include multiple memory cells and multiple bit lines 30, and the multiple memory cells may be distributed in an array along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1.

[0066] The bit line 30 can be a conductive line extending along the second direction Y. Multiple bit lines 30 of the same layer of memory cell array can be spaced apart from each other, and the multiple bit lines 30 can be distributed at intervals along the first direction X. Bit lines 30 of different layers of memory cell array can be stacked on the substrate 1, and bit lines 30 at the same position in different layers are spaced apart from each other.

[0067] The word line 40 can extend along a direction perpendicular to the substrate 1. Memory cells at the same location on different layers share a single word line 40.

[0068] In some embodiments, the back gate electrode 46 extends along a direction perpendicular to the substrate 1 and can be a linear electrode. However, the embodiments disclosed herein are not limited thereto, and the back gate electrode 46 can extend along a direction perpendicular to the substrate 1 as a whole, without limitation on the local morphology.

[0069] The storage unit can be applied to 1T or 2T storage units (such as 2T0C or 2T1C storage units) or other multi-transistor storage units.

[0070] Taking a 1T1C memory cell as an example, the memory cell includes a transistor and a capacitor connected to the transistor. The transistor may include a gate electrode 26, a first electrode 51, and a second electrode 52. The gate electrode 26 may be part of a word line 40, and the gate electrodes 26 of transistors at the same location on different layers may be different regions of the same word line 40. The capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42. The first electrode 51 may be connected to the first capacitor electrode 41 of the capacitor, and the first electrode 51 and the first capacitor electrode 41 may share a single electrode.

[0071] The second electrode 52 can be connected to the bit line 30. The second electrode 52 can be a part of the bit line 30. The second electrodes 52 of transistors in the same column of the same memory cell array can be connected to the same bit line 30. That is, the second electrodes 52 of the transistors in the same column distributed along the second direction Y are connected to form a bit line 30 extending along the second direction Y.

[0072] The transistors and capacitors in the same memory cell can be distributed along a first direction X.

[0073] The following explanation uses a semiconductor device comprising multiple vertically stacked transistors at the same location as an example. The memory cell is 1T1C.

[0074] like Figures 1A to 1E As shown, this disclosure provides a semiconductor device, including:

[0075] Multiple transistors are stacked in different layers along a direction perpendicular to substrate 1; this can be understood as multiple transistors stacked in a direction perpendicular to substrate 1 to form a vertical memory cell column, which are insulated from each other in the direction perpendicular to substrate 1; a word line 40 extends through the transistors in the different layers along a direction perpendicular to substrate 1; a word line 40 is connected to the multiple transistors;

[0076] Back gate electrode 46 extends through the different layers in a direction perpendicular to the substrate 1;

[0077] The transistor includes a semiconductor layer 23 surrounding the sidewall of the word line 40, and a first gate insulating layer 24 disposed between the semiconductor layer 23 and the word line 40; the back gate electrode 46 is distributed on the outer sidewall of the plurality of semiconductor layers 23 of the plurality of transistors and is insulated from the plurality of semiconductor layers 23 by a second gate insulating layer 27.

[0078] The solution provided in this embodiment can realize a dual-gate transistor by setting a back gate electrode, thereby improving the control capability of the channel and facilitating the adjustment of the transistor's threshold voltage.

[0079] In some embodiments, the semiconductor layer 23 can be a fully encircling type, fully encircling the sidewalls of the word line 40, that is, the cross-section of the semiconductor layer 23 along the direction parallel to the substrate 1 is a closed loop.

[0080] In some embodiments, such as Figure 1A As shown, the first electrode 51 and the second electrode 52 are distributed on the outer wall of the semiconductor layer 23 and spaced apart along the first direction X. The back gate electrode 46 is distributed on the outer wall of the semiconductor layer 23 in the region between the first electrode 51 and the second electrode 52. Specifically, a portion of the outer wall of the semiconductor layer 23 contacts the first electrode 51, called the first source / drain contact region, and another portion of the outer wall contacts the second electrode 52, called the second source / drain contact region. The region between the first source / drain contact region and the second source / drain region is the channel region. The back gate electrode 46 can be distributed on the outer wall of the channel region. The channel region can include two parts: a first sub-channel region 231 and a second sub-channel region 232. The first sub-channel region 231 and the second sub-channel region 232 can be spaced apart along the second direction Y. The back gate electrode 46 can be distributed on the outer wall of the first sub-channel region 231, or the outer wall of the second sub-channel region 232, or both.

[0081] In some embodiments, the semiconductor device includes a plurality of back gate electrodes 46, with two back gate electrodes 46 adjacent to the same transistor distributed on both sides of the transistor at intervals along a second direction Y parallel to the substrate. A transistor may have two back gate electrodes 46, with one back gate electrode 46 distributed on the outer wall of the first sub-channel region 231 of the transistor and another back gate electrode 46 distributed on the outer wall of the second sub-channel region 232 of the transistor, and these two back gate electrodes 46 may be electrically connected to each other. However, the embodiments of this disclosure are not limited to this, and the back gate electrode 46 may be provided only on the outer wall of the first sub-channel region 231 or the second sub-channel region 232 of the transistor.

[0082] In some embodiments, the plurality of back gate electrodes 46 may be connected, either in the peripheral circuit of the memory cell array, or on the side of the memory cell array facing the substrate 1 (i.e., at the bottom of the memory cell array), or on the side of the memory cell array away from the substrate 1 (i.e., at the top of the memory cell array).

[0083] In some embodiments, transistors on the same layer are arrayed along a first direction X and a second direction Y. A back gate electrode 46 is disposed between two adjacent transistors along the second direction Y, and the back gate electrode 46 is insulated from the semiconductor layers 23 of the two adjacent transistors by a second gate insulating layer 27 connected to form an integral structure. Figure 1A As shown, only one back gate electrode 46 is provided between two adjacent transistors in the same column. That is, the back gate electrode 46 can control the two adjacent transistors. The back gate electrode 46 is insulated from the semiconductor layer 23 of the two adjacent transistors by a second gate insulating layer 27 with an integral structure. However, the embodiments of this disclosure are not limited to this. The second gate insulating layers 27 of the two adjacent transistors along the second direction can be manufactured separately. The solution provided in this embodiment can control two transistors with one back gate electrode 46 and can manufacture the second gate insulating layers of multiple transistors at one time, thereby simplifying the process.

[0084] In some embodiments, two back gate electrodes 46 may be provided between two adjacent transistors in the same column, that is, one back gate electrode 46 may be provided between each of two adjacent transistors in the same column.

[0085] In some embodiments, the semiconductor device further includes: a plurality of bit lines 30 distributed in different layers extending along the second direction Y, each bit line 30 being connected to the second electrode 52 of a transistor in the same column distributed along the second direction Y in the same layer; the second gate insulating layer 27 of the integral structure having a groove with an opening facing away from the bit lines 30, the groove being connected to the sidewall of the bit line 30 near its bottom wall. Figure 1A As shown, the second gate insulating layer 27 can form a groove with an opening opposite to the bit line 30, and the bottom wall of the groove is connected to the side wall of the bit line 30. In the solution provided in this embodiment, the bit line 30 is typically completed in an earlier step of the semiconductor device manufacturing process, and the second gate insulating layer 27 can protect the completed bit line 30.

[0086] In some embodiments, a second insulating layer 12 covering the bottom wall of the groove and the back gate electrode 46 are further disposed between the second insulating layer 12 and the back gate electrode 46, and a third insulating layer 13 is disposed between the second insulating layer 12 and the back gate electrode 46. The second insulating layer 12 and the third insulating layer 13 can be made of low-k insulating material. The solution provided in this embodiment reduces the parasitic capacitance between the back gate electrode and the bit line by isolating the bit line and the second gate insulating layer through the second insulating layer, the third insulating layer, and the second gate insulating layer.

[0087] In some embodiments, multiple semiconductor layers 23 of multiple transistors distributed at the same location on different layers are spaced apart, for example, physically disconnected. The solution provided by this embodiment can eliminate parasitic MOS between layers and reduce leakage current.

[0088] In some embodiments, the semiconductor device may further include:

[0089] A first insulating layer and a conductive layer are alternately distributed along a direction perpendicular to the substrate 1, and the first electrode 51 and the second electrode 52 are disposed on the conductive layer;

[0090] A hole penetrates each of the first insulating layer and the conductive layer, and the semiconductor layer 23, the first gate insulating layer 24, and the word line 40 are sequentially distributed in the hole from the outside to the inside. The solution provided in this embodiment can form the semiconductor layer 23, the gate insulating layer 24, and the word line 40 of multiple transistors in a single process, simplifying the process.

[0091] In some embodiments, the aperture of the first sub-via corresponding to the conductive layer is larger than the aperture of the second sub-via corresponding to the first insulating layer. By providing different aperture diameters in the conductive layer and the first insulating layer, it is convenient to remove the interlayer semiconductor layer inside the aperture.

[0092] In some embodiments, such as Figure 1B As shown, the word line 40 may include a second portion 402 extending along the hole, and a first portion 401 located on the sidewall of each of the first gate insulating layers 24. That is, the word line 40 includes two portions formed separately by two manufacturing processes.

[0093] In some embodiments, a recessed region is formed at the contact area between the semiconductor layer 23 and the first insulating layer, and an isolation layer 19 is disposed in the recessed region. The isolation layer 19 is distributed on the surface of the semiconductor layer 23 and the surface of the first gate insulating layer 24. The isolation layer 19 can isolate the word line 40 and the semiconductor layer 23 to prevent leakage between the word line 40 and the semiconductor layer 23.

[0094] In some embodiments, the first electrode 51 and the second electrode 52 may be located in the same conductive film layer along a direction perpendicular to the substrate 1. This can be understood as the first electrode 51 and the second electrode 52 being patterned from the same conductive film layer. In some embodiments, the conductive film layer is approximately parallel to the upper surface of the substrate 1. However, the embodiments of this disclosure are not limited thereto, and the first electrode 51 and the second electrode 52 may be located in different conductive film layers.

[0095] In some embodiments, the second electrode 52 of the transistor may be a portion of the bit line 30 to which the second electrode 52 is connected. For example, the bit line 30 may be a straight line with its sidewalls connected to the semiconductor layer 23, or the bit line 30 may have integrally designed branches connected to the semiconductor layer 23, wherein the extension direction of the branches intersects the extension direction of the bit line 30, such as being approximately perpendicular. The branches may be multiple branches on one sidewall of the bit line 30, or multiple branches on both sidewalls simultaneously, each branch corresponding to form a transistor or a memory cell.

[0096] In some embodiments, two adjacent columns of transistors on the same layer may share a single bit line 30.

[0097] In some embodiments, the first electrode 51 may include a first end face facing the word line 40 and a second end face away from the word line 40, as well as a side surface connecting the first end face and the second end face. The first electrode 51 shares the same electrode with the first capacitor electrode 41 of the capacitor, and the second capacitor electrode 42 surrounds the side surface of the first electrode 51.

[0098] In some embodiments, a dielectric layer 43 may be disposed between the first capacitor electrode 41 and the second capacitor electrode 42.

[0099] In some embodiments, the semiconductor device may further include: a support layer 45 extending in a direction perpendicular to the substrate 1, the support layer 45 enclosing a second end face of each of the first electrodes 51, and enclosing a region of the side surface of the first electrode 51 near the second end face. The support layer 45 forms a plate-like film extending in a direction perpendicular to the substrate 1, and can be formed before the manufacture of the capacitor, providing support for the subsequent capacitor manufacturing process. The support layer 45 enclosing a portion of the side surface of the first electrode 51 can enhance the support performance of the support layer 45.

[0100] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of a film layer, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0101] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0102] 1) A first insulating film and a first conductive film are sequentially deposited on a substrate 1 to form a stacked structure, the structure including a first insulating layer 9 and a first conductive layer 10 sequentially disposed, such as... Figure 2 As shown, where, Figure 2 The cross-sectional view along the aa' direction after the stacked structure is formed is shown. The cross-sectional views along the bb', cc', and dd' directions are similar to those along the aa' direction and are omitted here.

[0103] The first insulating layer 9 and the first conductive layer 10 overlap in the orthogonal projection in the direction parallel to the substrate 1.

[0104] In some embodiments, the first insulating film may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2).

[0105] In some embodiments, the first conductive film may be a conductive material as follows:

[0106] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0107] Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0108] Alternatively, it could be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping.

[0109] Figure 2 The stacked structure shown includes four first insulating layers 9 and three first conductive layers 10, which is only an example. In other embodiments, the stacked structure may include more or fewer film layers.

[0110] 2) Form the first trench T1;

[0111] A first sacrificial layer film is deposited to form a first sacrificial layer 11; the first sacrificial layer 11 covers the stacked structure;

[0112] The stacked structure is etched from top to bottom using a dry etching method to form multiple first trenches T1 and second trenches T2. The first trenches T1 extend along a first direction X, and the second trenches T2 extend along a second direction Y. Adjacent first trenches T1 include transistor regions 100, and the second trenches T2 are spaced between two adjacent groups of memory cells (each group consists of two columns of memory cells). The multiple first trenches T1 and second trenches T2 enable the first conductive layer 10 to form a preset electrode pattern. The preset electrode pattern may include a first conductive portion 121 and a second conductive portion 122, wherein the first conductive portion 121 may extend along the first direction X, and the second conductive portion 122 may extend along the second direction Y. Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E As shown, where, Figure 3A This is a cross-sectional view along the aa' direction after the first trench T1 is formed. Figure 3B To form a cross-sectional view along the bb' direction after the first trench T1 is formed, Figure 3C To form a cross-sectional view along the cc' direction after the first trench T1 is formed, Figure 3D To form a cross-sectional view along the dd' direction after the first trench T1 is formed, Figure 3E This is a schematic diagram of the preset electrode pattern of the first conductive layer 10. The preset electrode pattern and the patterns of the plurality of first trenches T1 are complementary, that is, the combination of the preset electrode pattern and the pattern of the first trenches T1 constitutes the shape of the first conductive layer 10 in step 1).

[0113] The first conductive portion 121 can subsequently form the first electrode 51 of the transistor, the second conductive portion 122 can form the second electrode 52 of the transistor, and form the bit line 30.

[0114] Alternatively, the first conductive portion 121 may subsequently form the first electrode 51 and the second electrode 52 of the transistor, and the second conductive portion 122 may form the bit line 30.

[0115] Figure 3E The preset electrode pattern shown is only an example, and the preset electrode pattern can be other shapes.

[0116] The first sacrificial layer film may be an insulating film layer different from the first insulating film, including but not limited to silicon nitride (SiN).

[0117] 3) Form the second gate insulating layer 27, the second insulating layer 12, and the third insulating layer 13;

[0118] A second gate insulating film, a second insulating film, and a third insulating film are sequentially deposited on the substrate 1 on which the aforementioned structure is formed. After polishing, a second gate insulating layer 27, a second insulating layer 12, and a third insulating layer 13 are formed, as follows: Figure 4A , Figure 4B , Figure 4C ,and Figure 4D As shown, where, Figure 4A This is a cross-sectional view along the aa' direction. Figure 4B This is a cross-sectional view along the bb' direction. Figure 4C This is a cross-sectional view along the cc' direction. Figure 4D This is a cross-sectional view along the dd' direction. The third insulating layer 13 fills the first trench T1; the second gate insulating layer 27 covers the bottom and sidewalls of the first trench T1 and the second trench T2, and the second insulating layer covers the second gate insulating layer 27. The second conductive layer 122 forms part of the sidewall of the first trench T1. Therefore, the second insulating layer 27 and the third insulating layer 13 cover the sidewall of the second conductive layer 122, thereby protecting the second conductive layer 122 in subsequent processes, i.e., protecting the bit line 30. For example, when depositing the third insulating film, a spin coating (SOD) process can be used for deposition. This process is a high-temperature process, and the second gate insulating layer 27 and the second insulating layer 12 can protect the second conductive portion 122 during this process. In some embodiments, the third insulating layer 13 can be annealed, which can make the coated third insulating film denser. During grinding, the second insulating layer 12 is used as a stop layer.

[0119] In some embodiments, the second gate insulating film comprises one or more layers of a high-K dielectric material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials. The subsequent description of the first gate insulating film is similar and will not be repeated.

[0120] In some embodiments, the third gate insulating film may be a low-K dielectric layer, such as silicon dioxide (SiO2).

[0121] In some embodiments, the second insulating film may be an insulating material having an etching selectivity ratio with the third insulating film, such as silicon nitride (SiN).

[0122] 4) Expose the second trench T2;

[0123] After the third insulating layer 13 is formed, dry etching is used to etch from the top layer to the bottom layer of the stacked structure to remove the second gate insulating layer 27, the second insulating layer 12 and the third insulating layer 13 in the second trench T2.

[0124] The first insulating layer 9 is laterally etched within the second trench T2 for a first predetermined length, forming multiple lateral grooves A1, exposing the end face of the first conductive portion 121 and the sidewalls adjacent to the end face, such as... Figure 5A , Figure 5B As shown, where, Figure 5A This is a cross-sectional view along the aa' direction after the second trench T2 has been exposed. Figure 5B This is a cross-sectional view along the bb' direction after the second trench T2 has been exposed. Cross-sectional views along the cc' and dd' directions are the same as in the previous step and are omitted here. The purpose of lateral etching is to enhance the support performance of the subsequently formed support layer 45. In the bb' direction, a lateral groove A1 forms a hole that penetrates the stacked structure perpendicular to the substrate direction, and this hole communicates with the second trench T2.

[0125] In some embodiments, lateral etching can be performed using vapor phase etching.

[0126] In some embodiments, the ratio of the first preset length to the length of the first conductive layer 10 along the aa' direction may be less than or equal to 5%.

[0127] 5) Form a support layer 45;

[0128] The formation of the support layer 45 may include: depositing a support layer film in the second trench T2 and the transverse groove A1 to form the support layer 45, wherein the support layer 45 fills the second trench T2 and the transverse groove A1 and wraps the exposed end face and sidewall of the first conductive part 121;

[0129] The support layer 45 is ground flat so that it is flush with the topmost first insulating layer 9, as shown below. Figure 6A , Figure 6B As shown, where, Figure 6A To form a cross-sectional view along the aa' direction after the support layer 45 is formed. Figure 6B This is a cross-sectional view along the bb' direction after the support layer 45 is formed. When the support layer 45 is flattened, the surface of the topmost first insulating layer 9 away from the substrate 1 is exposed. That is, the first sacrificial layer 11, the second gate insulating layer 27, and the second insulating layer 12 covering the surface of the first insulating layer 9 away from the substrate 1 are removed, and the third insulating layer 13 is flush with the topmost first insulating layer 9.

[0130] In an exemplary embodiment, the support layer film may be an insulating material that has an etching selectivity ratio with the third insulating film, such as SiN.

[0131] The support layer 45 can provide support when the capacitor is formed later.

[0132] 6) Formation of the third trench T3;

[0133] A fourth insulating film is deposited on the substrate 1 on which the above structure is formed to form a fourth insulating layer 14; for example, the fourth insulating film can be deposited by ALD.

[0134] Deposit the first hard mask thin film to form the first hard mask layer 61;

[0135] Dry etching is used to etch from the top layer (here referring to the first hard mask layer 61) of the stacked structure to the bottom layer, removing the third insulating layer 13 located in the capacitor region 200 to form the third trench T3. At this time, there is no third insulating layer 14 between the first conductive portions 121 of the same layer in the capacitor region 200. Figure 7A , Figure 7B , Figure 7C and Figure 7D As shown, where, Figure 7A This is a cross-sectional view along the aa' direction after the formation of the third trench T3. Figure 7B This is a cross-sectional view along the bb' direction after the formation of the third trench T3. Figure 7C This is a cross-sectional view along the cc' direction after the formation of the third trench T3. Figure 7DThis is a cross-sectional view along the dd' direction after the formation of the third trench T3. For example, the first hard mask film can be deposited using low-pressure chemical vapor deposition (LPCVD).

[0136] In some embodiments, the fourth insulating film may be an insulating film layer different from the first insulating film, such as including but not limited to SiN.

[0137] In some embodiments, the first hard mask layer 61 may include, but is not limited to, polysilicon.

[0138] 7) Expose the first conductive part 121 located in the capacitor region 200;

[0139] The second gate insulating layer 27 on the sidewall of the third trench T3 is removed by etching, exposing the first insulating layer 9 covered by the second gate insulating layer 27; in some embodiments, the second gate insulating layer 27 can be removed by vapor phase etching.

[0140] The first insulating layer 9 located in the capacitor region 200 is removed by the third trench T3 wet lateral etching, exposing the first conductive part 121 located in the capacitor region 200 that was covered by the first insulating layer 9.

[0141] Etching removes the first hard mask layer 61, as shown Figure 8A , Figure 8B , Figure 8C and Figure 8D As shown, where, Figure 8A A cross-sectional view along the aa' direction after exposing the first conductive portion 121 located in the capacitor region 200. Figure 8B A cross-sectional view along the bb' direction after exposing the first conductive portion 121 located in the capacitor region 200. Figure 8C A cross-sectional view along the cc' direction after exposing the first conductive portion 121 located in the capacitor region 200. Figure 8D This is a cross-sectional view along the dd' direction after exposing the first conductive portion 121 located in the capacitor region 200. The exposed portion of the first conductive portion 121 can serve as the first electrode 41 of the capacitor. Subsequently, a dielectric layer 43 and a second electrode 42 can be sequentially formed on the exposed area of ​​the first electrode 41 to complete the manufacture of the capacitor.

[0142] In some embodiments, the first hard mask layer 61 can be removed by wet etching.

[0143] 8) Form dielectric layer 43, second electrode 42, second conductive layer 7, and fifth insulating layer 16;

[0144] In the substrate 1 that forms the above structure, a dielectric thin film and a conductor material are deposited sequentially to form a dielectric layer 43 and a second electrode 42, respectively. The dielectric layer 43 covers the area exposed by the first conductive layer 10.

[0145] A second conductive film is deposited to form a second conductive layer 7 that covers the second electrode 42 and fills the third trench; the second conductive layer 7 is connected to the second electrode 42 and can be grounded, thereby achieving capacitor grounding.

[0146] The second conductive layer 7 is ground smooth, and a fifth insulating film is deposited to form a fifth insulating layer 15, which covers the second conductive layer 7. Figure 9A , Figure 9B , Figure 9C and Figure 9D As shown, where, Figure 9A This is a cross-sectional view along the aa' direction after the dielectric layer 43 and the second electrode 42 have been formed. Figure 9B This is a cross-sectional view along the bb' direction. Figure 9C This is a cross-sectional view along the cc' direction. Figure 9D This is a cross-sectional view along the dd' direction. The fifth insulating layer 15 can serve as a stop layer for the subsequent grinding of the sixth insulating layer 16.

[0147] In this configuration, dielectric layer 43 serves as the dielectric between capacitor electrodes, and second electrode 42 serves as one electrode of the capacitor.

[0148] In some embodiments, the dielectric film and conductor material can be deposited by atomic layer deposition (ALD).

[0149] In some embodiments, the dielectric film may be a High-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0150] In some embodiments, the conductor material includes, but is not limited to, at least one of the following or a combination thereof:

[0151] Metals or alloys, such as those containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc., or metal alloys containing the aforementioned metals;

[0152] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other conductive metal oxide materials; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.

[0153] In some embodiments, the second conductive film includes, but is not limited to, metal, metal alloy, polycrystalline silicon, silicon-doped conductive layer, and metal oxide conductive layer, such as Poly-GiSe.

[0154] In some embodiments, the fifth insulating film includes, but is not limited to, SiN.

[0155] The second electrode 42 may surround the sidewall of the first conductive part 121, and the second electrode 42 is insulated from the first conductive part 121 through the dielectric layer 43.

[0156] 9) Formation of the fourth trench T4;

[0157] Using dry etching, starting from the fifth insulating layer 15, the second conductive layer 7, the second electrode 42, the dielectric layer 43, and the fourth insulating layer 14 are sequentially etched away in the region where the transistor region 100 and the second conductive portion 122 are located, to form the fourth trench T4. Since word lines 40, gate electrodes 26, etc. will be formed in this region later, the second conductive layer 7 and the second electrode 42 in this region are removed by forming the fourth trench T4 to avoid affecting the transistor.

[0158] A sixth insulating film is deposited on the substrate 1 with the above structure and then polished to form a sixth insulating layer 16 filling the fourth trench T4; the sixth insulating layer 16 is flush with the fifth insulating layer 15, as shown below. Figure 10A , Figure 10B , Figure 10C As shown, where, Figure 10A This is a cross-sectional view along the aa' direction after the fourth trench T4 is formed. Figure 10B This is a cross-sectional view along the bb' direction. Figure 10C This is a cross-sectional view along the cc' direction. The cross-sectional view along the dd' direction is the same as in the previous step and is omitted here.

[0159] 10) Form the seventh insulating layer 17 and the first hole K1;

[0160] A seventh insulating film is deposited on the substrate with the above structure to form a seventh insulating layer 17, which covers the fifth insulating layer 15 and the sixth insulating layer 16; the seventh insulating layer 17 serves as a stop layer for subsequent grinding of the word line 40.

[0161] In transistor region 100, the stacked structure is etched using dry etching to form multiple first holes K1 penetrating the stacked structure. The sidewalls of the first holes K1 expose each of the first conductive layers 10, and the aperture size of the first holes K1 in different layers is substantially the same. Furthermore, the first holes K1 do not disconnect the first conductive layers 10; the entire area of ​​the first conductive layers 10 remains connected. Figure 11A , Figure 11B , Figure 11C and Figure 11D As shown, where, Figure 11A To form a cross-sectional view along the aa' direction after the first hole K1 is formed, Figure 11B This is a cross-sectional view along the bb' direction. Figure 11C This is a cross-sectional view along the cc' direction. Figure 11D This is a cross-sectional view along the dd' direction. In subsequent steps, since the capacitor region 200 is not involved, the cross-sectional view along the dd' direction is omitted.

[0162] The first hole K1 may extend in a direction perpendicular to the substrate 1. In some embodiments, the orthographic projection of the first hole K1 onto a plane parallel to the substrate 1 may be circular or elliptical, but is not limited thereto, and may be square, hexagonal, etc.

[0163] In some embodiments, the seventh insulating film includes, but is not limited to, SiN.

[0164] 11) Laterally etch the first conductive layer 10;

[0165] The lateral etching of the first conductive layer 10 may include: laterally etching the first conductive layer 10 through the first hole K1 to form a lateral groove A2, that is, at this time, the first hole K1 includes a hole extending perpendicular to the substrate direction and the lateral groove A2, the first insulating layer 9 is hardly affected by the etching, such that on a plane parallel to the substrate 1, the orthographic projection of the first hole K1 located in the first sub-hole K11 of the first insulating layer 9 falls into the orthographic projection of the first hole K1 located in the second sub-hole K12 of the first conductive layer 10, and such that the first conductive layer 10 forms a first electrode 51 and a second electrode 52 that are separated from each other, and the first hole K1 exposes the sidewall of the second gate insulating layer 27; Figure 12A , Figure 12B , Figure 12C As shown, where, Figure 12A This is a cross-sectional view along the aa' direction after the first conductive layer 10 has been etched laterally. Figure 12BThis is a cross-sectional view along the bb' direction. Figure 12C This is a cross-sectional view along the cc' direction.

[0166] Multiple first sub-holes K11 and multiple second sub-holes K12 constitute the first hole K1.

[0167] In some embodiments, wet etching can be used, employing an acid solution with a high etching selectivity ratio for the first insulating layer 9 compared to the first conductive layer 10, to laterally etch the first conductive layer 10 to a first predetermined thickness L1 in a direction away from the initial via K0. Due to the high etching selectivity, almost no etching occurs on the first insulating layer 9.

[0168] 12) Forming a semiconductor layer 23, a first gate insulating layer 24, and a first portion 401 of a word line 40;

[0169] A semiconductor thin film and a first gate insulating film are sequentially deposited on the sidewall of the first hole K1 to form a semiconductor layer 23 and a first gate insulating layer 24.

[0170] A protective layer film is deposited in the first hole K1 to form a protective layer. The protective layer serves as a protective layer for the semiconductor layer 23 located on the sidewall of the first hole K1 in the first conductive layer 10 during subsequent etching of the semiconductor layer 23 located on the sidewall of the first hole K1 in the first insulating layer 9 and the seventh insulating layer 17 and the first gate insulating layer 24.

[0171] The protective layer distributed on the sidewalls of the first hole K1 located in the first insulating layer 8, the sixth insulating layer 16, and the seventh insulating layer 17, as well as the protective layer located on the surface of the first gate insulating layer 24 away from the substrate, are removed by wet etching. At this time, the protective layer is only distributed on the sidewalls of the first hole K1 located in the first conductive layer 10;

[0172] The semiconductor layer 23 and the first gate insulating layer 24, located on the sidewalls of the first hole K1 in the first insulating layer 9, the sixth insulating layer 16, and the seventh insulating layer 17, are removed by wet etching. At this time, the sidewalls of the first hole K1 in the first insulating layer 9, the sixth insulating layer 16, and the seventh insulating layer 17 are devoid of the semiconductor layer 23 and the first gate insulating layer 24. A portion of the semiconductor layer 23 and the gate insulating layer 24 on the sidewalls of the first hole K1 in the first conductive layer 10 are etched away, forming a lateral recessed region A3. A portion of the protective layer is etched away during this process, but a portion of the protective layer remains covering the first gate insulating layer 24. The retained protective layer serves as the first part 401 of the word line 40. Figure 13A and Figure 13B As shown, where, Figure 13A This is a cross-sectional view along the aa' direction after the semiconductor layer 23 has been formed. Figure 13B This is a cross-sectional view along the cc' direction. A cross-sectional view along the bb' direction is provided for reference. Figure 12BIn this embodiment, the interlayer semiconductor layer 23 is removed, thereby eliminating parasitic MOS transistors between layers and improving device stability.

[0173] In one exemplary embodiment, the material of the protective layer film can be a conductive material, such as the same material as the subsequent gate electrode film. Therefore, after etching away the semiconductor layer 23 and the first gate insulating layer 24 located on the sidewalls of the first hole K1 in the first insulating layer 9 and the seventh insulating layer 17, the protective layer 25 does not need to be removed before depositing the gate electrode film. The gate electrode film can be deposited directly, and the protective layer and the deposited gate electrode film together serve as the gate electrode of the final device. However, this embodiment is not limited to this; the material of the protective layer film may be different from that of the gate electrode film.

[0174] In an exemplary embodiment, the semiconductor thin film, the gate insulating film, and the protective layer film can be deposited by ALD.

[0175] In an exemplary embodiment of this disclosure, the material of the semiconductor layer 23 may be silicon or polycrystalline silicon with a band gap of less than 2 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 2 eV.

[0176] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0177] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0178] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0179] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0180] In one exemplary embodiment, the protective layer film may be one or more of the following different types of materials:

[0181] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0182] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and aluminum-doped zinc oxide (AZO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0183] Alternatively, it could be polycrystalline silicon, conductive doped semiconductor materials, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; or other materials that exhibit conductivity.

[0184] 13) Form an isolation layer 19;

[0185] The formation of the isolation layer 19 may include: depositing an isolation layer film in the first hole K1 to form an isolation layer 19, wherein the isolation layer 19 fills the recessed region A3 to avoid exposing the semiconductor layer 23;

[0186] The isolation layer 19 covering the first portion 401 of the word line facing the first hole K1 is removed by etching. This first portion 401, together with the subsequently deposited gate electrode film, forms the word line 40. Therefore, the isolation layer 19 covering the surface of the first portion 401 is removed to avoid affecting the resistance of the word line 40. Figure 14A , Figure 14B As shown, where, Figure 14A A cross-sectional view along the aa' direction after the formation of isolation layer 19. Figure 14BThis is a cross-sectional view along the cc' direction. The isolation layer 19 can be removed using dry etching. In this embodiment, the isolation layer 19 can isolate the semiconductor layer 23 and the second portion 402 of the subsequently deposited word line 40.

[0187] In one exemplary embodiment, the isolation layer film can be deposited via ALD.

[0188] In one exemplary embodiment, the insulating layer film may include, but is not limited to, silicon oxides, such as SiO2.

[0189] 14) Form the second part 402 of the character line 40.

[0190] The formation of the second portion 402 of the word line 40 may include: depositing a gate electrode film filling the first hole K1 within the first hole K1, and smoothing out the second portion 402 of the word line 40, as shown below. Figure 15A , Figure 15B As shown, where, Figure 15A This is a cross-sectional view along the aa' direction after the second part 402 of word line 40 is formed. Figure 15B This is a cross-sectional view along the cc' direction. The second portion 402 of the word line 40 fills the first hole K1. During grinding, the seventh insulating layer 17 is used as a stop layer, that is, the surface of the second portion 402 of the word line 40 away from the substrate 1 is flush with the surface of the seventh insulating layer 17 away from the substrate 1. The second portion 402 of the word line 40 and the first portion 401 of the word line 40 (i.e., the previously retained protective layer) together form the word line 40.

[0191] In one exemplary embodiment, the gate electrode film can be deposited by ALD.

[0192] In one exemplary embodiment, the gate electrode thin film may be one or more of the following different types of materials:

[0193] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0194] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and aluminum-doped zinc oxide (AZO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0195] Alternatively, it could be polycrystalline silicon, conductive doped semiconductor materials, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; or other materials that exhibit conductivity.

[0196] The subsequent back gate electrode film is similar to the gate electrode film, and will not be described in detail.

[0197] 15) Form the second hole K2;

[0198] In the first trench T1, the stacked structure is etched using dry etching to form a plurality of second holes K2 penetrating the stacked structure. The second holes K2 expose the second gate insulating layer 27 adjacent to the sidewall of the transistor region 100 (reference). Figure 16B That is, the second hole K2 is parallel to the two sidewalls of the first direction X, exposing the second gate insulating layer 27 on the outer sidewall of the semiconductor layer 23 of two adjacent transistors in the same column, so that the second gate insulating layer 27 contacts the back gate electrode 46, and the sidewall of the second hole K2 adjacent to the bit line 30 does not expose the second gate insulating layer 27 (and does not expose the second insulating layer 12, so as to reduce the parasitic capacitance between the bit line 30 and the back gate electrode 46), and the aperture size of the second hole K2 is basically the same in different layers, such as Figure 16A and Figure 16B As shown, where, Figure 16A To form a cross-sectional view along the bb' direction after forming the second hole K2, Figure 16B This is a cross-sectional view along the cc' direction. For the cross-sectional view along the aa' direction, please refer to the previous step.

[0199] In some embodiments, the orthographic projection of the second hole K2 onto a plane parallel to the substrate 1 is, for example, square, but the embodiments disclosed herein are not limited to this and may be of other shapes.

[0200] 16) Forming the back gate electrode 46;

[0201] A back gate electrode film is deposited within the second hole K2 to form a back gate electrode 46 filling the second hole K2, such as... Figure 17A and Figure 17B As shown, where, Figure 17A To form a cross-sectional view along the bb' direction after forming the back gate electrode 46, Figure 17B This is a cross-sectional view along the cc' direction. For the cross-sectional view along the aa' direction, please refer to step 14).

[0202] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device manufactured by the semiconductor device manufacturing method described in any of the embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0203] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Multiple transistors are stacked in different layers along the direction perpendicular to the substrate; Word lines, which extend through the transistors in the different layers, along a direction perpendicular to the substrate; The back gate electrode extends through the different layers along a direction perpendicular to the substrate. The transistor includes a semiconductor layer surrounding the word line sidewall, and a first gate insulating layer disposed between the semiconductor layer and the word line; The back gate electrode is distributed on the outer wall of the plurality of semiconductor layers of the plurality of transistors and is insulated from the plurality of semiconductor layers by a second gate insulating layer.

2. The semiconductor device according to claim 1, characterized in that, The transistor further includes a first electrode and a second electrode, which are distributed on the outer wall of the semiconductor layer and spaced apart along a first direction parallel to the substrate. The back gate electrode is distributed on the outer wall of the semiconductor layer in the region between the first electrode and the second electrode.

3. The semiconductor device according to claim 2, characterized in that, The semiconductor device includes a plurality of back gate electrodes. The region between the first electrode and the second electrode on the outer wall of the semiconductor layer includes a first sub-channel region and a second sub-channel region spaced apart along a second direction parallel to the substrate. A back gate electrode is distributed on the outer wall of the first sub-channel region and a back gate electrode is distributed on the outer wall of the second sub-channel region.

4. The semiconductor device according to claim 3, characterized in that, Transistors in the same layer are arrayed along a first direction and a second direction. A back gate electrode is disposed between two adjacent transistors along the second direction, and the back gate electrode is insulated from the semiconductor layers of the two adjacent transistors by a second gate insulating layer that is connected to form an integral structure.

5. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes: multiple bit lines distributed in different layers extending along the second direction, each bit line connecting to the second electrode of a transistor in the same column distributed along the second direction in the same layer; the second gate insulating layer of the integral structure has a groove with an opening opposite to the bit line, the groove being close to the bottom wall of the bit line and connected to the side wall of the bit line.

6. The semiconductor device according to claim 5, characterized in that, A second insulating layer covering the bottom wall is provided between the bottom wall of the groove near the bit line and the back gate electrode, and a third insulating layer is provided between the second insulating layer and the back gate electrode.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, Multiple semiconductor layers of transistors located at the same position in different layers are spaced apart.

8. The semiconductor device according to any one of claims 2 to 6, characterized in that, The semiconductor device further includes: A first insulating layer and a conductive layer are alternately distributed sequentially along a direction perpendicular to the substrate, and the first electrode and the second electrode are disposed on the conductive layer; A hole penetrating each of the first insulating layer and the conductive layer, wherein the semiconductor layer, the first gate insulating layer, and the word line are distributed sequentially from the outside to the inside of the hole.

9. The semiconductor device according to claim 8, characterized in that, The diameter of the first sub-hole corresponding to the conductive layer is larger than the diameter of the second sub-hole corresponding to the first insulating layer.

10. The semiconductor device according to claim 8, characterized in that, The word line includes a second portion extending along the hole and a first portion located on the sidewall of each of the first gate insulating layers.

11. The semiconductor device according to claim 8, characterized in that, A recessed region is formed at the contact area between the semiconductor layer and the first insulating layer, and an isolation layer is disposed in the recessed region. The isolation layer is distributed on the surface of the semiconductor layer and the surface of the first gate insulating layer.

12. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, and a first insulating film and a conductive layer film are sequentially and alternately deposited on the substrate to form a stacked structure including the alternating first insulating layer and conductive layer; The stacked structure is patterned to form a first trench penetrating each layer, and the conductive layer forms a bit line extending along a second direction, wherein the first trench extends along a first direction and a transistor region is included between adjacent first trenches. A second gate insulating layer is formed covering the sidewall of the first trench; A first hole is formed in the transistor region between adjacent first trenches, penetrating the stacked structure in a direction perpendicular to the substrate. The first hole exposes the second gate insulating layer along the sidewall of the second direction. A semiconductor layer, a first gate insulating layer, and a word line are sequentially formed in the first hole. The semiconductor layer is connected to the exposed second gate insulating layer. A second hole is formed in the first trench, penetrating the stacked structure in a direction perpendicular to the substrate. The second hole exposes the second gate insulating layer, and a back gate electrode is formed in the second hole to fill the second hole.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The formation of the second gate insulating layer covering the sidewall of the first trench includes: forming a second gate insulating layer covering the sidewall of the first trench and the sidewall of the bit line.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The second hole exposing the second gate insulating layer includes: the second hole exposing the second gate insulating layer on the two sidewalls of the first trench that are disposed opposite each other along the second direction, and not exposing the second gate insulating layer covering the sidewalls of the bit line.

15. An electronic device, characterized in that, This includes the semiconductor device as described in any one of claims 1 to 11, or the semiconductor device manufactured by the semiconductor device manufacturing method according to any one of claims 12 to 14.

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