Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment, and relates to but not limited to the semiconductor technology. The semiconductor device comprises a bit line, a transistor and a capacitor which are arranged on a substrate; the transistor comprises a channel, a first electrode and a second electrode, the first electrode and the second electrode are respectively connected with the channel, the first electrode comprises a first electrode part and a second electrode part, and the first electrode part and the second electrode part are different conductive film layers which are sequentially connected along the direction parallel to the substrate; the first electrode part is connected with the channel, the second electrode part and the first capacitor electrode are of an integrated structure, an insulating layer is arranged on the side wall of the second electrode part, and the insulating layer clamps the second electrode part; therefore, the stability of the first capacitor electrode is improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to but are not limited to semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiment of the present disclosure provides a semiconductor device, comprising: a bit line, a transistor and a capacitor arranged on a substrate;

[0006] The transistor comprises a channel, a first electrode and a second electrode, the first electrode and the second electrode are respectively connected to the channel, the first electrode is connected to the capacitor, and the second electrode is connected to the bit line;

[0007] The capacitor comprises a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, wherein the capacitor dielectric layer is at least arranged between the first capacitor electrode and the second capacitor electrode;

[0008] The first electrode includes a first electrode portion and a second electrode portion, the first electrode portion and the second electrode portion are connected in sequence along a first direction parallel to the substrate, the first electrode portion is connected to the channel, the second electrode portion and the first capacitor electrode are an integrated structure, and a capacitor fixed layer is provided on the side wall of the second electrode portion, and in the first direction, the capacitor fixed layer overlaps with the second electrode portion.

[0009] In some embodiments, the first electrode portion and the second electrode portion are the same conductive film layer sequentially connected along the first direction.

[0010] In some embodiments, the fixed capacitor layer contacts the second electrode portion, and a surface of the fixed capacitor layer contacting the second electrode portion has a roughness greater than a roughness of other surfaces of the fixed capacitor layer.

[0011] In some embodiments, a surface of the fixed capacitor layer in contact with the second electrode portion has a concave-convex structure.

[0012] In some embodiments, the fixed capacitor layer includes an insulating layer, and the insulating layer is located on two opposite sides of the second electrode portion in a direction perpendicular to the substrate.

[0013] In some embodiments, the fixed capacitor layer includes an isolation layer, and the isolation layer is located on two opposite sides of the second electrode portion in a direction parallel to the substrate.

[0014] In some embodiments, the capacitor dielectric layer and the second capacitor electrode are sequentially disposed on an end surface of the capacitor fixed layer away from one end of the bit line.

[0015] In some embodiments, a groove is formed between an end surface of the capacitor fixed layer away from one end of the bit line and a side wall of the adjacent first capacitor electrode, and the capacitor dielectric layer and the second capacitor electrode are sequentially disposed on the inner wall of the groove.

[0016] In some embodiments, a conductive filling layer is further included, at least a portion of which fills the groove and is connected to the second capacitor electrode in the groove.

[0017] In some embodiments, the groove does not overlap with an orthographic projection of the first electrode on the substrate.

[0018] In some embodiments, the second electrode and the bit line are an integrated structure.

[0019] In some embodiments, the transistor further includes a channel, a gate insulating layer, and a gate, the channel surrounds the gate, and the gate insulating layer is disposed between the gate and the channel.

[0020] The present disclosure also provides a method for manufacturing a semiconductor device, including:

[0021] An isolation sacrificial layer and an insulating layer are formed on the substrate, which are alternately arranged in sequence; the isolation sacrificial layer comprises a main structure and a plurality of branches connected to the main structure, wherein the branches extend along a first direction parallel to the substrate;

[0022] etching and removing a portion of each branch to form a fourth groove;

[0023] forming a capacitor electrode film in the fourth groove;

[0024] Etching and removing a portion of the insulating layer to form a sixth groove;

[0025] forming a capacitor dielectric layer and a second capacitor electrode in sequence on the side wall of the capacitor electrode film;

[0026] In the first direction, the portion where the capacitor electrode film overlaps with the second capacitor electrode serves as a first capacitor electrode; and the portion where the capacitor electrode film overlaps with the insulating layer serves as a second electrode portion.

[0027] In some embodiments, forming the fourth groove includes:

[0028] By using an etching process, a third groove extending in a direction perpendicular to the substrate is formed on a side of each branch away from the main structure, wherein the third groove exposes an end surface of each branch away from the main structure;

[0029] A lateral etching process is performed on the exposed end surface of each branch to remove a portion of each branch by etching to form a fourth groove.

[0030] The method for manufacturing a semiconductor device according to claim 13, wherein forming the sixth groove comprises:

[0031] forming a capacitor electrode film in the third groove;

[0032] Using an etching process, etching away the capacitor electrode film in the third groove to form a fifth groove, wherein the fifth groove exposes the insulating layer on the side wall of the capacitor electrode film in the fourth groove;

[0033] A lateral etching process is performed on the exposed insulating layer to remove a portion of the insulating layer by etching to form a sixth groove.

[0034] In some embodiments, a lateral etching depth of the sixth groove is less than a length of the capacitor electrode film in a first direction, and the first direction is the same as a lateral etching direction of the sixth groove.

[0035] An embodiment of the present disclosure also provides an electronic device, comprising any of the semiconductor devices described above.

[0036] In the embodiment of the present disclosure, the second electrode portion of the first electrode and the first capacitor electrode are formed into an integrated structure, and the capacitor fixed layer overlaps with the second electrode portion in the first direction to clamp the side wall of the second electrode portion, thereby improving the stability of the first capacitor electrode and preventing the first capacitor electrode from collapsing by clamping the second electrode portion.

[0037] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The objects and advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description and the drawings.

[0038] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution.

[0040] Figure 1 A schematic cross-sectional view of a semiconductor device along a direction parallel to a substrate provided in some embodiments;

[0041] Figure 2a for Figure 1 Schematic diagram of the semiconductor device in the a-a' direction;

[0042] Figure 2b for Figure 1 A schematic diagram of a semiconductor device in the b-b' direction;

[0043] Figure 2c for Figure 1 A schematic diagram of a semiconductor device in the d-d' direction;

[0044] Figure 2d for Figure 2a A schematic diagram of a semiconductor device in the e-e' direction;

[0045] Figure 3a for Figure 1 A schematic diagram in the direction aa' after forming a first capacitor electrode, a second electrode portion, a capacitor dielectric layer and a second capacitor electrode during the manufacturing process of a semiconductor device;

[0046] Figure 3b for Figure 1 A schematic diagram in the bb' direction after forming a first capacitor electrode, a second electrode portion, a capacitor dielectric layer and a second capacitor electrode in a manufacturing process of a semiconductor device;

[0047] Figure 3c for Figure 1 A schematic diagram in the c-c' direction after forming a first capacitor electrode, a second electrode portion, a capacitor dielectric layer and a second capacitor electrode during the manufacturing process of a semiconductor device;

[0048] Figure 3d for Figure 1 A schematic diagram in the d-d' direction after forming a first capacitor electrode, a second electrode portion, a capacitor dielectric layer and a second capacitor electrode during the manufacturing process of a semiconductor device;

[0049] Figure 4a for Figure 1 A schematic diagram in the a-a' direction after forming an insulating layer and an isolation sacrificial layer in the manufacturing process of a semiconductor device;

[0050] Figure 4b for Figure 1 A schematic diagram in the direction bb' after forming an insulating layer and an isolation sacrificial layer during the manufacturing process of a semiconductor device;

[0051] Figure 4c for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process in the c-c' direction after an insulating layer and an isolation sacrificial layer are formed;

[0052] Figure 4d for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process in the d-d' direction after an insulating layer and an isolation sacrificial layer are formed;

[0053] Figure 5 A schematic cross-sectional view of an isolation sacrificial layer in a semiconductor device provided in some embodiments along a direction parallel to a substrate;

[0054] Figure 6a for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process after forming a first groove and a second groove in the aa' direction;

[0055] Figure 6b for Figure 1 A schematic diagram in the bb' direction after forming a first groove and a second groove in a manufacturing process of a semiconductor device;

[0056] Figure 6c for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process in the c-c' direction after forming a first groove and a second groove;

[0057] Figure 6d for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process in the d-d' direction after forming a first groove and a second groove;

[0058] Figure 7a for Figure 1 A schematic diagram in the a-a' direction after an isolation layer is formed during the manufacturing process of a semiconductor device;

[0059] Figure 7b for Figure 1 A schematic diagram in the direction bb' after an isolation layer is formed during the manufacturing process of a semiconductor device;

[0060] Figure 7c for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process in the c-c' direction after an isolation layer is formed;

[0061] Figure 7d for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process of the semiconductor device in the d-d' direction after an isolation layer is formed;

[0062] Figure 8a for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process in the direction a-a' after a third groove is formed;

[0063] Figure 8b for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process after a third groove is formed in the bb' direction;

[0064] Figure 9a for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process after a fourth groove is formed in the aa' direction;

[0065] Figure 9b for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process of the semiconductor device in the d-d' direction after a fourth groove is formed;

[0066] Fig.10a for Figure 1 A schematic diagram in the a-a' direction after a capacitor electrode film is formed in the manufacturing process of a semiconductor device;

[0067] Fig.10b for Figure 1 A schematic diagram in the direction b-b' after a capacitor electrode film is formed in the manufacturing process of a semiconductor device;

[0068] Fig.10c for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process in the d-d' direction after a capacitor electrode film is formed;

[0069] Fig.11a for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process after a fifth groove is formed in the a-a' direction;

[0070] Fig.11b for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process after a fifth groove is formed in the bb' direction;

[0071] Fig.12a for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process after a sixth groove is formed in the aa' direction;

[0072] Figure 12b for Figure 1 A schematic diagram of a semiconductor device in the manufacturing process after a sixth groove is formed in the bb' direction;

[0073] Fig.12c for Figure 1A schematic diagram of a semiconductor device in the manufacturing process after a sixth groove is formed in the d-d' direction. DETAILED DESCRIPTION

[0074] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0075] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by one of ordinary skill in the art to which the present invention belongs.

[0076] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and size ratios of the components in the drawings belong to preferred embodiments. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0077] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0078] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0079] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0080] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0081] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0082] In the present disclosure, "electrical connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0083] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0084] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0085] The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0086] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0087] The embodiment of the present disclosure provides a semiconductor device, comprising: a bit line, a transistor and a capacitor arranged on a substrate;

[0088] The transistor comprises a channel, a first electrode and a second electrode, the first electrode and the second electrode are respectively connected to the channel, the first electrode is connected to the capacitor, and the second electrode is connected to the bit line;

[0089] The capacitor comprises a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, wherein the capacitor dielectric layer is at least arranged between the first capacitor electrode and the second capacitor electrode;

[0090] The first electrode includes a first electrode portion and a second electrode portion, the first electrode portion and the second electrode portion are different conductive film layers connected in sequence along a direction parallel to the substrate, the first electrode portion is connected to the channel, the second electrode portion and the first capacitor electrode are an integrated structure, and an insulating layer is provided on the side wall of the second electrode portion, and the insulating layer clamps the second electrode portion.

[0091] The memory disclosed in the present invention is described below by way of some exemplary embodiments.

[0092] Figure 1 A schematic cross-sectional view of a semiconductor device provided in some embodiments along a direction parallel to the substrate. Figure 1 As shown, the semiconductor device may include: a word line, a bit line 3, a transistor 1 and a capacitor 2 arranged on a substrate 102. In one embodiment, a semiconductor device containing only a transistor 1 and a capacitor 2 forms a 1T1C structure; the transistor 1 is connected to the bit line 3 and the capacitor 2 respectively, and the word line is connected to the gate of the transistor 1. The capacitor in this application can be understood as a capacitor. Among them, Figure 1 No word lines are shown.

[0093] In some embodiments, a word line may extend in a direction perpendicular to the substrate and be connected to gates of a plurality of transistors stacked in a direction perpendicular to the substrate, and the plurality of transistors may share the word line.

[0094] In some embodiments, the bit line may extend in a direction parallel to the substrate and be connected to electrodes of transistors located in the same layer. Transistors in the same layer may share the bit line.

[0095] Figure 2a for Figure 1 Schematic diagram of the semiconductor device in the a-a' direction; Figure 2b for Figure 1 A schematic diagram of a semiconductor device in the b-b' direction; Figure 2c for Figure 1 Schematic diagram of a semiconductor device in the d-d' direction. In some embodiments, Figure 2a , Figure 2b and Figure 2cAs shown, the transistor includes a gate 23, a gate insulating layer 24, a channel 25, and a first electrode 21 and a second electrode 22 respectively connected to the channel 25. The first electrode 21 and the second electrode 22 are respectively located on opposite sides of the channel 25 in a direction parallel to the substrate 102, and are connected through the channel 25. The first electrode 21 is located on the side of the channel 25 away from the bit line 3; the second electrode 22 is located on the side of the channel close to the bit line 3. The second electrode 22 and the bit line 3 can include different materials respectively, and the second electrode 22 can also be connected to the bit line 3 as a whole and include the same material. Among them, the channel 25 between the first electrode 21 and the second electrode 22 is a horizontal channel.

[0096] In some embodiments, the first electrode 21 includes a first electrode portion 211 and a second electrode portion 212 connected in sequence along a direction parallel to the substrate. The first electrode portion 211 is located on a side of the second electrode portion 212 away from the capacitor, and the first electrode portion 211 is in a strip shape extending along a direction parallel to the substrate. The first end of the first electrode portion 211 is connected to the first end of the channel 25, and the second end of the first electrode portion 211 is connected to the first end of the second electrode portion 212.

[0097] In some embodiments, the second electrode portion 212 is located on the side of the first electrode portion 211 close to the capacitor, and the second electrode portion 212 is in the shape of a strip extending in a direction parallel to the substrate. The second electrode portion 212 includes a surface close to the first electrode portion 211 and a surface away from the first electrode portion 211 and other surfaces, and the other surfaces include the side wall of the second electrode portion. The first end of the second electrode portion 212 is connected to the second end of the first electrode portion 211, and the second end of the second electrode portion 212 is connected to the first capacitor electrode 71 of the capacitor.

[0098] In some embodiments, the first electrode portion 211 and the second electrode portion 212 are different conductive film layers sequentially arranged along a direction parallel to the substrate.

[0099] In some embodiments, the second electrode portion 212 and the first capacitor electrode 71 of the capacitor are an integrated structure and include the same conductive material, that is, the second electrode portion 212 and the first capacitor electrode 71 of the capacitor are formed by the same conductive film layer.

[0100] In some embodiments, the first electrode portion and the second electrode portion are the same conductive film layer connected in sequence along the first direction. This arrangement can simplify the process, so that the first electrode and the first capacitor electrode are integrally arranged, while ensuring the stability of the first capacitor electrode.

[0101] In some embodiments, the first electrode portion 211 , the second electrode portion 212 , and the first capacitor electrode 71 include the same conductive material.

[0102] In some embodiments, a fixed capacitor layer is disposed on the sidewall of the first electrode 21, and the fixed capacitor layer includes an insulating layer 41, and the insulating layer 41 is located on two opposite sides of the first electrode 21 in a direction perpendicular to the substrate. The insulating layer 41 is at least located on two opposite sides of the second electrode portion 212 of the first electrode 21 in a direction perpendicular to the substrate, and in the first direction D1, the insulating layer 41 overlaps with the second electrode portion 212, clamping the second electrode portion 212.

[0103] The semiconductor device of the embodiment of the present application makes the second electrode portion 212 of the first electrode 21 and the first capacitor electrode 71 an integrated structure, and then sets a capacitor fixing layer on the side wall of the second electrode portion 212 to clamp the side wall of the second electrode portion 212, thereby improving the stability of the first capacitor electrode 71 by clamping the second electrode portion 212 and preventing the first capacitor electrode 71 from collapsing.

[0104] In some embodiments, the fixed capacitor layer contacts the second electrode portion 212, and the roughness of the surface of the fixed capacitor layer contacting the second electrode portion 212 is greater than the roughness of other surfaces of the fixed capacitor layer. The above arrangement can enhance the bonding force between the fixed capacitor layer and the second electrode portion 212 and ensure the stability of the first capacitor electrode.

[0105] In some embodiments, the surface of the capacitor fixed layer in contact with the second electrode portion has a concave-convex structure. The concave-convex structure of the capacitor fixed layer and the concave-convex structure of the second electrode portion interlock with each other, which can enhance the bonding force between the capacitor fixed layer and the second electrode portion 212 and ensure the stability of the first capacitor electrode.

[0106] Figure 2d for Figure 2a Schematic diagram of a semiconductor device in the e-e' direction. In some embodiments, as Figure 2d As shown, the capacitor fixed layer includes an isolation layer 61 , which is located on opposite sides of the second electrode portion 212 in a direction parallel to the substrate, clamping the second electrode portion 212 of the first electrode 21 , thereby improving the stability of the first capacitor electrode 71 .

[0107] In some embodiments, the second electrode 22 and the bit line 3 are an integrated structure and include the same conductive material, that is, the second electrode 22 and the bit line 3 are formed by the same conductive film layer.

[0108] In some embodiments, the second electrode 22 and the bit line 3 are different regions of an integrated structure extending in a direction parallel to the substrate. One end of the integrated structure is connected to the second end of the channel.

[0109] In some embodiments, the gate 23 and the word line 4 are an integrated structure.

[0110] In some embodiments, the channel 25 surrounds the gate 23, and the channel 25 extends along the sidewall of the gate 23 to form a ring extending in a direction perpendicular to the substrate. The film thickness direction of the channel 25 is parallel to the substrate.

[0111] Wherein, the channel surrounding the gate can be understood as the channel partially or completely surrounding the gate. In some embodiments, the surrounding can be completely surrounded as a whole, and the cross section of the channel after the surrounding is a closed ring. The interception direction of the cross section is intercepted along the direction parallel to the substrate. In some embodiments, the surrounding can be partially surrounded, and the cross section after the surrounding is not closed, but presents a ring shape. For example, a ring with an opening.

[0112] In some embodiments, a gate insulating layer 24 is disposed between the gate 23 and the channel 25 .

[0113] In some embodiments, the capacitor includes a first capacitor electrode 71 , a second capacitor electrode 72 , and a capacitor dielectric layer 73 . The first capacitor electrode 71 and the second electrode portion 212 of the first electrode 21 are an integrated structure and include the same conductive material.

[0114] In some embodiments, at least a portion of the second capacitor electrode 72 surrounds the sidewall of the first capacitor electrode 71 via the capacitor dielectric layer 73 , and covers an end surface of the first capacitor electrode 71 away from the channel 25 .

[0115] In some embodiments, the capacitor dielectric layer 73 is at least disposed between the first capacitor electrode 71 and the second capacitor electrode 72 .

[0116] In some embodiments, a capacitor dielectric layer 73 and a second capacitor electrode 72 are sequentially disposed on an end surface of the capacitor fixed layer away from the word line.

[0117] In some embodiments, a groove is formed between the end surface of the capacitor fixed layer away from one end of the word line and the side wall of the adjacent first capacitor electrode 71, and the capacitor dielectric layer 73 and the second capacitor electrode 72 are sequentially arranged on the inner wall of the groove.

[0118] In some embodiments, the groove does not overlap with the orthographic projection of the first electrode 21 on the substrate.

[0119] In some embodiments, the capacitor further includes a conductive filling layer 74, the second capacitor electrode 72 is a film structure, and at least a portion of the conductive filling layer 74 fills the groove and is connected to the second capacitor electrode 72 in the groove. At least a portion of the conductive filling layer 74 is located on a side of the first capacitor electrode 71 away from the channel. The material of the conductive filling layer 74 may include germanium-doped polysilicon.

[0120] In some embodiments, the conductive filling layer 74 does not overlap with the orthographic projection of the first electrode 21 on the substrate.

[0121] In some embodiments, in a direction perpendicular to the substrate, the second capacitor electrodes 72 of the capacitors at different layers may be connected to form an integrated structure, that is, the capacitors at different layers share the same second capacitor electrode 72 .

[0122] In some embodiments, in a direction perpendicular to the substrate, the capacitor dielectric layers 73 of the capacitors at different layers may be connected into an integrated structure, that is, the capacitors at different layers share the same capacitor dielectric layer 73 .

[0123] The technical solution of this embodiment is further explained below through the manufacturing process of the memory of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" also requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0124] In this embodiment, each layer includes a plurality of storage units, but the embodiments of the present disclosure are not limited thereto, and each layer may include one storage unit.

[0125] In some embodiments, the semiconductor device may be any of the semiconductor devices described above, and the manufacturing process of the semiconductor device may include:

[0126] Step 101: forming an insulating layer and an isolation sacrificial layer.

[0127] Forming an insulating layer and an isolation sacrificial layer: forming a buffer layer 101 on a substrate 102; then, forming an isolation sacrificial layer 42 and an insulation layer 41 alternately deposited in sequence on the buffer layer 101 to form a stacked structure; then, patterning and etching the stacked structure through a mask to form a plurality of grooves vertical to the substrate, wherein each layer of the insulation layer 41 forms a first patterned structure stacked on each other and distributed in sequence, and each layer of the isolation sacrificial layer 42 forms a second patterned structure stacked on each other and distributed in sequence; then, etching the stacked structure through dry etching to form a plurality of through holes penetrating the plurality of isolation sacrificial layers 42 and the plurality of insulation layers 41, wherein the side walls of the through holes expose the side walls of each isolation sacrificial layer 42 and each insulation layer 41; finally, forming a sacrificial layer 43 in the plurality of through holes, such as Figure 4a , Figure 4b , Figure 4c and Figure 4d shown.

[0128] In some embodiments, in the subsequent process of forming a transistor, the isolation sacrificial layer 42 and the sacrificial layer 43 are first etched away, and then the first electrode, the second electrode and the bit line of the transistor are formed in the area where the isolation sacrificial layer 42 is etched away; then, the channel, the gate insulation layer and the gate of the transistor are sequentially formed on the side walls of the through hole.

[0129] In some embodiments, the material of the insulating layer 41 may be silicon oxide, and the material of the isolation sacrificial layer 42 may be silicon nitride.

[0130] In some embodiments, the orthographic projection of the through hole on a plane parallel to the substrate may be a square or the like.

[0131] In some embodiments, the insulating layer and the isolation sacrificial layer may be deposited using a chemical vapor deposition method.

[0132] In some embodiments, the substrate may be a semiconductor substrate, such as a silicon substrate. Of course, it may be any substrate that plays a supporting role, not just a base, but may be a substrate formed by peripheral circuits on the substrate.

[0133] In some embodiments, the insulating layer serves to isolate devices and may be a low-K dielectric layer, ie, a dielectric layer with a dielectric constant K<3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2).

[0134] Figure 5 A schematic cross-sectional view of an isolation sacrificial layer in a semiconductor device provided in some embodiments along a direction parallel to the substrate. Figure 5As shown, the second patterned structure formed by each layer of isolation sacrificial layer 42 includes a main structure 422 and a plurality of branches 421 connected to the main structure 422. The main structure 422 is in a strip shape and extends along the second direction D2; each branch 421 is in a strip shape and extends along the first direction D1, the first end of each branch 421 is connected to the main structure 422, and the second end of each branch 421 extends along the first direction D1. The plurality of branches 421 are arranged at intervals along the second direction D2 on the main structure 422, and the plurality of branches 421 are located on the same side of the main structure 422. The first direction D1 and the second direction D2 are both parallel to the upper surface of the substrate, and the first direction D1 and the second direction D2 intersect, and for example, the first direction D1 and the second direction D2 are perpendicular.

[0135] In some embodiments, in the subsequent process of forming a transistor, the main structure 422 and the multiple branches 421 are first etched away; then, a bit line is formed in the area where the main structure 422 is etched away, and a first electrode and a second electrode are formed in the area where the multiple branches 421 are etched away.

[0136] In some embodiments, each branch 421 is provided with a through hole K, and the through hole K is located at a portion of the branch 421 close to the bit line 3 .

[0137] Step 102: forming a first groove and a second groove.

[0138] The first groove and the second groove are formed by: on the basis of the substrate having the aforementioned pattern, etching away the stacked structure on opposite sides of the first direction D1 by an etching process to form a first groove 51 extending in a direction perpendicular to the substrate, and etching away the insulating layer 41 on opposite sides of each branch 421 in a second direction D2 to form a second groove 52 extending in a direction perpendicular to the substrate, wherein the bottoms of the first groove 51 and the second groove 52 both extend to the surface of the buffer layer 101, and then, wet cleaning is performed, such as Figure 6a , Figure 6b , Figure 6c and Figure 6d As shown, in the cross section parallel to the substrate direction, the first groove 51 is in the shape of a strip extending along the second direction D2, and the second groove 52 is in the shape of a strip extending along the first direction D1.

[0139] Step 103: forming an isolation layer.

[0140] The formation of the isolation layer includes: on the basis of the substrate formed with the aforementioned pattern, depositing an isolation material in the first groove and the second groove, so that the isolation material forms an isolation layer 61, and then performing a grinding process on the isolation layer 61, such as Figure 7a , Figure 7b , Figure 7c and Figure 7dAs shown. The isolation layer 61 may be made of silicon nitride. The insulating layer 41 and the isolation layer 61 form a fixed capacitor layer.

[0141] Step 104: forming a third groove.

[0142] The third groove is formed by etching away the isolation layer on the capacitor side of each branch 421 on the basis of the substrate having the aforementioned pattern, to form a third groove 53 extending in a direction perpendicular to the substrate, wherein the bottom of the third groove 53 extends to the surface of the buffer layer 101, and the third groove 53 exposes an end surface of each branch 421 away from the sacrificial layer 43, and then, wet cleaning is performed, such as Figure 8a and Figure 8b As shown, in the cross section parallel to the substrate direction, the third groove 53 is in the shape of a strip extending along the second direction D2.

[0143] Step 105: forming a fourth groove.

[0144] The fourth groove is formed by performing a lateral etching process on the exposed end surface of each branch 421 on the basis of the substrate having the aforementioned pattern, etching away a portion of each branch 421 to form a fourth groove 54, and retaining a portion of each branch 421 close to the sacrificial layer 43, such as Figure 9a and Figure 9b The first end of the fourth groove 54 is connected to the retained branch 421 , and the fourth groove 54 extends along the first direction D1 and is connected to the third groove 53 .

[0145] In some embodiments, the length of the fourth groove 54 in the first direction D1 is greater than the length of a first capacitor electrode subsequently formed in the semiconductor device in the first direction D1.

[0146] Step 106, forming a capacitor electrode film.

[0147] The formation of the capacitor electrode film includes: on the basis of the substrate formed with the aforementioned pattern, depositing a conductive material in the third groove 53 and the fourth groove 54, so that the conductive material forms a capacitor electrode film 70, the capacitor electrode film 70 fills the third groove 53 and the fourth groove 54, and the capacitor electrode film 70 is connected to the reserved branch 421, such as Fig.10a , Fig.10b and Fig.10c As shown, the conductive material may be titanium nitride.

[0148] Step 107: forming a fifth groove.

[0149] The fifth groove is formed by: forming an insulating layer 41 and an isolating sacrificial layer 42 on the side of the stacked structure away from the substrate on the basis of the substrate having the aforementioned pattern, wherein the isolating sacrificial layer 42 is located on the side of the insulating layer 41 away from the substrate; then, using an etching process, etching away the capacitor electrode film 70 located in the third groove to form a fifth groove 55, retaining the capacitor electrode film 70 located in the fourth groove, and the fifth groove 55 exposes the insulating layer 41 and the isolating layer 61 located on the side wall of the retained capacitor electrode film 70, and then, using a wet cleaning method, such as Fig.11a and Fig.11b As shown, the third direction D3 is a direction perpendicular to the substrate.

[0150] Step 108 , forming a sixth groove.

[0151] The sixth groove is formed by: performing a lateral etching process on the exposed sidewalls of the insulating layer 41 and the isolation layer 61 on the substrate having the aforementioned pattern, etching away a portion of the insulating layer 41 and the isolation layer 61 located on the sidewall of the retained capacitor electrode film 70, and forming a sixth groove 56, wherein the sixth groove 56 surrounds the sidewall of the retained capacitor electrode film 70, and the sixth groove 56 is in a ring shape extending along the first direction D1, and the sixth groove 56 exposes the sidewall of the retained capacitor electrode film 70; retaining a portion of the insulating layer 41 and the isolation layer 61 on the sidewall of the capacitor electrode film 70, such as Fig.12a , Figure 12b and Fig.12c shown.

[0152] In some embodiments, the depth of the lateral etching of the sixth groove 56 is less than the length of the capacitor electrode film 70 in the first direction D1, and the first direction D1 is the same as the direction of the lateral etching of the sixth groove 56, that is, the length of the sixth groove 56 in the first direction D1 is less than the length of the retained capacitor electrode film 70 in the first direction D1.

[0153] Step 109 , forming a first capacitor electrode, a second electrode portion, a capacitor dielectric layer and a second capacitor electrode.

[0154] The formation of the first capacitor electrode, the second electrode portion, the capacitor dielectric layer and the second capacitor electrode comprises: on the basis of the substrate having the aforementioned pattern, using an atomic deposition process, sequentially forming a capacitor dielectric layer 73 and a second capacitor electrode 72 on the sidewall of the exposed capacitor electrode film 70, then depositing a conductive filling layer 74 in the sixth groove and the fifth groove, the conductive filling layer 74 filling the sixth groove and the fifth groove, and finally, performing a grinding process on the conductive filling layer 74, such as Figure 3a , Figure 3b , Figure 3c and Figure 3d shown.

[0155] In some embodiments, the capacitor electrode film forms a first capacitor electrode 71 and a second electrode portion 212, the first capacitor electrode 71 and the second capacitor electrode 72 are arranged opposite to each other, the second electrode portion 212 is arranged opposite to the insulating layer, and the orthographic projections of the second electrode portion 212 and the second capacitor electrode 72 on the substrate do not overlap.

[0156] In some embodiments, the capacitor fixed layer formed by the insulating layer 41 and the isolation layer 61 can clamp the second electrode portion 212. The method for manufacturing a semiconductor device according to an embodiment of the present application clamps the second electrode portion 212 through the capacitor fixed layer, thereby improving the stability of the first capacitor electrode.

[0157] In some embodiments, the capacitor dielectric layer 73 may be made of a high-K dielectric material, that is, a dielectric material with a dielectric constant K≥3.9. The high-K dielectric material may include but is not limited to at least one of the following: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.

[0158] In some embodiments, the second capacitor electrode 72 may be made of titanium nitride.

[0159] In some embodiments, the conductive filling layer 74 may be made of polysilicon doped with chromium (Ge).

[0160] Step 110 , forming a first electrode, a second electrode, a channel, a gate insulating layer and a gate.

[0161] The formation of the first electrode, the second electrode, the channel, the gate insulating layer and the gate includes: on the basis of the substrate formed with the aforementioned pattern, etching away the sacrificial layer and the isolation sacrificial layer, forming the first electrode portion 211 of the first electrode 21 of the transistor, the second electrode 22 and the bit line 3 in the region where the isolation sacrificial layer is etched away; the first electrode portion 211 of the first electrode 21 is connected to the second electrode portion 212 in the first electrode 21, and the second electrode 22 is connected to the bit line 3 as a whole; then, in the region (through hole) where the sacrificial layer is etched away, the channel 25, the gate insulating layer 24 and the gate 23 are sequentially formed, as shown in FIG. Figure 2a shown.

[0162] The solution provided in this embodiment simplifies the process flow, is easy to implement, improves production efficiency, and has the advantages of easy process implementation, low production cost, and high yield rate.

[0163] The present disclosure also provides a method for manufacturing a semiconductor device, comprising:

[0164] An isolation sacrificial layer and an insulating layer are formed on the substrate, which are alternately arranged in sequence; the isolation sacrificial layer comprises a main structure and a plurality of branches connected to the main structure;

[0165] By using an etching process, a third groove extending in a direction perpendicular to the substrate is formed on a side of each branch away from the main structure, wherein the third groove exposes an end surface of each branch away from the main structure;

[0166] Performing a lateral etching process on the exposed end surface of each branch to remove a portion of each branch by etching to form a fourth groove, and retaining a portion of each branch;

[0167] forming a capacitor electrode film in the third groove and the fourth groove;

[0168] Using an etching process, etching away the capacitor electrode film in the third groove to form a fifth groove, wherein the fifth groove exposes the insulating layer on the side wall of the capacitor electrode film in the fourth groove;

[0169] Performing a lateral etching process on the exposed insulating layer to remove a portion of the insulating layer by etching to form a sixth groove, and retaining a portion of the insulating layer to be disposed on the side wall of the capacitor electrode film, wherein the sixth groove exposes the side wall of the capacitor electrode film;

[0170] Using an atomic deposition process, a capacitor dielectric layer and a second capacitor electrode are sequentially formed on the exposed side wall of the capacitor electrode film; a portion of the capacitor electrode film opposite to the second capacitor electrode forms a first capacitor electrode, and a portion of the capacitor electrode film opposite to the insulating layer forms a second electrode portion;

[0171] Each branch is removed by etching, and a first electrode portion and a second electrode are formed in a region where each branch is removed by etching, and the first electrode portion is connected to the second electrode portion to form a first electrode.

[0172] In some embodiments, a lateral etching depth of the sixth groove is less than a length of the capacitor electrode film in a first direction, and the first direction is the same as a lateral etching direction of the sixth groove.

[0173] The present disclosure also provides an electronic device, including the semiconductor device described in any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0174] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: include: A bit line, a transistor and a capacitor are disposed on a substrate; The transistor comprises a channel, a first electrode and a second electrode, the first electrode and the second electrode are respectively connected to the channel, the first electrode is connected to the capacitor, and the second electrode is connected to the bit line; The capacitor comprises a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, wherein the capacitor dielectric layer is at least arranged between the first capacitor electrode and the second capacitor electrode; The first electrode includes a first electrode portion and a second electrode portion, the first electrode portion and the second electrode portion are connected in sequence along a first direction parallel to the substrate, the first electrode portion is connected to the channel, the second electrode portion and the first capacitor electrode are an integrated structure, and a capacitor fixed layer is provided on the side wall of the second electrode portion, and in the first direction, the capacitor fixed layer overlaps with the second electrode portion.

2. The semiconductor device according to claim 1, wherein: The first electrode portion and the second electrode portion are the same conductive film layer sequentially connected along the first direction.

3. The semiconductor device according to claim 1, wherein: The fixed capacitor layer contacts the second electrode portion, and a surface of the fixed capacitor layer contacting the second electrode portion has a roughness greater than a roughness of other surfaces of the fixed capacitor layer.

4. The semiconductor device according to claim 1, wherein: A surface of the fixed capacitance layer in contact with the second electrode portion has a concavo-convex structure.

5. The semiconductor device according to claim 1, wherein: The fixed capacitance layer includes an insulating layer, and the insulating layer is located at two opposite sides of the second electrode portion in a direction perpendicular to the substrate.

6. The semiconductor device according to claim 1, wherein: The fixed capacitance layer includes an isolation layer, and the isolation layer is located on two opposite sides of the second electrode portion in a direction parallel to the substrate.

7. The semiconductor device according to claim 1, wherein: The capacitor dielectric layer and the second capacitor electrode are sequentially arranged on an end surface of the capacitor fixed layer away from one end of the bit line.

8. The semiconductor device according to claim 1, wherein: A groove is formed between the end surface of the capacitor fixed layer away from one end of the bit line and the side wall of the adjacent first capacitor electrode, and the capacitor dielectric layer and the second capacitor electrode are sequentially arranged on the inner wall of the groove.

9. The semiconductor device according to claim 8, characterized in that It also includes a conductive filling layer, at least a portion of which fills the groove and is connected to the second capacitor electrode in the groove.

10. The semiconductor device according to claim 8, characterized in that The groove does not overlap with an orthographic projection of the first electrode on the substrate.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that: The second electrode and the bit line are an integrated structure.

12. The semiconductor device according to any one of claims 1 to 10, characterized in that: The transistor further includes a channel, a gate insulating layer and a gate, wherein the channel surrounds the gate and the gate insulating layer is disposed between the gate and the channel.

13. A method for manufacturing a semiconductor device, characterized in that: include: forming an isolation sacrificial layer and an insulating layer alternately arranged in sequence on the substrate; The isolation sacrificial layer comprises a main structure and a plurality of branches connected to the main structure, wherein the branches extend along a first direction parallel to the substrate; etching and removing a portion of each branch to form a fourth groove; forming a capacitor electrode film in the fourth groove; Etching and removing a portion of the insulating layer to form a sixth groove; forming a capacitor dielectric layer and a second capacitor electrode in sequence on the side wall of the capacitor electrode film; In the first direction, the portion where the capacitor electrode film overlaps with the second capacitor electrode serves as a first capacitor electrode; and the portion where the capacitor electrode film overlaps with the insulating layer serves as a second electrode portion.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: Forming the fourth groove includes: By using an etching process, a third groove extending in a direction perpendicular to the substrate is formed on a side of each branch away from the main structure, wherein the third groove exposes an end surface of each branch away from the main structure; A lateral etching process is performed on the exposed end surface of each branch to remove a portion of each branch by etching to form a fourth groove.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: Forming the sixth groove includes: forming a capacitor electrode film in the third groove; Using an etching process, etching away the capacitor electrode film in the third groove to form a fifth groove, wherein the fifth groove exposes the insulating layer on the side wall of the capacitor electrode film in the fourth groove; A lateral etching process is performed on the exposed insulating layer to remove a portion of the insulating layer by etching to form a sixth groove.

16. The method for manufacturing a semiconductor device according to claim 13, wherein: The lateral etching depth of the sixth groove is less than the length of the capacitor electrode film in the first direction, and the first direction is the same as the lateral etching direction of the sixth groove.

17. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 12.

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