Semiconductor devices and their manufacturing methods, electronic devices

Abstract

A semiconductor device and its manufacturing method, and an electronic device, relating to but not limited to semiconductor technology, are disclosed. The semiconductor device includes: bit lines, a transistor, and a capacitor disposed on a substrate; the transistor includes a channel, a first electrode, and a second electrode, the first electrode and the second electrode being respectively connected to the channel; the first electrode includes a first electrode portion and a second electrode portion, the first electrode portion and the second electrode portion being different conductive film layers sequentially connected along a direction parallel to the substrate; the first electrode portion is connected to the channel; the second electrode portion and the first capacitor electrode are integrally structured; an insulating layer is disposed on the sidewall of the second electrode portion, the insulating layer clamping the second electrode portion; thereby improving the stability of the first capacitor electrode.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a semiconductor device, including: a bit line, a transistor, and a capacitor disposed on a substrate;

[0006] The transistor includes a channel, a first electrode, and a second electrode. The first electrode and the second electrode are respectively connected to the channel. The first electrode is connected to the capacitor, and the second electrode is connected to the bit line.

[0007] The capacitor includes a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode, wherein the capacitor dielectric layer is disposed at least between the first capacitor electrode and the second capacitor electrode.

[0008] The first electrode includes a first electrode portion and a second electrode portion, which are sequentially connected along a first direction parallel to the substrate. The first electrode portion is connected to the channel, and the second electrode portion and the first capacitor electrode are integrally formed. A capacitor fixing layer is provided on the sidewall of the second electrode portion, and the capacitor fixing layer overlaps with the second electrode portion in the first direction.

[0009] In some embodiments, the first electrode portion and the second electrode portion are the same conductive film layer connected sequentially along the first direction.

[0010] In some embodiments, the capacitor fixing layer is in contact with the second electrode portion, and the roughness of the surface of the capacitor fixing layer in contact with the second electrode portion is greater than the roughness of the other surfaces of the capacitor fixing layer.

[0011] In some embodiments, the surface of the capacitor fixing layer that contacts the second electrode portion has an uneven structure.

[0012] In some embodiments, the capacitor fixing layer includes an insulating layer located on opposite sides of the second electrode portion in a direction perpendicular to the substrate.

[0013] In some embodiments, the capacitor fixing layer includes an isolation layer located on opposite sides of the second electrode portion in a direction parallel to the substrate.

[0014] In some embodiments, the capacitor dielectric layer and the second capacitor electrode are sequentially disposed on the end face of the capacitor fixing layer away from the bit line.

[0015] In some embodiments, a groove is formed between the end face of the capacitor fixing layer away from the bit line and the sidewall of the adjacent first capacitor electrode, and the capacitor dielectric layer and the second capacitor electrode are sequentially disposed on the inner wall of the groove.

[0016] In some embodiments, a conductive filler layer is further included, which at least partially fills the groove and is connected to a second capacitor electrode within the groove.

[0017] In some embodiments, the groove does not overlap with the orthographic projection of the first electrode onto the substrate.

[0018] In some embodiments, the second electrode and the bit line are an integral structure.

[0019] In some embodiments, the transistor further includes a channel, a gate insulating layer, and a gate, the channel surrounding the gate and the gate insulating layer disposed between the gate and the channel.

[0020] This disclosure also provides a method for manufacturing a semiconductor device, comprising:

[0021] An isolation sacrificial layer and an insulating layer are formed alternately on a substrate; the isolation sacrificial layer includes a main structure and a plurality of branches connected to the main structure, the branches extending along a first direction parallel to the substrate;

[0022] A portion of each branch is etched away to form a fourth groove;

[0023] A capacitor electrode film is formed within the fourth groove;

[0024] A portion of the insulating layer is etched away to form a sixth groove;

[0025] A capacitor dielectric layer and a second capacitor electrode are sequentially formed on the sidewall of the capacitor electrode film.

[0026] In the first direction, the portion where the capacitor electrode film overlaps with the second capacitor electrode serves as the first capacitor electrode; the portion where the capacitor electrode film overlaps with the insulating layer serves as the second electrode portion.

[0027] In some embodiments, forming the fourth groove includes:

[0028] An etching process is used to form a third groove extending along a direction perpendicular to the substrate on the side of each branch away from the main structure. The third groove exposes the end face of each branch away from the main structure.

[0029] A transverse etching process is performed on the end face of each exposed branch to remove a portion of each branch, forming a fourth groove.

[0030] The method for manufacturing a semiconductor device according to claim 13, characterized in that forming the sixth groove includes:

[0031] A capacitor electrode film is formed within the third groove;

[0032] An etching process is used to etch away the capacitor electrode film located in the third groove to form a fifth groove, which exposes the insulating layer on the sidewall of the capacitor electrode film located in the fourth groove.

[0033] A lateral etching process is performed on the exposed insulating layer to remove a portion of it, forming the sixth groove.

[0034] In some embodiments, the depth of the lateral etching of the sixth groove is less than the length of the capacitor electrode film in a first direction, which is the same as the direction of the lateral etching of the sixth groove.

[0035] This disclosure also provides an electronic device, including any of the semiconductor devices described above.

[0036] This embodiment of the invention integrates the second electrode portion of the first electrode with the first capacitor electrode, and further, by having the capacitor fixing layer overlap with the second electrode portion in the first direction, clamps the sidewall of the second electrode portion, thereby improving the stability of the first capacitor electrode and preventing the first capacitor electrode from collapsing.

[0037] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description and the drawings.

[0038] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0039] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of the present invention and do not constitute a limitation on the technical solutions.

[0040] Figure 1 A schematic cross-sectional view of a semiconductor device along a direction parallel to the substrate, provided for some embodiments;

[0041] Figure 2a for Figure 1 A schematic diagram of a semiconductor device in the a-a' direction;

[0042] Figure 2b for Figure 1 A schematic diagram of a semiconductor device in the b-b' direction;

[0043] Figure 2c for Figure 1 A schematic diagram of a semiconductor device in the d-d' direction;

[0044] Figure 2d for Figure 2a A schematic diagram of a semiconductor device in the e-e' direction;

[0045] Figure 3a for Figure 1 A schematic diagram in the a-a' direction after the formation of the first capacitor electrode, the second electrode portion, the capacitor dielectric layer, and the second capacitor electrode during the manufacturing process of a semiconductor device;

[0046] Figure 3b for Figure 1 A schematic diagram in the b-b' direction after the formation of the first capacitor electrode, the second electrode portion, the capacitor dielectric layer, and the second capacitor electrode during the manufacturing process of a semiconductor device.

[0047] Figure 3c for Figure 1 A schematic diagram in the c-c' direction after the first capacitor electrode, the second electrode portion, the capacitor dielectric layer, and the second capacitor electrode are formed during the manufacturing process of a semiconductor device.

[0048] Figure 3d for Figure 1 A schematic diagram in the d-d' direction after the formation of the first capacitor electrode, the second electrode portion, the capacitor dielectric layer, and the second capacitor electrode during the manufacturing process of a semiconductor device;

[0049] Figure 4a for Figure 1 A schematic diagram in the a-a' direction after the formation of the insulating layer and the isolation sacrificial layer during the manufacturing process of a semiconductor device;

[0050] Figure 4b for Figure 1 A schematic diagram in the b-b' direction after the formation of the insulating layer and the isolation sacrificial layer during the manufacturing process of a semiconductor device;

[0051] Figure 4c for Figure 1 A schematic diagram in the c-c' direction after the formation of the insulating layer and the isolation sacrificial layer during the manufacturing process of a semiconductor device;

[0052] Figure 4d for Figure 1 A schematic diagram in the d-d' direction after the formation of the insulating layer and the isolation sacrificial layer during the manufacturing process of a semiconductor device;

[0053] Figure 5 A schematic cross-sectional view of an isolation sacrificial layer in a semiconductor device provided for some embodiments, along a direction parallel to the substrate;

[0054] Figure 6a for Figure 1 A schematic diagram in the a-a' direction after the formation of the first and second grooves during the manufacturing process of a semiconductor device;

[0055] Figure 6b for Figure 1 A schematic diagram in the b-b' direction after the formation of the first and second grooves during the manufacturing process of a semiconductor device;

[0056] Figure 6c for Figure 1 A schematic diagram in the c-c' direction after the first and second grooves are formed during the manufacturing process of a semiconductor device;

[0057] Figure 6d for Figure 1 A schematic diagram in the d-d' direction after the formation of the first and second grooves during the manufacturing process of a semiconductor device;

[0058] Figure 7a for Figure 1 A schematic diagram of the semiconductor device after the isolation layer is formed in the a-a' direction during the manufacturing process;

[0059] Figure 7b for Figure 1 A schematic diagram in the b-b' direction after the isolation layer is formed during the manufacturing process of a semiconductor device;

[0060] Figure 7c for Figure 1 A schematic diagram of the semiconductor device after the isolation layer is formed in the c-c' direction during the manufacturing process;

[0061] Figure 7d for Figure 1 A schematic diagram in the d-d' direction after the isolation layer is formed during the manufacturing process of a semiconductor device;

[0062] Figure 8a for Figure 1 A schematic diagram in the a-a' direction after the third groove is formed during the manufacturing process of a semiconductor device;

[0063] Figure 8b for Figure 1 A schematic diagram in the b-b' direction after the third groove is formed during the manufacturing process of a semiconductor device;

[0064] Figure 9a for Figure 1 A schematic diagram in the a-a' direction after the fourth groove is formed during the manufacturing process of a semiconductor device;

[0065] Figure 9b for Figure 1 A schematic diagram in the d-d' direction after the fourth groove is formed during the manufacturing process of a semiconductor device;

[0066] Figure 10a for Figure 1 A schematic diagram of the capacitor electrode thin film formed in the a-a' direction during the manufacturing process of semiconductor devices;

[0067] Figure 10b for Figure 1 A schematic diagram in the b-b' direction after the capacitor electrode thin film is formed during the manufacturing process of a semiconductor device;

[0068] Figure 10c for Figure 1 A schematic diagram in the d-d' direction after the capacitor electrode thin film is formed during the manufacturing process of a semiconductor device;

[0069] Figure 11a for Figure 1 A schematic diagram in the a-a' direction after the fifth groove is formed during the manufacturing process of a semiconductor device;

[0070] Figure 11b for Figure 1 A schematic diagram in the b-b' direction after the fifth groove is formed during the manufacturing process of a semiconductor device;

[0071] Figure 12a for Figure 1 A schematic diagram in the a-a' direction after the sixth groove is formed during the manufacturing process of a semiconductor device;

[0072] Figure 12b for Figure 1 A schematic diagram in the b-b' direction after the sixth groove is formed during the manufacturing process of a semiconductor device;

[0073] Figure 12c for Figure 1A schematic diagram in the d-d' direction after the sixth groove is formed during the manufacturing process of a semiconductor device. Detailed Implementation

[0074] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0075] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0076] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and proportions of the components in the drawings represent preferred embodiments. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0077] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0078] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0079] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0080] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0081] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0082] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0083] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0084] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0085] The phrase "A and B are set on the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0086] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0087] This disclosure provides a semiconductor device, including: a bit line, a transistor, and a capacitor disposed on a substrate;

[0088] The transistor includes a channel, a first electrode, and a second electrode. The first electrode and the second electrode are respectively connected to the channel. The first electrode is connected to the capacitor, and the second electrode is connected to the bit line.

[0089] The capacitor includes a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode, wherein the capacitor dielectric layer is disposed at least between the first capacitor electrode and the second capacitor electrode.

[0090] The first electrode includes a first electrode portion and a second electrode portion. The first electrode portion and the second electrode portion are different conductive film layers connected sequentially along a direction parallel to the substrate. The first electrode portion is connected to the channel. The second electrode portion and the first capacitor electrode are integrally formed. An insulating layer is provided on the sidewall of the second electrode portion, and the insulating layer clamps the second electrode portion.

[0091] The present invention's memory will be illustrated by some exemplary embodiments below.

[0092] Figure 1 A schematic cross-sectional view of a semiconductor device along a direction parallel to the substrate, provided for some embodiments. In some embodiments, such as Figure 1 As shown, the semiconductor device may include: word lines, bit lines 3, transistor 1, and capacitor 2 disposed on substrate 102. In one embodiment, the semiconductor device containing only transistor 1 and capacitor 2 forms a 1T1C structure; the transistor 1 is connected to the bit line 3 and the capacitor 2 respectively, and the word line is connected to the gate of the transistor 1. The capacitor in this application can be understood as a capacitor. Figure 1 No word lines are displayed.

[0093] In some embodiments, the word line may extend along a direction perpendicular to the substrate and be connected to the gate of a plurality of transistors stacked along the direction perpendicular to the substrate, wherein the plurality of transistors may share the word line.

[0094] In some embodiments, the bit line may extend in a direction parallel to the substrate and be connected to the electrode of a transistor located in the same layer, and the transistors in the same layer may share the bit line.

[0095] Figure 2a for Figure 1 A schematic diagram of a semiconductor device in the a-a' direction; Figure 2b for Figure 1 A schematic diagram of a semiconductor device in the b-b' direction; Figure 2c for Figure 1 A schematic diagram of a semiconductor device in the d-d' direction. In some embodiments, such as Figure 2a , Figure 2b and Figure 2cAs shown, the transistor includes a gate 23, a gate insulating layer 24, a channel 25, and a first electrode 21 and a second electrode 22 respectively connected to the channel 25. The first electrode 21 and the second electrode 22 are located on opposite sides of the channel 25 in a direction parallel to the substrate 102 and are connected through the channel 25. The first electrode 21 is located on the side of the channel 25 away from the bit line 3; the second electrode 22 is located on the side of the channel closer to the bit line 3. The second electrode 22 and the bit line 3 can each be made of different materials, or the second electrode 22 can be integrally connected to the bit line 3 and made of the same material. The channel 25 between the first electrode 21 and the second electrode 22 is a horizontal channel.

[0096] In some embodiments, the first electrode 21 includes a first electrode portion 211 and a second electrode portion 212 connected sequentially along a direction parallel to the substrate. The first electrode portion 211 is located on the side of the second electrode portion 212 away from the capacitor. The first electrode portion 211 is strip-shaped extending along the direction parallel to the substrate. A first end of the first electrode portion 211 is connected to a first end of the channel 25, and a second end of the first electrode portion 211 is connected to a first end of the second electrode portion 212.

[0097] In some embodiments, the second electrode portion 212 is located on the side of the first electrode portion 211 near the capacitor. The second electrode portion 212 is strip-shaped and extends along the direction parallel to the substrate. The second electrode portion 212 includes a surface near the first electrode portion 211, a surface away from the first electrode portion 211, and other surfaces, including sidewalls of the second electrode portion. A first end of the second electrode portion 212 is connected to a second end of the first electrode portion 211, and the second end of the second electrode portion 212 is connected to the first capacitor electrode 71 of the capacitor.

[0098] In some embodiments, the first electrode portion 211 and the second electrode portion 212 are different conductive film layers sequentially disposed along the direction parallel to the substrate.

[0099] In some embodiments, the second electrode portion 212 and the first capacitor electrode 71 of the capacitor are integral structures and include the same conductive material, that is, the second electrode portion 212 and the first capacitor electrode 71 of the capacitor are formed by the same conductive film layer.

[0100] In some embodiments, the first electrode portion and the second electrode portion are the same conductive film layer connected sequentially along the first direction. This arrangement can simplify the process, make the first electrode and the first capacitor electrode integrally formed, and at the same time ensure the stability of the first capacitor electrode.

[0101] In some embodiments, the first electrode portion 211, the second electrode portion 212, and the first capacitor electrode 71 comprise the same conductive material.

[0102] In some embodiments, a capacitor fixing layer is provided on the sidewall of the first electrode 21. The capacitor fixing layer includes an insulating layer 41, which is located on opposite sides of the first electrode 21 in a direction perpendicular to the substrate. The insulating layer 41 is located on at least opposite sides of the second electrode portion 212 of the first electrode 21 in a direction perpendicular to the substrate. In the first direction D1, the insulating layer 41 overlaps with the second electrode portion 212, clamping the second electrode portion 212.

[0103] In this embodiment of the semiconductor device, the second electrode portion 212 of the first electrode 21 and the first capacitor electrode 71 are integrated into one structure, and a capacitor fixing layer is disposed on the side wall of the second electrode portion 212 to clamp the side wall of the second electrode portion 212. By clamping the second electrode portion 212, the stability of the first capacitor electrode 71 is improved and the collapse of the first capacitor electrode 71 is prevented.

[0104] In some embodiments, the capacitor fixing layer contacts the second electrode portion 212, and the surface roughness of the capacitor fixing layer in contact with the second electrode portion 212 is greater than the roughness of other surfaces of the capacitor fixing layer. This configuration enhances the bonding force between the capacitor fixing layer and the second electrode portion 212, ensuring the stability of the first capacitor electrode.

[0105] In some embodiments, the surface of the capacitor fixing layer that contacts the second electrode portion has an uneven structure. The uneven structure of the capacitor fixing layer and the uneven structure of the second electrode portion interlock, which can enhance the bonding force between the capacitor fixing layer and the second electrode portion 212 and ensure the stability of the first capacitor electrode.

[0106] Figure 2d for Figure 2a A schematic diagram of a semiconductor device in the e-e' direction. In some embodiments, such as Figure 2d As shown, the capacitor fixing layer includes an isolation layer 61, which is located on opposite sides of the second electrode portion 212 in the direction parallel to the substrate, clamping the second electrode portion 212 of the first electrode 21, thereby improving the stability of the first capacitor electrode 71.

[0107] In some embodiments, the second electrode 22 and the bit line 3 are an integral structure and include the same conductive material, that is, the second electrode 22 and the bit line 3 are formed by the same conductive film layer.

[0108] In some embodiments, the second electrode 22 and the bit line 3 are different regions of an integral structure extending along a direction parallel to the substrate. One end of the integral structure is connected to the second end of the channel.

[0109] In some embodiments, the gate 23 and the word line 4 are an integral structure.

[0110] In some embodiments, the channel 25 surrounds the gate 23 and extends along the sidewall of the gate 23, forming an annular shape extending in a direction perpendicular to the substrate. The thickness direction of the channel 25 is parallel to the substrate.

[0111] In this context, "channel surrounding the gate" can be understood as the channel partially or completely surrounding the gate. In some embodiments, the surrounding can be a complete surround, resulting in a closed annular cross-section of the channel. The cross-section is taken in a direction parallel to the substrate. In some embodiments, the surrounding can be a partial surround, where the resulting cross-section is not closed but exhibits a ring shape. For example, an annular shape with an opening.

[0112] In some embodiments, the gate insulating layer 24 is disposed between the gate 23 and the channel 25.

[0113] In some embodiments, the capacitor includes a first capacitor electrode 71, a second capacitor electrode 72, and a capacitor dielectric layer 73. The first capacitor electrode 71 and the second electrode portion 212 of the first electrode 21 are integral structures and include the same conductive material.

[0114] In some embodiments, at least a portion of the second capacitor electrode 72 surrounds the sidewall of the first capacitor electrode 71 via the capacitor dielectric layer 73, and covers the end face of the first capacitor electrode 71 away from the channel 25.

[0115] In some embodiments, the capacitor dielectric layer 73 is disposed at least between the first capacitor electrode 71 and the second capacitor electrode 72.

[0116] In some embodiments, a capacitor dielectric layer 73 and a second capacitor electrode 72 are sequentially disposed on the end face of the capacitor fixing layer away from the word line.

[0117] In some embodiments, a groove is formed between the end face of the capacitor fixing layer away from the word line and the sidewall of the adjacent first capacitor electrode 71, and the capacitor dielectric layer 73 and the second capacitor electrode 72 are sequentially disposed on the inner wall of the groove.

[0118] In some embodiments, the groove does not overlap with the orthographic projection of the first electrode 21 onto the substrate.

[0119] In some embodiments, the capacitor further includes a conductive filling layer 74, and the second capacitor electrode 72 is a film structure. At least a portion of the conductive filling layer 74 fills the groove and is connected to the second capacitor electrode 72 within the groove. At least a portion of the conductive filling layer 74 is located on the side of the first capacitor electrode 71 away from the channel. The material of the conductive filling layer 74 may include germanium-doped polycrystalline silicon.

[0120] In some embodiments, the conductive filling layer 74 does not overlap with the orthographic projection of the first electrode 21 onto the substrate.

[0121] In some embodiments, in the direction perpendicular to the substrate, the second capacitor electrodes 72 of the capacitors in different layers can be connected into a single structure, that is, the capacitors in different layers share the same second capacitor electrode 72.

[0122] In some embodiments, in the direction perpendicular to the substrate, the capacitor dielectric layers 73 of the capacitors in different layers can be connected into a single structure, that is, the capacitors in different layers share the same capacitor dielectric layer 73.

[0123] The technical solution of this embodiment is further illustrated below through the manufacturing process of the memory in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of a film layer, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0124] In this embodiment, each layer includes multiple storage units, but this embodiment is not limited to this, and each layer may include one storage unit.

[0125] In some embodiments, the semiconductor device may be any of the semiconductor devices described above, and the manufacturing process of the semiconductor device may include:

[0126] Step 101: Form an insulating layer and an isolation sacrificial layer.

[0127] Forming an insulating layer and a sacrificial isolation layer: A buffer layer 101 is formed on a substrate 102; subsequently, a stacked structure is formed by sequentially and alternately depositing sacrificial isolation layers 42 and insulating layers 41 on the buffer layer 101; subsequently, the stacked structure is patterned by etching using a mask to form multiple trenches perpendicular to the substrate, each insulating layer 41 forming a first patterned structure that is stacked and cyclically distributed, and each sacrificial isolation layer 42 forming a second patterned structure that is stacked and cyclically distributed; subsequently, the stacked structure is etched by dry etching to form multiple vias penetrating the multiple sacrificial isolation layers 42 and the multiple insulating layers 41, the sidewalls of the vias exposing the sidewalls of each sacrificial isolation layer 42 and each insulating layer 41; finally, a sacrificial layer 43 is formed within the multiple vias, such as... Figure 4a , Figure 4b , Figure 4c and Figure 4d As shown.

[0128] In some embodiments, in the subsequent transistor formation process, the isolation sacrificial layer 42 and the sacrificial layer 43 are first etched away, and then the first electrode, the second electrode, and the bit line of the transistor are formed in the area where the isolation sacrificial layer 42 has been etched away; subsequently, the transistor channel, the gate insulating layer, and the gate are sequentially formed on the sidewall of the via.

[0129] In some embodiments, the insulating layer 41 may be made of silicon oxide, and the isolation sacrificial layer 42 may be made of silicon nitride.

[0130] In some embodiments, the orthogonal projection of the via on a plane parallel to the substrate may be square or the like.

[0131] In some embodiments, the insulating layer and the isolation sacrificial layer may be deposited using a chemical vapor deposition method.

[0132] In some embodiments, the substrate may be a semiconductor substrate, such as a silicon substrate, or any substrate that serves as a support, not just a substrate, but a substrate formed by peripheral circuits on the substrate.

[0133] In some embodiments, the insulating layer serves to isolate devices and may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2).

[0134] Figure 5 This is a schematic cross-sectional view of an isolation sacrificial layer in a semiconductor device, provided for some embodiments, along a direction parallel to the substrate. In some embodiments, such as... Figure 5As shown, the second patterned structure formed by each isolation sacrificial layer 42 includes a main structure 422 and a plurality of branches 421 connected to the main structure 422. The main structure 422 is strip-shaped and extends along a second direction D2; each branch 421 is strip-shaped and extends along a first direction D1, with a first end of each branch 421 connected to the main structure 422 and a second end of each branch 421 extending along the first direction D1. The plurality of branches 421 are spaced apart on the main structure 422 along the second direction D2, and the plurality of branches 421 are located on the same side of the main structure 422. The first direction D1 and the second direction D2 are both parallel to the upper surface of the substrate, and the first direction D1 and the second direction D2 intersect; for example, the first direction D1 and the second direction D2 are perpendicular.

[0135] In some embodiments, in the subsequent transistor formation process, the main structure 422 and the plurality of branches 421 are first etched away; then, bit lines are formed in the region where the main structure 422 is etched away, and a first electrode and a second electrode are formed in the region where the plurality of branches 421 are etched away.

[0136] In some embodiments, each branch 421 is provided with a through hole K, which is located in the portion of the branch 421 near the bit line 3.

[0137] Step 102: Form the first groove and the second groove.

[0138] Forming the first and second grooves includes: on the substrate forming the aforementioned pattern, using an etching process, etching away the stacked structure on opposite sides in the first direction D1 to form a first groove 51 extending perpendicular to the substrate direction; and etching away the insulating layer 41 on opposite sides of each branch 421 in the second direction D2 to form a second groove 52 extending perpendicular to the substrate direction. The bottoms of both the first and second grooves 51 extend to the surface of the buffer layer 101. Subsequently, wet cleaning is performed, such as... Figure 6a , Figure 6b , Figure 6c and Figure 6d As shown. In a cross-section parallel to the substrate direction, the first groove 51 is a strip extending along the second direction D2, and the second groove 52 is a strip extending along the first direction D1.

[0139] Step 103: Form an isolation layer.

[0140] Forming the isolation layer includes: depositing isolation material in the first and second grooves on the substrate with the aforementioned pattern, thereby forming an isolation layer 61; and then performing a polishing process on the isolation layer 61, such as... Figure 7a , Figure 7b , Figure 7c and Figure 7dAs shown. The isolation layer 61 can be made of silicon nitride. The insulating layer 41 and the isolation layer 61 form a capacitor fixing layer.

[0141] Step 104: Form the third groove.

[0142] Forming the third groove includes: on the substrate with the aforementioned pattern, using an etching process, removing the isolation layer near the capacitor side of each branch 421 to form a third groove 53 extending perpendicular to the substrate direction. The bottom of the third groove 53 extends to the surface of the buffer layer 101. The third groove 53 exposes the end face of each branch 421 away from the sacrificial layer 43. Subsequently, wet cleaning is performed, such as... Figure 8a and Figure 8b As shown. In a cross-section parallel to the substrate direction, the third groove 53 is a strip extending along the second direction D2.

[0143] Step 105: Form the fourth groove.

[0144] Forming the fourth groove includes: on the substrate forming the aforementioned pattern, performing a lateral etching process on the end face of each exposed branch 421 to etch away a portion of each branch 421, forming the fourth groove 54, while retaining the portion of each branch 421 near the sacrificial layer 43, such as... Figure 9a and Figure 9b As shown. The first end of the fourth groove 54 is connected to the reserved branch 421, and the fourth groove 54 extends along the first direction D1 and is connected to the third groove 53.

[0145] In some embodiments, the length of the fourth groove 54 in the first direction D1 is greater than the length of the first capacitor electrode subsequently formed in the semiconductor device in the first direction D1.

[0146] Step 106: Form a capacitor electrode thin film.

[0147] Forming the capacitor electrode film includes: depositing conductive material in the third groove 53 and the fourth groove 54 on the substrate with the aforementioned pattern, so that the conductive material forms a capacitor electrode film 70, the capacitor electrode film 70 fills the third groove 53 and the fourth groove 54, and the capacitor electrode film 70 is connected to the retained branch 421, such as... Figure 10a , Figure 10b and Figure 10c As shown. The conductive material can be titanium nitride.

[0148] Step 107: Form the fifth groove.

[0149] Forming the fifth groove includes: based on the substrate on which the aforementioned pattern is formed, forming an insulating layer 41 and an isolation sacrificial layer 42 on the side of the stacked structure away from the substrate, the isolation sacrificial layer 42 being located on the side of the insulating layer 41 away from the substrate; subsequently, using an etching process, etching away the capacitor electrode film 70 located in the third groove to form the fifth groove 55, retaining the capacitor electrode film 70 located in the fourth groove, the fifth groove 55 exposing the insulating layer 41 and the isolation layer 61 located on the sidewalls of the retained capacitor electrode film 70; subsequently, using a wet cleaning process, such as... Figure 11a and Figure 11b As shown in the figure. Here, the third direction D3 is perpendicular to the substrate.

[0150] Step 108, forming the sixth groove.

[0151] Forming the sixth groove includes: on the substrate forming the aforementioned pattern, performing a lateral etching process on the sidewalls of the exposed insulating layer 41 and the isolation layer 61 to etch away a portion of the insulating layer 41 and the isolation layer 61 located on the sidewalls of the retained capacitor electrode film 70, forming a sixth groove 56. The sixth groove 56 surrounds the sidewalls of the retained capacitor electrode film 70 and is annular in shape extending along the first direction D1. The sixth groove 56 exposes the sidewalls of the retained capacitor electrode film 70; a portion of the insulating layer 41 and the isolation layer 61 are retained on the sidewalls of the capacitor electrode film 70, such as... Figure 12a , Figure 12b and Figure 12c As shown.

[0152] In some embodiments, the depth of the lateral etching of the sixth groove 56 is less than the length of the capacitor electrode film 70 in the first direction D1, and the first direction D1 is the same as the direction of the lateral etching of the sixth groove 56, that is, the length of the sixth groove 56 in the first direction D1 is less than the length of the retained capacitor electrode film 70 in the first direction D1.

[0153] Step 109: Form the first capacitor electrode, the second electrode portion, the capacitor dielectric layer, and the second capacitor electrode.

[0154] The formation of the first capacitor electrode, the second electrode portion, the capacitor dielectric layer, and the second capacitor electrode includes: based on the substrate with the aforementioned pattern, using an atomic deposition process, sequentially forming a capacitor dielectric layer 73 and a second capacitor electrode 72 on the sidewalls of the exposed capacitor electrode film 70; subsequently, depositing a conductive filling layer 74 in the sixth and fifth grooves, the conductive filling layer 74 filling the sixth and fifth grooves; and finally, performing a polishing process on the conductive filling layer 74, such as... Figure 3a , Figure 3b , Figure 3c and Figure 3d As shown.

[0155] In some embodiments, the capacitor electrode film forms a first capacitor electrode 71 and a second electrode portion 212, the first capacitor electrode 71 and the second capacitor electrode 72 are disposed opposite to each other, the second electrode portion 212 is disposed opposite to the insulating layer, and the orthogonal projections of the second electrode portion 212 and the second capacitor electrode 72 on the substrate do not overlap.

[0156] In some embodiments, the capacitor fixing layer formed by the insulating layer 41 and the isolation layer 61 can clamp the second electrode portion 212. The semiconductor device manufacturing method of this application improves the stability of the first capacitor electrode by clamping the second electrode portion 212 using the capacitor fixing layer.

[0157] In some embodiments, the capacitor dielectric layer 73 may be made of a high-k dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. The high-k dielectric material may include, but is not limited to, at least one of the following: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.

[0158] In some embodiments, the second capacitor electrode 72 may be made of titanium nitride.

[0159] In some embodiments, the conductive filler layer 74 may be made of chromium (Ge)-doped polycrystalline silicon.

[0160] Step 110: Form the first electrode, the second electrode, the channel, the gate insulating layer, and the gate.

[0161] The formation of the first electrode, second electrode, channel, gate insulating layer, and gate includes: etching away the sacrificial layer and isolation sacrificial layer on the substrate with the aforementioned pattern; forming the first electrode portion 211, second electrode 22, and bit line 3 of the transistor's first electrode 21 in the region where the isolation sacrificial layer has been etched away; the first electrode portion 211 of the first electrode 21 is connected to the second electrode portion 212 in the first electrode 21, and the second electrode 22 is integrally connected to the bit line 3; subsequently, a channel 25, gate insulating layer 24, and gate 23 are sequentially formed in the region (via) where the sacrificial layer has been etched away, as shown below. Figure 2a As shown.

[0162] The solution provided in this embodiment simplifies the process flow, is easy to implement, and improves production efficiency. It has the advantages of easy process implementation, low production cost, and high yield.

[0163] This disclosure also provides a method for manufacturing a semiconductor device, comprising:

[0164] An isolation sacrificial layer and an insulating layer are formed alternately in sequence on a substrate; the isolation sacrificial layer includes a main structure and multiple branches connected to the main structure.

[0165] An etching process is used to form a third groove extending along a direction perpendicular to the substrate on the side of each branch away from the main structure. The third groove exposes the end face of each branch away from the main structure.

[0166] A lateral etching process is performed on the end face of each exposed branch to etch away a portion of each branch, forming a fourth groove, while retaining a portion of each branch;

[0167] A capacitor electrode film is formed in the third and fourth grooves;

[0168] An etching process is used to etch away the capacitor electrode film located in the third groove to form a fifth groove, which exposes the insulating layer on the sidewall of the capacitor electrode film located in the fourth groove.

[0169] A lateral etching process is performed on the exposed insulating layer to remove a portion of the insulating layer, forming a sixth groove, while a portion of the insulating layer is retained on the sidewall of the capacitor electrode film. The sixth groove exposes the sidewall of the capacitor electrode film.

[0170] Using an atomic deposition process, a capacitor dielectric layer and a second capacitor electrode are sequentially formed on the exposed sidewall of the capacitor electrode film; the portion of the capacitor electrode film opposite to the second capacitor electrode forms a first capacitor electrode, and the portion of the capacitor electrode film opposite to the insulating layer forms a second electrode portion;

[0171] Each branch is etched away, and a first electrode portion and a second electrode portion are formed in the region where each branch is etched away. The first electrode portion and the second electrode portion are connected to form a first electrode.

[0172] In some embodiments, the depth of the lateral etching of the sixth groove is less than the length of the capacitor electrode film in a first direction, which is the same as the direction of the lateral etching of the sixth groove.

[0173] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0174] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Bit lines, transistors, and capacitors are disposed on a substrate; The transistor includes a channel, a first electrode, and a second electrode. The first electrode and the second electrode are respectively connected to the channel. The first electrode is connected to the capacitor, and the second electrode is connected to the bit line. The capacitor includes a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode, wherein the capacitor dielectric layer is disposed at least between the first capacitor electrode and the second capacitor electrode. The first electrode includes a first electrode portion and a second electrode portion, which are sequentially connected along a first direction parallel to the substrate. The first electrode portion is connected to the channel, and the second electrode portion and the first capacitor electrode are integrally formed. At least two sidewalls of the second electrode portion are provided with capacitor fixing layers. In the first direction, the capacitor fixing layers overlap with the second electrode portion, and the capacitor fixing layers clamp the second electrode portion. Wherein, the capacitor fixing layer is in contact with the second electrode portion, and the roughness of the surface of the capacitor fixing layer in contact with the second electrode portion is greater than the roughness of the other surfaces of the capacitor fixing layer; or, the surface of the capacitor fixing layer in contact with the second electrode portion has an uneven structure.

2. The semiconductor device according to claim 1, characterized in that, The first electrode portion and the second electrode portion are identical conductive film layers connected sequentially along the first direction.

3. The semiconductor device according to claim 1, characterized in that, The capacitor fixing layer includes an insulating layer located on opposite sides of the second electrode portion in a direction perpendicular to the substrate.

4. The semiconductor device according to claim 1, characterized in that, The capacitor fixing layer includes an isolation layer located on opposite sides of the second electrode portion in a direction parallel to the substrate.

5. The semiconductor device according to claim 1, characterized in that, The capacitor dielectric layer and the second capacitor electrode are sequentially disposed on the end face of the capacitor fixing layer away from the bit line.

6. The semiconductor device according to claim 1, characterized in that, A groove is formed between the end face of the capacitor fixing layer away from the bit line and the side wall of the adjacent first capacitor electrode, and the capacitor dielectric layer and the second capacitor electrode are sequentially disposed on the inner wall of the groove.

7. The semiconductor device according to claim 6, characterized in that, It also includes a conductive filling layer that at least partially fills the groove and is connected to a second capacitor electrode within the groove.

8. The semiconductor device according to claim 6, characterized in that, The groove does not overlap with the orthographic projection of the first electrode on the substrate.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The second electrode and the bit line are an integral structure.

10. The semiconductor device according to any one of claims 1 to 8, characterized in that, The transistor further includes a channel, a gate insulating layer, and a gate, the channel surrounding the gate, and the gate insulating layer disposed between the gate and the channel.

11. A method for manufacturing a semiconductor device, characterized in that, include: An isolation sacrificial layer and an insulating layer are formed alternately in sequence on the substrate; The isolation sacrificial layer includes a main structure and multiple branches connected to the main structure, the branches extending along a first direction parallel to the substrate; the insulating layer constitutes a capacitor fixing layer; A portion of each branch is etched away to form a fourth groove; A capacitor electrode film is formed within the fourth groove; A portion of the insulating layer is etched away to form a sixth groove; A capacitor dielectric layer and a second capacitor electrode are sequentially formed on the sidewall of the capacitor electrode film. In the first direction, the portion where the capacitor electrode film overlaps with the second capacitor electrode serves as the first capacitor electrode; the portion where the capacitor electrode film overlaps with the insulating layer serves as the second electrode portion; the second electrode portion and the first capacitor electrode are integrally formed, and capacitor fixing layers are provided on both sidewalls of the second electrode portion. In the first direction, the capacitor fixing layer overlaps with the second electrode portion, and the capacitor fixing layer clamps the second electrode portion; the capacitor fixing layer contacts the second electrode portion, and the surface roughness of the capacitor fixing layer in contact with the second electrode portion is greater than the roughness of other surfaces of the capacitor fixing layer; or, the surface of the capacitor fixing layer in contact with the second electrode portion has an uneven structure.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, The formation of the fourth groove includes: An etching process is used to form a third groove extending along a direction perpendicular to the substrate on the side of each branch away from the main structure. The third groove exposes the end face of each branch away from the main structure. A transverse etching process is performed on the end face of each exposed branch to remove a portion of each branch, forming a fourth groove.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The formation of the sixth groove includes: A capacitor electrode film is formed within the third groove; An etching process is used to etch away the capacitor electrode film located in the third groove to form a fifth groove, which exposes the insulating layer on the sidewall of the capacitor electrode film located in the fourth groove. A lateral etching process is performed on the exposed insulating layer to remove a portion of it, forming the sixth groove.

14. The method for manufacturing a semiconductor device according to claim 11, characterized in that, The depth of the lateral etching of the sixth groove is less than the length of the capacitor electrode film in the first direction, which is the same as the direction of the lateral etching of the sixth groove.

15. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 10.

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