Semiconductor device, storage system and preparation method of semiconductor device

Abstract

The invention provides a semiconductor device, a storage system and a preparation method of the semiconductor device, relates to the technical field of semiconductor chips, and aims to improve the capacitance and the integration level of a capacitor structure in the semiconductor device. The semiconductor device includes a stack structure, a first contact structure, and a plurality of second contact structures. The stacked structure comprises a plurality of first insulating layers, a plurality of first conducting layers and a plurality of second conducting layers which are arranged in a stacked mode, and at least one second conducting layer is arranged between every two adjacent first conducting layers. The first contact structure penetrates through the stack structure and is connected with the plurality of first conductive layers. The plurality of second contact structures penetrate through at least part of the stacked structure, and each second contact structure is connected with the corresponding second conductive layer. The semiconductor device has relatively high integration level and capacitance.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device, a storage system, and a method for preparing the semiconductor device. Background Art

[0002] With the development of semiconductor technology, semiconductor devices that use multiple capacitors to achieve corresponding device functions have emerged. For example, a dynamic random access memory (DRAM) with multiple capacitor structures can use the charge storage function of capacitors to store and read data.

[0003] For example, DRAM may be a 1TnC storage structure, in which each storage unit includes a transistor (T) and at least one capacitor (C). The capacitor in the 1TnC storage structure is used to store charge, that is, to store information (such as information "1" and information "0"), and the transistor in the 1TnC storage structure is a switch that controls the inflow and release of charge from the capacitor.

[0004] As the integration of semiconductor devices gradually increases, the design space of capacitors in semiconductor devices (such as DRAM) gradually decreases. How to increase the capacitance of capacitors within the limited design space to achieve the corresponding functions of semiconductor devices (such as achieving the high storage density storage function of DRAM memory) has become a problem that needs to be solved urgently. Summary of the invention

[0005] Embodiments of the present disclosure provide a semiconductor device, a storage system, and a method for manufacturing a semiconductor device, aiming to increase the capacitance of a capacitor in a semiconductor device.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] In one aspect, a semiconductor device is provided, comprising a stack structure, a first contact structure, and a plurality of second contact structures.

[0008] The stacked structure includes multiple first insulating layers, multiple first conductive layers, and multiple second conductive layers. The first conductive layers and the second conductive layers are stacked, at least one second conductive layer is provided between two adjacent first conductive layers, and the first insulating layer is provided between the first conductive layer and the second conductive layer. The first contact structure runs through the stacked structure and is connected to the multiple first conductive layers. Multiple second contact structures run through at least part of the stacked structure, and each second contact structure is connected to a corresponding second conductive layer.

[0009] In the semiconductor device provided in the embodiment of the present application, a flat design of the capacitor plates is achieved by stacking multiple first conductive layers and multiple second conductive layers. On the one hand, the difficulty of preparing the semiconductor device is reduced (not subject to the limitations of the punching process). On the other hand, a larger capacitance can be achieved in a smaller plane area, which is conducive to the preparation of large capacitor devices.

[0010] In some embodiments, along the stacking direction of the stacking structure, the first conductive layers and the second conductive layers are alternately arranged in sequence.

[0011] In this embodiment, a first conductive layer is disposed on both sides of a second conductive layer. When current is passed through the second conductive layer, a sandwich capacitor (a capacitor with three plates) can be formed with two first conductive layers at the same time, thereby increasing the effective facing area of ​​the capacitor and improving the capacitance of the capacitor per unit area. In addition, two capacitors disposed adjacent to each other in the third direction can share the same plate (i.e., the first conductive layer), thereby reducing the size of the semiconductor device in the third direction and improving the integration of the capacitor.

[0012] In some embodiments, the semiconductor device includes multiple memory cell layers and multiple second insulating layers. Each memory cell layer includes a first conductive layer, a first insulating layer, and a second conductive layer; the first insulating layer is disposed around the first conductive layer, and the second conductive layer is disposed around the first insulating layer. The multiple second insulating layers are stacked and alternately disposed with the multiple memory cell layers.

[0013] In this embodiment, one electrode plate of the capacitor (for example, the second conductive layer) is arranged around another electrode plate (for example, the first conductive layer), that is, all side surfaces of one electrode plate of the capacitor can be used as effective capacitance area, further increasing the effective facing area of ​​the capacitor and improving the capacitance of the capacitor per unit area.

[0014] In some embodiments, the first contact structure includes a first dielectric layer and a first conductive column, the first conductive column runs through the stacked structure, and at least a portion of the first dielectric layer is located between the second conductive layer and the first conductive column. In particular, a plurality of first conductive layers runs through the first dielectric layer and is connected to the first conductive column, and the second conductive layer is insulated from the first conductive column by the first dielectric layer.

[0015] The structural design of the first contact structure in this embodiment can realize the external connection of all first conductive layers in the semiconductor device through only one structure.

[0016] In some embodiments, the first dielectric layer includes a plurality of first sub-portions arranged in sequence along the stacking direction of the stacking structure, at least part of the first sub-portions is located between the second conductive layer and the first conductive pillar, and at least part of the first conductive layer is disposed between two adjacent first sub-portions.

[0017] In some embodiments, the second contact structure includes a second dielectric layer, a second conductive pillar, and a first conductive block.

[0018] The first conductive block is connected to the corresponding second conductive layer. The second conductive column at least penetrates the stacked structure to the corresponding second conductive layer and is connected to the first conductive block. At least part of the second dielectric layer is located between the second conductive layer other than the corresponding second conductive layer and the second conductive column.

[0019] The structural design of the second contact structure in this embodiment can satisfy the selection of a certain capacitor among a plurality of stacked capacitors, so that different capacitors can flexibly store different information.

[0020] In some embodiments, the second dielectric layer includes a plurality of second sub-portions sequentially arranged along a stacking direction of the stack structure, and at least a portion of the second sub-portions is located between a second conductive layer other than a corresponding second conductive layer and the second conductive pillar.

[0021] In some embodiments, when the first conductive layer and the second conductive layer are alternately arranged in sequence, the semiconductor device further includes a plurality of third sub-sections, the plurality of third sub-sections are arranged at intervals along the stacking direction of the stacking structure, and the third sub-sections are arranged between the second conductive pillar and the first conductive layer, so as to achieve electrical insulation between the second conductive pillar and the first conductive layer, and avoid the failure of the capacitor caused by the conduction between the two.

[0022] In some embodiments, the first insulating layer and the third sub-section are made of the same material. For example, the two can be integrally provided, thereby simplifying the preparation step.

[0023] In some embodiments, the semiconductor device further includes a plurality of transistors, the plurality of transistors are disposed on one side of the stack structure, and each transistor is connected to a corresponding second contact structure.

[0024] The transistor is used to control the input of the electrical signal of the second contact structure. For example, when the transistor is turned on, the external electrical signal can be transmitted to the second contact structure connected to the transistor, thereby charging the second conductive layer connected to the second contact structure to achieve information storage.

[0025] In some embodiments, the semiconductor device further comprises a gate line layer and a plurality of bit lines. The gate line layer is disposed on one side of the stack structure; the gate line layer comprises at least one gate line. The plurality of bit lines are disposed on a side of the gate line layer away from the stack structure and are insulated from the gate line layer.

[0026] The transistor includes a semiconductor part and a gate oxide layer, the semiconductor part passes through the gate line, and the gate oxide layer surrounds the side wall of the semiconductor part that is perpendicular to the gate line layer; in multiple transistors, one end of the semiconductor part of each transistor is connected to the second contact structure, and the other end is connected to a corresponding bit line. Through the gate line and the bit line, the address of a capacitor among multiple capacitors can be selected.

[0027] In some embodiments, the first contact structure penetrates the gate line layer and is insulated from the gate line, so as to facilitate electrical connection between the first contact structure and an external electrical signal.

[0028] In some embodiments, the first conductive layer and / or the second conductive layer includes a first sublayer and a second sublayer, wherein the first sublayer surrounds and is attached to the surface of the second sublayer. The resistivity of the first sublayer is less than the resistivity of the second sublayer. Thus, the first conductive layer or the second conductive layer can be ensured to have good conductivity, while taking into account the electrical performance and structural stability of the semiconductor device.

[0029] In another aspect, a method for preparing a semiconductor device is provided, the method comprising:

[0030] A stacking structure is formed; the stacking structure includes multiple first insulating layers, multiple first conductive layers, and multiple second conductive layers, the first conductive layers and the second conductive layers are stacked, and the first insulating layer is arranged between the first conductive layers and the second conductive layers. A first contact structure is formed; the first contact structure penetrates the stacking structure and is connected to the multiple first conductive layers. A plurality of second contact structures are formed; the plurality of second contact structures penetrate at least part of the stacking structure, and each second contact structure is connected to a corresponding second conductive layer.

[0031] It can be understood that the beneficial effects that can be achieved by the method for preparing the semiconductor device provided by the above embodiments of the present disclosure can refer to the beneficial effects brought about by the design method of the semiconductor device mentioned above, and will not be repeated here.

[0032] In some embodiments, forming a stacked structure includes: forming an initial stacked structure; the initial stacked structure includes a first functional layer and a second functional layer alternately stacked; forming a first opening penetrating the initial stacked structure; removing the first functional layer through the first opening to form a first accommodation cavity; and depositing a conductive material on an inner wall of the first accommodation cavity to form a first conductive layer or a second conductive layer.

[0033] In some embodiments, depositing a conductive material on an inner wall of the first receiving cavity includes depositing a conductive material in the first receiving cavity so that the conductive material fills the first receiving cavity to form one of a first conductive layer and a second conductive layer.

[0034] Wherein, forming the stacked structure further comprises: removing the second functional layer through the first opening to form a second accommodation cavity; depositing an insulating material on the inner wall of the second accommodation cavity to form a first insulating layer; and depositing a conductive material on a side of the first insulating layer away from the inner wall of the second accommodation cavity to form the other of the first conductive layer and the second conductive layer.

[0035] In this embodiment, only the first functional layer needs to be removed to realize the preparation of the capacitor (eg, the storage unit layer), and the process steps are simple, which can effectively improve the preparation efficiency.

[0036] In some embodiments, depositing a conductive material on the inner wall of the first receiving cavity includes depositing a conductive film on the inner wall of the first receiving cavity to form a second conductive layer.

[0037] The forming of the stacking structure further includes: forming a first insulating layer on a side of the second conductive layer away from the inner wall of the first accommodating cavity; forming a first conductive layer on a side of the first insulating layer away from the inner wall of the first accommodating cavity; the first insulating layer surrounds the first conductive layer, and the second conductive layer surrounds the first insulating layer.

[0038] In this embodiment, the thickness of the first functional layer can be substantially the same as the thickness of the second functional layer, that is, the formed first accommodating cavity and the second accommodating cavity only need to be filled with one of the first conductive layer and the second conductive layer. Therefore, there is no need to set a first accommodating cavity and a second accommodating cavity with larger thickness. On the one hand, the difficulty of preparation is reduced. On the other hand, the first accommodating cavity and the second accommodating cavity with smaller thickness can correspond to the first opening with smaller size, thereby effectively improving the utilization rate of the design space on the plane where the first direction and the second direction are located in the semiconductor device.

[0039] In some embodiments, the first contact structure includes a first dielectric layer and a first conductive pillar.

[0040] Forming the first contact structure includes: removing the portion of the second conductive layer near the first opening through the first opening to form a first receiving groove, filling the first receiving groove with insulating material to form a first dielectric layer, and filling the first opening with conductive material to form a first conductive column.

[0041] In some embodiments, the second contact structure includes a second dielectric layer, a second conductive pillar, and a first conductive block.

[0042] After forming the initial stacking structure, forming a plurality of second contact structures includes: forming a plurality of second openings; the second openings at least penetrate the initial stacking structure to the corresponding first functional layer. Through the second openings, a portion of the corresponding first functional layer close to the second openings is removed to form a second receiving groove. A conductive material is filled into the second receiving groove to form a first conductive block. A second dielectric layer is formed through the second openings; at least a portion of the second dielectric layer is disposed in the first functional layer penetrated by the second openings, on a side of the first functional layer close to the second openings except for the corresponding first functional layer. A conductive material is filled into the second openings to form a second conductive column.

[0043] In some embodiments, the second dielectric layer includes a plurality of second sub-portions. Forming the second dielectric layer through the second opening includes: oxidizing, through the second opening, a portion of the first functional layer other than the corresponding first functional layer in the plurality of first functional layers penetrated by the second opening and close to the second opening to form the second sub-portion.

[0044] In some embodiments, the preparation method further includes: forming a plurality of transistors; the transistors are arranged on one side of the stacked structure, and each transistor is connected to a corresponding second contact structure.

[0045] In some embodiments, forming a plurality of transistors includes: forming a third functional layer; the third functional layer is used to be stacked with the stack structure. Forming a plurality of semiconductor parts; the semiconductor part penetrates the third functional layer; one end of the semiconductor part facing the stack structure is used to connect with the second contact structure. A third opening is opened to penetrate the third functional layer, and the third functional layer is removed through the third opening to form a third accommodating cavity. A gate oxide layer is deposited on the side of the semiconductor part perpendicular to the third functional layer through the third accommodating cavity. A gate material is filled into the third accommodating cavity through the third opening to form a gate line.

[0046] In some embodiments, after the initial stacking structure is formed, a third opening is opened through the third functional layer; the third opening is opened simultaneously with the first opening, thereby saving preparation steps and improving preparation efficiency.

[0047] In another aspect, a storage system is provided, which includes a controller and a semiconductor device provided in any one of the above embodiments, wherein the controller is coupled to the semiconductor device so as to control the semiconductor device to store data.

[0048] It can be understood that the beneficial effects that can be achieved by the storage system provided by the above embodiments of the present disclosure can refer to the beneficial effects brought about by the design method of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present disclosure, the actual process of the method, etc.

[0050] Figure 1 is a schematic diagram of the structure of a storage system according to some embodiments;

[0051] Figure 2 is a top view of a semiconductor device according to some embodiments;

[0052] Figure 3 For along Figure 2 A cross-sectional view of the structure of the section line AA';

[0053] Figure 4 for Figure 3 The local enlarged image corresponding to the dotted box B in FIG.

[0054] Figure 5 For along Figure 2 Another cross-sectional view of the structure along the section line AA';

[0055] Figure 6 for Figure 5 The local enlarged image corresponding to the dotted box D in FIG.

[0056] Figure 7 for Figure 3 The local enlarged image corresponding to the dotted box E in FIG.

[0057] Figure 8 for Figure 5 The local enlarged image corresponding to the dotted frame F in FIG.

[0058] Fig. 9 for Figure 3 A local enlarged view corresponding to the dotted frame H in FIG.

[0059] Fig.10 for Figure 5 The local enlarged view corresponding to the dotted frame I in FIG.

[0060] Fig.11 for Figure 3 Another partial enlarged view corresponding to the dotted frame H in FIG.

[0061] Fig.12 for Figure 3 Another partial enlarged view corresponding to the dotted frame H in FIG.

[0062] Fig.13 is another top view of a semiconductor device according to some embodiments;

[0063] Fig.14 is an equivalent circuit diagram of a semiconductor device according to some embodiments;

[0064] Figures 15 to 20 is a flow chart of manufacturing a semiconductor device according to some embodiments;

[0065] Figure 21 to Figure 56 It is a cross-sectional view corresponding to each preparation step of the semiconductor device. DETAILED DESCRIPTION

[0066] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0067] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0068] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0069] In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that a particular feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0070] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0071] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0072] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0073] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0074] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0075] In the context of this disclosure, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0076] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0077] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0078] The present disclosure provides an electronic device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a charging small household appliance (e.g., a soymilk machine, a sweeping robot), a drone, a radar, an aerospace equipment, a vehicle-mounted device, a vehicle, and other different types of user devices or terminal devices; the electronic device may also be a network device such as a base station. The embodiments of the present application do not impose any special restrictions on the specific form of the electronic device.

[0079] The electronic device is provided with a storage system 1000 (see Figure 1 ) in order to realize the storage of relevant data in the electronic device.

[0080] Exemplarily, the electronic device 1000 may further include at least one of a central processing unit (CPU) and a cache.

[0081] The present disclosure also provides a storage system. Figure 1 A schematic diagram of the structure of a storage system 1000 provided in an embodiment of the present disclosure.

[0082] like Figure 1 As shown, the storage system 1000 includes a semiconductor device 100 and a controller 200. The controller 200 is coupled to the semiconductor device 100 to control the semiconductor device 100 to store data.

[0083] The storage system 1000 can be applied to the above-mentioned electronic devices, for example, can be integrated or packaged in the electronic device, for example, can be packaged in the electronic device through Universal Flash Storage (UFS) or Embedded Multi Media Card (eMMC).

[0084] Alternatively, the storage system 1000 may also be integrated into a card-type memory. The card-type memory may include any one of a PC card (PCMCIA, Personal Computer 3D Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a 3D memory, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

[0085] Alternatively, the storage system 1000 may also be integrated into a solid state drive (SSD).

[0086] Exemplarily, the storage system 1000 may include one semiconductor device 100, or may include a plurality of semiconductor devices 100 (eg, Figure 1 shown).

[0087] Exemplarily, the aforementioned controller 200 may be configured to manage data stored in the semiconductor device 100 and communicate with an external device (eg, a host).

[0088] Exemplarily, the controller 200 may also be configured to control the operation of the semiconductor device 100 , such as controlling the semiconductor device 100 to perform read, erase, and program operations.

[0089] Exemplarily, the controller 200 may also be configured to manage various functions regarding data stored or to be stored in the semiconductor device 100 , including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling.

[0090] Exemplarily, the controller 200 may also be configured to process an error correction code regarding data read from or written to the semiconductor device 100 .

[0091] Of course, the controller 200 may also perform any other suitable functions, such as formatting the semiconductor device 100 . For example, the controller 200 may also communicate with an external device (eg, a host) via at least one of various interface protocols.

[0092] It should be noted that the interface protocol may include at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0093] By way of example, the semiconductor device 100 may be a memory (eg, a DRAM). Alternatively, the semiconductor device 100 may be a part of a memory.

[0094] The present disclosure also provides a semiconductor device 100. Figure 2 A top view of a semiconductor device 100 provided in an embodiment of the present disclosure, Figure 3 For along Figure 2 The cross-sectional view of the section line A-A' in Figure 4 for Figure 3 The enlarged view of the structure corresponding to the dotted box B in FIG.

[0095] The semiconductor device 100 may be used in the aforementioned storage system 1000 , or may be used as a separate device in other electronic devices, and the present disclosure does not limit its specific application scenario.

[0096] In some embodiments, Figure 2 and Figure 3 As shown, the semiconductor device 100 includes a stack structure 1 , a first contact structure 2 and a plurality of second contact structures 3 .

[0097] For example, see Figure 3 The semiconductor device 100 may further include a substrate B2, and the stacked structure 1 may be disposed on the substrate B2.

[0098] Exemplarily, the material of the substrate B2 may include a semiconductor material. For example, it may be one of bulk silicon, bulk germanium, silicon germanium, silicon carbide, silicon on insulator (SOI), and silicon germanium on insulator (SGOI). The substrate B2 is used as a carrier for setting a structure such as the stacking structure 1. Any material of the carrier with a certain supporting force is within the protection scope of the embodiment of the present disclosure, and the embodiment of the present disclosure does not limit the material of the substrate B2.

[0099] Among them, see Figure 3 and Figure 4 The stacked structure 1 includes a plurality of first insulating layers 13 , a plurality of first conductive layers 11 and a plurality of second conductive layers 12 .

[0100] The first conductive layer 11 and the second conductive layer 12 are stacked, at least one second conductive layer 12 is disposed between two adjacent first conductive layers 11 , and the first insulating layer 13 is disposed between the first conductive layer 11 and the second conductive layer 12 .

[0101] It should be noted that the aforementioned “the first conductive layer 11 and the second conductive layer 12 are stacked” means that there is a facing area between the first conductive layer 11 and the second conductive layer 12, so as to form a capacitor C (see Figure 4 ), wherein the embodiments of the present disclosure do not limit the specific implementation method of the "stacked arrangement", and any stacking method that can achieve a facing area between the first conductive layer 11 and the second conductive layer 12 is within the protection scope of the embodiments of the present disclosure.

[0102] For example, see Figure 4 The first conductive layer 11 and the second conductive layer 12 can be alternately stacked in sequence in the third direction Z (the direction perpendicular to the substrate B2), or for example, see Figure 6 The second conductive layer 12 can be disposed around the first conductive layer 11 so that the two have a facing area.

[0103] Among them, the first conductive layer 11 is used to form one plate of the capacitor C, and the second conductive layer 12 is used to form the other plate of the capacitor C. The two are stacked to form an electric field between the two plates after current is passed (ie, having capacitor properties).

[0104] The first insulating layer 13 serves as a dielectric layer of the capacitor C and is disposed between the first conductive layer 11 and the second conductive layer 12 to prevent direct conduction between the first conductive layer 11 and the second conductive layer 12 , thereby forming a complete capacitor C structure.

[0105] Exemplarily, the material of the first conductive layer 11 and the second conductive layer 12 may include tungsten, cobalt, copper, aluminum, and at least one of metal silicide and metal nitride (eg, titanium nitride), or the first conductive layer 11 and the second conductive layer 12 may also include other conductive materials.

[0106] Exemplarily, the material of the first insulating layer 13 may be a material with a high dielectric constant (i.e., a HIK material). For example, the dielectric constant of the material of the first insulating layer 13 may be greater than 3.7, for example, the dielectric constant may be 4 to 15, so that the first insulating layer 13 has a strong electrical insulation property, thereby improving the electrical performance of the capacitor C. It is understandable that the first insulating layer 13 may also include other materials capable of achieving electrical insulation. For example, the material of the first insulating layer 13 may also include at least one of aluminum oxide, hafnium oxide, titanium dioxide, polyethylene, perovskite, and some composite materials or ferroelectric materials. The examples of the materials of the first insulating layer 13 here are only exemplary and do not limit the specific materials of the first insulating layer 13.

[0107] For example, see Figure 6 , the first conductive layer 11 may include a first sublayer 111 and a second sublayer 112 .

[0108] Among them, see Figure 6 , the first sub-layer 111 is arranged around the second sub-layer 112 , and the first sub-layer 111 is attached to the surface of the second sub-layer 112 .

[0109] Exemplarily, the resistivity of the first sub-layer 111 is smaller than the resistivity of the second sub-layer 112 .

[0110] For example, the material of the first sub-layer 111 disposed on the outer layer may be titanium nitride material having good electrical conductivity, and the material of the second sub-layer 112 disposed on the inner layer may be tungsten.

[0111] By making the inner layer of a material with a higher resistivity (such as tungsten), the pores in the film layer where the first conductive layer 11 is located can be fully filled, thereby improving the structural stability of the semiconductor device 100 and reducing the difficulty of preparing the first conductive layer 11. By making the outer layer of a material with a lower resistivity (such as titanium nitride), it can be ensured that the first conductive layer 11 has better conductivity, taking into account both the electrical performance and structural stability of the semiconductor device 100.

[0112] Understandably, see Figure 4 The second conductive layer 12 may also include a first sub-layer 111 and a second sub-layer 112, and the corresponding effects are the same as those of the first conductive layer 11, which will not be described in detail here.

[0113] See also Figure 3 The first contact structure 2 penetrates the stack structure 1 and is connected to the multi-layer first conductive layer 11 .

[0114] The first contact structure 2 is used to realize external connection of the first conductive layer 11 , thereby facilitating transmission of electrical signals to the first conductive layer 11 .

[0115] Understandably, see Figure 3Each first conductive layer 11 is electrically connected to the first contact structure 2 so as to synchronously transmit the same electrical signal to all first conductive layers 11 .

[0116] For example, Figure 2 As shown, the cross section of the first contact structure 2 parallel to the substrate B2 may be strip-shaped and extend along the second direction Y (the second direction Y is parallel to the substrate B2).

[0117] Or exemplarily, in other embodiments, the cross-section of the first contact structure 2 parallel to the substrate B2 may also be in any other shape, for example, it may be roughly circular, or may be in a ring shape surrounding multiple second contact structures 3, or may be in a rectangular shape extending along the first direction X (parallel to the substrate B2 and intersecting with the second direction Y), etc. As long as it can completely penetrate the stacking structure 1, any shape or any extension direction of the first contact structure 2 is within the protection scope of the present disclosure.

[0118] For example, see Figure 2 , the semiconductor device 100 may include a plurality of first contact structures 2. For example, see Figure 2 The plurality of first contact structures 2 are arranged along the first direction X and are spaced apart from each other.

[0119] Since the first contact structure 2 penetrates the stack structure 1 , the plurality of first contact structures 2 arranged at intervals can divide the stack structure 1 into a plurality of rows of memory modules G arranged along the first direction X, thereby achieving superposition of the storage capacity of the semiconductor device 100 in the first direction X.

[0120] For example, among multiple rows of memory modules G, only the first conductive layer 11 in one row of memory modules G is connected to the first contact structure 2 adjacent to the row of memory modules G, for example, Figure 2 Taking the orientation in FIG. 1 as an example, the first contact structure 2 is only connected to the first conductive layer 11 in a row of memory modules G located therebelow, so that the electrical signal can be transmitted only to the first conductive layer 11 in the row of memory modules G.

[0121] Alternatively, illustratively, in a plurality of rows of memory modules G, the first conductive layers 11 in two adjacent rows of memory modules G disposed on both sides of the first contact structure 2 are connected to the first contact structure 2, for example, Figure 2 Taking the orientation in as an example, the first contact structure 2 can be connected to the first conductive layers 11 in the two rows of memory modules G located above and below it, so that electrical signals can be transmitted to the first conductive layers 11 in the two rows of memory modules G synchronously.

[0122] For example, see Figure 2 , the semiconductor device 100 may further include at least one isolation portion 4 .

[0123] See also Figure 2 The isolation portion 4 extends along the first direction X, and a plurality of isolation portions 4 are arranged along the second direction Y and are spaced apart.

[0124] The isolation portion 4 may have electrical insulation properties and, similar to the first contact structure 2 , also completely penetrate the stacking structure 1 , thereby dividing the stacking structure 1 into multiple rows of storage modules G arranged along the second direction Y, thereby achieving the superposition of the storage capacity of the semiconductor device 100 in the second direction Y.

[0125] See also Figure 3 A plurality of second contact structures 3 penetrate at least a portion of the stacked structure 1 , and each second contact structure 3 is connected to a corresponding second conductive layer 12 .

[0126] It should be noted that “a plurality of second contact structures 3 penetrate at least a portion of the stacked structure 1” herein may mean that each second contact structure 3 penetrates the entire stacked structure 1 (ie, see Figure 3 , completely penetrates the stack structure 1). Alternatively, it may also mean that the second contact structure 3 only penetrates a portion of the stack structure 1 (see the following Fig.11 and Fig.12 ), for example, the second contact structure 3 only penetrates the stack structure 1 to the corresponding second conductive layer 12.

[0127] It can be understood that the “corresponding second conductive layer 12” here can be understood as the second conductive layer 12 to which a certain second contact structure 3 is connected, that is, if a certain second contact structure 3 among a plurality of second contact structures 3 is connected to a second conductive layer 12 among a plurality of second conductive layers 12, then the second contact structure 3 and the second conductive layer 12 to which it is connected are mutually corresponding. Figure 3 , the second contact structure 3 closest to the first contact structure 2 is connected to the fifth second conductive layer 12 from top to bottom, then the second contact structure 3 closest to the first contact structure 2 and the fifth second conductive layer 12 correspond to each other, that is, the fifth second conductive layer 12 is the corresponding second conductive layer 12 of the second contact structure 3 closest to the first contact structure 2. The term "corresponding" in the subsequent embodiments shall be understood in the same manner.

[0128] The second contact structure 3 is used to realize external connection of the corresponding second conductive layer 12 , thereby facilitating transmission of electrical signals to the second conductive layer 12 .

[0129] Understandably, see Figure 3When a certain second conductive layer 12 needs to store data, an electrical signal can be transmitted to the second contact structure 3 connected to the second conductive layer 12, so as to realize the charging of the capacitor C corresponding to the second conductive layer 12, that is, to realize the information storage of the capacitor C (for example, information "1" or information "0").

[0130] For example, Figure 2 As shown, the cross section of the second contact structure 3 parallel to the substrate B2 may be circular.

[0131] It can be understood that, in other embodiments, the cross-section of the second contact structure 3 parallel to the substrate B2 can also be in any other shape, for example, it can be roughly rectangular, or it can be elliptical, etc. As long as it can penetrate the stacking structure 1 to the corresponding second conductive layer 12, any shape of the second contact structure 3 is within the protection scope of the present disclosure.

[0132] For example, see Figure 2 The plurality of second contact structures 3 may be arranged in an array along the first direction X and the second direction Y.

[0133] For example, see Figure 2 , a plurality of second contact structures 3 may be correspondingly arranged in each storage module G, for example, 16 second contact structures 3 may be arranged.

[0134] It can be understood that the effective area of ​​the memory C connected to each second contact structure 3 (ie, the facing area of ​​the first conductive layer 11 and the second conductive layer 12 ) is substantially equal to the area of ​​a storage module G surrounded by the first contact structure 2 and the isolation portion 4 .

[0135] It can be understood that the maximum number of second contact structures 3 that can be set in each storage module G (i.e., the number of holes that can be punched) depends on the area of ​​a single storage module G, that is, on the effective area of ​​the memory C in the single storage module G (the area facing the first conductive layer 11 and the second conductive layer 12).

[0136] Exemplarily, the stacking structure 1 can also be stacked along the stacking direction (i.e., the third direction Z). The more the first conductive layers 11 and the second conductive layers 12 are stacked, the more memories C are formed. That is, the semiconductor device 100 can also achieve the stacking of storage capacity along the stacking direction (i.e., the third direction Z) of the stacking structure 1.

[0137] It can be understood that the plurality of second contact structures 3 are arranged in one-to-one correspondence with the plurality of second conductive layers 12 (i.e., one second contact structure 3 is connected to a corresponding second conductive layer 12), that is, the number of second conductive layers 12 stacked in the stacked structure 1 depends on the number of second contact structures 3. That is, the larger the effective area of ​​a single memory C (i.e., the area of ​​the memory module G), the greater the number of corresponding second contact structures 3, and the greater the number of corresponding second conductive layers 12, that is, the greater the number of corresponding memories C that can be formed.

[0138] In some embodiments, a capacitor for storing information is usually formed in a vertical tube manner, for example, a hole is dug in the dielectric layer, and the capacitor plate and insulating layer are deposited in the hole. Due to the limitations of the punching process, it is difficult to increase the capacitance of the capacitor in this embodiment, which limits the improvement of the storage capacity of the semiconductor device. In addition, the vertical tubular capacitor in this embodiment is difficult to prepare, and the process window for realizing storage capacitor superposition is small.

[0139] In the semiconductor device 100 provided in the embodiment of the present application, a plurality of first conductive layers 11 and a plurality of second conductive layers 12 are stacked to realize a flat design of the capacitor C plate, which reduces the difficulty of manufacturing the semiconductor device 100 (not subject to the limitation of the punching process) on the one hand, and can realize a larger capacitance in a smaller plane area on the other hand. For example, see Figure 2 In a storage module G, the area occupied by 16 holes (i.e., 16 second contact structures 3) can meet the capacitance requirement of a single capacitor C, and 16 capacitors C can be set in the area (XY plane) corresponding to the storage module G, which greatly increases the capacitance, storage capacity and integration (the number of memory devices C per unit area) of the semiconductor device 100, and makes it easy to prepare a large capacitor device.

[0140] In addition, the semiconductor device 100 provided in the embodiment of the present application can be flexibly expanded in the first direction X, the second direction Y and the third direction Z, and the expansion difficulty is relatively low, so that the capacitance of a single capacitor C and the storage capacity of the semiconductor device 100 can be flexibly controlled according to needs.

[0141] In some embodiments, Figure 3 and Figure 4 As shown, along the stacking direction (ie, the third direction Z) of the stacking structure 1, the first conductive layers 11 and the second conductive layers 12 are alternately arranged in sequence. That is, in the third direction Z, a second conductive layer 12 is arranged between two adjacent first conductive layers 11.

[0142] It can be understood that a first insulating layer 13 is provided between the first conductive layer 11 and the second conductive layer 12. Figure 4The first conductive layer 11, the first insulating layer 13 and the second conductive layer 12 are alternately arranged and stacked in sequence.

[0143] See also Figure 4 In this embodiment, a first conductive layer 11 is disposed on both sides of a second conductive layer 12. When current is passed through the second conductive layer 12, a sandwich-structured capacitor C (a capacitor C with three plates) can be formed with two first conductive layers 11 at the same time, thereby increasing the effective facing area of ​​the capacitor C and improving the capacitance of the capacitor C per unit area. In addition, two capacitors C disposed adjacent to each other along the third direction Z can share the same plate (i.e., the first conductive layer 11), thereby reducing the size of the semiconductor device 100 in the third direction Z and improving the integration of the capacitor C.

[0144] Figure 5 For along Figure 2 Another cross-sectional view of the section line A-A' in FIG. Figure 6 Bit Figure 5 The dotted box D in the figure corresponds to the enlarged view of the structure.

[0145] In some embodiments, Figure 5 and Figure 6 As shown, the semiconductor device 100 includes a plurality of memory cell layers M1 and a plurality of second insulating layers M2 , which are stacked and alternately arranged in a third direction Z.

[0146] See also Figure 6 A second insulating layer M2 is disposed between two adjacent memory cell layers M1, thereby achieving electrical insulation between the two adjacent memory cell layers M1 and preventing the two second conductive layers 12 belonging to the two capacitors C from being short-circuited.

[0147] Among them, see Figure 6 Each memory cell layer M1 includes a first conductive layer 11 , a first insulating layer 13 and a second conductive layer 12 .

[0148] The first insulating layer 13 is disposed around the first conductive layer 11 , and the second conductive layer 12 is disposed around the first insulating layer 13 .

[0149] It should be noted that the aforementioned “surrounded” is used to describe the relative positional relationship among the first conductive layer 11, the first insulating layer 13 and the second conductive layer 12, but is not limited to “the first conductive layer 11 is completely surrounded by the first insulating layer 13” or “the first insulating layer 13 is completely surrounded by the second conductive layer 12”. For example, at the position where the first conductive layer 11 is connected to the first contact structure 2, there must be an unsurrounded portion of the first conductive layer 11 to facilitate the connection between the first conductive layer 11 and the first contact structure 2.

[0150] For example, see Figure 6 The first insulating layer 13 surrounds the upper and lower surfaces and the left side of the first conductive layer 11 , while the right side of the first conductive layer 11 is not surrounded, so that the first conductive layer 11 can be connected to the first contact structure 2 .

[0151] See also Figure 6 In the stacking direction (ie, the third direction Z) of the stacking structure 1, two second conductive layers 12 are provided between two adjacent first conductive layers 11. It can be understood that the "two second conductive layers 12" herein belong to two memory cell layers M1.

[0152] In this embodiment, one memory cell layer M1 may form one capacitor C.

[0153] See also Figure 6 In this embodiment, one plate of the capacitor C (e.g., the second conductive layer 12) is arranged around another plate (e.g., the first conductive layer 11), that is, multiple sides (e.g., six sides of a rectangle, or e.g., Figure 6 The five side surfaces except the right side surface can all form the effective capacitance area of ​​the capacitor C, further increasing the effective facing area of ​​the capacitor C and improving the capacitance of the capacitor C per unit area.

[0154] Figure 7 for Figure 3 The dotted box E in the figure corresponds to the enlarged view of the structure. Figure 8 for Figure 5 The enlarged view of the structure corresponding to the dotted box F in FIG.

[0155] In some embodiments, Figure 7 and Figure 8 As shown, the first contact structure 2 includes a first dielectric layer 21 and a first conductive column 22 .

[0156] Among them, see Figure 7 and Figure 8 , the first conductive column 22 passes through the stack structure 1 .

[0157] Exemplarily, the material of the first conductive pillar 22 may include metal conductive materials such as copper, aluminum, silver, etc., or may also include doped semiconductor materials, or may also include other materials with conductive properties.

[0158] See also Figure 7 and Figure 8 At least a portion of the first dielectric layer 21 is located between the second conductive layer 12 and the first conductive pillar 22 , so as to achieve electrical insulation between the first contact structure 2 and the second conductive layer 12 .

[0159] For example, see Figure 7 and Figure 8 The first dielectric layer 21 surrounds the side surface of the first conductive column 22, which is the side surface whose extension direction intersects with the substrate B2 (for example Figure 7 On the left side surface or the right side surface of the first conductive column 22).

[0160] Among them, see Figure 7 and Figure 8 , a plurality of first conductive layers 11 penetrate the first dielectric layer 21 and are connected to the first conductive pillars 22 , and the second conductive layers 12 and the first conductive pillars 22 are insulated by the first dielectric layer 21 .

[0161] The first conductive pillar 22 is used to transmit external electrical signals to each first conductive layer 11 of the stacked structure 1, and the first dielectric layer 21 is used to achieve electrical insulation between the first conductive pillar 22 and the second conductive layer 12, so that the first conductive pillar 22 transmits the external electrical signal only to the first conductive layer 11, thereby realizing charging of one of the two plates of the multiple memory cells C.

[0162] For example, see Figure 7 and Figure 8 , the first dielectric layer 21 may include a plurality of first sub-portions 211 .

[0163] See also Figure 7 and Figure 8 The multiple first sub-portions 211 are arranged in sequence along the stacking direction (i.e., the third direction Z) of the stacking structure 1, and at least part of the first sub-portion 211 is located between the second conductive layer 12 and the first conductive column 22, thereby realizing electrical insulation between the second conductive layer 12 and the first conductive column 22, and at least part of the first conductive layer 11 is arranged between two adjacent layers of the first sub-portion 211, thereby facilitating electrical connection between the first conductive layer 11 and the first conductive column 22.

[0164] It is understandable that the specific location of the first sub-section 211 may be adaptively adjusted according to different requirements or preparation processes.

[0165] For example, see Figure 7 In the case where the first conductive layer 11 and the second conductive layer 12 are alternately arranged, the first sub-portion 211 can be arranged in the same layer as the second conductive layer 12 .

[0166] Or, for example, see Figure 8 In the case where the semiconductor device 100 includes a memory cell layer M1, every two first sub-portions 211 are arranged in the same memory cell layer M1, and the two first sub-portions 211 are arranged on both sides of the first conductive layer 11 away from the substrate B2 and close to the substrate B2, so that the second conductive layer 12 located on both sides of the first conductive layer 11 is insulated from the first conductive pillars 22.

[0167] For example, in other embodiments, the first dielectric layer 21 may also be provided as a whole layer (relative to the first dielectric layer 21 being divided into a plurality of first sub-portions 211, which is not shown in the figure), and only the first conductive layer 11 penetrates the first dielectric layer 21. For example, holes are punched in the first dielectric layer 21 in a direction parallel to the substrate B2, so that the conductive material of the first conductive layer 11 is filled into the holes, thereby achieving conduction between the first conductive layer 11 and the first conductive pillar 22.

[0168] It can be understood that, in addition to the structural design of the aforementioned multiple first sub-sections 211 and the entire layer design of the first dielectric layer 21, any other structural design of the first contact structure 2 that can achieve conduction between the first conductive layer 11 and the first conductive column 22 and insulation between the second conductive layer 12 and the first conductive column 22 is also within the protection scope of the embodiments of the present disclosure, and the embodiments of the present disclosure do not impose any restrictions on this.

[0169] For example, the optional structural variations could be as follows:

[0170] For example, see Figure 7 The first insulating layer 13 may also penetrate the first dielectric layer 21, thereby improving the protection capability of the portion of the first conductive layer 11 that penetrates the first dielectric layer 21, preventing the portion of the first conductive layer 11 from being damaged externally, and preventing the first conductive layer 11 from having unexpected electrical connections.

[0171] Optionally, the first insulating layer 13 may also be disposed on a side of the first dielectric layer 21 away from the first conductive pillar 22 (eg, Figure 8 as shown, or in Figure 7 deformation of the structure).

[0172] For example, see Figure 8 The second insulating layer M2 may also penetrate the first dielectric layer 21, for example Figure 8 In the embodiment, at least a portion of the second insulating layer M2 may also be disposed between two adjacent first sub-portions 211 .

[0173] Similarly, optionally, the second insulating layer M2 may also be disposed on a side of the first dielectric layer 21 away from the first conductive pillar 22 .

[0174] Fig. 9 , Fig.11 and Fig.12 for Figure 3 Enlarged views of some structures corresponding to the dotted box H in FIG. Fig.10 for Figure 5 The dotted box I in the figure corresponds to an enlarged view of the structure.

[0175] In some embodiments, Figures 9 to 12As shown, the second contact structure 3 includes a second dielectric layer 31 , a second conductive column 32 and a first conductive block 33 .

[0176] Among them, see Figures 9 to 12 , the first conductive block 33 is connected to the corresponding second conductive layer 12 .

[0177] For example, see Fig. 9 When the first conductive layers 11 and the second conductive layers 12 are alternately arranged in sequence, the first conductive blocks 33 are located in the same layer as the corresponding second conductive layers 12 and are connected to the corresponding second conductive layers 12 .

[0178] For example, see Fig.10 In the case where the semiconductor device 100 includes multiple memory cell layers M1, the first conductive block 33 is located in the same layer as the corresponding memory cell layer M1 and is connected to the corresponding memory cell layer M1. For example, see Fig.10 The first conductive block 33 is connected to the second conductive layer 12 in the corresponding memory cell layer M1.

[0179] It should be noted that the “corresponding” mentioned in the embodiments of the present disclosure means that the second contact structure 3 and the structure to be connected or controlled by it correspond to each other. For example, among multiple second contact structures 3, different second contact structures 3 are respectively connected to different second conductive layers 12, then “the second conductive layer 12 corresponding to the second contact structure 3” refers to a second conductive layer 12 to be controlled by the second contact structure 3 among multiple second conductive layers 12. Or for example, “the storage unit layer M1 corresponding to the second contact structure 3” refers to a storage unit layer M1 where a second conductive layer 12 to be controlled by the second contact structure 3 is located among multiple second conductive layers 12.

[0180] See also Figures 9 to 12 The second conductive column 32 at least penetrates the stack structure 1 to the corresponding second conductive layer 12 and is connected to the first conductive block 33, so as to facilitate the transmission of the external electrical signal to the second conductive layer 12 through the second conductive column 32 and the first conductive block 33 in sequence.

[0181] For example, see Fig. 9 and Fig.10 The second conductive pillar 32 can completely penetrate the stack structure 1 and be connected to the first conductive block 33 in the film layer where the corresponding second conductive layer 12 is located.

[0182] Or, for example, see Fig.11 and Fig.12 The second conductive pillar 32 may only penetrate the stacked structure 1 to the corresponding second conductive layer 12 and be connected to the first conductive block 33 .

[0183] See also Figures 9 to 12At least a portion of the second dielectric layer 31 is located between the second conductive layer 12 excluding the corresponding second conductive layer 12 and the second conductive pillar 32 .

[0184] That is, the second dielectric layer 31 can at least achieve electrical insulation between the second conductive pillars 32 and the second conductive layers 12 other than the corresponding second conductive layer 12 , so that the electrical signal transmitted by the second conductive pillars 32 is only transmitted to the corresponding second conductive layer 12 .

[0185] For example, Fig. 9 and Fig.10 As shown, the second dielectric layer 31 may include a plurality of second sub-portions 311 arranged in sequence along the stacking direction (ie, the third direction Z) of the stacking structure 1, and at least a portion of the second sub-portion 311 is located between the second conductive layer 12 other than the corresponding second conductive layer 12 and the second conductive column 32.

[0186] For example, see Fig. 9 In the case where the first conductive layers 11 and the second conductive layers 12 are alternately arranged in sequence, the second sub-portion 311 is arranged in the same layer as the second conductive layers 12 except for the corresponding second conductive layers 12 .

[0187] For example, see Fig.10 In the case where the semiconductor device 100 includes a plurality of memory cell layers M1 , the second sub-portion 311 is disposed at the same layer as the memory cell layers M1 except for the corresponding memory cell layer M1 .

[0188] Or, for example, Fig.11 As shown, the second dielectric layer 31 may be provided as a whole layer (relative to the second dielectric layer 31 being divided into a plurality of second sub-sections 311 ).

[0189] See also Fig.11 In the case where the second dielectric layer 31 is provided as a whole layer, at least a portion of the second dielectric layer 31 is located between the second conductive pillar 32 and the second conductive layer 12 other than the corresponding second conductive layer 12, and at least a portion of the second dielectric layer 31 is also located between the second conductive pillar 32 and the first conductive layer 11, thereby achieving not only electrical insulation between the second conductive pillar 32 and the second conductive layer 12 other than the corresponding second conductive layer 12, but also electrical insulation between the second conductive pillar 32 and the first conductive layer 11.

[0190] Understandably, Fig.11It is only exemplarily shown that in the case where the first conductive layer 11 and the second conductive layer 12 are alternately arranged in sequence, the second dielectric layer 31 is a structural design arranged as a whole layer. In other structures, the second dielectric layer 31 can also be arranged as a whole layer. For example, in the case where the semiconductor device 100 includes a storage unit layer M1, the second dielectric layer 31 can also be arranged as a whole layer (not shown in the figure).

[0191] In some embodiments, Fig. 9 As shown, in the case where the first conductive layers 11 and the second conductive layers 12 are alternately arranged in sequence, the semiconductor device 100 may further include a plurality of third sub-portions 31A.

[0192] See also Fig. 9 The plurality of third sub-portions 31A may be spaced apart along the third direction Z, and each third sub-portion 31A may be located between the second conductive pillar 32 and the first conductive layer 11 , so as to achieve electrical insulation between the second conductive pillar 32 and the first conductive layer 11 .

[0193] Exemplarily, similar to the second sub-portion 311 , the third sub-portion 31A may be independently disposed between the second conductive pillar 32 and the first conductive layer 11 (not shown in the figure).

[0194] Or, for example, see Fig.11 The portion of the second dielectric layer 31 disposed as a whole and located between the second conductive pillar 32 and the first conductive layer 11 can serve as the third sub-portion 31A.

[0195] Or, for example, see Fig.12 The first insulating layer 13 can be made of the same material as the third sub-portion 31A, for example, the two can be integrally arranged, that is, in this embodiment, the first insulating layer 13 can be arranged around the first conductive layer 11, wherein the portion of the first insulating layer 13 located between the first conductive layer 11 and the second conductive column 32 can serve as the third sub-portion 31A.

[0196] Understandably, see Fig.10 In the case where the semiconductor device 100 includes a memory cell layer M1, the first conductive layer 11 is surrounded by the first insulating layer 13 and the second conductive layer 12 in the inner layer. Therefore, there is no need to separately design an insulating structure between the first conductive layer 11 and the second conductive column 32 (similar to the third sub-portion 31A), thereby simplifying the preparation process of the second contact structure 3.

[0197] In other embodiments, the first conductive layer 11 may be disposed around the first insulating layer 13, and the first insulating layer 13 may be disposed around the second conductive layer 12. Fig.10In contrast to the structure shown, in the memory cell layer M1, the first conductive layer 11 may be located at the outer layer, and the second conductive layer 12 may be located at the inner layer. The present application does not limit the relative positional relationship between the first conductive layer 11 and the second conductive layer 12 in the memory cell layer M1.

[0198] Exemplarily, when the first conductive layer 11 can be arranged around the first insulating layer 13, and the first insulating layer 13 can be arranged around the second conductive layer 12, one end of the second conductive layer 12 facing the second conductive column 32 can pass through the first insulating layer 13 and the first conductive layer 11 and then be connected to the second conductive column 32, and at this time, the second dielectric layer 31 can be arranged between the first conductive layer 11 and the second conductive column 32 to achieve electrical insulation.

[0199] In some embodiments, Figure 3 and Figure 5 As shown, the semiconductor device 100 may further include a transistor 5 .

[0200] See also Figure 3 and Figure 5 The transistor 5 is arranged on one side of the stack structure 1 , and each transistor 5 is connected to a corresponding second contact structure 3 .

[0201] For example, see Figure 3 and Figure 5 The transistor 5 is electrically connected to an end of the second conductive column 32 in the second contact structure 3 that is away from the substrate B2 .

[0202] The transistor 5 is used to control the input of the electrical signal of the second contact structure 3. For example, when the transistor 5 is turned on, the external electrical signal can be transmitted to the second contact structure 3 connected to the transistor 5, thereby charging the second conductive layer 12 connected to the second contact structure 3 to achieve information storage.

[0203] For example, Figure 3 and Figure 5 As shown, the transistor 5 may include a source 51 , a drain 52 , a gate 53 , a gate oxide layer 54 and a semiconductor portion 55 .

[0204] Among them, see Figure 3 and Figure 5 The source 51 and the drain 52 are respectively arranged at the two ends of the semiconductor portion 55, and the gate oxide layer 54 is arranged between the semiconductor portion 55 and the gate 53. Under the control of the gate 53, a channel can be formed in the semiconductor portion 55, so as to realize the conduction between the source 51 and the drain 52, that is, to realize the opening of the transistor 5. On the contrary, under the control of the gate 53, no channel is formed in the semiconductor portion 55, so that the transistor 5 is closed.

[0205] It is understandable that the structures of the aforementioned “source 51 ” and “drain 52 ” can be completely the same, and their positions can be interchanged according to design requirements, which is not limited in the embodiments of the present disclosure.

[0206] For example, see Figure 3 and Figure 5 , the second contact structure 3 may be in electrical contact with the source 51 (or the drain 52 ) of the transistor 5 .

[0207] In some embodiments, Figure 3 and Figure 5 As shown, the semiconductor device 100 may further include a gate line layer C1 and a plurality of bit lines 62 .

[0208] Among them, see Figure 3 and Figure 5 The gate line layer C1 is disposed on one side of the stack structure 1 , for example, on a side of the stack structure 1 away from the substrate B2 .

[0209] For example, see Figure 3 and Figure 5 An insulating material is provided between the gate line layer C1 and the stacked structure 1 to avoid unexpected electrical connection between the two.

[0210] See also Figure 3 and Figure 5 , the gate line layer C1 includes at least one gate line 61 .

[0211] For example, see Figure 3 and Figure 5 The semiconductor portion 55 of the transistor 5 passes through the gate line 61 , so that at least a portion of the gate line 61 (ie, the gate 53 ) has a facing area with the semiconductor portion 55 , thereby facilitating the control of forming a channel in the semiconductor portion 55 and realizing the opening of the transistor 5 .

[0212] Understandably, see Figure 3 and Figure 5 A portion of the gate line 61 close to the semiconductor portion 55 serves as the gate 53 of the transistor 5 , and a gate oxide layer 54 is provided between the semiconductor portion 55 and the gate line 61 .

[0213] The gate line 61 is used to transmit a gate signal to the transistor 5 (eg, to the gate 53 ) in the semiconductor device 100 , so as to control the on and off of the transistor 5 .

[0214] See also Figure 3 and Figure 5 The plurality of bit lines 62 are disposed on a side of the gate line layer C1 away from the stack structure 1 and are insulated from the gate line layer C1 .

[0215] For example, see Figure 3 and Figure 5 An insulating material may be provided between the film layer where the plurality of bit lines 62 are located and the gate line layer C1 , thereby achieving electrical insulation between the bit lines 62 and the gate lines 61 .

[0216] Understandably, see Figure 3 and Figure 5 The bit line 62 is connected to the drain 52 (or source 51) of the transistor 5, so that when the transistor 5 is turned on, the bit line 62 transmits an external electrical signal to the transistor 5, and the external electrical signal is transmitted from the drain 52 of the transistor 5 to the source 51, and finally transmitted to the second conductive layer 12 corresponding to the second contact structure 3, completing the charging and discharging of the capacitor C where the second conductive layer 12 is located.

[0217] For example, see Figure 3 and Figure 5 The first contact structure 2 penetrates the gate line layer C1 and is insulated from the gate line 61 , so that the first contact structure 2 can access external signals without affecting the signal transmission of the gate line 61 and transmit them to the first conductive layer 11 , so as to realize charging and discharging of the first conductive layer 11 .

[0218] For example, see Figure 3 and Figure 5 The semiconductor device 100 may include a third insulating layer 63, which may be disposed in the same layer as the gate line layer C1, and the third insulating layer 63 is disposed around the first conductive pillar 22 of the first contact structure 2, thereby achieving electrical insulation between the gate line 61 in the gate line layer C1 and the first contact structure 2.

[0219] For example, see Figure 3 and Figure 5 The semiconductor device 100 may further include a first signal line L1, which is electrically connected to an end of the first contact structure 2 away from the substrate B2, and is used to transmit an electrical signal to the first conductive layer 11 connected to the first contact structure 2 to realize charging and discharging of the first conductive layer 11.

[0220] For example, see Figure 3 and Figure 5 The semiconductor device 100 may further include a second signal line L2 , wherein the second signal line L2 is connected to the gate line 61 and is used to transmit a gate line signal to the gate line 61 .

[0221] Fig.13 Another top view of the semiconductor device 100 provided in the embodiment of the present disclosure, Fig.14 is an equivalent circuit diagram corresponding to the semiconductor device 100.

[0222] In some embodiments, Fig.13As shown, the semiconductor device 100 may include a plurality of transistors 5 .

[0223] See also Fig.13 The multiple transistors 5 are arranged in an array along a first direction X and a second direction Y, wherein the multiple transistors 5 arranged along the first direction X are called a row of transistors 5, and the multiple transistors 5 arranged along the second direction Y are called a column of transistors 5.

[0224] For example, see Figure 3 , Figure 5 and Fig.13 , multiple transistors 5 in the same row can share the same gate line 61 , so that they can be synchronously turned on or off under the control of the gate line 61 .

[0225] For example, see Fig.13 In the case where a plurality of transistors 5 are arranged in an array, the semiconductor device 100 may further include a plurality of gate lines 61 and a plurality of bit lines 62, wherein Fig.13 , a plurality of gate lines 61 may be arranged at intervals along the second direction Y, and a plurality of bit lines 62 may be arranged at intervals along the first direction X.

[0226] See also Fig.14 One plate (i.e., the first conductive layer 11) of each capacitor C in the storage module G is connected to the first signal line L1, and the other plate (i.e., the second conductive layer 12) is connected to a bit line 62 through a corresponding transistor 5, thereby facilitating charging and discharging of the capacitor C.

[0227] See also Fig.14 The electrical signal transmitted by the bit line 62 is controlled by the transistor 5. When the transistor 5 is turned on, the electrical signal transmitted by the bit line 62 is smoothly transmitted to the capacitor C.

[0228] See also Fig.13 and Fig.14 It can be understood that by transmitting an electrical signal to a gate line 61, a row of transistors 5 corresponding to the gate line 61 can be selected, thereby turning on the row of transistors 5. By transmitting an electrical signal to a bit line 62, a column of transistors 5 corresponding to the bit line 62 can be selected, and the gate line 61 and the bit line 62 jointly confirm the address of the capacitor C to be accessed.

[0229] For example, see Fig.13 and Fig.14 , the plurality of transistors 5 in at least one memory module G can synchronously input a bit line signal (ie, an external electrical signal transmitted by the bit line 62), for example, see Fig.13 , three bit lines 62 corresponding to at least three transistors 5 are connected to each other, or for example, see Fig.14Every three capacitors C can be connected to the same bit line 62, so that in a storage module G, multiple capacitors C can be selected at the same time, so that the semiconductor device 100 can meet various storage scenarios.

[0230] In some embodiments, the semiconductor device 100 may further include peripheral devices (not shown in the figure, for example, the peripheral circuit may include Figure 3 or Figure 5 The metal conductive layer C2 shown in FIG.

[0231] The peripheral device may be disposed on a side of the transistor 5 away from the stack structure 1 , or may be disposed on a side of the stack structure 1 away from the transistor 5 , which is not limited in the present disclosure.

[0232] The peripheral device may include at least a peripheral circuit. The peripheral circuit may be any suitable digital, analog, and / or mixed signal control and sensing circuit, including but not limited to a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a gate driver), a charge pump, a current or voltage reference, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). The peripheral circuit may also include any other circuit compatible with an advanced logic process, including a logic circuit (e.g., a processor and a programmable logic device (PLD)) or other storage circuits.

[0233] The aforementioned second contact structure 3 and transistor 5 and other structures can be connected to a peripheral device, and the peripheral device is used to control access to a specific storage unit (such as a 1T1C structure) in the semiconductor device 100. For example, the peripheral device can control writing data to the storage unit, or control reading data from the storage unit.

[0234] Exemplarily, the peripheral devices may include a word line selection circuit, a bit line selection circuit, a control circuit, and a read / write circuit.

[0235] In order to prepare the semiconductor device 100 , the embodiment of the present disclosure further provides a method for preparing the semiconductor device 100 .

[0236] Figures 15 to 20 A flow chart of the preparation of a semiconductor device 100 provided in an embodiment of the present disclosure, Figure 21 to Figure 56 1 and 2 are cross-sectional views corresponding to various preparation steps of the semiconductor device 100 .

[0237] like Fig.15 As shown, the method for preparing the semiconductor device 100 includes the following steps S1 to S3:

[0238] S1: forming a stacking structure 1.

[0239] For example, see Fig.40 and Fig.54 The stacked structure 1 includes a plurality of first insulating layers 13, a plurality of first conductive layers 11 and a plurality of second conductive layers 12. The first conductive layers 11 and the second conductive layers 12 are stacked, and the first insulating layer 13 is arranged between the first conductive layers 11 and the second conductive layers 12.

[0240] For example, Fig.16 As shown, step S1 may include steps S11 to S14:

[0241] S11: See Fig.21 , forming an initial stacking structure 1'.

[0242] See also Fig.21 The initial stacked structure 1' includes first functional layers A1 and second functional layers A2 which are alternately stacked.

[0243] For example, see Fig.21 , the initial stacking structure 1 ′ may be disposed on a substrate B1 .

[0244] Exemplarily, the material of the first functional layer A1 may include silicon oxide or polysilicon.

[0245] Exemplarily, the material of the second functional layer A2 may include silicon nitride, thereby having better insulation properties.

[0246] S12: Fig. 27 and Fig.34 As shown, a first opening K1 is formed penetrating the initial stacking structure 1 ′.

[0247] For example, see Fig.34 The first opening K1 completely penetrates the initial stacking structure 1 ′.

[0248] For example, see Fig.33 and Fig.34 In order to facilitate the subsequent filling of the first conductive layer 11 and the second conductive layer 12 through the first opening K1, the step of preparing the first opening K1 may include forming a first opening K1 that penetrates the initial stacking structure 1' (see Fig.33 ), and then the hole wall of the first opening K1 is laterally etched to increase the hole diameter of the first opening K1 (see Fig.34 ).

[0249] S13: Fig.35 and Fig.47 As shown, the first functional layer A1 is removed through the first opening K1 to form a first receiving cavity Q1.

[0250] See also Fig.35 and Fig.37 After removing the first functional layer A1, a first accommodating cavity Q1 is formed between two adjacent second functional layers A2, which is convenient for subsequent deposition or filling of conductive materials.

[0251] It is understandable that the first functional layer A1 can be removed by injecting etching solution through the first opening K1.

[0252] S14: Fig.38 or Fig.48 As shown, a conductive material is deposited on the inner wall of the first receiving cavity Q1 to form a first conductive layer 11 or a second conductive layer 12 .

[0253] For example, Fig.17 and Fig.38 As shown, step S14 may include:

[0254] S141: See Fig.38 A conductive film is deposited on the inner wall of the first receiving cavity Q1 to form a second conductive layer 12 .

[0255] like Fig.17 In the case where step S14 includes step S141, forming the stacking structure 1 (ie, step S1) may further include:

[0256] S15: See Fig.39 A first insulating layer 13 is formed on a side of the second conductive layer 12 away from the inner wall of the first accommodation cavity Q1 .

[0257] S16: See Fig.40 A first conductive layer 11 is formed on a side of the first insulating layer away from the inner wall of the first accommodating cavity Q1.

[0258] For example, see Fig.40 The first conductive layer 11 may include a first sublayer 111 and a second sublayer 112. In step S16, the first sublayer 111 may be deposited first, and then the second sublayer 112 may be filled in the remaining space.

[0259] It can be understood that in this embodiment, the first conductive layer 11 and the second conductive layer 12 are both formed in the first receiving cavity Q1, and the first insulating layer 13 can be arranged around the first conductive layer 11, and the second conductive layer 12 can be arranged around the first insulating layer 13, that is, a storage unit layer M1 is formed.

[0260] Exemplarily, it can be understood that, in this case, the second functional layer A2 is used as the second insulating layer M2 to achieve electrical insulation between two adjacent memory cell layers M1.

[0261] For example, see Figures 35 to 40In this embodiment, the thickness of the first functional layer A1 is greater than the thickness of the second functional layer A2, so that after the first functional layer A1 is removed to form the first accommodating cavity Q1, it is ensured that the space of the accommodating cavity Q1 can accommodate the first conductive layer 11 and the second conductive layer 12 at the same time.

[0262] In this embodiment, the capacitor C (eg, the memory cell layer M1 ) can be fabricated by only removing the first functional layer A1 . The process steps are simple and the fabrication efficiency can be effectively improved.

[0263] Or, for example, Fig.18 and Fig.48 As shown, step S14 may include:

[0264] S142: See Fig.48 , depositing a conductive material in the first receiving cavity Q1 so that the conductive material fills the first receiving cavity Q1 to form one of the first conductive layer 11 and the second conductive layer 12 ( Fig.48 In the figure, the step S142 of forming the second conductive layer 12 is taken as an example).

[0265] For example, see Fig.48 The second conductive layer 12 may include a first sublayer 111 and a second sublayer 112. In step S142, the first sublayer 111 may be deposited first, and then the second sublayer 112 may be filled in the remaining space.

[0266] It can be understood that the second sub-layer 112 completely fills the remaining cavity, so that the aforementioned first receiving cavity Q1 is fully filled, thereby preventing the film layer structure from collapsing and improving the structural stability of the semiconductor device 100 .

[0267] Exemplarily, when the second conductive layer 12 includes only one sublayer (eg, only the first sublayer 111 ), the process of preparing the second conductive layer 12 includes: directly depositing a conductive film, such as a tungsten metal film, on the inner wall of the first receiving groove U1 .

[0268] like Fig.18 In the case where step S14 includes step S142, forming the stacking structure 1 (ie, step S1) may further include:

[0269] S17: See Fig.51 , remove the second functional layer A2 through the first opening K1 to form a second accommodating cavity Q2.

[0270] S18: See Fig.53 , an insulating material is deposited on the inner wall of the second receiving cavity Q2 to form a first insulating layer 13 .

[0271] S19: See Fig.54, a conductive material is deposited on one side of the first insulating layer 13 away from the inner wall of the second accommodation cavity Q2 to form the other of the first conductive layer 11 and the second conductive layer 12 ( Fig.54 In the example, step S19 to form the first conductive layer 11 is taken as an example).

[0272] For example, see Fig.54 In this embodiment, the first insulating layer 13 can be arranged around the first conductive layer 11, so as to avoid unexpected electrical connection between the first conductive layer 11 and other conductive structures (such as the second contact structure 3 prepared subsequently).

[0273] It can be understood that, in this embodiment, one of the first conductive layer 11 and the second conductive layer 12 is formed in the first accommodating cavity Q1, and the other is formed in the second accommodating cavity Q2, that is, the aforementioned first functional layer A1 is used to replace the formation of one of the first conductive layer 11 and the second conductive layer 12, and the aforementioned second functional layer A2 is used to replace the formation of the other of the first conductive layer 11 and the second conductive layer 12.

[0274] Exemplarily, it can be understood that the thickness of the first functional layer A1 in this embodiment can be substantially the same as the thickness of the second functional layer A2, that is, the first accommodating cavity Q1 and the second accommodating cavity Q2 formed only need to be filled with one of the first conductive layer 11 and the second conductive layer 12, so there is no need to set the first accommodating cavity Q1 and the second accommodating cavity Q2 with larger thickness. On the one hand, the difficulty of preparation is reduced, and on the other hand, the first accommodating cavity Q1 and the second accommodating cavity Q2 with smaller thickness can correspond to the first opening K1 with smaller size, thereby effectively improving the utilization rate of the design space in the plane where the first direction X and the second direction Y are located in the semiconductor device 100.

[0275] S2: forming a first contact structure 2.

[0276] See also Fig.43 and Fig.55 The first contact structure 2 may include a first dielectric layer 21 and a first conductive pillar 22 .

[0277] For example, see Fig.19 , the step S2 may include:

[0278] S21: Fig.41 and Fig.49 As shown, a portion of the second conductive layer 12 close to the first opening K1 is removed through the first opening K1 to form a first receiving groove U1.

[0279] For example, see Fig.41This step S21 is performed after step S16, so that the end of the first conductive layer 11 facing the first opening K1 can protrude from the second conductive layer 12, which facilitates the subsequent electrical connection between the first conductive layer 11 and the first conductive column 22 and the electrical insulation between the second conductive layer 12 and the first conductive column 22.

[0280] Or, for example, see Fig.49 Step S21 is performed after step S142 and before step S17, so that electrical isolation of the end of the second conductive layer 12 facing the first opening K1 can be achieved after the second conductive layer 12 is formed and before the first conductive layer 11 is formed, thereby effectively preventing the second conductive layer 12 from being damaged during the process of forming the first conductive layer 11.

[0281] S22: Fig.42 and Fig.50 As shown, the first receiving groove U1 is filled with insulating material to form a first dielectric layer 21 .

[0282] For example, see Fig.42 and Fig.50 , the first dielectric layer 21 may include a plurality of first sub-portions 211 .

[0283] S23: Fig.43 and Fig.55 As shown, the first opening K1 is filled with a conductive material to form a first conductive column 22 .

[0284] It is understandable that step S23 is performed after the first conductive layer 11 and the second conductive layer 12 are prepared to prevent the first conductive column 22 from blocking the first opening K1, resulting in the functional layer (first functional layer A1 or second functional layer A2) being unable to be replaced by the conductive layer (first conductive layer 11 or second conductive layer 12).

[0285] That is, the process of preparing the first contact structure 2 can be compatible with the process of preparing the stacked structure 1 . For example, the first opening K1 can be used together to achieve preparation, thereby effectively saving process steps and improving preparation efficiency.

[0286] S3: forming a plurality of second contact structures 3.

[0287] See also Fig.32 The second contact structure 3 may include a second dielectric layer 31 , a second conductive column 32 and a first conductive block 33 .

[0288] Exemplarily, the step of forming multiple first contact structures 2 can be performed after forming the first conductive layer 11 and the second conductive layer 12, or before forming the first conductive layer 11 and the second conductive layer 12. The embodiment of the present application only exemplarily provides an implementation method in which the step of forming the first contact structure 2 is performed before forming the first conductive layer 11 and the second conductive layer 12. It can be understood that other preparation processes for the first contact structure 2 are also within the protection scope of the embodiment of the present application. The embodiment of the present application does not limit the preparation order of the first contact structure 2.

[0289] For example, see Fig. 20 After the initial stacking structure 1' is formed, the step S3 may include steps S31 to S35:

[0290] S31: See Fig. 22 and Fig. 27 , forming a second opening K2.

[0291] See also Fig. 22 The second opening H2 at least penetrates the initial stacking structure 1 ′ to the corresponding first functional layer A1 .

[0292] It should be noted that, in this embodiment, only the first functional layer A1 is used in a subsequent step to form a second conductive layer 12 (including a separate second conductive layer 12, or a second conductive layer 12 in the storage unit layer M1) as an example to exemplarily illustrate the preparation process of the second contact structure 3. It can be understood that, when the first functional layer A1 is subsequently used to replace the first conductive layer 11, and the second functional layer A2 is subsequently used to replace the second conductive layer 12, in this step, the second opening H2 at least penetrates the initial stacking structure 1' to the corresponding second functional layer A2, so as to facilitate the electrical connection between the first conductive block 33 in the second contact junction 3 and the second conductive layer 12, that is, to facilitate the second contact structure 3 formed in this step to transmit electrical signals to the corresponding second conductive layer 12.

[0293] S32: See Fig.25 , through the second opening K2, remove the corresponding portion of the first functional layer A1 close to the second opening K2 to form a second receiving groove U2.

[0294] S33: See Fig.26 , filling the second receiving groove U2 with conductive material to form a first conductive block 33 .

[0295] S34: See Fig.23 and Fig.31 , a second dielectric layer 31 is formed through the second opening K2.

[0296] See also Fig.23 and Fig.31At least part of the second dielectric layer 31 is disposed in the first functional layer A1 penetrated by the second opening K2, on one side of the first functional layer A1 close to the second opening K2 except for the corresponding first functional layer A1.

[0297] For example, see Fig.23 and Fig.31 , the second dielectric layer 31 may include a plurality of second sub-portions 311 .

[0298] Exemplarily, step S34 may include: oxidizing, through the second opening K2 , a portion of the first functional layer A1 close to the second opening K2 except for the corresponding first functional layer A1 among the multiple first functional layers A1 penetrated by the second opening K2 to form the second sub-portion 311 .

[0299] S35: See Fig.32 , a conductive material is filled into the second opening K2 to form a second conductive column 32 .

[0300] For example, the second conductive pillar 32 may only penetrate the initial stacking structure 1' to the corresponding first functional layer A1, that is, the second opening H2 may only penetrate a portion of the initial stacking structure 1' (see the aforementioned Fig.11 ).

[0301] Or, for example, see Fig.32 The second conductive pillar 32 may penetrate the entire initial stacking structure 1 ′.

[0302] For example, when the second conductive pillar 32 passes through the entire initial stacking structure 1 ′, the second opening K2 may be formed in stages, for example:

[0303] See also Fig. 22 First, the second opening K2 is made to penetrate a portion of the initial stacking structure 1 ′.

[0304] See also Fig.23 ,exist Fig. 22 The side of the portion of the first functional layer A1 through which the second opening K2 passes, which faces the second opening K2, forms a portion of the second dielectric layer 31 (eg, forms a portion of the second sub-portion 311 ).

[0305] See also Fig.24 , further increasing the depth of the second opening K2 so that the bottom of the second opening K2 is located in the corresponding first functional layer A1, so as to form the first conductive block 33 in the corresponding first functional layer A1 (see Fig.25 and Fig.26 ).

[0306] See also Fig. 27After forming the first conductive block 33 , the depth of the second opening K2 is increased again, so that the second opening K2 runs through the entire initial stacking structure 1 ′.

[0307] For example, see Fig. 27 In this step, the first opening K1 can be formed synchronously so that the process steps of preparing the second contact structure 3 can be partially compatible with the process steps of preparing the stacking structure 1 and the process steps of preparing the first contact structure 2, thereby saving the process steps of drilling and improving the preparation efficiency.

[0308] For example, see Fig.28 , Fig.29 and Fig.30 Before continuing to prepare the second contact structure 3, the first opening K1 may be filled and covered, for example, see Fig.28 First, fill the first opening K1 and the second opening K2 with the intermediate material D1, see Fig.29 Then, a cover D2 is provided on the side of the first opening K1 and the second opening K2 away from the substrate B1, see Fig.30 Then, only the cover D2 of the second opening K2 is opened, and the intermediate material D1 filled in the second opening K2 is removed. This process can prevent the process steps of preparing the second contact structure 3 from affecting the subsequent preparation of the stacked structure 1 and the first contact structure 2.

[0309] See also Fig.31 , the preparation of the remaining portion of the second dielectric layer 31 is completed through the second opening K2.

[0310] In some embodiments, Fig.46 and Fig.56 As shown, the method for preparing the semiconductor device 100 may further include:

[0311] S4: forming a plurality of transistors 5.

[0312] See also Fig.46 and Fig.56 , the transistor 5 is arranged at one side of the stack structure 1, and the plurality of transistors 5 are connected one-to-one with the plurality of second contact structures 3. That is, each transistor 5 is connected with one second contact structure 3.

[0313] Exemplarily, the transistor 5 may be disposed on a side of the stack structure 1 close to the substrate B1 , or may be disposed on a side of the stack structure 1 far from the substrate B1 , which is not limited in the embodiment of the present application.

[0314] Exemplarily, the transistor 5 may be prepared after forming the second contact structure 3. For example, the second contact structure 3 may only penetrate a portion of the stacked structure 1, and after the second contact structure 3 is prepared, the transistor 5 is formed on a side of the second contact structure 3 away from the stacked structure 1 that is not penetrated.

[0315] Or, for example, see Fig.21 , Fig.31 , Fig.35 , Fig.36 , Fig.37 As shown in the above figures, the manufacturing process of the transistor 5 can be compatible with the process steps of manufacturing the stacking structure 1 , the first contact structure 2 and the second contact structure 3 .

[0316] For example, step S4 may also include:

[0317] S41: See Fig.21 , forming a third functional layer A3.

[0318] The third functional layer A3 is used to be stacked with the stacked structure 1 formed subsequently. Fig.21 The third functional layer A3 is stacked with the initial stacking structure 1'. The third functional layer A3 is used to replace the gate line 61 in the subsequent steps.

[0319] See also Fig.21 The semiconductor portion 55 penetrates the third functional layer A3.

[0320] S42: See Fig.21 , forming a plurality of semiconductor portions 55.

[0321] The semiconductor portion 55 penetrates the third functional layer A3 . One end of the semiconductor portion 55 facing the stack structure 1 is used to connect with the second contact structure 3 .

[0322] For example, see Fig.21 , the semiconductor portion 55 of the transistor 5 may be formed on the substrate B1 before forming the initial stacked structure 1 ′.

[0323] For example, see Fig.31 After forming the second opening K2 and before filling the second conductive pillar 32 , the portion of the semiconductor portion 55 facing the second opening K2 may be oxidized to form the source 51 .

[0324] S43: See Fig.35 and Fig.51 , a third opening K3 penetrating the third functional layer A3 is opened, and the third functional layer A3 is removed through the third opening K3 to form a third accommodating cavity Q3.

[0325] For example, see Fig.35 and Fig.51 The third opening K3 and the first opening K1 are opened synchronously. For example, the third opening K3 can be equivalent to the first opening K1, that is, the portion of the first opening K1 that passes through the third functional layer A3 can be used as the third opening K3. That is, the steps of preparing the transistor 5 can be compatible with the preparation process of preparing the stacked structure 1 and the preparation process of preparing the first contact structure 2, thereby improving the preparation efficiency.

[0326] For example, see Fig.35 and Fig.51 The step of removing the third functional layer A3 can be performed simultaneously with the step of removing the first functional layer A1 or the step of removing the second functional layer A2 to improve the preparation efficiency.

[0327] S44: See Fig.36 and Fig.52 , a gate oxide layer 54 is deposited on the side of the semiconductor portion 55 perpendicular to the third functional layer A3 through the third receiving cavity Q3.

[0328] S45: filling the third receiving cavity Q3 with a gate material through the third opening K3 to form a gate line 61 (a portion of the gate line 61 close to the gate oxide layer 54 can be used as the gate 53 of the transistor 5).

[0329] For example, see Fig.44 and Fig.56 The method for preparing the semiconductor device 100 may further include forming a metal conductive layer C2 on one side of the stacked structure 1, and the metal conductive layer C2 may be used to form structures such as peripheral circuits.

[0330] For example, see Fig.45 and Fig.56 The method for preparing the semiconductor device 100 may further include turning over the semiconductor device 100 and forming a substrate B2 on a side of the stack structure 1 away from the transistor 5 .

[0331] For example, see Fig.46 and Fig.56 The method for preparing the semiconductor device 100 may further include removing the substrate B1 and oxidizing the end of the semiconductor portion 55 away from the stacked structure 1 to form a drain 52 of the transistor 5, and may further include sequentially forming a bit line 62, a first signal line L1, and a second signal line L2, etc.

[0332] It is understandable that the order of the multiple steps provided in the aforementioned embodiments of the present application can be swapped, or some steps can be performed simultaneously, and the embodiments of the present application are not limited to this.

[0333] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A stacked structure, comprising a plurality of first insulating layers, a plurality of first conductive layers and a plurality of second conductive layers, wherein the first conductive layers and the second conductive layers are stacked, at least one second conductive layer is provided between two adjacent first conductive layers, and the first insulating layer is provided between the first conductive layer and the second conductive layer; A first contact structure, penetrating the stacked structure and connected to the multiple first conductive layers; A plurality of second contact structures penetrate at least a portion of the stacked structure, and each second contact structure is connected to a corresponding second conductive layer.

2. The semiconductor device according to claim 1, wherein: Along the stacking direction of the stacking structure, the first conductive layers and the second conductive layers are alternately arranged in sequence.

3. The semiconductor device according to claim 1, wherein: include: A plurality of memory cell layers, each memory cell layer comprising the first conductive layer, the first insulating layer and the second conductive layer; The first insulating layer is arranged around the first conductive layer, and the second conductive layer is arranged around the first insulating layer; The multi-layer second insulating layer is stacked with the multi-layer memory cell layer and is alternately arranged in sequence.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The first contact structure includes a first dielectric layer and a first conductive column, the first conductive column runs through the stacked structure, and at least a portion of the first dielectric layer is located between the second conductive layer and the first conductive column; The plurality of first conductive layers penetrate the first dielectric layer and are connected to the first conductive pillars, and the second conductive layer and the first conductive pillars are insulated by the first dielectric layer.

5. The semiconductor device according to claim 4, characterized in that The first dielectric layer includes a plurality of first sub-portions sequentially arranged along the stacking direction of the stacking structure, at least part of the first sub-portions is located between the second conductive layer and the first conductive pillar, and at least part of the first conductive layer is disposed between two adjacent first sub-portions.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that: The second contact structure includes a second dielectric layer, a second conductive column and a first conductive block; The first conductive block is connected to the corresponding second conductive layer; The second conductive column at least penetrates the stack structure to the corresponding second conductive layer and is connected to the first conductive block; At least a portion of the second dielectric layer is located between a second conductive layer other than the corresponding second conductive layer and the second conductive pillar.

7. The semiconductor device according to claim 6, characterized in that The second dielectric layer includes a plurality of second sub-portions sequentially arranged along a stacking direction of the stacking structure, and at least a portion of the second sub-portions is located between a second conductive layer other than the corresponding second conductive layer and the second conductive pillar.

8. The semiconductor device according to claim 6, characterized in that In the case where the first conductive layer and the second conductive layer are alternately arranged in sequence, the semiconductor device further includes: A plurality of third sub-portions are arranged at intervals along the stacking direction of the stacking structure, and the third sub-portions are arranged between the second conductive pillar and the first conductive layer.

9. The semiconductor device according to claim 8, characterized in that The first insulating layer is made of the same material as that of the third sub-portion.

10. The semiconductor device according to any one of claims 1 to 3, characterized in that Also includes: A plurality of transistors are arranged on one side of the stack structure, and each transistor is connected to a corresponding second contact structure.

11. The semiconductor device according to claim 10, characterized in that Also includes: A gate line layer is provided on one side of the stacked structure; the gate line layer comprises at least one gate line; A plurality of bit lines are arranged on a side of the gate line layer away from the stack structure and insulated from the gate line layer; The transistor includes a semiconductor portion and a gate oxide layer, the semiconductor portion passes through the gate line, and the gate oxide layer surrounds the side wall of the semiconductor portion that is perpendicular to the gate line layer; among the multiple transistors, one end of the semiconductor portion of each transistor is connected to the second contact structure, and the other end is connected to a corresponding bit line.

12. The semiconductor device according to claim 11, characterized in that The first contact structure passes through the gate line layer and is insulated from the gate line.

13. The semiconductor device according to any one of claims 1 to 3, characterized in that: The first conductive layer and / or the second conductive layer comprises: a first sublayer and a second sublayer, wherein the first sublayer surrounds and is attached to a surface of the second sublayer; The resistivity of the first sub-layer is smaller than the resistivity of the second sub-layer.

14. A method for preparing a semiconductor device, characterized in that: include: Forming a stacked structure; the stacked structure comprises a plurality of first insulating layers, a plurality of first conductive layers and a plurality of second conductive layers, the first conductive layers and the second conductive layers are stacked, and the first insulating layer is arranged between the first conductive layer and the second conductive layer; forming a first contact structure; the first contact structure penetrates the stacked structure and is connected to the multi-layer first conductive layer; forming a plurality of second contact structures; The plurality of second contact structures penetrate at least a portion of the stacked structure, and each second contact structure is connected to a corresponding second conductive layer.

15. The preparation method according to claim 14, characterized in that: The forming of the stacked structure comprises: forming an initial stacking structure; the initial stacking structure comprises a first functional layer and a second functional layer alternately stacked; forming a first opening penetrating the initial stacking structure; Removing the first functional layer through the first opening to form a first accommodating cavity; A conductive material is deposited on the inner wall of the first accommodating cavity to form a first conductive layer or a second conductive layer.

16. The preparation method according to claim 15, characterized in that: The step of depositing a conductive material on the inner wall of the first accommodating cavity comprises: Depositing a conductive material in the first receiving cavity so that the conductive material fills the first receiving cavity to form one of the first conductive layer and the second conductive layer; Wherein, forming the stacked structure further comprises: Removing the second functional layer through the first opening to form a second accommodating cavity; Depositing insulating material on the inner wall of the second accommodating cavity to form the first insulating layer; A conductive material is deposited on a side of the first insulating layer away from the inner wall of the second accommodating cavity to form the other of the first conductive layer and the second conductive layer.

17. The preparation method according to claim 15, characterized in that: The step of depositing a conductive material on the inner wall of the first accommodating cavity comprises: Depositing a conductive film on the inner wall of the first accommodating cavity to form the second conductive layer; Wherein, forming the stacked structure further comprises: forming a first insulating layer on a side of the second conductive layer away from the inner wall of the first accommodating cavity; A first conductive layer is formed on a side of the first insulating layer away from the inner wall of the first accommodating cavity; the first insulating layer surrounds the first conductive layer, and the second conductive layer surrounds the first insulating layer.

18. The preparation method according to any one of claims 15 to 17, characterized in that: The first contact structure includes a first dielectric layer and a first conductive column; The forming of the first contact structure comprises: Removing a portion of the second conductive layer close to the first opening through the first opening to form a first receiving groove; Filling the first receiving groove with insulating material to form the first dielectric layer; The first opening is filled with a conductive material to form the first conductive column.

19. The preparation method according to any one of claims 15 to 17, characterized in that: The second contact structure includes a second dielectric layer, a second conductive column and a first conductive block; After forming the initial stacking structure, forming a plurality of second contact structures comprises: forming a plurality of second openings; wherein the second openings at least penetrate the initial stacking structure to the corresponding first functional layer; Removing a portion of the corresponding first functional layer close to the second opening through the second opening to form a second receiving groove; Filling the second receiving groove with a conductive material to form the first conductive block; The second dielectric layer is formed through the second opening; at least a portion of the second dielectric layer is disposed in the first functional layer penetrated by the second opening, on a side of the first functional layer other than the corresponding first functional layer close to the second opening; The second opening is filled with a conductive material to form the second conductive column.

20. The preparation method according to claim 19, characterized in that: The second dielectric layer includes a plurality of second sub-portions; The forming of the second dielectric layer through the second opening includes: The second sub-portion is formed by oxidizing a portion of the first functional layer other than the corresponding first functional layer in the multiple first functional layers penetrated by the second opening and close to the second opening.

21. The preparation method according to any one of claims 15 to 17, characterized in that: Also includes: forming a plurality of transistors; The transistors are arranged at one side of the stack structure, and each transistor is connected to a corresponding second contact structure.

22. The preparation method according to claim 21, characterized in that: The forming of the plurality of transistors comprises: forming a third functional layer; the third functional layer is used to be stacked with the stacking structure; forming a plurality of semiconductor portions; the semiconductor portions penetrate the third functional layer; and one end of the semiconductor portion facing the stacking structure is used to connect with the second contact structure; Opening a third opening penetrating through the third functional layer, and removing the third functional layer through the third opening to form a third accommodating cavity; Depositing a gate oxide layer on a side of the semiconductor portion perpendicular to the third functional layer through the third receiving cavity; The gate material is filled into the third receiving cavity through the third opening to form a gate line.

23. The preparation method according to claim 22, characterized in that: After the initial stacking structure is formed, a third opening is opened that penetrates the third functional layer; the third opening is opened synchronously with the first opening.

24. A storage system, characterized in that: include: The semiconductor device according to any one of claims 1 to 13; The controller is coupled to the semiconductor device to control the semiconductor device to store data.

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