Memory device and manufacturing method thereof

Abstract

A memory device includes a substrate, a word line, a word line cap layer, a landing pad, a cell contact, and a bit line. The word line is buried in the substrate and extends along a first direction. A wordline cap layer is on the wordline. The landing pad is on the substrate and the word line cap layer and contacts the substrate and the word line cap layer. A unit contact is on and contacts the landing pad. The bit lines are on the word lines and extend along a second direction, and the second direction is perpendicular to the first direction. The contact area between the cell contact and the transistor is increased, so that the transistor can be well connected with the corresponding capacitance. Thus, the cell contact does not need to perfectly overlap with the transistor.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a manufacturing method thereof. Background Art

[0002] The size of memory cells in dynamic random access memory (DRAM) is continuously reduced to achieve a greater number of memory cells in a unit area. The DRAM scaling process may cause some problems. For example, alignment between two components may become difficult. Summary of the invention

[0003] Some embodiments of the present disclosure provide a memory device, including a substrate, a word line, a word line cap layer, a landing pad, a cell contact, and a bit line. The word line is buried in the substrate and extends along a first direction. The word line cap layer is on the word line. The landing pad is on the substrate and the word line cap layer and contacts the substrate and the word line cap layer. The cell contact is on the landing pad and contacts the landing pad. The bit line is on the word line and extends along a second direction, the second direction being perpendicular to the first direction.

[0004] In some embodiments, the landing pad and the substrate are made of silicon.

[0005] In some embodiments, the memory device further includes an isolation structure buried in the substrate and contacting the landing pad.

[0006] In some embodiments, the memory device further includes a dielectric layer covering the landing pad, the word line cap layer, and the isolation structure.

[0007] In some embodiments, a dielectric layer contacts the landing pads and the cell contacts.

[0008] In some embodiments, the bottom of the landing pad is substantially flush with the top surface of the isolation structure.

[0009] In some embodiments, the substrate has a portion of a top surface that protrudes beyond the isolation structure, and the landing pad contacts a sidewall of the portion of the substrate.

[0010] In some implementations, the memory device further includes a bit line contact below the bit line, wherein a bottom of the bit line contact is lower than a bottom of the landing pad.

[0011] In some implementations, the bottom of the landing pad is substantially flush with the top surface of the word line cap layer.

[0012] In some implementations, a portion of the landing pad is between the cell contact and the word line cap layer.

[0013] A method for manufacturing a memory device includes: forming a word line and a word line cap layer buried in the substrate in a substrate, wherein the word line extends along a first direction and the word line cap layer is on the word line, forming a mask layer on the substrate, wherein the mask layer exposes a first portion of the substrate, performing a selective epitaxial growth process to form a landing pad on the first portion of the substrate, forming a dielectric layer on the landing pad, the substrate and the word line cap layer, and forming a cell contact, wherein the cell contact penetrates the dielectric layer and contacts the landing pad.

[0014] In some embodiments, during the selective epitaxial growth process, the landing pad extends onto a top surface of the word line cap layer.

[0015] In some embodiments, the method further includes: after forming the dielectric layer, removing the mask layer to expose a second portion of the substrate, forming a bit line contact hole in the substrate using the dielectric layer as an etching mask, and forming a bit line contact in the bit line contact hole.

[0016] In some embodiments, the method further includes forming a bit line on the bit line contact and the dielectric layer, forming a bit line capping layer on the bit line, and forming spacers along a plurality of sidewalls of the bit line contact, the bit line, and the bit line capping layer.

[0017] In some embodiments, the spacer is separated from the landing pad by a dielectric layer.

[0018] In some embodiments, the bit lines are separated from the landing pads by a dielectric layer.

[0019] In some embodiments, after forming the cell contact, a portion of the landing pad is between the cell contact and the word line cap layer.

[0020] In some embodiments, the bottom of the bit line contact hole is lower than the landing pad.

[0021] In some embodiments, the method further includes performing a cleaning process before performing the selective epitaxial growth process, such that after the cleaning process, a plurality of sidewalls of the first portion of the substrate are exposed.

[0022] In some embodiments, the landing pad contacts a sidewall of the first portion of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A circuit diagram of a memory according to some embodiments of the present disclosure is shown.

[0024] Figure 2 A top view illustrating an intermediate process of manufacturing a memory device according to some embodiments of the present disclosure.

[0025] Figure 3A and Figure 4A To illustrate the Figure 2 A cross-sectional view of a fabricated memory device taken along line XX'.

[0026] Figure 3B and Figure 4B To illustrate the Figure 2 A cross-sectional view of a fabricated memory device taken along line YY'.

[0027] Figure 5 A top view illustrating an intermediate process of manufacturing a memory device according to some embodiments of the present disclosure.

[0028] Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A To illustrate the Figure 5 A cross-sectional view of a fabricated memory device taken along line XX'.

[0029] Figure 6B , Figure 7B , Figure 8B , Fig. 9B and Fig. 10B To illustrate the Figure 5 A cross-sectional view of a fabricated memory device taken along line YY'.

[0030] Fig.11 A top view illustrating an intermediate process of manufacturing a memory device according to some embodiments of the present disclosure.

[0031] Fig. 12A To illustrate the Fig.11 A cross-sectional view of a fabricated memory device taken along line XX'.

[0032] Fig. 12B To illustrate the Fig.11 A cross-sectional view of a fabricated memory device taken along line YY'.

[0033] Fig.13A , Fig.14A and Fig.15A To illustrate other embodiments along Figure 5 A cross-sectional view of a fabricated memory device taken along line XX'.

[0034] Fig. 13B , Fig. 14B and Fig. 15B To illustrate other embodiments along Figure 5 A cross-sectional view of a fabricated memory device taken along line YY'. DETAILED DESCRIPTION

[0035] The following will disclose multiple embodiments of the present disclosure with the accompanying drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and elements will be depicted in a simple schematic manner in the drawings.

[0036] Figure 1 FIG. 1 is a circuit diagram of a memory device according to some embodiments of the present disclosure. Figure 1 , a memory device (e.g., a dynamic random access memory, Dynamic Random Access Memory, DRAM) may include a plurality of memory cells MC. A typical DRAM memory cell combines a capacitor CA with a transistor TR, wherein the capacitor CA temporarily stores data according to the charge state of the capacitor CA. The bit line BL is electrically connected to the source / drain region of the transistor TR, and the word line WL is electrically connected to the gate region of the transistor TR. The capacitor CA is electrically connected to the corresponding transistor TR through a cell contact. In the present disclosure, the contact area between the cell contact and the transistor is increased, so that the transistor and the corresponding capacitor can be well connected. Therefore, the cell contact does not need to perfectly overlap with the transistor.

[0037] Figure 2 A top view illustrating an intermediate process of manufacturing a memory device according to some embodiments of the present disclosure. Figure 3A and Figure 4A To illustrate the Figure 2 A cross-sectional view of the fabricated memory device along line XX', and Figure 3B and Figure 4B To illustrate the Figure 2 A cross-sectional view of a fabricated memory device taken along line Y-Y'. Figure 2 Only some components are shown, and other components are omitted to simplify the drawings. Figure 2 , Figure 3A and Figure 3B , providing a substrate 100, and forming an isolation structure 105 in the substrate 100, and the area of ​​the substrate 100 not covered by the isolation structure 105 can be regarded as Figure 2The active area AA of the transistor is formed, and the active area AA can be used as a diffusion area of ​​the transistor. In some embodiments, the substrate 100 can be made of silicon, and the isolation structure 105 can be made of a dielectric material, such as silicon oxide. Next, a dielectric layer 108, a word line 110, and a word line cap layer 112 buried in the substrate 100 are formed in the substrate 100. The word line cap layer 112 is on the word line 110, the word line cap layer 112 and the word line 110 are formed in the dielectric layer 108, and the word line cap layer 112 and the word line 110 extend along a first direction (such as the Y direction). The word line cap layer 112 and the word line 110 span the active area AA and the isolation structure 105 and contact the isolation structure 105. The top surface of the word line cap layer 112 is substantially flush with the top surface of the substrate 100. In some embodiments, the dielectric layer 108 may be made of an oxide, the word line 110 may be made of a conductive material such as a metal (eg, tungsten), and the word line cap layer 112 may be made of a dielectric material.

[0038] The substrate 100 may include a doped region 106 on opposite sides of the word line 110. Here, the word line 110, the dielectric layer 108, the pair of doped regions 106 on opposite sides of the word line 110, and the substrate 100 may collectively serve as Figure 1 The transistor TR of the memory cell MC of the memory cell MC. In more detail, the word line 110 can be used as the gate electrode of the transistor TR, the dielectric layer 108 can be used as the gate dielectric layer of the transistor TR, the substrate 100 can be used as the channel region of the transistor TR, and the doped region 106 can be used as the source / drain region of the transistor TR. The doped region 106 has a conductor type opposite to that of the substrate 100. For example, if the substrate 100 is a P-type substrate, the doped region 106 is an N-type doped region. If the substrate 100 is an N-type substrate, the doped region 106 is a P-type doped region.

[0039] refer to Figure 4A and Figure 4B , a dielectric layer 122 and a dielectric layer 124 are formed on the substrate 100. The dielectric layer 124 is on the dielectric layer 122, and the dielectric layer 122 contacts the substrate 100, the isolation structure 105, and the word line cap layer 112. The dielectric layer 122 and the dielectric layer 124 are made of different materials. In some embodiments, the dielectric layer 122 is made of silicon oxide, and the dielectric layer 124 is made of silicon nitride.

[0040] Figure 5 A top view illustrating an intermediate process of manufacturing a memory device according to some embodiments of the present disclosure. Fig. 6A , Fig. 7A , Fig. 8A and Fig.9A To illustrate the Figure 5 A cross-sectional view of the fabricated memory device along line XX', and Figure 6B , Figure 7B, Figure 8B and Fig. 9B To illustrate the Figure 5 A cross-sectional view of a fabricated memory device taken along line Y-Y'. Figure 5 Only some components are shown, and other components are omitted to simplify the drawings. Figure 5 , Fig. 6A and Figure 6B , a mask layer 120 is formed on the substrate 100, and the mask layer 120 exposes a first portion of the substrate 100. Specifically, the mask layer 120 is formed by patterning the dielectric layer 122 and the dielectric layer 124. After the mask layer 120 is formed, a bit line contact reverse pattern RP is formed in the mask layer 120. The bit line contact reverse pattern RP exposes a first portion of the substrate 100, a first portion of the word line cap layer 112, and a first portion of the isolation structure 105. The mask layer 120 covers a second portion of the substrate 100, a second portion of the word line cap layer 112, and a second portion of the isolation structure 105. In the process discussed later, the first portion of the substrate 100 will be electrically connected to the cell contact (see Fig. 12B ), and the second portion of the substrate 100 is electrically connected to the bit line contact (see Fig. 12B ).

[0041] refer to Fig. 7A and Figure 7B , the dielectric layer 124 is removed and then a selective epitaxial growth process is performed to form the landing pad 130 on the first portion of the substrate 100. Specifically, the dielectric layer 124 can be removed by an etching process having etching selectivity to the material of the dielectric layer 124, such as an etching process having an etching rate for the dielectric layer 124 greater than an etching rate for the dielectric layer 122. After the dielectric layer 124 is removed, the top surface of the dielectric layer 122 is exposed and the dielectric layer 122 remains substantially intact.

[0042] Next, a landing pad 130 is selectively grown on the first portion of the substrate 100, and the first portion of the substrate 100 contacts the landing pad 130. During the selective epitaxial growth process, the landing pad 130 completely covers the first portion of the substrate 100, and the material of the landing pad 130 extends to the top surface of the word line cap layer 112 and the top surface of the isolation structure 105. The bottom of the landing pad 130 contacts the top surface of the dielectric layer 108 and the top surface of the isolation structure 105, and is substantially flush with the top surface of the word line cap layer 112 and the top surface of the isolation structure 105. The selective epitaxial growth layer of the landing pad 130 can be controlled so that the size of the landing pad 130 is within a suitable range. For example, the top surface of the landing pad 130 is lower than the dielectric layer 122. In some embodiments, the landing pad 130 still exposes most of the word line cap layer and the isolation structure 105. In some embodiments where the substrate 100 is made of silicon, the landing pad 130 grown on the substrate 100 is also made of silicon. Fig. 12B In some embodiments, the landing pad 130 may be made of single crystal silicon. In some embodiments, the landing pad 130 is an undoped silicon epitaxial layer. In other embodiments, the landing pad 130 is a doped silicon epitaxial layer and is formed by in-situ doping during the selective epitaxial growth process. In some embodiments, if the landing pad 130 is doped, the conductor type of the landing pad 130 may be the same as the conductor type of the doped region 106.

[0043] refer to Fig. 8A and Figure 8B , a dielectric layer 140 is formed on the landing pad 130, the substrate 100, and the word line cap layer 112. In some embodiments, the dielectric layer 140 can be formed by the following process: first forming a dielectric material layer that fills and overflows the bit line contact reverse pattern RP, and then performing a planarization process to remove the excess portion of the dielectric material layer until the top surface of the dielectric layer 122 is exposed. Therefore, the dielectric layer 140 is formed on the landing pad 130, the substrate 100, and the word line cap layer 112. The top surface of the dielectric layer 140 is substantially flush with the top surface of the dielectric layer 122, and the dielectric layer 140 is thicker than the landing pad 130 to completely cover the landing pad 130. The dielectric layer 140 and the dielectric layer 122 are formed of different materials. In some embodiments, the dielectric layer 140 is made of silicon nitride.

[0044] refer to Fig.9A and Fig. 9BAfter the dielectric layer 140 is formed, the mask layer 120 is removed to expose the second portion of the substrate 100. Specifically, the mask layer 120 (i.e., the dielectric layer 122) can be removed by an etching process having an etching selectivity to the material of the mask layer 120 (i.e., the dielectric layer 122), such as an etching process in which the etching rate of the mask layer 120 (i.e., the dielectric layer 122) is greater than the etching rate of the dielectric layer 140. After the mask layer 120 (i.e., the dielectric layer 122) is removed, the dielectric layer 140 remains substantially intact, and the second portion of the substrate 100, the second portion of the word line cap layer 112, and the second portion of the isolation structure 105 are exposed.

[0045] refer to Fig. 10A and Fig. 10B , using the dielectric layer 140 as an etching mask, a bit line contact hole H is formed in the substrate 100. Specifically, the bit line contact hole H can be formed by an anisotropic etching process. The etching process of the bit line contact hole H can be controlled so that the bottom of the bit line contact hole H is at a suitable height. For example, the bottom of the bit line contact hole H is lower than the landing pad 130 and higher than the word line 110. Therefore, the bit line contact (see FIG. 1 ) formed later can be guaranteed to be Fig. 12B ) contacts the active area AA of the substrate 100 (see Fig.11 ), but does not contact word line 110.

[0046] Fig.11 A top view illustrating an intermediate process of manufacturing a memory device according to some embodiments of the present disclosure. Fig. 12A To illustrate the Fig.11 A cross-sectional view of the fabricated memory device along line XX', and Fig. 12B To illustrate the Fig.11 A cross-sectional view of a fabricated memory device taken along line Y-Y'. Fig.11 Only some components are shown, and other components are omitted to simplify the drawings. Fig.11 , Fig. 12A and Fig. 12B, forming the bit line contact 152, the bit line 154, the bit line capping layer 156, the spacer 160 and the cell contact 170. In more detail, the bit line contact 152, the bit line 154 and the bit line capping layer 156 may be formed by the following process: sequentially forming a bit line contact layer, a bit line layer and a dielectric layer on the substrate 100 and the dielectric layer 140, then patterning the bit line contact layer, the bit line layer and the dielectric layer to form the bit line contact 152 in the bit line contact hole H, forming the bit line 154 on the bit line contact 152, and forming the bit line capping layer 156 on the bit line 154. The bit line contact 152, the bit line 154 and the bit line capping layer 156 extend along the second direction (e.g., the X direction), and the second direction is perpendicular to the first direction. After the bit line 154 is formed, the top surface of the landing pad 130 is lower than the bottom of the bit line 154, and the bit line 154 is separated from the landing pad 130 by the dielectric layer 140. Next, a spacer 160 is formed along the sidewalls of the bit line contact 152, the bit line 154, and the bit line cap layer 156. After the spacer 160 is formed, the bottom of the spacer 160 is on the dielectric layer 140, and the spacer 160 is separated from the landing pad 130 by the dielectric layer 140. Next, a cell contact 170 is formed that penetrates the dielectric layer 140 and contacts the landing pad 130. The landing pad 130 provides a larger contact area between the cell contact 170 and the active area AA of the substrate 100. Therefore, the cell contact 170 has a better electrical connection with the active area AA of the substrate 100. In some embodiments, the bit line contact 152 is made of a conductive material, such as polysilicon, the bit line 154 is made of a conductive material, such as a metal, such as tungsten, the bit line cap layer 156 is made of a dielectric material, such as silicon nitride, the spacer 160 is made of a dielectric material, such as silicon oxide, silicon nitride, or a combination thereof, and the cell contact 170 is made of polysilicon, a metal (such as tungsten), or a combination thereof. In some embodiments, the cell contact 170 can be electrically connected to a capacitor, such as Figure 1 The capacitor CA in question is contacted to the top surface of the cell contact 170 in some embodiments.

[0047] The resulting memory device is Fig. 12A and Fig. 12BAs shown, the memory device includes a substrate 100, an isolation structure 105, a word line 110, a word line cap layer 112, a landing pad 130, a dielectric layer 140, a cell contact 170, a bit line 154, and a bit line contact 152. The isolation structure 105 is buried in the substrate 100. The word line 110 is buried in the substrate 100 and extends along a first direction. The word line cap layer 112 is on the word line 110, wherein the top surface of the word line cap layer 112 is substantially flush with the top surface of the substrate 100. The landing pad 130 is on the substrate 100, the word line cap layer 112, and the isolation structure 105 and contacts the substrate 100, the word line cap layer 112, and the isolation structure 105. The cell contact 170 is on the landing pad 130 and contacts the landing pad 130. The dielectric layer 140 covers the landing pad 130, the word line cap layer 112 and the isolation structure 105, and the dielectric layer 140 contacts the cell contact 170 and the landing pad 130. The bit line 154 is on the word line 110 and extends along the second direction, which is perpendicular to the first direction. The bit line contact 152 is below the bit line 154, and the bottom of the bit line contact 152 is lower than the bottom of the landing pad 130.

[0048] Fig.13A , Fig.14A and Fig.15A To illustrate other embodiments along Figure 5 A cross-sectional view of the fabricated memory device along line XX', and Fig. 13B , Fig. 14B and Fig. 15B To illustrate other embodiments along Figure 5 A cross-sectional view of a fabricated memory device taken along line Y-Y'. Fig.13A and Fig. 13B ,exist Fig. 6A and Figure 6B Afterwards, a cleaning process may be performed before the selective epitaxial growth process to remove oxides on the surface of the substrate 100. That is, the cleaning process may be performed before the selective epitaxial growth process. Fig. 7A and Figure 7B During the cleaning process, the isolation structure 105 and the dielectric layer 108 may be partially etched and recessed, the substrate 100 has a portion protruding from the top surface of the isolation structure 105 and the dielectric layer 108, and the landing pad 130 contacts the sidewall of the portion of the substrate 100. The first portion of the substrate 100 is also exposed. In some embodiments, the cleaning process may be performed by a dry etching process.

[0049] refer to Fig.14A and Fig. 14B A selective epitaxial growth process is performed to form a landing pad 130 on a first portion of the substrate 100 (ie, a portion of the substrate 100 not covered by the mask layer 120 ). Fig. 7A and Figure 7B as well as Fig.14A and Fig. 14B The difference between the two is that the landing pad 130 contacts the sidewall of the first portion of the substrate 100, and Fig.14A and Fig. 14B The contact area between the landing pad 130 formed in the substrate 100 is larger. Other relevant details are in Fig. 7A and Figure 7B The memory device thus obtained is as follows: Fig.15A and Fig. 15B As shown. The landing pad 130 provides a larger contact area between the cell contact 170 and the active area AA of the substrate 100. Therefore, the cell contact 170 has a better electrical connection with the active area AA of the substrate 100. Specifically, the landing pad 130 is a selective epitaxial growth area on the substrate 100. In some embodiments, the substrate 100 and the landing pad 130 are made of silicon. During the selective epitaxial growth, the landing pad 130 grows vertically and horizontally from the substrate 100. Therefore, the landing pad 130 provides a larger contact area between the cell contact 170 and the active area AA of the substrate 100. For example, a portion of the landing pad 130 is between the cell contact 170 and the word line cap layer 112. Therefore, even if the cell contact 170 does not perfectly overlap with the active area AA of the substrate 100, the cell contact 170 can still be well connected to the landing pad 130.

[0050] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the definition of the attached claims.

[0051]

Explanation of symbols

[0052] 100: Substrate

[0053] 105: Isolation Structure

[0054] 106: Doping area

[0055] 108, 122, 124, 140: Dielectric layer

[0056] 110: Character line

[0057] 112: Character line cap layer

[0058] 120: Mask layer

[0059] 130: Landing Pad

[0060] 152: Bit line contacts

[0061] 154: Bit line

[0062] 156: Bit line cap layer

[0063] 160: Spacer

[0064] 170: Unit contact

[0065] AA: Active Area

[0066] BL: Bit Line

[0067] CA: Capacitance

[0068] H: Bit line contact hole

[0069] RP: Bit line contact reverse pattern

[0070] TR: Transistor

[0071] WL: character line

[0072] X-X', Y-Y': line.

Claims

1. A memory device, characterized in that: Include: substrate; A word line, buried in the substrate and extending along a first direction; A character line cap layer, on the character line; A landing pad is on the substrate and the word line cap layer and contacts the substrate and the word line cap layer; a unit contact on and in contact with the landing pad; as well as The bit line is on the word line and extends along a second direction, and the second direction is perpendicular to the first direction.

2. The memory device according to claim 1, wherein: The landing pad and the substrate are made of silicon.

3. The memory device according to claim 1, wherein: Also includes: An isolation structure is buried in the substrate and contacts the landing pad.

4. The memory device according to claim 3, wherein: Also includes: The dielectric layer covers the landing pad, the word line cap layer and the isolation structure.

5. The memory device according to claim 4, wherein: The dielectric layer contacts the landing pad and the cell contact.

6. The memory device according to claim 3, wherein: The bottom of the landing pad is substantially flush with the top surface of the isolation structure.

7. The memory device according to claim 3, wherein: The substrate has a portion protruding from a top surface of the isolation structure, and the landing pad contacts a sidewall of the portion of the substrate.

8. The memory device according to claim 1, wherein: Also includes: A bit line contact is below the bit line, wherein a bottom of the bit line contact is lower than a bottom of the landing pad.

9. The memory device according to claim 1, wherein: The bottom of the landing pad is substantially flush with the top surface of the word line cap layer.

10. The memory device according to claim 1, wherein: A portion of the landing pad is between the cell contact and the word line cap layer.

11. A method for manufacturing a memory device, characterized in that: Include: Forming a word line and a word line cap layer buried in the substrate in a substrate, wherein the word line extends along a first direction and the word line cap layer is on the word line; forming a mask layer on the substrate, wherein the mask layer exposes a first portion of the substrate; performing a selective epitaxial growth process to form a landing pad on the first portion of the substrate; forming a dielectric layer on the landing pad, the substrate and the word line cap layer; as well as A cell contact is formed, the cell contact penetrating the dielectric layer and contacting the landing pad.

12. The method according to claim 11, characterized in that During the selective epitaxial growth process, the landing pad extends onto a top surface of the word line cap layer.

13. The method according to claim 11, characterized in that Also includes: After forming the dielectric layer, removing the mask layer to expose a second portion of the substrate; forming a bit line contact hole in the substrate using the dielectric layer as an etching mask; as well as A bit line contact is formed in the bit line contact hole.

14. The method according to claim 13, characterized in that Also includes: forming a bit line on the bit line contact and the dielectric layer; forming a bit line cap layer on the bit line; and Spacers are formed along sidewalls of the bit line contact, the bit line, and the bit line capping layer.

15. The method according to claim 14, characterized in that The spacer is separated from the landing pad by the dielectric layer.

16. The method according to claim 14, characterized in that The bit line is separated from the landing pad by the dielectric layer.

17. The method according to claim 13, characterized in that After forming the cell contact, a portion of the landing pad is between the cell contact and the word line cap layer.

18. The method according to claim 13, characterized in that The bottom of the bit line contact hole is lower than the landing pad.

19. The method according to claim 11, characterized in that Also includes: Before performing the selective epitaxial growth process, a cleaning process is performed, so that after the cleaning process, a plurality of sidewalls of the first portion of the substrate are exposed.

20. The method according to claim 19, characterized in that The landing pad contacts the plurality of sidewalls of the first portion of the substrate.

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