Storage unit, memory and electronic equipment

Abstract

The invention provides a memory cell, a memory and electronic equipment. The memory cell comprises a substrate, a transistor unit and a capacitor, the transistor unit comprises a first source and drain electrode, a second source and drain electrode, a channel layer, a gate dielectric layer, a gate and an interlayer insulating layer; the capacitor comprises a first polar plate, a second polar plate and a dielectric layer located between the first polar plate and the second polar plate. According to the transistor of the CAA architecture with the channel surrounding the grid electrode, the source electrode and the drain electrode are arranged in the space in the vertical direction, and occupation of the transistor in the horizontal direction is reduced; meanwhile, the capacitor is arranged in a longitudinal space, so that the electric connection effect between the transistor and the capacitor is improved, the area occupation of the capacitor in the horizontal direction is reduced, and the capacitance value of the capacitor is improved by increasing the contact area between the polar plates in combination with the arrangement of the extension parts of the polar plates; a vertical space is fully utilized to complete transistor and capacitor deployment, so that the arrangement density of the storage unit is improved, and the chip miniaturization design is completed.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor storage technology, and in particular to a storage unit, a memory, and an electronic device. Background Art

[0002] With the widespread use of semiconductor devices, the 1T1C structure composed of semiconductor transistors and capacitors is often used as a storage unit to form a dynamic random access memory (DRAM). However, with the miniaturization and high-density characteristics of DRAM memory, the chip area used to prepare the storage unit has been reduced. At present, transistors are usually fin field effect transistors (FinFETs), which have a small leakage current and a long channel length, but are limited by their size and are not suitable for chips below 10nm. Due to their width scaling limitations, performance and power consumption will be affected at small sizes; in addition, after the chip is reduced or the density is increased, the chip area used to prepare the capacitor is continuously reduced, resulting in a decrease in capacitance, but the decrease in capacitance is likely to lead to the instability of its storage function, and the occurrence of storage data reading errors, so how to reduce the occupied area of ​​the storage unit is a problem that needs to be solved. Summary of the invention

[0003] The purpose of the embodiments of the present disclosure is to provide a storage unit, a memory and an electronic device to solve the problem of how to reduce the occupied area of ​​the storage unit in the prior art.

[0004] The embodiment of the present disclosure adopts the following technical solution: a storage unit, comprising: a substrate, a transistor unit and a capacitor sequentially arranged on the surface of one side of the substrate; the transistor unit at least comprises: a first source and a drain, a second source and a drain, a channel layer, a gate dielectric layer, a gate and an interlayer insulating layer; wherein the gate extends in a direction perpendicular to the surface of the substrate, the gate dielectric layer is arranged around the outside of the gate, the channel layer is arranged around the outside of the gate dielectric layer, the first source and the drain are arranged around the end of the gate away from the substrate and are located outside the channel layer, and the second source and the drain are arranged around the gate near the substrate. The first electrode is electrically connected to the second source and drain, and the first electrode has a first extension portion extending toward the substrate, the second electrode is arranged on a side surface of the substrate, and has a second extension portion extending away from the substrate, and the shapes of the first extension portion and the second extension portion match each other.

[0005] In some embodiments, an orthographic projection of the capacitor on the substrate surface is completely covered by an orthographic projection of the transistor unit on the substrate surface.

[0006] In some embodiments, the second plate is grounded.

[0007] In some embodiments, the second source and drain are integrated with the first electrode plate.

[0008] In some embodiments, the first source and drain, the second source and drain, the first electrode plate and the second electrode plate are made of any one of the following materials: aluminum, copper, tungsten, molybdenum, titanium nitride, indium tin oxide, indium zinc oxide.

[0009] In some embodiments, the channel layer is made of indium gallium zinc oxide (IGZO) material.

[0010] In some embodiments, the gate dielectric layer and the dielectric layer are made of a high dielectric constant material.

[0011] In some embodiments, the gate dielectric layer and the dielectric layer are made of any one of the following materials: hafnium oxide HfO 2 , zirconium oxide ZrO 2 , and hafnium silicate nitride HfSiON.

[0012] The embodiment of the present disclosure further provides a memory, comprising a plurality of storage units as described above, wherein the plurality of storage units are arranged in an array.

[0013] An embodiment of the present disclosure also provides an electronic device, which at least includes the memory as described above.

[0014] The beneficial effects of the embodiments of the present disclosure are as follows: a transistor with a CAA architecture in which the channel surrounds the gate is adopted, the horizontal channel transistor is optimized into a vertical channel transistor, and the source and drain are arranged in the vertical space, thereby reducing the area occupied by the transistor in the horizontal direction, which is conducive to setting up more transistor structures while keeping the total area of ​​the chip unchanged; at the same time, the longitudinal space is used to set the capacitor, which is conducive to improving the electrical connection effect between the transistor and the capacitor, and is also conducive to reducing the area occupied by the capacitor in the horizontal direction. Combined with the extension part arrangement of the two plates of the capacitor, the contact area between the plates is increased to improve the capacitance of the capacitor, and the vertical space is fully utilized to complete the deployment of transistors and capacitors, so as to improve the storage unit arrangement density and complete the chip miniaturization design. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0016] Figure 1 is a schematic diagram of the hierarchical structure of a storage unit in the first embodiment of the present disclosure;

[0017] Figure 2 is another hierarchical structure diagram of the storage unit in the first embodiment of the present disclosure;

[0018] Figure 3 is another hierarchical structure diagram of the storage unit in the first embodiment of the present disclosure;

[0019] Figure 4 Flow chart of the method for preparing a storage unit in the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will be combined with the drawings in one or more embodiments of this specification to clearly and completely describe the technical solutions in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.

[0021] With the widespread use of semiconductor devices, the 1T1C structure composed of semiconductor transistors and capacitors is often used as a storage unit to form DRAM. However, with the miniaturization and high-density requirements of DRAM memory, the chip area used to prepare storage units has been reduced. Currently, transistors are usually FinFETs, which have a small leakage current and a long channel length. However, due to their size, they are not suitable for chips below 10nm. Due to their width scaling limitations, performance and power consumption will be affected at small sizes. In addition, after the chip is reduced or the density is increased, the chip area used to prepare capacitors continues to decrease, resulting in a decrease in capacitance. However, the decrease in capacitance can easily lead to instability in its storage function, resulting in errors in reading stored data. Therefore, how to reduce the area occupied by storage units is a problem that needs to be solved.

[0022] In order to solve the above problems, the first embodiment of the present disclosure provides a storage unit, which is mainly composed of a transistor and a capacitor, that is, a 1T1C structure. The storage unit can be used as a basic building block of a dynamic random access memory (DRAM). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0023] Figure 1 FIG. 4 shows a schematic diagram of the hierarchical structure of the storage unit in this embodiment. Figure 1 As shown, it at least includes a substrate 10, a transistor unit 20 and a capacitor 30 sequentially arranged on a surface of one side of the substrate. The transistor unit 20 controls the on-off of the channel between the source and the drain through the gate to complete the signal writing or reading operation to the capacitor 30.

[0024] Specifically, the transistor unit 20 at least includes: a first source and drain 21, a second source and drain 22, a channel layer 23, a gate dielectric layer 24, a gate 25, and an interlayer insulating layer 26. The on-off control between the first source and drain region 21 and the second source and drain region 22 is achieved by adjusting the voltage of the gate 25. In this embodiment, the transistor unit 20 is a CAA architecture, and the gate 25 is perpendicular to the surface of the substrate 10 (i.e., Figure 1The gate dielectric layer 24 is arranged around the outside of the gate 25, the channel layer 23 is arranged around the outside of the gate dielectric layer 24, the first source and drain 21 and the second source and drain 22 are arranged around the outside of the channel layer 23 along the vertical direction, wherein the first source and drain 21 is located at the end of the gate 25 away from the substrate 10, and the second source and drain 22 is located at the end of the gate 25 close to the substrate 10, and an interlayer insulating layer 26 is arranged between the first source and drain 21 and the second source and drain 22, and the interlayer insulating layer 26 is also arranged around the outside of the channel layer 23 to achieve insulation between the first source and drain 21 and the second source and drain 22.

[0025] The capacitor 30 of this embodiment is arranged at Figure 1 Below the transistor unit 20, it mainly includes a first plate 31, a second plate 32 and a dielectric layer 33 located between the two plates. The first plate 31, the dielectric layer 33 and the second plate 32 are generally arranged in a vertical direction, wherein the first plate 31 is electrically connected to the second source and drain 22 of the transistor unit 20, so that the electrical signal input from the transistor unit 20 can be directly stored in the capacitor 30, and the second plate 32 is arranged on one side surface of the substrate 10, and the dielectric layer 33 between the two forms a capacitor structure. At the same time, the first plate 31 has a direction toward the substrate 10 (i.e. Figure 1 The first extension portion 311 extends from the top to the bottom in the figure, and accordingly, the second electrode plate 32 has a direction away from the substrate 10 (i.e. Figure 1 The second extension portion 321 extends from the bottom to the top in the middle (in the direction from the bottom to the top), and the shapes of the first extension portion 311 and the second extension portion 321 match each other to increase the facing area between the first electrode plate 31 and the second electrode plate 32. When the overall occupied area and size remain unchanged, the surface area extended by the extension portion is used to increase the facing area between the electrode plates, thereby increasing the capacitance of the capacitor.

[0026] In actual implementation, the larger the capacitance, the more charge the capacitor can store. During the reading operation, a larger amount of charge will produce a stronger signal, which helps to improve the reliability and accuracy of the reading and reduce the possibility of misreading. At the same time, a larger capacitor has a lower leakage rate, so the frequency of refresh operations can be reduced. A lower refresh frequency means less refresh overhead, which can free up more bandwidth for read and write operations, thereby improving the overall storage rate. Normally, the second plate 32 of the capacitor 30 is grounded, and the specific method of connecting it to the ground terminal is not shown in the figure. For example, the second plate can be connected to the ground terminal using a connecting wire, or other conventional grounding methods can be used, which are not limited in this embodiment.

[0027] This embodiment adopts a transistor with a CAA architecture in which the channel surrounds the gate, optimizes the horizontal channel transistor into a vertical channel transistor, and utilizes the space in the vertical direction to set the source and drain, thereby reducing the area occupied by the transistor in the horizontal direction, which is beneficial for arranging more transistor structures while keeping the total area of ​​the chip unchanged; at the same time, the longitudinal space is utilized to set the capacitor, which is beneficial for improving the electrical connection effect between the transistor and the capacitor, and is also beneficial for reducing the area occupied by the capacitor in the horizontal direction. Combined with the extension of the two plates of the capacitor, the contact area between the plates is increased to increase the capacitance of the capacitor, and the vertical space is fully utilized to complete the deployment of transistors and capacitors, so as to improve the storage unit layout density and complete the chip miniaturization design.

[0028] In some embodiments, when actually designing and implementing the capacitor 30 and the transistor unit 20, it should be limited that the orthographic projection of the capacitor 30 on the surface of the substrate 10 is completely covered by the orthographic projection of the transistor unit 20 on the surface of the substrate 10, so as to ensure that the two occupy the same area of ​​the substrate. In addition, Figure 1 Only a schematic diagram of a cross-sectional level of the memory cell in the vertical direction is shown. In practice, the specific shapes and sizes of the first source and drain 21, the second source and drain 22, the first electrode 31 (including the first extension 311) and the second electrode 32 (including the second extension 321) can be adjusted in accordance with the preparation process and actual needs. Figure 2 and Figure 3 The cross-sectional level diagrams of two different storage units are shown respectively. Figure 1 , Figure 2 Different implementations are made on the shapes of the second source and drain 22, the first electrode 31 and the second electrode 32. Figure 3 The second source and drain 22 and the first electrode 31 are an integrated structure, that is, they are part of the transistor unit 20 and also part of the capacitor 30. The preparation process can be completed through only one step, which improves the integrity of the device structure and reduces the preparation process steps.

[0029] In the actual setting process, the memory cell usually does not exist in the form of a single unit. Generally, multiple 1T1C structure memory cells are designed on a substrate, and the memory cells are arranged in an array. The word line (WordLine, WL) and the bit line (Bit Line, BL) are used to write and read data from the memory cell, wherein the word line is located above the gate and can be connected to the gate through a via to control the on and off of the transistor, and the bit line is connected to the first source and drain 21 to write and read data. In order to further save space, in some embodiments, the hierarchical structure of the first source and drain 21 of each memory cell can be used as a bit line to further compact the layout of the memory cell. It should be noted that the word line and the bit line should be perpendicular to each other between the positive projections on the substrate surface, and each intersection corresponds to the setting of a memory cell, that is, by controlling the word line and the bit line, the read and write operations of any memory cell in the array can be realized.

[0030] In some embodiments, the first source and drain 21, the second source and drain 22 in the transistor unit 20, and the first electrode 31 and the second electrode 32 in the capacitor 30 can be made of any of the following materials, such as metals or alloys such as aluminum, copper, tungsten, and molybdenum, or compounds with conductive properties, such as titanium nitride TiN, indium tin oxide ITO, indium zinc oxide IZO, etc. The selection of specific materials can be combined with the preparation process, device performance requirements, etc., and this embodiment does not impose specific restrictions. Alternatively, for any of the above-mentioned metal hierarchical structures, a stacked structure of different materials can be used in actual implementation. For example, a material with better contact performance is used on the side of the first source and drain 21 close to the interlayer insulating layer 26, while a material with better conductive properties and better anti-oxidation performance can be used on the side away from the interlayer insulating layer 26.

[0031] Corresponding to the channel layer 23 in the transistor unit 20, it is usually made of semiconductor materials, such as silicon materials. As the demand for higher performance, lower power consumption and smaller size of transistors continues to increase, silicon germanium (SiG e ), III-V compound semiconductors, oxide semiconductors and other new materials are also often used as channel materials. Indium Gallium Zinc Oxide (IGZO) can be used in this embodiment. c Oxid e ) is used to prepare the channel layer 23. This material has low leakage current characteristics and is suitable for storage cells that need to retain data for a long time.

[0032] Optionally, the gate dielectric layer 24 and the dielectric layer 33 can be made of a material with a high dielectric constant (HighK). Since the dielectric constant of the high-K material is relatively high, the physical thickness of the dielectric layer can be increased without sacrificing the gate control force, which helps to improve the threshold voltage control and subthreshold slope of the transistor, thereby improving the overall performance of the device, while reducing leakage current and significantly improving static power consumption; in addition, when it is used as a dielectric layer material, at the same physical thickness, they can provide a larger capacitance value, making the reading result of the device more stable.

[0033] Specifically, common high-K materials include hafnium-based oxides (such as HfO2, HfSiOx, HfSiON), zirconium-based oxides (such as ZrO2), aluminum oxide (Al2O3), etc. For example, when actually preparing the gate dielectric layer 24 and the dielectric layer 33, materials such as hafnium oxide HfO2, zirconium oxide ZrO2 or hafnium silicate nitride HfSiON can be selected, which have good stability and are compatible with CMOS processes, and can significantly reduce the generation of device leakage current.

[0034] Figure 4 This embodiment shows Figure 1 The preparation flow chart of the storage unit shown in FIG. 1 mainly includes the following steps:

[0035] S10. Providing a substrate;

[0036] S20, preparing a second electrode plate of the capacitor on one side of the substrate; in the actual process of preparing the second electrode plate, it is necessary to combine a deposition process and a photolithography process to achieve the desired shape of the second electrode plate formed after photolithography, especially the shape of the second extension portion, can be achieved by combining different mask plates according to needs;

[0037] S30, preparing a dielectric layer and a first electrode plate on a side of the second electrode plate away from the substrate; specifically, a dielectric layer with the same thickness can be grown on the exposed outer surface of the second electrode plate by a growth process, and the first electrode plate can be prepared by combining a deposition process and a photolithography process;

[0038] S40, preparing a second source and drain electrode, an interlayer insulating layer and a first source and drain electrode layer on a side of the first electrode plate away from the substrate, and forming via holes penetrating the above layers to serve as preparation spaces for subsequent layers;

[0039] S50, sequentially growing a channel layer and a gate dielectric layer in the via hole;

[0040] S60, depositing a gate material to form a gate; finally, the upper surface of the gate may be polished by a CMP process, and subsequent layers (such as a protection layer, a word line metal layer, etc.) may be prepared.

[0041] It should be noted that the above-mentioned preparation processes can be directly implemented by conventional processes in semiconductor processing, and will not be described in detail in this embodiment.

[0042] This embodiment adopts a transistor with a CAA architecture in which the channel surrounds the gate, optimizes the horizontal channel transistor into a vertical channel transistor, and utilizes the space in the vertical direction to set the source and drain, thereby reducing the area occupied by the transistor in the horizontal direction, which is beneficial for arranging more transistor structures while keeping the total area of ​​the chip unchanged; at the same time, the longitudinal space is utilized to set the capacitor, which is beneficial for improving the electrical connection effect between the transistor and the capacitor, and is also beneficial for reducing the area occupied by the capacitor in the horizontal direction. Combined with the extension of the two plates of the capacitor, the contact area between the plates is increased to increase the capacitance of the capacitor, and the vertical space is fully utilized to complete the deployment of transistors and capacitors, so as to improve the storage unit layout density and complete the chip miniaturization design.

[0043] The second embodiment of the present disclosure provides a memory, which can be a DRAM memory, at least including a plurality of memory cells provided by the first embodiment of the present disclosure, the memory cells are arranged according to a preset array, the gates of the memory cells in the same row are controlled by the same word line, and the second source and drain of the memory cells in the same column are controlled based on the same bit line. In actual implementation, a stacking structure design of multiple array boards can also be realized, and more memory cells can be arranged by using vertical space to increase the storage capacity.

[0044] The third embodiment of the present disclosure provides an electronic device, which at least includes the memory provided by the third embodiment of the present disclosure. Specifically, the electronic device can be a mobile phone, a computer, a tablet computer, a smart watch, a smart TV, or other device with computing and processing functions.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A storage unit, characterized in that: include: A substrate, a transistor unit and a capacitor sequentially arranged on a surface of one side of the substrate; The transistor unit at least includes: a first source and drain, a second source and drain, a channel layer, a gate dielectric layer, a gate and an interlayer insulating layer; wherein, The gate extends in a direction perpendicular to the surface of the substrate, the gate dielectric layer is disposed around the outside of the gate, the channel layer is disposed around the outside of the gate dielectric layer, the first source and drain are disposed around an end of the gate away from the substrate and are located outside the channel layer, the second source and drain are disposed around an end of the gate close to the substrate and are located outside the channel layer, and the interlayer insulating layer is disposed around the outside of the gate and is located between the first source and drain and the second source and drain; The capacitor at least comprises: a first plate, a second plate, and a dielectric layer located between the first plate and the second plate; wherein, The first electrode plate is electrically connected to the second source and drain, and has a first extension portion extending toward the substrate. The second electrode plate is arranged on a side surface of the substrate and has a second extension portion extending away from the substrate. The shapes of the first extension portion and the second extension portion match each other.

2. The storage unit according to claim 1, characterized in that The orthographic projection of the capacitor on the substrate surface is completely covered by the orthographic projection of the transistor unit on the substrate surface.

3. The storage unit according to claim 1, characterized in that The second electrode plate is grounded.

4. The storage unit according to claim 1, characterized in that The second source and drain are integrated with the first electrode plate.

5. The storage unit according to claim 1, characterized in that The first source and drain electrode, the second source and drain electrode, the first electrode plate and the second electrode plate are made of any one of the following materials: aluminum, copper, tungsten, molybdenum, titanium nitride, indium tin oxide, and indium zinc oxide.

6. The storage unit according to claim 1, characterized in that The channel layer is made of indium gallium zinc oxide (IGZO) material.

7. The storage unit according to any one of claims 1 to 6, characterized in that: The gate dielectric layer and the dielectric layer are made of high dielectric constant materials.

8. The storage unit according to claim 7, characterized in that The gate dielectric layer and the dielectric layer are made of any one of the following materials: hafnium oxide HfO2, zirconium oxide ZrO2, and hafnium silicate nitride HfSiON.

9. A memory, characterized in that: It comprises a plurality of storage units as claimed in any one of claims 1 to 7, wherein the plurality of storage units are arranged in an array.

10. An electronic device, characterized in that: At least comprising the memory as claimed in claim 9.

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