Semiconductor device, capacitor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor device, a capacitor structure and a manufacturing method thereof, and is applied to the technical field of semiconductors. According to the capacitor structure, the semiconductor layer and the oxide layer are arranged in the capacitor structure, so that the purposes of improving the efficiency and the reliability of a semiconductor device while providing a new structure of the capacitor structure are achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device, a capacitor structure and a manufacturing method thereof. Background Art

[0002] Dynamic random access memory (DRAM) is a type of volatile memory, including an array area consisting of multiple memory cells and a peripheral area consisting of a control circuit. Each memory cell is composed of a transistor and a capacitor electrically connected to the transistor, and the transistor controls the storage or release of the charge in the capacitor to achieve the purpose of storing data. The control circuit can address each memory cell to control the access of data to each memory cell through word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell. However, due to the limitations of process technology, the existing dynamic random access memory still has many defects, and further improvements are needed to effectively enhance the performance and reliability of related memory components. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor device, a capacitor structure and a manufacturing method thereof, so as to improve the performance and reliability of the semiconductor device and the capacitor structure.

[0004] In a first aspect, in order to solve the above technical problems, the present invention provides a semiconductor device, which may include: a substrate;

[0005] A plurality of capacitor structures are arranged on the substrate at intervals, wherein the capacitor structures include: a lower electrode, a capacitor dielectric layer, an upper electrode, and a semiconductor layer stacked in sequence;

[0006] Wherein, an oxide layer is further disposed between the upper electrode and the semiconductor layer in at least one of the capacitor structures.

[0007] Optionally, the semiconductor device may further include:

[0008] A plurality of support structures are disposed between adjacent lower electrodes and include multiple support layers spaced apart in a vertical direction. The capacitor dielectric layer and the upper electrode also extend and cover the spaces between adjacent support layers in the support structure.

[0009] Optionally, the lower electrode of the capacitor structure may include a cylindrical or columnar shape.

[0010] Optionally, the upper electrode of the capacitor structure having the cylindrical lower electrode may be surrounded by a first gap.

[0011] Optionally, a second gap may be formed around the upper electrode in the interval between the support layers.

[0012] Optionally, the oxide layer is located on an inner surface of the first gap or the second gap, and surrounds the third gap to form a third gap.

[0013] Alternatively, the oxide layer may include a discontinuous oxide.

[0014] Optionally, the discontinuous oxide may have a plurality of air gaps, wherein the plurality of air gaps interrupt the discontinuous oxide into a plurality of sub-segments spaced apart from each other.

[0015] Optionally, the oxide layer has a plurality of gaps.

[0016] Optionally, the semiconductor layer is located on the oxide layer and fills the third gap.

[0017] In a second aspect, in order to solve the above technical problems, the present invention further provides a capacitor structure, which may at least include:

[0018] The surrounding structure includes a semiconductor layer, an oxide layer, an upper electrode, a capacitor dielectric layer and a lower electrode in sequence from the outside to the inside, wherein the oxide layer physically contacts the semiconductor layer and the upper electrode.

[0019] Optionally, the surrounding structure may further include the capacitor dielectric layer, the upper electrode, the oxide layer and the semiconductor layer from the lower electrode inward.

[0020] Optionally, the lower electrode of the capacitor structure may include a cylindrical or columnar shape.

[0021] In a third aspect, in order to solve the above technical problems, the present invention also provides a method for manufacturing a semiconductor device, which may include:

[0022] providing a substrate;

[0023] A plurality of capacitor structures are formed and arranged on the substrate at intervals. The capacitor structures include a lower electrode, a capacitor dielectric layer, an upper electrode, and a semiconductor layer stacked in sequence. An oxide layer is sandwiched between the upper electrode and the semiconductor layer in at least one of the capacitor structures.

[0024] Optionally, the method for manufacturing the semiconductor device may further include:

[0025] A plurality of support structures are formed between adjacent lower electrodes and include multiple support layers spaced apart in a vertical direction. The capacitor dielectric layer and the upper electrode also extend and cover the spaces between adjacent support layers in the support structure.

[0026] Optionally, the lower electrode of the capacitor structure may include a cylindrical or columnar shape.

[0027] Alternatively, the oxide layer may include a discontinuous oxide.

[0028] Optionally, the discontinuous oxide may have a plurality of air gaps, and the plurality of air gaps may interrupt the discontinuous oxide into a plurality of sub-segments.

[0029] Optionally, the oxide layer may have a plurality of gaps.

[0030] Optionally, the semiconductor layer may be located on the oxide layer and fill the plurality of gaps or the plurality of air gaps.

[0031] In the present invention, the semiconductor device may include multiple capacitor structures, each of which includes a lower electrode, a capacitor dielectric layer, an upper electrode, and a semiconductor layer stacked in sequence, and an oxide layer is sandwiched between the upper electrode and the semiconductor layer in at least one capacitor structure, so as to propose a new structure of the capacitor structure and simultaneously achieve the purpose of improving the performance and reliability of the semiconductor device and the capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0033] Figure 1 to Figure 4 It is a schematic structural diagram of the semiconductor device provided in the first embodiment of the present invention during the preparation process.

[0034] Figures 5 to 8 It is a schematic structural diagram of a semiconductor device provided in a second embodiment of the present invention during the preparation process.

[0035] Figure 9-10 It is a schematic structural diagram of a semiconductor device provided in a third embodiment of the present invention during the preparation process.

[0036] Figure 11-12 It is a schematic structural diagram of a semiconductor device provided in a fourth embodiment of the present invention during the preparation process.

[0037] Wherein, the accompanying drawings are marked as follows:

[0038] 100-substrate, 110-support structure, 111-first support layer, 113-second support layer, 115-third support layer, 120-capacitor structure, 121-lower electrode, 122-capacitor dielectric layer, 123-upper electrode, 130-oxide layer, 140-semiconductor layer, 101-first gap, 102-second gap, 103-third gap, 104-air gap, 105-notch, 131-sub-segment.

[0039] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0040] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0041] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It is understood that the meanings of "on", "above" and "above" in the present invention should be interpreted in the broadest way, so that "on" not only means that it is "on" something and there are no intervening features or layers (i.e. directly on something), but also includes the meaning of being "on" something and having intervening features or layers.

[0042] Additionally, for ease of description, spatially relative terms such as "on," "over," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0043] In the embodiments of the present invention, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions recorded in the embodiments of the present invention can be combined arbitrarily without conflict.

[0044] Please refer to Figure 3 and Figure 4 ,in Figure 3 is a cross-sectional schematic diagram of a semiconductor device in a first embodiment of the present invention, Figure 4 for Figure 3 The semiconductor device is shown as a top view along the AA cut line. The semiconductor device of the present invention can be used to manufacture dynamic random access memory (DRAM). Without departing from the spirit of the present invention, the present invention can also be applied to other types of memory.

[0045] like Figure 3 and Figure 4 As shown, the semiconductor device includes a substrate 100, which may be, for example, a silicon substrate, a silicon-containing substrate (such as SiC, SiGe) or a silicon-on-insulator substrate or a substrate composed of other suitable materials, but is not limited thereto. A plurality of capacitor structures 120 arranged at intervals from each other are arranged on the substrate 100 in a direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction). The capacitor structure 120 may include a lower electrode 121, a capacitor dielectric layer 122, an upper electrode 123, and a semiconductor layer 140 stacked in sequence, and an oxide layer 130 is also sandwiched between the upper electrode 123 and the semiconductor layer 140 in at least one of the plurality of capacitor structures 120.

[0046] It should be understood that the substrate 100 may further include components such as a bit line structure, a sidewall structure, a contact structure, and a connection pad structure (not shown), but the present invention is not limited thereto.

[0047] Specifically, in the first embodiment of the present invention, the lower electrode 121 of the capacitor structure 120 is cylindrical in shape, and the multiple lower electrodes 121 in the multiple capacitor structures 120 are arranged on the substrate 100 in a spaced relationship along the horizontal direction, and a support structure 110 is also arranged between the adjacent lower electrodes 121; the capacitor dielectric layer 122, the upper electrode 123 and the oxide layer 130 in the capacitor structure 120 are conformally covered on the multiple lower electrodes 121 in the cylindrical shape, and the semiconductor layer 140 fills the gaps in the oxide layer 130 in the multiple capacitor structures 120. Further, the support structure 110 may include multiple support layers arranged in sequence from bottom to top, such as a first support layer 111, a second support layer 113 and a third support layer 115 arranged in sequence from bottom to top along the vertical direction. The capacitor dielectric layer 122, the upper electrode 123, the oxide layer 130, and the semiconductor layer 140 in the multiple capacitor structures 120 also extend and cover the gaps between adjacent support layers in the multiple support structures 110, such as the gap between the first support layer 111 and the second support layer 113, and the gap between the second support layer 113 and the third support layer 115, but is not limited to this.

[0048] In one embodiment, the material of the lower electrode 121 and the upper electrode 123 may include titanium nitride, tantalum nitride, SiGe, a combination of the above materials, or other suitable multilayer conductive materials, but not limited thereto; the capacitor dielectric layer 122 may include a high dielectric constant material layer, such as TaOO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST ((Ba, Sr)TiO), STO (SrTiO), BTO (BaTiO), PZT (Pb (Zr, Ti) O), (Pb, La) (Zr, Ti) O, Ba (Zr, Ti) OO, Sr (Zr, Ti) O, a combination of the above materials, or other suitable dielectric materials, but not limited thereto; the material of the oxide layer 130 may be an insulating material, such as oxide or nitride, but not limited thereto; the material of the semiconductor layer 140 may be single crystal silicon (crystalline silicon), polycrystalline silicon (poly The materials of the first support layer 111, the second support layer 113 and the third support layer 115 in the support structure 110 may be oxide materials, such as silicon oxide, boro-phospho-silicate-glass (BPSG), but not limited thereto.

[0049] A person skilled in the art of the present invention should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device of the present invention may also have other aspects and is not limited to the above. Other embodiments or variations of the semiconductor device of the present invention will be further described below. In order to simplify the description, the following description mainly describes the differences between the embodiments, and does not repeat the same aspects. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0050] Please refer to Figure 7 and Figure 8 ,in Figure 7 is a cross-sectional schematic diagram of a semiconductor device in a second embodiment of the present invention, Figure 8 for Figure 7 The top view of the semiconductor device shown is along the AA cut line. Figure 7 and Figure 8 As shown, the structure of the semiconductor device of this embodiment is substantially the same as that of the semiconductor device in the aforementioned first embodiment, such as the semiconductor device also includes a substrate 100 and a plurality of capacitor structures 120 disposed on the substrate 100, and the capacitor structure 120 may also include a lower electrode 121, a capacitor dielectric layer 122, an upper electrode 123, and a semiconductor layer 140 stacked in sequence, and an oxide layer 130 is also sandwiched between the upper electrode 123 and the semiconductor layer 140 in at least one of the plurality of capacitor structures 120, etc., and the same parts are not repeated here. The main difference between the semiconductor device of this embodiment and the aforementioned first embodiment is that the shape of the lower electrode 121 in the capacitor structure 120 in this embodiment is columnar; under this setting, the capacitor dielectric layer 122, the upper electrode 123 and the oxide layer 130 in each capacitor structure 120 are sequentially conformally formed on the surface of the plurality of columnar lower electrodes 121, that is, the upper electrode 123 in each capacitor structure 120 in this embodiment is not provided with the first gap 101, as shown in FIG. Figure 5 Similarly, the oxide layer 130 formed subsequently in the capacitor structure 120 is also not provided with a third gap 103, such as Figure 6 shown.

[0051] Please refer to Fig. 9 and Fig.10 ,in Fig. 9 is a cross-sectional schematic diagram of a semiconductor device in a third embodiment of the present invention, Fig.10 for Fig. 9 The top view of the semiconductor device shown is along the AA cut line. Fig. 9 and Fig.10As shown, the structure of the semiconductor device of this embodiment is substantially the same as the structure of the semiconductor device in the aforementioned first or second embodiment, such as the semiconductor device also includes a substrate 100 and a plurality of capacitor structures 120 disposed on the substrate 100, and the capacitor structure 120 may also include a lower electrode 121, a capacitor dielectric layer 122, an upper electrode 123, and a semiconductor layer 140 stacked in sequence, and an oxide layer 130 is further sandwiched between the upper electrode 123 and the semiconductor layer 140 in at least one of the plurality of capacitor structures 120, etc., and the same parts are not repeated here. The main difference between the semiconductor device of this embodiment and the first or second embodiment is that the oxide layer 130 in the capacitor structure 120 and the gap between the adjacent support layers in the support structure 110 in this embodiment can be a discontinuous oxide (e.g., discontinuous silicon dioxide); specifically, the oxide layer 130 of the discontinuous oxide can have a plurality of air gaps 104, and the plurality of air gaps 104 interrupt the oxide layer 130 (i.e., the discontinuous oxide) into a plurality of mutually spaced sub-segments 131. In this way, the semiconductor layer 140 formed subsequently not only fills the third gap 103 formed around the oxide layer 130, but also further fills the plurality of air gaps 104 in the oxide layer 130, so that the semiconductor layer 140 passes through the oxide layer 130 through the air gaps 104 and directly contacts the upper electrode 123 in the capacitor structure 120 or the support structure 110. In one embodiment, the widths or depths of the plurality of air gaps 104 along the horizontal direction or the vertical direction may be the same or different, and the intervals between adjacent air gaps 104 may be the same or different.

[0052] Please refer to Fig.11 and Fig.12 ,in Fig.11 is a cross-sectional schematic diagram of a semiconductor device in a fourth embodiment of the present invention, Fig.12 for Fig.11 The top view of the semiconductor device shown is along the AA cut line. Fig.11 and Fig.12As shown, the structure of the semiconductor device of this embodiment is substantially the same as that of the semiconductor device in the first to third embodiments described above, such as the semiconductor device also includes a substrate 100 and a plurality of capacitor structures 120 disposed on the substrate 100, and the capacitor structure 120 may also include a lower electrode 121, a capacitor dielectric layer 122, an upper electrode 123, and a semiconductor layer 140 stacked in sequence, and an oxide layer 130 is also sandwiched between the upper electrode 123 and the semiconductor layer 140 in at least one of the plurality of capacitor structures 120, etc., and the same is not repeated here. The main difference between the semiconductor device of this embodiment and the first to third embodiments described above is that: in this embodiment, the oxide layer 130 located in the capacitor structure 120 and in the interval between the adjacent support layers in the support structure 110 may have a plurality of notches 105, and the bottoms of the plurality of notches 105 all have oxide layers 130 remaining. In this way, the plurality of notches 105 make the surface of the oxide layer 130 present an uneven wave shape, and the semiconductor layer 140 formed subsequently not only fills the third gap 103 formed around the oxide layer 130, but also further fills the plurality of notches 105 in the oxide layer 130, but the semiconductor layer 140 in this embodiment is only in direct contact with the oxide layer 130. In one embodiment, the width, depth or shape of the plurality of notches 105 along the horizontal direction or the vertical direction may be the same or different, and the intervals between adjacent notches 105 may be the same or different.

[0053] In addition, based on the above, the fifth embodiment of the present invention further provides a capacitor structure, such as Figure 4 , Figure 8 , Fig.10 or Fig.12 As shown, the capacitor structure may specifically include:

[0054] The surrounding structure includes, from outside to inside, a semiconductor layer 140 , an oxide layer 130 , an upper electrode 123 , a capacitor dielectric layer 122 and a lower electrode 121 , wherein the oxide layer 130 physically contacts the semiconductor layer 140 and the upper electrode 123 .

[0055] In one embodiment, the surrounding structure further includes the capacitor dielectric layer 122, the upper electrode 123, the oxide layer 130 and the semiconductor layer 140 from the lower electrode 121 inward. In addition, the lower electrode 121 of the capacitor structure includes a cylindrical or columnar shape, but is not limited thereto. Further, the oxide layer 130 may include a discontinuous oxide; illustratively, the discontinuous oxide may have a plurality of air gaps 104, so that the oxide layer 130 (i.e., the discontinuous oxide) is interrupted into a plurality of mutually spaced sub-segments 131 through the plurality of air gaps 104; or, the oxide layer 130 has a plurality of gaps 105, and the semiconductor layer 140 fills the third gap 103, the plurality of air gaps 104 or the plurality of gaps 105 formed around the oxide layer 130, but is not limited thereto.

[0056] It should be understood that the "common shape" in the present invention refers to constructing a continuous structural shape by utilizing the morphological similarities and correlations between two or more shapes.

[0057] In order to enable general technicians in the technical field to which the present invention belongs to easily understand the semiconductor device in the embodiment of the present invention, the embodiment of the present invention also provides a method for manufacturing the semiconductor device. The following will further illustrate the method for manufacturing the semiconductor device proposed in the present invention in combination with various structural schematic diagrams of the manufacturing method during the preparation process.

[0058] in, Figure 1 to Figure 4 It is a structural schematic diagram of the manufacturing method of the semiconductor device provided in the first embodiment of the present invention during the manufacturing process.

[0059] See also Figure 1The formation of the capacitor structure 120 having the cylindrical lower electrode 121 is, for example, first providing a substrate 100 (material is, for example, a silicon substrate), and then using a deposition process to form a multilayer structure of a support structure 110 on the substrate 100, such as the first support layer 111 (material is, for example, silicon oxide or borophosphosilicate glass), a first sacrificial layer (not shown), a second support layer 113 (material is, for example, silicon oxide or borophosphosilicate glass), a second sacrificial layer (not shown), and a third support layer 115 (material is, for example, silicon oxide or borophosphosilicate glass), and then forming a plurality of through holes ( Not shown), and using at least one of a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process, a lower electrode material layer (material such as titanium nitride, tantalum nitride, or SiGe) is conformally formed in the plurality of through holes, that is, a plurality of lower electrodes 121 are formed on the substrate 100, and then after removing part of the supporting structure 110 by using a photolithography and etching process such as a dry etching process and / or a wet etching process, a deposition process is further used to conformally form the capacitor dielectric layer 122 (material such as a high dielectric constant material layer) and the upper electrode 123 (material such as titanium nitride, tantalum nitride, or SiGe).

[0060] It should be understood that under this configuration, the conformally formed upper electrode 123 surrounds and forms a first gap 101 in each capacitor structure 120 , and surrounds and forms a second gap 102 in the interval between adjacent support layers in the support structure 110 .

[0061] See also Figure 2 Then, the oxide layer 130 (the material is, for example, oxide or nitride) is conformally formed by a deposition process such as a chemical vapor deposition process. In this way, the conformally formed oxide layer 130 is specifically located on the upper electrode 123 and on the inner surface of the first gap 101 or the second gap 102, thereby forming a third gap 103 around the upper electrode 123 on the substrate 100.

[0062] See also Figure 3 or Figure 4 Finally, a deposition process such as a chemical vapor deposition process is used to form a semiconductor layer 140 (material such as semiconductor materials such as single crystal silicon and polycrystalline silicon) which fills the third gap 103 and has a top surface higher than the top surface of the oxide layer 130 .

[0063] Obviously, the semiconductor device formed by the manufacturing method provided in the embodiment of the present invention may include a substrate 100, and a plurality of capacitor structures 120 located on the substrate 100 and spaced apart from each other; specifically, the capacitor structure 120 includes: a lower electrode 121, a capacitor dielectric layer 122, an upper electrode 123, and a semiconductor layer 140 stacked in sequence; wherein, an oxide layer 130 is also sandwiched between the upper electrode 123 and the semiconductor layer 140 in at least one of the capacitor structures 120, and the capacitor dielectric layer 122 and the upper electrode 123 also extend to cover the gap between adjacent support layers in the support structure 110.

[0064] Furthermore, in order to enable a person skilled in the art to which the present invention belongs to easily understand the semiconductor device and the capacitor structure in the second embodiment of the present invention, the present invention also provides a method for manufacturing the semiconductor device and the capacitor structure in the second embodiment, wherein Figures 5 to 8 The structure diagram of the manufacturing method of the semiconductor device provided in the second embodiment of the present invention during the manufacturing process is shown in FIG. Since the semiconductor device of the second embodiment of the present invention is substantially the same as that of the first embodiment, the manufacturing method of the corresponding components and / or devices is also the same. The same parts of the manufacturing method of the second embodiment of the present invention and the first embodiment will not be described in detail below, and only the different manufacturing processes between the two will be explained.

[0065] Specifically, if Figure 5 As shown, in the process of forming a plurality of lower electrodes 121 on the substrate 100 by conformally forming a lower electrode material layer (material such as titanium nitride, tantalum nitride or SiGe) in the plurality of through holes using a deposition process such as at least one of a physical vapor deposition process, a chemical vapor deposition process and an atomic layer deposition process, the shape of the lower electrode 121 formed in the through hole in the second embodiment of the present invention is different from the shape of the lower electrode 121 in the first embodiment, that is, the shape of the lower electrode 121 in the capacitor structure 120 in the second embodiment of the present invention is a columnar shape. Under this setting, the portion of the upper electrode 123 formed conformally thereafter in the capacitor structure 120 does not enclose the first gap 101, but only surrounds the second gap 102 in the interval between adjacent support layers in the support structure 110.

[0066] Furthermore, in order to enable a general technician in the technical field to which the present invention belongs to easily understand the semiconductor device in the third embodiment of the present invention, the present invention also provides a method for manufacturing the semiconductor device in the second embodiment. Since the semiconductor device in the third embodiment of the present invention is substantially the same as the aforementioned first or second embodiment, the manufacturing methods of its corresponding components and / or devices are also the same. The following will not repeat the same parts of the manufacturing methods of the third embodiment of the present invention as those of the aforementioned first or second embodiment, and only the different preparation processes between the two will be explained.

[0067] Specifically, if Fig. 9 As shown, the main difference between the third embodiment of the present invention and the manufacturing method in the first or second embodiment is that after the oxide layer 130 is conformally formed by a deposition process, an etching process such as a dry etching process can be further used to form a plurality of air gaps 104 with the same or different widths and / or depths in the oxide layer 130 to expose a portion of the top surface of the upper electrode 123 located in the capacitor structure 120 or the support structure 110, but not limited to this.

[0068] Furthermore, in order to enable a general technician in the technical field to which the present invention belongs to easily understand the semiconductor device in the fourth embodiment of the present invention, the present invention also provides a method for manufacturing the semiconductor device in the fourth embodiment. Since the semiconductor device in the fourth embodiment of the present invention is substantially the same as the aforementioned first to third embodiments, the manufacturing methods of its corresponding components and / or devices are also the same. The following will not repeat the same parts of the fourth embodiment of the present invention as the manufacturing methods of the aforementioned first to third embodiments, and only the different preparation processes between the two will be explained.

[0069] Specifically, if Fig.11 As shown, the main difference between the fourth embodiment of the present invention and the manufacturing method in the aforementioned first to third embodiments is that after the oxide layer 130 is conformally formed by a deposition process, an etching process such as a dry etching process can be further used to form a plurality of gaps 105 with the same or different widths, depths and / or shapes in the oxide layer 130, and the gaps 105 do not penetrate the oxide layer 130, but are not limited to this.

[0070] It should be understood that the capacitor structure 120 in the fifth embodiment of the present invention is the capacitor structure 120 corresponding to the semiconductor device in any one of the first to fourth embodiments above. Therefore, the manufacturing method of the capacitor structure 120 in the fifth embodiment can be specifically referred to the manufacturing method corresponding to the semiconductor device in any one of the first to fourth embodiments above, and will not be repeated here.

[0071] In summary, the multiple capacitor structures in the present invention respectively include a lower electrode, a capacitor dielectric layer, an upper electrode, and a semiconductor layer stacked in sequence, and an oxide layer is also sandwiched between the upper electrode and the semiconductor layer in at least one capacitor structure, so as to propose a new structure of the capacitor structure and simultaneously achieve the purpose of improving the performance and reliability of the semiconductor device.

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; A plurality of capacitor structures are arranged on the substrate at intervals, wherein the capacitor structures include: a lower electrode, a capacitor dielectric layer, an upper electrode, and a semiconductor layer stacked in sequence; Wherein, an oxide layer is further disposed between the upper electrode and the semiconductor layer in at least one of the capacitor structures.

2. The semiconductor device according to claim 1, wherein Also includes: A plurality of support structures are disposed between adjacent lower electrodes and include multiple support layers spaced apart in a vertical direction. The capacitor dielectric layer and the upper electrode also extend and cover the spaces between adjacent support layers in the support structure.

3. The semiconductor device according to claim 1, wherein The lower electrode of the capacitor structure includes a cylindrical shape or a columnar shape.

4. The semiconductor device according to claim 3, characterized in that The upper electrode of the capacitor structure having the lower electrode in the cylindrical shape surrounds and forms a first gap.

5. The semiconductor device according to claim 2, wherein: A second gap is formed around the upper electrode in the space between the support layers.

6. The semiconductor device according to claim 4 or 5, characterized in that The oxide layer is located on an inner surface of the first void or the second void and surrounds a third void.

7. The semiconductor device according to claim 6, wherein: The oxide layer includes a discontinuous oxide.

8. The semiconductor device according to claim 7, wherein: The discontinuous oxide has a plurality of air gaps, which interrupt the discontinuous oxide into a plurality of sub-segments spaced apart from each other.

9. The semiconductor device according to claim 6, wherein: The oxide layer has a plurality of gaps.

10. The semiconductor device according to claim 8 or 9, characterized in that The semiconductor layer is located on the oxide layer and fills the third gap, the plurality of notches or the plurality of air gaps.

11. A capacitor structure, characterized in that: include: The surrounding structure includes a semiconductor layer, an oxide layer, an upper electrode, a capacitor dielectric layer and a lower electrode in sequence from the outside to the inside, wherein the oxide layer physically contacts the semiconductor layer and the upper electrode.

12. The capacitor structure according to claim 11, characterized in that: The surrounding structure further includes the capacitor dielectric layer, the upper electrode, the oxide layer and the semiconductor layer from the lower electrode inward.

13. The capacitor structure according to claim 11, characterized in that: The lower electrode of the capacitor structure includes a cylindrical shape or a columnar shape.

14. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; A plurality of capacitor structures are formed and arranged on the substrate at intervals. The capacitor structures include a lower electrode, a capacitor dielectric layer, an upper electrode, and a semiconductor layer stacked in sequence. An oxide layer is sandwiched between the upper electrode and the semiconductor layer in at least one of the capacitor structures.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: Also includes: A plurality of support structures are formed between adjacent lower electrodes and include multiple support layers spaced apart in a vertical direction. The capacitor dielectric layer and the upper electrode also extend and cover the spaces between adjacent support layers in the support structure.

16. The method for manufacturing a semiconductor device according to claim 14, wherein: The lower electrode of the capacitor structure includes a cylindrical shape or a columnar shape.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The oxide layer includes a discontinuous oxide.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: The discontinuous oxide has a plurality of air gaps that interrupt the discontinuous oxide into a plurality of sub-segments.

19. The method for manufacturing a semiconductor device according to claim 16, wherein: The oxide layer has a plurality of gaps.

20. The method for manufacturing a semiconductor device according to claim 18 or 19, characterized in that: The semiconductor layer is located on the oxide layer and fills the plurality of gaps or the plurality of air gaps.

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