Semiconductor devices, three-dimensional memory devices, and methods of forming the same

Abstract

Disclosed herein are semiconductor devices, three-dimensional memory devices, and methods of forming the same. A semiconductor device includes a semiconductor layer, a stack structure over the semiconductor layer, a first contact structure, and a second contact structure. The stack structure includes alternating first layers and first dielectric layers. The stack structure includes a first portion and a second portion adjacent to the first portion, the first layers of the first portion include second dielectric layers, and the first layers of the second portion include conductive layers. The first contact structure extends through the first portion and the semiconductor layer. The second contact structure extends through a portion of the first portion and is connected with one of the conductive layers.

Description

Background Technology

[0001] This disclosure relates to semiconductor devices having multiple contact structures, three-dimensional (3D) memory devices, and methods for manufacturing the same.

[0002] Through improvements in process technology, circuit design, programming algorithms, and manufacturing processes, planar memory cells have been scaled to smaller sizes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells is approaching its upper limit.

[0003] 3D memory architecture can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention

[0004] In one aspect, a semiconductor device includes a semiconductor layer, a stacked structure situated on the semiconductor layer, a first contact structure, and a second contact structure. The stacked structure includes alternating first layers and first dielectric layers. The stacked structure includes a first portion and a second portion adjacent to the first portion, the first layer of the first portion including a second dielectric layer, and the first layer of the second portion including a conductive layer. The first contact structure extends through the first portion and the semiconductor layer. The second contact structure extends through a portion of the first portion and is connected to a conductive layer in the conductive layers.

[0005] In some embodiments, the first contact structure includes a first segment and a second segment connected to the first segment in a first direction. The first segment includes a first end that contacts the second segment, and the second segment includes a second end that contacts the first segment. In the second direction perpendicular to the first direction, the dimension of the first end is larger than the dimension of the second end.

[0006] In some embodiments, the first segment further includes a third end remote from the first end, and the second segment further includes a fourth end remote from the second end. In a second direction, the third end is larger than the first end, and in the second direction, the second end is larger than the fourth end.

[0007] In some implementations, the first segment is located on the side of the second segment away from the semiconductor layer.

[0008] In some embodiments, the second contact structure includes a vertical direct contact structure and a lateral contact structure connected to the vertical direct contact structure. The vertical direct contact structure extends in the same direction as the first contact structure. The lateral contact structure is connected to a conductive layer in the conductive layer.

[0009] In some embodiments, the first contact structure includes a first junction located in the first stack pair, and a vertical contact structure extends into the first stack pair. The first stack pair is a pair including one of the first dielectric layers and one of the first layers in contact with the first dielectric layer.

[0010] In some embodiments, the semiconductor device further includes a third contact structure extending through a portion of the first portion. The third contact structure is connected to a second stack pair, and the first contact structure includes a second junction located within the second stack pair.

[0011] In some embodiments, the first contact structure includes a first conductor layer and a first spacer surrounding the first conductor layer. The second contact structure includes a second conductor layer and a second spacer surrounding the second conductor layer. The first spacer and the second spacer comprise the same material, and the first conductor layer and the second conductor layer comprise the same material.

[0012] In some embodiments, the first contact structure further includes a first filler body surrounded by a first conductor layer.

[0013] In some embodiments, the second contact structure further includes a second filler body surrounded by a second conductor layer, and the first filler body and the second filler body comprise the same material.

[0014] In some embodiments, the semiconductor device further includes a channel structure that extends through the second portion into the semiconductor layer.

[0015] In some implementations, the length of the first contact structure is greater than the length of the channel structure in the vertical direction.

[0016] In some embodiments, the second part includes the first part and a second part spaced apart from the first part. The first part connects the first part and the second part.

[0017] In some embodiments, the semiconductor device further includes peripheral circuitry connected to the first contact structure.

[0018] In some embodiments, the semiconductor device further includes a first interconnect layer and a second interconnect layer, the first interconnect layer being connected to a first contact structure and the second interconnect layer being connected to peripheral circuitry. The first interconnect layer and the second interconnect layer are bonded together.

[0019] In some implementations, the peripheral circuitry is disposed beneath the stacked structure, and the first contact structure extends through the semiconductor layer to connect to the peripheral circuitry.

[0020] In another embodiment, the memory device includes a first semiconductor structure, a second semiconductor structure, and a first peripheral circuit. The first semiconductor structure includes: a first stacked structure comprising alternating first and second dielectric layers; and a first contact structure extending through the first stacked structure. The second semiconductor structure includes: a second stacked structure comprising alternating third and fourth dielectric layers; and a second contact structure extending through the second stacked structure. The first peripheral circuit is connected to the first and second contact structures.

[0021] In some implementations, the first peripheral circuit is bonded to the first semiconductor structure, and the first peripheral circuit includes a first connection structure located between the first semiconductor structure and the second semiconductor structure.

[0022] In some embodiments, the memory device further includes a second peripheral circuit bonded to the second semiconductor structure. The second peripheral circuit includes a second connection structure connecting to the second contact structure.

[0023] In some implementations, the second semiconductor structure is located between the first peripheral circuit and the second peripheral circuit.

[0024] In some implementations, the first peripheral circuitry also includes a semiconductor layer and interconnect structures extending through the semiconductor layer.

[0025] In some embodiments, the first contact structure includes an insulating filler and a conductive layer surrounding the insulating filler, the interconnect structure includes a conductive filler and a spacer surrounding the conductive filler, and the conductive layer is connected to the conductive filler.

[0026] In some embodiments, the first contact structure includes a first segment and a second segment connected to the first segment in a first direction. The first segment includes a first end that contacts the second segment, and the second segment includes a second end that contacts the first segment. In the second direction perpendicular to the first direction, the size of the first end is larger than the size of the second end.

[0027] In some embodiments, the first segment further includes a third end remote from the first end, and the second segment further includes a fourth end remote from the second end, wherein the third end is larger than the first end in a second direction, and the second end is larger than the fourth end in a second direction.

[0028] In some implementations, the first stacked structure is disposed on the semiconductor layer, and the first segment is located on the side of the second segment away from the semiconductor layer.

[0029] In some embodiments, the first semiconductor structure further includes a third contact structure extending through a portion of the first stacked structure. The third contact structure includes a vertical direct contact structure and a lateral contact structure connected to the vertical direct contact structure, and the vertical direct contact structure extends in the same direction as the first contact structure.

[0030] In some embodiments, the first contact structure includes a first junction located in the first stack pair, and a vertical contact structure extends into the first stack pair. The first stack pair is a pair including a first dielectric layer in a first dielectric layer and a second dielectric layer in a second dielectric layer that contacts the first dielectric layer in the first dielectric layer.

[0031] In some embodiments, the memory device further includes a fourth contact structure extending through a portion of the first stack structure. The fourth contact structure is connected to the second stack pair, and the first contact structure includes a second engagement portion located within the second stack pair.

[0032] In some embodiments, the first contact structure includes a first conductor layer and a first spacer surrounding the first conductor layer. The second contact structure includes a second conductor layer and a second spacer surrounding the second conductor layer. The third contact structure includes a second conductor layer and a second spacer surrounding the second conductor layer. The first spacer and the second spacer comprise the same material, and the first conductor layer and the second conductor layer comprise the same material.

[0033] In some embodiments, the first contact structure further includes a first filler body surrounded by a first conductor layer.

[0034] In another aspect, a method for forming a semiconductor device is disclosed. The method includes: forming a stacked structure comprising alternating first and second dielectric layers. The method further includes: forming a first contact hole extending through the stacked structure. The method further includes: during the formation of the first contact hole, forming a second contact hole extending through a portion of the stacked structure.

[0035] In some embodiments, forming a first contact hole and forming a second contact hole during the formation of the first contact hole includes: using a first mask to etch the stacked structure to form a first opening extending into the stacked structure and one or more second openings, wherein the second contact hole includes one or more second openings; and using a second mask to etch the first opening to form a third opening further extending through the stacked structure, wherein the first contact hole includes the first opening and the third opening.

[0036] In some embodiments, forming the second contact hole further includes etching the stacked structure using a third mask to form one or more fourth openings extending into the stacked structure. The second contact hole also includes one or more fourth openings.

[0037] In some embodiments, the method further includes: forming a first contact structure in a first contact hole, and forming a second contact structure in a second contact hole during the formation of the first contact structure.

[0038] In some embodiments, the first contact structure includes a first spacer, a first conductor layer surrounded by the first spacer, and a first filler body surrounded by the first conductor layer. The second contact structure includes a second spacer, a second conductor layer surrounded by the second spacer, a transverse contact structure connected to the second conductor layer, and a second filler body surrounded by the second conductor layer.

[0039] In some embodiments, forming the first contact structure and forming the second contact structure includes: forming a first spacer on the sidewall of the first contact hole and forming a second spacer on the sidewall of the second contact hole; forming a transverse contact structure of the second contact structure below the bottom of the second contact hole; forming a first conductor layer above the first spacer and the bottom of the first contact hole and forming a second conductor layer above the second spacer and the transverse contact structure; and filling the remaining portion of the first contact hole with a first filler body and filling the remaining portion of the second contact hole with a second filler body.

[0040] In some embodiments, the lateral contact structure in which the second contact structure is formed below the bottom of the second contact hole includes: removing the portions of the respective second dielectric layers exposed at the bottom of the second contact hole to form lateral recesses; and filling the lateral recesses by depositing conductive material through the second contact hole to form the lateral contact structure.

[0041] In some embodiments, forming the first contact structure and forming the second contact structure further includes: forming a first contact pad on the first conductor layer and the first filler body, respectively, and forming a second contact pad on the second conductor layer and the second filler body.

[0042] In another aspect, a semiconductor device includes a stacked structure, a first contact structure, and a second contact structure. The stacked structure includes alternating first and second dielectric layers. The first contact structure extends through the stacked structure and includes a first conductor layer and a first spacer surrounding a sidewall of the first conductor layer. The second contact structure extends through a portion of the stacked structure and includes a second conductor layer and a second spacer surrounding a sidewall of the second conductor layer. The first and second spacers include a first material, and the first and second conductor layers include a second material different from the first material.

[0043] In some embodiments, the first contact structure includes a first segment and a second segment connected to the first segment in a first direction. The first segment includes a first end that contacts the second segment, and the second segment includes a second end that contacts the first segment. In the second direction perpendicular to the first direction, the dimension of the first end is larger than the dimension of the second end.

[0044] In some embodiments, the first segment further includes a third end remote from the first end, and the second segment further includes a fourth end remote from the second end. In a second direction, the third end is larger than the first end, and in the second direction, the second end is larger than the fourth end.

[0045] In some implementations, the first stacked structure is disposed on the semiconductor layer, and the first segment is located on the side of the second segment away from the semiconductor layer.

[0046] In some embodiments, the second contact structure includes a vertical direct contact structure and a transverse contact structure connected to the vertical direct contact structure, and the vertical direct contact structure extends in the same direction as the first contact structure.

[0047] In some embodiments, the first contact structure includes a first junction located in the first stack pair, and a vertical contact structure extends into the first stack pair. The first stack pair is a pair including a first dielectric layer in a first dielectric layer and a second dielectric layer in a second dielectric layer that contacts the first dielectric layer in the first dielectric layer.

[0048] In some embodiments, the semiconductor device further includes a third contact structure extending through the stacked structure. The third contact structure is connected to the second stacked pair, and the first contact structure includes a second junction located in the second stacked pair.

[0049] In some embodiments, the semiconductor device further includes peripheral circuitry connected to the first contact structure and the second contact structure.

[0050] In another aspect, the memory device includes a first contact structure and a second contact structure. The first contact structure includes an insulating filler and a conductive layer surrounding the insulating filler and extending in a first direction. The second contact structure includes a conductive filler and a spacer surrounding the sidewalls of the conductive filler and extending in the first direction. The conductive layer is connected to the conductive filler.

[0051] In another aspect, a semiconductor device includes: a semiconductor layer; a stacked structure situated above the semiconductor layer and including alternating conductive and dielectric layers; a first contact structure extending through the stacked structure and including a first conductive layer and a first spacer surrounding a sidewall of the first conductive layer; and a second contact structure extending through a portion of the stacked structure and including a second conductive layer and a second spacer surrounding a sidewall of the second conductive layer. The second conductive layer is connected to a conductive layer in the conductive layers, and the first conductive layer is separated from the conductive layers by the first spacer. Attached Figure Description

[0052] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to implement and use this disclosure.

[0053] Figure 1A A plan view of a semiconductor structure having multiple contact structures according to some aspects of this disclosure is shown.

[0054] Figure 1B Another plan view of a semiconductor structure having multiple contact structures according to some aspects of this disclosure is shown.

[0055] Figure 2A A cross-sectional side view of a first exemplary embodiment of a contact structure according to some aspects of this disclosure is shown.

[0056] Figure 2B Some aspects of this disclosure are shown. Figure 2A A cross-sectional side view of the first contact structure in the image.

[0057] Figure 2C A cross-sectional side view of a second exemplary embodiment of a contact structure according to some aspects of this disclosure is shown.

[0058] Figure 3A A cross-sectional side view of a semiconductor device based on some examples is shown.

[0059] Figure 3B A cross-sectional side view of a semiconductor device having multiple contact structures according to some aspects of this disclosure is shown.

[0060] Figure 4A A cross-sectional side view of a 3D memory device based on some examples is shown.

[0061] Figure 4B A cross-sectional side view of a 3D memory device having multiple contact structures according to some aspects of this disclosure is shown.

[0062] Figure 4C A cross-sectional side view of another 3D memory device having multiple contact structures according to some aspects of this disclosure is shown.

[0063] Figure 5 A cross-sectional side view of another semiconductor device having multiple contact structures according to some aspects of this disclosure is shown.

[0064] Figure 6 A cross-sectional side view of another semiconductor device having multiple contact structures according to some aspects of this disclosure is shown.

[0065] Figure 7 This is a flowchart of a method for forming a semiconductor device having multiple contact structures according to some aspects of this disclosure.

[0066] Figures 8A-8F A manufacturing process for forming a semiconductor device having multiple contact structures is shown according to some aspects of this disclosure.

[0067] Figure 9 This is a flowchart of a method for forming multiple contact structures in a semiconductor structure according to some aspects of this disclosure.

[0068] Figures 10A-10G A manufacturing process for forming multiple contact structures in a semiconductor structure is shown according to some aspects of this disclosure.

[0069] Figure 11 A block diagram of an exemplary system having a 3D memory device according to some aspects of this disclosure is shown.

[0070] Figure 12A A schematic diagram of an exemplary memory card having a 3D memory device is shown according to some aspects of this disclosure.

[0071] Figure 12B A schematic diagram of an exemplary solid-state drive (SSD) having a 3D memory device is shown according to some aspects of this disclosure.

[0072] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0073] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other constructions and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified in relation to each other and in ways not explicitly depicted in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0074] Generally, terms can be understood at least partially from their usage in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partially on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, also depending at least partially on the context, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described.

[0075] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with an intermediate feature or layer between them, and that “above” or “on top of” means not only “above” or “on top of” but also includes “above” or “on top of” without an intermediate feature or layer between them (i.e., directly on).

[0076] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature and another (or more) elements or features as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0077] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0078] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnects and / or vertical contacts are formed) and one or more dielectric layers.

[0079] In some 3D memory devices (e.g., 3D NAND memory devices), a channel structure is formed in the core array region. Memory cells for storing data are vertically stacked via a stacking structure (e.g., a memory stack body) in the vertical channel structure. For purposes such as word line pickup / fan-out using word line contacts landing on different steps / levels of the stepped structure, 3D memory devices typically include stepped structures formed in the stepped regions (e.g., on one or more sides (edges) or at the center of the stacked memory structure). Through-substrate vias (TSVs) may also be formed at the edges of the stepped regions or outside the stepped regions to provide interconnects across the entire stacked structure.

[0080] Initially, the stacked structure may include staggered first dielectric layers (e.g., silicon oxide layers) and second dielectric layers (e.g., silicon nitride layers). During the formation of the channel structure, all second dielectric layers in the core array region and a portion of the second dielectric layers in the stepped region are replaced by conductive layers, leaving the remaining second dielectric layers in the stepped region. In some applications, it is necessary to remove the remaining second dielectric layers in the stepped region and then replace them with silicon oxide. The region where the TSV is located is also filled with silicon oxide. The word line contacts and TSV can then be formed by first etching the silicon oxide to form contact holes in the silicon oxide region and then filling the contact holes with a conductive material. However, with the removal of the remaining second dielectric layers in the stepped region, the manufacturing process can be complex and costly.

[0081] To address one or more of the aforementioned problems, this disclosure presents a solution that allows multiple contact structures to be formed in a connection region (a region located outside the core array region) without removing the remaining second dielectric layer in the connection region. The multiple contact structures formed therefrom may include contact structures extending only through a portion of the stacked structure, contact structures extending through the entire stacked structure and only penetrating a portion of the stacked structure disposed thereon through a semiconductor layer, contact structures extending through both the stacked structure and the semiconductor layer, or any combination thereof. Contact structures extending through both the stacked structure and the semiconductor layer can be used as interconnect structures between stacked dies. Since the contact structures disclosed herein can be formed by etching the first dielectric layer and the remaining second dielectric layer, the manufacturing process can be simplified and cost-effective.

[0082] Figure 1A A plan view of a semiconductor structure 100 having multiple contact structures according to some aspects of this disclosure is shown. In some embodiments, the semiconductor structure 100 may be part of a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings. Note that in Figure 1A The diagram includes an x-axis and a y-axis to represent two orthogonal (perpendicular) directions in the wafer plane. The x-direction is the word line direction of the semiconductor structure 100, and the y-direction is the bit line direction of the semiconductor structure 100.

[0083] like Figure 1A As shown, the semiconductor structure 100 may include one or more blocks 102 arranged in the y-direction (bit line direction) and separated by parallel slot structures 108 (e.g., gate line slots (GLS)). In some embodiments where the semiconductor structure 100 is a NAND flash memory device, each block 102 is the smallest erasable cell of the NAND flash memory device. Each block 102 may also include a plurality of fingers 104 separated in the y-direction by some slot structures in the slot structures 108 having "H" cutouts 109.

[0084] like Figure 1A As shown, the semiconductor structure 100 can be at least divided into a core array region 101 and a connection region 103. An array of channel structures 110 is formed in the core array region 101, and a plurality of contact structures 106, 116 are formed in the connection region 103. According to some embodiments, the core array region 101 and the connection region 103 are arranged in the x-direction (word line direction). It should be understood that, although Figure 1AThe diagram shows a core array region 101 and a connection region 103, but the semiconductor structure 100 may include multiple core array regions 101 and / or multiple connection regions 103, for example, a connection region 103 located between two core array regions 101 in the x-direction, or a core array region 101 located between two connection regions 103. It should also be understood that... Figure 1A Only the portion of the core array region 101 adjacent to the connection region 103 is shown.

[0085] As described in detail below, the connection region 103 may include a conductive portion 105 and a dielectric portion 107 arranged in the y-direction. Figure 1A As shown, according to some embodiments, contact structures 106, 116 are disposed in the dielectric portion 107, while a dummy channel structure 112 is disposed in the conductive portion 105 of the connection region 103 to provide mechanical support and / or load balancing. In some embodiments (e.g., as...) Figure 1A As shown), the dummy channel structure 112 is also provided in the dielectric portion 107 of the connection region 103, for example, located between contact structures 106 and 116 in the x-direction. In some embodiments, the dummy channel structure 112 is not provided in the dielectric portion 107 of the connection region 103, that is, it is only provided in the conductive portion 105 of the connection region 103. Figure 1A As shown, each finger 104 of the semiconductor structure 100 may include a row of contact structures 106, 116 disposed in the dielectric portion 107 of the connection region 103. It should be understood that the layout and arrangement of the contact structures 106, 116 and the shape of each contact structure 106, 116 may vary in different examples.

[0086] Figure 1B Another plan view of a semiconductor structure 100 having multiple contact structures according to some aspects of this disclosure is shown. Figure 1B It can include and Figure 1A Similar components to those in the text, and similar descriptions will not be repeated in this article. Figure 1B In the core array region 101, a first part 101A and a second part 101B separated from the first part 101A may be included. A connecting region 103 may connect the first part 101A and the second part 101B of the core array region 101. For example, the connecting region 103 may be located between the first part 101A and the second part 101B of the core array region 101.

[0087] Figure 2A A cross-sectional side view of a first exemplary embodiment of contact structures 106, 116 according to some aspects of this disclosure is shown. Figure 2B Some aspects of this disclosure are shown. Figure 2A A cross-sectional side view of the first contact structure 116. This is described in more detail below. Figure 2A and Figure 2B The cross-section can be along... Figure 1A or Figure 1B The AA direction in the dielectric portion 107 of the connection region 103.

[0088] like Figure 2A As shown, a stacked structure 203 can be formed on the semiconductor layer 201. In some embodiments, the semiconductor layer 201 can be a substrate, which may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, the substrate includes single-crystal silicon, which is part of the wafer on which the semiconductor structure 100 is fabricated, and the substrate is at its original thickness or has been thinned. In some embodiments, for example, the substrate includes polycrystalline silicon as a semiconductor layer replacing a portion of the wafer on which the semiconductor structure 100 is fabricated. It should be noted that the x and z axes are included. Figure 2A The spatial relationships of components in semiconductor structure 100 are further illustrated below. Semiconductor layer 201 of semiconductor structure 100 includes two lateral surfaces extending laterally in the xy-plane: a top surface located on the front side of the wafer on which a stacked structure 203 may be formed, and a bottom surface located on the back side of the wafer opposite the front side. The z-axis is perpendicular to both the x-axis and y-axis. As used herein, whether a component (e.g., layer or device) of semiconductor structure 100 is “on,” “above,” or “below” another component (e.g., layer or device) is determined by its position relative to semiconductor layer 201 of semiconductor structure 100 in the z-direction (a vertical direction perpendicular to the xy-plane). The same concepts used to describe spatial relationships apply throughout this disclosure.

[0089] The stack structure 203 may include alternating first layers and first dielectric layers 224. The first layers and first dielectric layers 224 may alternate in the vertical direction (z direction). In some embodiments, the stack structure 203 may include a plurality of stacked pairs vertically stacked in the z direction, and each stacked pair includes one of the first layers and one of the first dielectric layers 224.

[0090] The stacked structure 203 may include a first portion and a second portion adjacent to the first portion. The first portion may be located in the connection region 103. For example, refer to... Figure 3BThe first and second portions of the stacked structure 203 can be labeled as first element 362 and second element 364, respectively. The second portion 364 may include a portion of the core array region 101 and the connection region 103, and the first portion 362 may include the remaining portion of the connection region 103. In another example, the second portion may include conductive portions 105 of the core array region 101 and the connection region 103. The first portion may include dielectric portions 107 of the connection region 103. By way of example, Figure 2A Only the first part of the stacked structure 203 is shown.

[0091] In some embodiments, semiconductor structure 100 may be part of a NAND flash memory device, and stack structure 203 may be a memory structure through which stacked NAND memory strings are formed. As described below... Figure 3B and Figures 8B-8F As shown, the first layer of the stacked structure 203 can be made of different materials in different regions / parts of the semiconductor structure 100. For example, the first layer located in the first part of the stacked structure 203 may include a second dielectric layer 222. The first layer located in the second part of the stacked structure may include a conductive layer 302. Figure 2A A first portion of the stacked structure 203 is shown, which may include interleaved first dielectric layers 224 and second dielectric layers 222. (See diagram below.) Figure 3B and Figures 8B-8F As shown, the second part of the stacked structure 203 may include an interleaved first dielectric layer 224 and a conductive layer 302.

[0092] The following text is about Figures 8A-8F As detailed in the manufacturing process, by controlling the different degrees and extents of the gate replacement process in different regions / parts, a stacked structure 203 with different materials for the first layer can be formed in different regions / parts. For example, the stacked structure 203 may have undergone a complete gate replacement process in the core array region 101, whereby the conductive layer 302 replaces all the second dielectric layers 222, while in the connection region 103, a partial gate replacement process has been performed, whereby the conductive layer 302 replaces some of the second dielectric layers 222 in a part of the connection region 103, leaving the remaining second dielectric layers 222 in the remaining part of the connection region 103.

[0093] In some embodiments, each conductive layer in the second portion of the stacked structure 203 (within the core array region 101 and the conductive portion 105 of the connection region 103) serves as a gate line (in the form of a channel structure 110) of the NAND memory string in the core array region 101, and a word line in the conductive portion 105 of the connection region 103 that extends laterally from the gate line and terminates for word line pickup / fan-out via a word line pickup structure (e.g., contact structure 106). According to some embodiments, each word line (i.e., conductive layer) located at different depths / levels in the second portion of the stacked structure 203 extends laterally in the core array region 101 and the conductive portion 105 of the connection region 103, but is discontinuous in the dielectric portion 107 of the connection region 103 (e.g., replaced by a second dielectric layer 222).

[0094] The conductive layer 302 may include a conductive material, including but not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon, doped silicon, silicide, or any combination thereof. The first dielectric layer 224 or the second dielectric layer 222 may include a dielectric material, including but not limited to: silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The first dielectric layer 224 and the second dielectric layer 222 may have different dielectric materials, for example, silicon oxide and silicon nitride, respectively. In some embodiments, the conductive layer 302 includes a metal (e.g., tungsten), the first dielectric layer 224 includes silicon oxide, and the second dielectric layer 222 includes silicon nitride.

[0095] By way of examples Figure 2A A first contact structure 116, a second contact structure 106A, and a third contact structure 106B are shown. The second contact structure 106A and the third contact structure 106B (referred to individually or collectively as 106) can be examples of word line pickup structures. According to some embodiments, the second contact structure 106A and the third contact structure 106B extend vertically into the stacked structure 203 (the dielectric portion 107 of the connection region 103) at different depths in the z-direction. The top surfaces of the second contact structure 106A and the third contact structure 106B may be flush with each other, while the bottom surfaces of the second contact structure 106A and the third contact structure 106B may extend to different horizontal planes, for example, different second dielectric layers 222 of the stacked structure 203.

[0096] In some embodiments, each of the second contact structure 106A and the third contact structure 106B includes a vertical direct contact structure (e.g., conductor layer 202) and a lateral contact structure 206 connected to the vertical direct contact structure. The vertical direct contact structure extends in the same direction as the first contact structure 116. The lateral contact structure 206 is connected to a conductive layer in the conductive layer 302. For example, each of the second contact structure 106A and the third contact structure 106B includes a conductor layer 202, a spacer 204 surrounding the conductor layer 202, and a lateral contact structure 206 located below and in contact with the conductor layer 202. The conductor layer 202 and the lateral contact structure 206 may include a conductive material, including but not limited to: W, Co, Cu, Al, TiN, polycrystalline silicon, doped silicon, silicide, or any combination thereof. The spacer 204 may include a dielectric material, including but not limited to: silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductor layer 202 and the lateral contact structure 206 comprise TiN / W, and the spacer 204 comprises silicon oxide.

[0097] In some embodiments, each of the second contact structure 106A and the third contact structure 106B may further include a filler body 208 surrounded by the conductor layer 202. The filler body 208 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Each of the second contact structure 106A and the third contact structure 106B may further include a contact pad 210 located on top of the filler body 208 and the conductor layer 202 and in contact with the filler body 208 and the conductor layer 202. The contact pad 210 may be electrically connected to the conductor layer 202. The contact pad 210 may include a conductive material, including but not limited to W, Co, Cu, Al, TiN, polysilicon, doped silicon, silicide, or any combination thereof.

[0098] The first contact structure 116 may be a contact structure that extends through a portion or the entire semiconductor layer 201 of the stacked structure 203 and the semiconductor layer 201. For example, the first contact structure 116 may extend through a portion of the stacked structure 203 and the semiconductor layer 201. In another example, such as Figure 2A As shown, the first contact structure 116 can penetrate both the stacked structure 203 and the semiconductor layer 201.

[0099] refer to Figure 2BThe first contact structure 116 may include a first segment 250 and a second segment 252 connected to the first segment 250 in the z-direction. The first segment 250 may be located on the side of the second segment 252 away from the semiconductor layer 201. The first segment 250 may include a first end 256 contacting the second segment 252, and the second segment 252 may include a second end 258 contacting the first segment 250. In the x-direction perpendicular to the z-direction, the size of the first end 256 may be larger than the size of the second end 258. The first segment 250 may also include a third end 254 away from the first end 256, and the second segment 252 may also include a fourth end 260 away from the second end 258. In the x-direction, the size of the third end 254 may be larger than the size of the first end 256, and in the x-direction, the size of the second end 258 may be larger than the size of the fourth end 260.

[0100] Return to reference Figure 2A The first contact structure 116 may include a conductor layer 212 and spacers 214 surrounding the conductor layer 212. The first contact structure 116 may also include a filler body 218 surrounded by the conductor layer 212, and contact pads 220 located on top of and in contact with the filler body 218 and the conductor layer 212. Contact pads 220 may be electrically connected to the conductor layer 212. In some embodiments, spacers 204 and 214 may comprise the same or different materials, without limitation herein. Conductor layers 202 and 212 may comprise the same or different materials, without limitation herein. Fillers 208 and 218 may comprise the same or different materials, without limitation herein.

[0101] In some embodiments, the vertical direct contact structure (e.g., conductor layer 202) of the second contact structure 106A may extend to the first stack pair. The first stack pair may be a pair comprising (a) one of the first dielectric layers 224 and (b) one of the first layers that contacts one of the first dielectric layers 224. For example, as Figure 2A As shown, the first stack pair may include a first dielectric layer 224A and a second dielectric layer 222A adjacent to the first dielectric layer 224A. The lateral contact structure 206 of the second contact structure 106A may be located within the second dielectric layer 222A of the first stack pair. The first contact structure 116 may include a first junction 216 located within the first stack pair. Figure 2B As shown, the first segment 250 and the second segment 252 of the first contact structure 116 can be connected to each other at the first joint 216.

[0102] In some implementations, such as Figure 2AAs shown, the vertical direct contact structure (e.g., conductor layer 202) of the third contact structure 106B can extend into the second stack pair. The second stack pair may include a first dielectric layer 224B and a second dielectric layer 222B adjacent to the first dielectric layer 224B. The lateral contact structure 206 of the third contact structure 106B may be located in the second dielectric layer 222B of the second stack pair.

[0103] Figure 2C A cross-sectional side view of a second exemplary embodiment of the contact structures 106, 116 according to some aspects of this disclosure is shown. The cross-section can be along... Figure 1A or Figure 1B The AA direction in the dielectric portion 107 of the connection region 103. Figure 2C It can include and Figures 2A-2B Similar components to those in [the document], and similar descriptions will not be repeated in this document. Figures 2A-2B compared to, Figure 2C The first contact structure 116 may include three segments, for example, a first segment, a second segment, and a third segment from top to bottom. The first segment and the second segment are connected to each other at a first joint 216. The second segment and the third segment are connected to each other at a second joint 217. Figure 2A In contrast, the third contact structure 106B may include two segments, for example, a first segment located at the top of the third contact structure 106B and a second segment located at the bottom of the third contact structure. The first segment and the second segment of the third contact structure 106B may be connected to each other at the third joint 219.

[0104] The vertical direct contact structure (e.g., conductor layer 202) of the second contact structure 106A may extend into the first stack pair (first dielectric layer 224A and second dielectric layer 222A). The lateral contact structure 206 of the second contact structure 106A may be located in the second dielectric layer 222A of the first stack pair. The first junction 216 of the first contact structure 116 and the third junction 219 of the third contact structure 106B may be located in the first stack pair.

[0105] The vertical direct contact structure (e.g., conductor layer 202) of the third contact structure 106B can extend into the second stack pair (first dielectric layer 224B and second dielectric layer 222B). The lateral contact structure 206 of the third contact structure 106B can be located in the second dielectric layer 222B of the second stack pair. The second junction 217 of the first contact structure 116 can be located in the second stack pair.

[0106] Figure 3AA cross-sectional side view of a semiconductor device 300 according to some examples is shown. The semiconductor device 300 may include a semiconductor structure 329 and peripheral circuitry 330 stacked on and connected to the semiconductor structure 329. The peripheral circuitry 330 may include a semiconductor layer 331 and a device layer 332 disposed on and in contact with the semiconductor layer 331. In some embodiments, the device layer 332 includes one or more circuits, such as driver circuitry, page buffer circuitry, and logic circuitry. In some embodiments, the device layer 332 includes a plurality of transistors 333 in contact with the semiconductor layer 331. The transistors 333 may include any transistor, such as a metal-oxide-semiconductor (MOS) transistor, a complementary metal-oxide-semiconductor (CMOS) transistor, or other types of transistors.

[0107] In some embodiments, the peripheral circuit 330 may further include a connection layer 334 and a bonding layer 335. The connection layer 334 may be connected to the device layer 332 to transmit electrical signals to and from the device layer 332. Figure 3A As shown, the connection layer 334 may be vertically located between the bonding layer 335 and the device layer 332. The connection layer 334 may include multiple interconnects (also referred to herein as “contacts”), which include lateral lines and vias. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as mid-stage (MEOL) interconnects and back-end (BEOL) interconnects. The interconnects in the connection layer 334 may be coupled to transistors 333 located in the device layer 332. The connection layer 334 may also include lateral lines and vias that can be formed in one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”). That is, the connection layer 334 may include lateral lines and vias located in multiple ILD layers. In some embodiments, devices located in the device layer 332 are coupled to each other via interconnects located in the connection layer 334. For example, different transistors 333 may be coupled to each other via the connection layer 334. The interconnects located in the interconnect layer 334 may include conductive materials, including but not limited to: W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer located in the interconnect layer 334 may include dielectric materials, including but not limited to: silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof. In some embodiments, the interconnects located in the interconnect layer 334 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, e.g., voids) among conductive metallic materials.

[0108] The semiconductor structure 329 can be divided into at least a core array region 311 and a connection region 315. The connection region 315 can also be divided into a stepped region 316 and a region 313 located outside the stepped region 316. In the core array region 311, the semiconductor structure 329 can include a semiconductor layer 301 and a stacked structure formed on the semiconductor layer 301. The stacked structure can include an interleaved conductive layer 302 and a first dielectric layer 304. The semiconductor structure 329 can also include a channel structure 310 extending through the stacked structure. Memory cells for storing data are vertically stacked through the stacked structure (e.g., a memory stack) in the vertical channel structure.

[0109] like Figure 3A As shown, the semiconductor structure 329 may further include an interconnect layer 308 formed on and electrically connected to the channel structure 310 to transmit electrical signals to and from memory cells formed in the channel structure 310. In some embodiments, the interconnect layer 308 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 308 may also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 308 may also include lateral lines and vias that can be formed in one or more ILD layers. The interconnects in the interconnect layer 308 may include conductive materials, including but not limited to: W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 308 may include dielectric materials, including but not limited to: silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0110] In the stepped region 316, the semiconductor structure 329 may include a stepped structure. The semiconductor structure 329 may also include word line contacts 312 that extend through a dielectric material (e.g., oxynitride) filling above the stepped structure and land on different steps / levels of the stepped structure. In a region 313 located at the edge of the stepped region 316 or outside the stepped region 316, the semiconductor structure 329 may also include a TSV 314 extending through both (a) the dielectric material (e.g., oxynitride) and (b) the semiconductor layer 301 filling the region 313.

[0111] like Figure 3AAs shown, semiconductor structure 329 may include a bonding layer 325 located above and in contact with interconnect layer 308. In some embodiments, semiconductor structure 329 and peripheral circuitry 330 may be coupled to each other via hybrid bonding. Hybrid bonding (also known as “metal / dielectric hybrid bonding”) is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. Face-to-face hybrid bonding can enable millions of parallel short interconnects between bonded semiconductor structures, thereby increasing the throughput and input / output (I / O) speed of the semiconductor package structure. Each bonding layer of bonding layers 325, 335 may include multiple bonding contacts and a dielectric that electrically isolates the bonding contacts. The bonding contacts may include a conductive material, such as Cu. The remaining regions of each bonding layer of bonding layers 325, 335 may be formed of a dielectric material (e.g., silicon oxide). The bonding contacts and surrounding dielectric in each of the bonding layers 325 and 335 can be used for hybrid bonding.

[0112] This document briefly describes the fabrication process of semiconductor structure 329. Initially, a stacked structure comprising an interlaced first dielectric layer 304 (e.g., a silicon oxide layer) and a second dielectric layer (e.g., a silicon nitride layer) can be formed on semiconductor layer 301. Channel structure 310 can be formed to extend through the stacked structure and into semiconductor layer 301. Then, all the second dielectric layers in core array region 311 and a portion of the second dielectric layers in the stepped structure are replaced by conductive layer 302, leaving the remaining second dielectric layers in stepped region 316. The remaining second dielectric layers in stepped region 316 can be removed and then replaced with silicon oxide. Region 313 is also filled with silicon oxide. As a result, silicon oxide region 328 can be formed. Word line contacts 312 in stepped region 316 and TSVs 314 in region 313 can then be formed by first forming contact holes in silicon oxide region 328 and then filling the contact holes with conductive material. This fabrication process requires the removal of the remaining second dielectric layers in stepped region 316, which can be complex.

[0113] Figure 3B A cross-sectional side view of a semiconductor device 350 having multiple contact structures 106, 116 according to some aspects of this disclosure is shown. As described in more detail below, with... Figure 3A Unlike other methods, multiple contact structures 106, 116 can be formed in the connection region 103 without removing the remaining second dielectric layer 222 in the connection region 103. Therefore, the manufacturing process of the semiconductor device 350 can be simplified. Figure 3B It can include and Figure 1A-Figure 1B , Figures 2A-2C and Figure 3A The components are similar to those in the text, and similar descriptions will not be repeated in this article.

[0114] Semiconductor device 350 may include semiconductor structure 360 ​​and peripheral circuitry 330 stacked on and connected to semiconductor structure 360. Semiconductor structure 360 ​​may be divided into at least a core array region 101 and a connection region 103. In some embodiments, semiconductor structure 360 ​​may include semiconductor layer 201 and a stacked structure 203 located on semiconductor layer 201. Stacked structure 203 may include alternating first layers and first dielectric layers 224. Stacked structure 203 may include a first portion 362 and a second portion 364 adjacent to the first portion 362. In some examples, the second portion 364 of stacked structure 203 may include a first portion located in core array region 101A and a second portion located in core array region 101B spaced apart from the first portion (e.g., ...). Figure 1B As shown in the figure, the first part 362 of the stacked structure 203 connects the first part and the second part.

[0115] The first layer of the first portion 362 may include a second dielectric layer 222, while the first layer of the second portion 364 may include a conductive layer 302. For example, the first portion 362 of the stacked structure 203 may include staggered second dielectric layers 222 and first dielectric layers 224. The second portion 364 of the stacked structure 203 may include staggered conductive layers 302 and first dielectric layers 224.

[0116] In some embodiments, the semiconductor structure 360 ​​may further include (a) a first contact structure 116 extending through the first portion 362 and the semiconductor layer 201, and (b) a second contact structure 106 extending through a portion of the first portion 362 and connected to a conductive layer in the conductive layer 302. For example, the vertical direct contact structure of the second contact structure 106 (e.g., conductor layer 202) may extend to a first stack pair (e.g., a stack pair including a first dielectric layer 224A and a second dielectric layer 222A). The lateral contact structure 206 of the second contact structure 106 may be located in the second dielectric layer 222A and connected to the conductive layer 302A located in the same layer (e.g., the second dielectric layer 222A and the conductive layer 302A are different portions of the same first layer).

[0117] The semiconductor structure 360 ​​may also include a channel structure 110 that extends through the second portion 364 into the semiconductor layer 201. In the vertical direction (e.g., the z-direction), the length of the first contact structure 116 may be greater than the length of the channel structure 110.

[0118] like Figure 3BAs shown, the semiconductor structure 360 ​​may further include a connection layer 308, which is formed on and electrically connected to the channel structure 110 to transmit electrical signals to and from memory cells formed in the channel structure 110. The connection layer 308 may also be connected to the first contact structure 116 and the second contact structure 106. Figure 3B As shown, the semiconductor structure 360 ​​may include a bonding layer 325 located above and in contact with the connection layer 308. In some embodiments, the semiconductor structure 360 ​​and the peripheral circuitry 330 may be coupled to each other via hybrid bonding. For example, the connection layer 334 of the peripheral circuitry 330 may be bonded to the connection layer 308 of the semiconductor structure 360 ​​using bonding layers 335 and 325. The bonding contacts and surrounding dielectric in each of the bonding layers 325 and 335 may be used for hybrid bonding.

[0119] In some embodiments, the peripheral circuit 330 may be connected to the first contact structure 116. In some embodiments, the peripheral circuit 330 may be disposed under the stacked structure 203, and the first contact structure 116 may extend through the semiconductor layer 301 to connect to the peripheral circuit 330.

[0120] Consistent with some aspects of this disclosure, the semiconductor structure 360 ​​may include a stacked structure 203 with a uniform height (e.g., without steps) and a second contact structure 106 for word line pickup / fan-out located in the dielectric portion 107 of the connection region 103, instead of having a stepped structure and word line contacts landing on different levels / steps of the stepped structure. Figure 3B As shown, the lateral contact structure 206 of each second contact structure 106 in the dielectric portion 107 can extend laterally in a plane defined by the x and y directions to contact the corresponding conductive layer 302 (word line) in the conductive portion 105 located at the same horizontal plane of the stacked structure 203. According to some embodiments, since the lateral contact structure 206 contacts the conductor layer 202 of the second contact structure 106, each second contact structure 106 is electrically connected to the corresponding conductive layer 302 (word line) across the conductive portion 105 and the core array region 101 in the connection region 103. In other words, the second contact structure 106 can extend vertically through the stacked structure 203 at different depths to electrically connect to word lines located at different horizontal planes, thereby achieving word line pickup / fan-out.

[0121] Consistent with some aspects of this disclosure, the first contact structure 116 and the second contact structure 106 may be formed in the same region or in different regions, and this is not limited herein. For example, the first contact structure 116 may be formed near the sealing ring, while the second contact structure 106 may be formed in a region close to the core array region 101. The semiconductor device disclosed herein may include: (a) a stacked structure including alternating first and second dielectric layers; (b) a first contact structure 116 extending through the stacked structure and including a first conductor layer and a first spacer surrounding the sidewalls of the first conductor layer; and (c) a second contact structure extending through a portion of the stacked structure and including a second conductor layer and a second spacer surrounding the sidewalls of the second conductor layer. The first and second spacers may include a first material (e.g., a dielectric material), and the first and second conductor layers may include a second material (e.g., a conductive material) different from the first material.

[0122] Figure 4A A cross-sectional side view of a 3D memory device 400 according to some examples is shown. The memory device 400 may include a first semiconductor device 300A and a second semiconductor device 300B. The first semiconductor device 300A and the second semiconductor device 300B may have... Figure 3A The structure of the semiconductor device 300 is similar to that described herein, and similar descriptions will not be repeated here. The first semiconductor device 300A and the second semiconductor device 300B can be bonded together to form the memory device 400.

[0123] For example, the first semiconductor device 300A may include a first semiconductor structure 329A and a first peripheral circuit 330A. The first semiconductor structure 329A may include word line contacts 312A and TSV 314A. The second semiconductor device 300B may include a second semiconductor structure 329B and a second peripheral circuit 330B. The second semiconductor structure 329B may include word line contacts 312B and TSV 314B. It is anticipated that the first semiconductor structure 329A and the second semiconductor structure 329B may have the same characteristics as... Figure 3A The structure is similar to that of semiconductor structure 329. The first peripheral circuit 330A and the second peripheral circuit 330B can have the same... Figure 3A The structure is similar to that of the peripheral circuit 330. The word line contacts 312A and 312B can have the same... Figure 3A The structure is similar to that of the word line contact 312 in the TSV 314A and 314B. Figure 3A The structure is similar to that of TSV 314. Similar descriptions will not be repeated in this article.

[0124] like Figure 4A As shown, the memory device 400 may further include a through-die contact structure 402 extending through both the first semiconductor device 300A and the second semiconductor device 300B. In addition to the TSVs 314A, 314B and word line contacts 312A, 312B, the additional formation of the through-die contact structure 402 in the memory device 400 may require additional manufacturing operations, such as forming vias extending through both the first semiconductor device 300A and the second semiconductor device 300B, forming spacers on the sidewalls of the vias, and then filling the vias with a conductive material to form a filler body. Forming the through-die contact structure 402 may complicate the manufacturing process.

[0125] Figure 4B A cross-sectional side view of a 3D memory device 450 having multiple contact structures 106, 116 according to some aspects of this disclosure is shown. Figure 4A Unlike other devices, memory device 450 can utilize contact structure 116 to form a through-die contact structure, and therefore does not require forming a contact structure with... Figure 4A An additional through-hole contact structure 402, similar to the through-hole contact structure in the original, is used. Therefore, the manufacturing process can be simplified.

[0126] Memory device 450 may include a first semiconductor device 350A and a second semiconductor device 350B. The first semiconductor device 350A and the second semiconductor device 350B may have the same characteristics as... Figure 3B The semiconductor device 350 has a similar structure, and similar descriptions will not be repeated herein. For example, the first semiconductor device 350A may include a first semiconductor structure 360A and a first peripheral circuit 330A. The first semiconductor structure 360A may include a first stacked structure 203A and a channel structure 110A extending through the first stacked structure 203A. The first semiconductor structure 360A may also include a first contact structure 116A, which may include a spacer 214A, a conductor layer 212A, and a filler body 218A. The second semiconductor device 350B may include a second semiconductor structure 360B and a second peripheral circuit 330B. The second semiconductor structure 360B may include a second stacked structure 203B and a channel structure 110B extending through the second stacked structure 203B. The second semiconductor structure 360B may also include a second contact structure 116B, which may include a spacer 214B, a conductor layer 212B, and a filler body 218B. It is expected that the first semiconductor structure 360A and the second semiconductor structure 360B can have the same characteristics as... Figure 3B The semiconductor structure 360 ​​in the image has a similar structure. The stacked structures 203A and 203B can have similar characteristics to... Figures 2A-2B and Figure 3BThe stacked structure 203 in the middle has a similar structure. The first contact structure 116A and the second contact structure 116B can have the same structure as the stacked structure 203 in the middle. Figures 2A-2B and Figure 3B The structure of the first contact structure 116 is similar to that in this paper. Similar descriptions will not be repeated here.

[0127] The first semiconductor device 350A and the second semiconductor device 350B can be bonded together to form a memory device 450. For example, a bonding layer 454 can be formed between the first semiconductor device 350A and the second semiconductor device 350B to bond the two devices together. Any suitable bonding technique can be applied to the bonding layer 454, such as hybrid bonding, anodic bonding, fused bonding, transfer bonding, adhesive bonding, eutectic bonding, etc. Interconnect structures 458 can be formed in the bonding layer 454, such that the interconnect structure 452A of the first peripheral circuit 330A can be connected to the second contact structure 116B of the semiconductor structure 360B through the interconnect structure 458.

[0128] Consistent with some aspects of this disclosure, the memory device 450 may include: (a) a first semiconductor structure 360A, the first semiconductor structure 360A including a first stacked structure and a first contact structure 116A extending through the first stacked structure 203A; (b) a second semiconductor structure 360B, the second semiconductor structure 360B including a second stacked structure 203B and a second contact structure 116B extending through the second stacked structure 203B; and (c) a first peripheral circuit 330A, the first peripheral circuit 330A being connected to the first contact structure 116A and the second contact structure 116B.

[0129] In some embodiments, the first stack structure 203A may include alternating first and second dielectric layers. The second stack structure 203B may include alternating third and fourth dielectric layers. The third and fourth dielectric layers may each comprise the same material as the first and second dielectric layers.

[0130] In some embodiments, the first peripheral circuit 330A may be bonded to the first semiconductor structure 360A, and the first peripheral circuit 330A may include a first connection structure 455A located between the first semiconductor structure 360A and the second semiconductor structure 360B. The first connection structure 455A may be filled with a filler body 456A.

[0131] In some embodiments, the memory device 450 may further include a second peripheral circuit 330B bonded to the second semiconductor structure 360B. The second semiconductor structure 360B may be located between the first peripheral circuit 330A and the second peripheral circuit 330B. The second peripheral circuit 330B may include a second connection structure 455B connected to the second contact structure 116B. The second connection structure 455B may be filled with a filler body 456B.

[0132] In some embodiments, the first peripheral circuit 330A may further include a semiconductor layer 331A and an interconnect structure 452A extending through the semiconductor layer 331A. The interconnect structure 452A may include a conductive filler 454A and spacers 453A surrounding the conductive filler 454A. Similarly, the second peripheral circuit 330B may further include a semiconductor layer 331B and an interconnect structure 452B extending through the semiconductor layer 331B. The interconnect structure 452B may include a conductive filler 454B and spacers 453B surrounding the conductive filler 454B.

[0133] In some embodiments, the first contact structure 116A may include an insulating filler (e.g., filler body 218A) and a conductive layer 212A surrounding the insulating filler, while the interconnect structure 452A may include a conductive filler 454A and spacers 453A surrounding the conductive filler 454A. The conductive layer 212A of the first contact structure 116A may be connected to the conductive filler 454A of the interconnect structure 452A. Similarly, the second contact structure 116B may include an insulating filler (e.g., filler body 218B) and a conductive layer 212B surrounding the insulating filler, while the interconnect structure 452B may include a conductive filler 454B and spacers 453B surrounding the conductive filler 454B. The conductive layer 212B of the second contact structure 116B may be connected to the conductive filler 454B of the interconnect structure 452B.

[0134] Consistent with some aspects of this disclosure, the memory device disclosed herein may include: (a) a first contact structure (e.g., 116A) including an insulating filler and a conductive layer surrounding the insulating filler and extending in a first direction (e.g., the z-direction); and (b) a second contact structure (e.g., 116B) including a conductive filler and spacers surrounding the sidewalls of the conductive filler and extending in the first direction. The conductive layer is connected to the conductive filler.

[0135] Figure 4C A cross-sectional side view of another 3D memory device 480 having multiple contact structures according to some aspects of this disclosure is shown. The memory device 480 may have... Figure 4B The components of the memory device 450 are similar to those in the document, and similar descriptions will not be repeated here. Figure 4C The first contact structure 116 in the middle can have the same as Figure 4B The structures within are different. Specifically, in Figure 4C In this embodiment, each first contact structure 116 may include a conductive filler body and spacers surrounding the conductive filler body. The conductive filler body may include any conductive material disclosed herein. For example, such as Figure 4C As shown, the first contact structure 116A of the first semiconductor device 350A may include a conductive filler body 484 and a spacer body 214 surrounding the conductive filler body 484.

[0136] Figure 5 A cross-sectional side view of another semiconductor device 500 having multiple contact structures according to some aspects of the present disclosure is shown. The semiconductor device 500 may include a semiconductor structure 550 and peripheral circuitry 330. The semiconductor structure 550 may include a semiconductor layer 501, a stacked structure situated above the semiconductor layer 501 and including alternating conductive layers 502 and dielectric layers 504, a channel structure 110 extending through the stacked structure, a first contact structure 516 extending through the stacked structure, and a second contact structure 506 extending through a portion of the stacked structure. The first contact structure 516 may include a first conductor layer 522 and a first spacer 524 surrounding the sidewalls of the first conductor layer 522. The second contact structure 506 may include a second conductor layer 512 and a second spacer 514 surrounding the sidewalls of the second conductor layer 512. The second conductor layer 512 is connected to one of the conductive layers 502 (e.g., conductive layer 502A), and the first conductor layer 522 and the conductive layer 302 are separated by the first spacer 524.

[0137] The first contact structure 516 is expected to have the same characteristics as... Figures 2A-2C , Figure 3B and Figure 4B The first contact structure 116 has a similar structure to the second contact structure 506, and the second contact structure 506 may have the same structure as the first contact structure 116. Figures 2A-2C , Figure 3B and Figure 4B The second contact structure 106 in the middle has a similar structure. However, Figure 5 The first contact structure 516 and the second contact structure 506 extend through the alternating conductive layer 502 and dielectric layer 504, while Figures 2A-2C , Figure 3B and Figure 4B The first contact structure 116 and the second contact structure 106 extend through the alternating first dielectric layer 224 and second dielectric layer 222. Figure 5The second contact structure 506 has no lateral contact structure. The second contact structure 506 may extend to a stack pair including a conductive layer 502A and a dielectric layer 504A, and the first contact structure 516 may have a joint located in the stack pair.

[0138] Figure 6 A cross-sectional side view of another semiconductor device 600 having multiple contact structures according to some aspects of the present disclosure is shown. The semiconductor device 600 may include a semiconductor structure 650 and peripheral circuitry 330. The semiconductor structure 650 may include a semiconductor layer 601, a stacked structure situated above the semiconductor layer 601 and including alternating conductive and dielectric layers, a channel structure 110 extending through the stacked structure, and contact structures 616A and 616B extending through the stacked structure and the semiconductor layer 601. Contact structures 616A and 616B are located in connection regions 103A and 103B, respectively. In some embodiments, the peripheral circuitry 330 may be disposed below the stacked structure, and the contact structures 616A and 616B may extend through the semiconductor layer 601 to connect to the peripheral circuitry 330.

[0139] The expected contact structures 616A and 616B can have the same characteristics as... Figures 2A-2C , Figure 3B and Figure 4B The structure of the first contact structure 116 is similar to that of the first contact structure 116. However, contact structures 616A and 616B extend through alternating conductive and dielectric layers, while Figures 2A-2C , Figure 3B and Figure 4B The first contact structure 116 extends through alternating first dielectric layer 224 and second dielectric layer 222.

[0140] Figure 7 This is a flowchart of a method 700 for forming a semiconductor device having multiple contact structures according to some aspects of this disclosure. Figures 8A-8F A manufacturing process for forming a semiconductor device having multiple contact structures is shown according to some aspects of this disclosure. Figure 7 and Figures 8A-8F Examples of semiconductor devices depicted include Figure 3B The semiconductor device 350 depicted in the image will be described together. Figure 7 and Figures 8A-8F It should be understood that the operations shown in method 700 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of these operations may be performed simultaneously, or in conjunction with... Figure 7 The different orders shown are executed sequentially.

[0141] refer to Figure 7Method 700 begins at operation 702, in which a stacked structure comprising an interleaved first dielectric layer and a second dielectric layer is formed on a semiconductor layer. The first dielectric layer may comprise silicon oxide, and the second dielectric layer may comprise silicon nitride. The stacked structure may be formed by one or more thin-film deposition processes, including but not limited to ALD, CVD, PVD, or any combination thereof.

[0142] Method 700 proceeds to operation 704, such as... Figure 7 As shown, in operation 704, a channel structure extending through the first and second dielectric layers is formed in the core array region of the stacked structure. For example, refer to... Figure 8A A stacked structure 203 comprising an interleaved first dielectric layer 224 and a second dielectric layer 222 can be formed on the semiconductor layer 201. The channel structure 110 can be formed to extend through the stacked structure 203 into the semiconductor layer 201.

[0143] In some embodiments, to form a channel structure, a channel via extending vertically through the stacked structure is formed, and a memory layer and a channel layer are sequentially formed on the sidewalls of the channel via. In some embodiments, to form a channel structure, a channel via extending vertically through the stacked structure is formed, and a high-k gate dielectric layer, a memory layer, and a channel layer are sequentially formed on the sidewalls of the channel via. In some embodiments, in the same process as forming the channel structure, a dummy channel structure extending through the first and second dielectric layers is formed in a second region of the stacked structure (e.g., Figure 1A The virtual channel structure 112 in the stacked structure. That is to say, a channel structure and a virtual channel structure can be formed simultaneously through the first dielectric layer and the second dielectric layer in the first part and the second part of the stacked structure, respectively.

[0144] In some embodiments, multiple vias are opened to form the channel structure, such that each via becomes a location for growing a single channel structure in subsequent processes. In some embodiments, the fabrication process for the vias used to form the channel structure includes wet etching and / or dry etching, such as deep ion reactive etching (DRIE). Subsequently, a memory layer (including a barrier layer, a storage layer, and a tunneling layer) and a channel layer are formed sequentially along the sidewalls and bottom surface of the vias. In some embodiments, a memory layer is first deposited along the sidewalls and bottom surface of the channel vias, and then a semiconductor channel is deposited over the memory layer. The barrier layer, storage layer, and tunneling layer can then be deposited sequentially using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to form the memory layer. The channel layer can then be formed by depositing a semiconductor material (e.g., polysilicon) over the tunneling layer of the memory layer using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (“SONO” structure) are subsequently deposited to form a memory layer and a channel layer with a channel structure.

[0145] In some embodiments, a high-k gate dielectric layer is formed prior to the formation of the memory layer. That is, the high-k gate dielectric layer, the memory layer (including a barrier layer, a storage layer, and a tunneling layer), and the channel layer can be formed sequentially along the sidewalls and bottom surface of the channel via. In some embodiments, a high-k gate dielectric layer is first deposited along the sidewalls and bottom surface of the channel via, then the memory layer is deposited over the high-k gate dielectric layer, and then a semiconductor channel is deposited over the memory layer. The high-k gate dielectric layer can be formed by depositing a high-k dielectric material (e.g., alumina) using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). Subsequently, the barrier layer, the storage layer, and the tunneling layer can be sequentially deposited over the high-k gate dielectric layer using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to form the memory layer. The channel layer can then be formed by depositing a semiconductor material (e.g., polysilicon) over the tunneling layer of the memory layer using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In some embodiments, an aluminum oxide layer, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (“SONO” structure) are subsequently deposited to form the high-k gate dielectric layer, memory layer, and channel layer of the channel structure.

[0146] In some implementations, in the same process of forming the channel structure, in the stacked structure (e.g., Figure 2A , Figure 2C and Figure 3B The connection region of the stacked structure 203 in the middle (e.g., Figure 1A-Figure 1B and Figure 3B A virtual channel structure can be formed in the connecting region 103 (e.g., Figure 1A-Figure 1B (Dummy channel structure 112 in the example). To form each dummy channel structure, a dummy channel via can be formed simultaneously with a channel via in the interconnect region by the same wet etching and / or dry etching (e.g., DRIE), the dummy channel via being another opening extending vertically through the stacked structure. The dummy channel structure can then be formed simultaneously with the channel structure by depositing a memory layer (including a barrier layer, a storage layer, and a tunneling layer) and a channel layer, or a high-k gate dielectric layer, a memory layer (including a barrier layer, a storage layer, and a tunneling layer), and a channel layer using the same thin-film deposition process (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). It should be understood that in some examples, the dummy channel structure can be formed in a separate process from the channel structure.

[0147] Method 700 proceeds to operation 706, such as... Figure 7 As shown, in operation 706, for example, through a gate replacement process, a conductive layer is used to replace all the second dielectric layers in the second portion of the stacked structure and a portion of the second dielectric layers in the first portion. The conductive layer may include a metal. For example, refer to... Figure 8B The stacked structure 203 may include a first portion 362 and a second portion 364. For example, by a gate replacement process, a conductive layer 302 is used to replace all the second dielectric layers 222 located in the second portion 364 (including a portion of the core array region 101 and the connection region 103).

[0148] At the start of the gate replacement process, a slot is formed extending through the first dielectric layer 224 and the second dielectric layer 222 and across the first portion 362 and the second portion 364 of the stacked structure 203. In some embodiments, the slot also extends vertically through the local contact layer. The slot may also extend laterally across the core array region 101 and the interconnect region 103 in the x-direction (word line direction). In some embodiments, the fabrication process for forming the slot includes wet etching and / or dry etching, such as DRIE, of the first and second dielectric layers. The etching process through the stacked structure may not stop at the top surface of the silicon substrate and may continue etching portions of the silicon substrate to ensure that the slot extends vertically through all the first and second dielectric layers of the stacked structure 203.

[0149] Subsequently, the portion of the slot located in the core array region is covered by a sacrificial layer. In some embodiments, a sacrificial layer (e.g., a polysilicon layer or a carbon layer) different from the first and second dielectric layers is deposited into the slot using one or more thin-film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) to at least partially fill the slot (covering the exposed first and second dielectric layers in the slot). The sacrificial layer can then be patterned using photolithography and wet etching and / or dry etching to remove the portion of the sacrificial layer located in the connection region, leaving only the portion of the sacrificial layer located in the core array region, thereby covering only the portion of the slot located in the core array region.

[0150] Subsequently, a portion of the second dielectric layer 222 in the connection region 103 of the stacked structure 203 is removed through gaps in the connection region 103. Removal can be performed by wet etching to form lateral recesses, thereby leaving the remaining second dielectric layer 222 in the dielectric portion of the connection region 103 intact. In some embodiments, a portion of the second dielectric layer is wet-etched by applying a wet etchant through the portion of the gaps in the connection region not covered by the sacrificial layer, thereby creating lateral recesses staggered between the first dielectric layers 224. The wet etchant may include phosphoric acid for etching the second dielectric layer comprising silicon nitride. In some embodiments, one or both of the etching rate and etching time are controlled to remove only conductive portions (e.g., Figure 1A-Figure 1B The conductive portion 105) of the second dielectric layer 222 in the dielectric portion (e.g., Figure 1A-Figure 1B The remaining second dielectric layer 222 in the dielectric portion 107 of the junction region 103 remains intact. By controlling the etching time, the wet etchant does not travel all the way to completely remove the second dielectric layer in the junction region 103, thereby defining two portions in the junction region: a dielectric portion in which the second dielectric layer is removed, and a dielectric portion in which the second dielectric layer is retained. Since the portion of the gap located in the core array region 101 is covered by a sacrificial layer (which is resistant to the etchant used to remove the second dielectric layer), all second dielectric layers remain intact in the core array region 101.

[0151] Then, the gaps in the core array region 101 of the stacked structure are opened. Specifically, the portion of the gap located in the core array region 101 is reopened by removing the sacrificial layer to expose the first dielectric layer and the second dielectric layer. In some embodiments, for example, potassium hydroxide (KOH), used for etching a sacrificial layer having polysilicon, is used to selectively etch away the sacrificial layer from the portion of the gap located in the core array region to open the portion of the gap located in the core array region.

[0152] Subsequently, the gaps in the connection region 103 of the covered stacked structure are filled. Specifically, the portions of the lateral recesses and gaps located in the connection region are covered by another sacrificial layer. In some embodiments, a sacrificial layer (e.g., a polysilicon layer or a carbon layer) different from the first and second dielectric layers is deposited into the lateral recesses and gaps using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof) to at least partially fill the gaps (covering the exposed first and second dielectric layers). The sacrificial layer can then be patterned using photolithography and wet etching and / or dry etching to remove the portion of the sacrificial layer located in the core array region, leaving only the portion of the sacrificial layer located in the connection region, to cover only the portions of the lateral recesses and gaps located in the core array region, not the portions located in the core array region. It should be understood that the lateral recesses can be considered as the portions of the gaps located in the connection region. Therefore, even if only the lateral recesses are completely or partially filled by the sacrificial layer, the portions of the gaps located in the connection region can still be considered as covered.

[0153] Then, all second dielectric layers in the core array region 101 of the stacked structure are removed through the gaps in the core array region 101. Specifically, all second dielectric layers in the core array region 101 are completely removed by wet etching to form lateral recesses. In some embodiments, the second dielectric layers are wet-etched by applying a wet etchant through the portion of the gaps in the core array region not covered by the sacrificial layer, thereby creating lateral recesses staggered between the first dielectric layers. The wet etchant may include phosphoric acid for etching the second dielectric layers, including silicon nitride. In some embodiments, one or both of the etching rate and etching time are controlled to ensure that all second dielectric layers in the core array region are completely etched away. Because the portion of the gap located in the connection region 103 is covered by a sacrificial layer (which is resistant to the etchant used to remove the second dielectric layers), the remaining second dielectric layers in the dielectric portion 107 of the connection region 103 remain intact.

[0154] Subsequently, the gap in the connection region 103 of the stacked structure is opened. Specifically, the portion of the gap located in the connection region is reopened by removing the sacrificial layer to expose the first dielectric layer and the remaining second dielectric layer in the connection region. In some embodiments, for example, KOH used for etching a sacrificial layer having polysilicon is used to selectively etch away the sacrificial layer from the portion of the gap located in the connection region to open the portion of the gap (and the lateral recess) located in the connection region.

[0155] Finally, a conductive layer is deposited through the gaps into the lateral recesses in the conductive portions 105 of the core array region 101 and the connection region 103. In some embodiments where a high-k gate dielectric layer is not formed in the channel structure, the high-k gate dielectric layer is deposited into the lateral recesses prior to the conductive layer, such that the conductive layer is deposited on and surrounded by the high-k gate dielectric layer. In some embodiments where a high-k gate dielectric layer is formed in the channel structure, the high-k gate dielectric layer is not deposited into the lateral recesses prior to the conductive layer, such that the conductive layer is deposited on and surrounded by the first dielectric layer. The conductive layer (e.g., a metal layer) can be deposited using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0156] As described above, by partially covering the gaps in the core array region or the connection region, the removal of the second dielectric layer (e.g., a stacked sacrificial layer with silicon nitride) can be performed separately in the core array region and the connection region, allowing the second dielectric layer to be removed at different extents (e.g., completely removed in the core array region and partially removed in the connection region). It should be understood that in another gate replacement process, the removal of the second dielectric layer can be performed first in the core array region and then in the connection region.

[0157] Return to reference Figure 7 Method 700 proceeds to operation 708, such as... Figure 7 As shown, in operation 708, contact structures extending through the first dielectric layer and the remaining second dielectric layer in the first portion of the stacked structure are formed at different depths. For example, see reference... Figure 8C A first contact structure 116 extending through the first dielectric layer 224 and the remainder of the second dielectric layer 222, and a second contact structure 106 extending through a portion of the first dielectric layer 224 and the remainder of the second dielectric layer 222, can be formed in the connection region 103. See below for reference. Figure 9 and Figures 10A-10G Exemplary methods and exemplary manufacturing processes for forming contact structures are shown respectively.

[0158] Return to reference Figure 7 Method 700 proceeds to operation 710, such as... Figure 7 As shown, in operation 710, a connecting layer is formed over the contact structure and the channel structure. For example, refer to... Figure 8D A connection layer 308 can be formed on the contact structures 116, 106 and the channel structure 110. As a result, a semiconductor structure 360 ​​can be formed.

[0159] Return to reference Figure 7Method 700 proceeds to operation 712, such as... Figure 7 As shown, in operation 712, the peripheral circuit is formed. For example, refer to... Figure 8E The peripheral circuit 330 can be formed by forming a device layer 332 on the semiconductor layer 331 and a connection layer 334 on the device layer 332.

[0160] Return to reference Figure 7 Method 700 proceeds to operation 714, such as... Figure 7 As shown, in operation 714, a semiconductor device is formed by bonding a connection layer to a peripheral circuit. For example, see reference... Figure 8F It can Figure 8C The peripheral circuitry 330 is flipped and bonded to the interconnect layer 308 of the semiconductor structure 360 ​​to form Figure 3B Semiconductor device 350 in the middle.

[0161] Figure 9 This is a flowchart of a method 900 for forming a plurality of contact structures in a semiconductor structure according to some aspects of this disclosure. Figures 10A-10G A manufacturing process for forming multiple contact structures in a semiconductor structure is shown according to some aspects of this disclosure. Figure 9 and Figures 10A-10G Examples of semiconductor structures depicted include Figure 3B The semiconductor structure depicted in Figure 360 ​​will be described together. Figure 9 and Figures 10A-10G It should be understood that the operations shown in method 900 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of these operations may be performed simultaneously, or in conjunction with... Figure 9 The different orders shown are executed sequentially.

[0162] refer to Figure 9 Method 900 begins at operation 902, in which a stacked structure comprising alternating (interleaved) first and second dielectric layers is formed on a semiconductor layer. The first dielectric layer may comprise silicon oxide, and the second dielectric layer may comprise silicon nitride. The stacked structure may be formed by one or more thin-film deposition processes, including but not limited to ALD, CVD, PVD, or any combination thereof.

[0163] Method 900 proceeds to operation 904, such as... Figure 9 As shown, in operation 904, a first contact hole extending through the stacked structure is formed. Method 900 proceeds to operation 906, as follows: Figure 9 As shown, in operation 906, a second contact hole extending through a portion of the stacked structure is formed during the formation of the first contact hole.

[0164] For example, refer to Figure 10A A stacked structure comprising an interleaved first dielectric layer 224 and a second dielectric layer 222 is formed on semiconductor layer 201. The stacked structure can be etched using a first mask to form a first opening 1002 and a second opening 1004 extending into the stacked structure. In some embodiments, the second opening 1004 may form at least one second contact hole in the second contact holes. The first opening 1002 and the second opening 1004 may have the same depth and extend into a first stack pair comprising the first dielectric layer 224A and the second dielectric layer 222A to expose the second dielectric layer 222A. Although... Figure 10A Only one second opening 1004 is shown in the document, but multiple second openings 1004 can be formed, and this is not a limitation herein.

[0165] refer to Figure 10B A second mask can be used to etch the first opening 1002 to form a third opening 1006 that further extends through the stacked structure and the semiconductor layer 201. Thus, a first contact hole is formed including the first opening 1002 and the third opening 1006. It should be noted that when forming the third opening 1006, the smaller remaining portion of the semiconductor layer 201 may not be etched away, allowing the material of the first contact structure formed in the first contact hole to be deposited over the remaining portion of the semiconductor layer 201. As described below... Figure 10G As shown, this remaining portion of the semiconductor layer 201 can be removed after the first contact structure is formed.

[0166] In some embodiments, a third mask may be used to further etch the stacked structure to form a fourth opening (not shown) extending into the stacked structure at a depth different from that of opening 1004. The second contact hole may also include the fourth opening. For example, the fourth opening may be formed for... Figure 2A The second contact hole in the second contact structure 106A. By performing a similar operation, multiple second contact holes with the same or different depths extending into the stacked structure can be formed by etching the stacked structure using the same or different masks.

[0167] A method for forming openings of varying depths is referred to as a cutting process. As used herein, a "cutting" process is a process that increases the depth of one or more openings extending through a stacked structure comprising interleaved first and second dielectric layers by multiple etch cycles. Each etch cycle may include one or more dry and / or wet etch processes that etch a pair of first and second dielectric layers (i.e., reduce the depth by one dielectric layer pair). The purpose of a cutting process is to form multiple openings at varying depths. Therefore, depending on the number of openings, a specific number of cutting processes and a certain number of cutting masks may be required. It should be understood that the number of cutting masks, the order of the cutting masks, the design of each cutting mask (e.g., the number and pattern of openings), and / or the depth reduced by each cutting process (e.g., the number of etch cycles) may affect the specific depth of each opening after the cutting process. A detailed description of a cutting process can be found in U.S. Patent Application No. 16 / 881,168, filed May 22, 2022, and U.S. Patent Application No. 16 / 881,339, filed May 22, 2022, both of which are incorporated herein by reference in their entirety.

[0168] Method 900 proceeds to operation 908, such as... Figure 9 As shown, in operation 908, a first contact structure is formed in the first contact hole. Method 900 proceeds to operation 910, as follows: Figure 9 As shown, in operation 910, during the formation of the first contact structure, a second contact structure is formed in the second contact hole.

[0169] For example, refer to Figure 10C A first spacer 214 can be formed on the sidewall of the first contact hole, and can be in Figure 10C A second spacer 204 is formed on the sidewall of the second contact hole shown. Specifically, a first spacer 214 can be formed on the sidewall and bottom of the first contact hole, and a second spacer 204 can be formed on the sidewall and bottom of the second contact hole, thereby covering the first dielectric layer 224 and the second dielectric layer 222 exposed from the sidewall and bottom of the first and second contact holes. In some embodiments, the first spacer 214 and the second spacer 204 can be formed by depositing a dielectric material (e.g., silicon oxide) on the sidewall and bottom surfaces of the first and second contact holes using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0170] Then, the portion of the first spacer 214 located at the bottom of the first contact hole is removed to expose the remaining portion of the semiconductor layer 201. The portion of the second spacer 204 located at the bottom of the second contact hole is also removed to expose the second dielectric layer 222A. In some embodiments, dry etching can be applied to remove the portions of the first spacer 214 located at the bottom of the first contact hole and the portions of the second spacer 204 located at the bottom of the second contact hole. For example, the etching rate, direction, and / or duration of the RIE are controlled to etch only the portions of the first spacer 214 and the second spacer 204 located on the bottom surface, without etching the portions located on the sidewalls; that is, "punching" through the first spacer 214 and the second spacer 204 in the z-direction to expose the remaining portion of the semiconductor layer 201 and the second dielectric layer 222A, respectively.

[0171] Subsequently, reference Figure 10D and Figure 10E A transverse contact structure 206 can be formed below the bottom of the second contact hole. For example, as shown... Figure 10D As shown, a portion of the second dielectric layer 222A exposed at the bottom of the second contact hole is removed by wet etching to form a lateral recess 1008. In some embodiments, a portion of the second dielectric layer 222A is wet-etched by applying a wet etchant through the second contact hole, thereby creating a lateral recess 1008 sandwiched between the two first dielectric layers 224. The wet etchant may include phosphoric acid for etching the second dielectric layer 222A, which comprises silicon nitride. In some embodiments, the etching rate and / or etching time are controlled to remove only a portion of the second dielectric layer 222A sufficient to expose the corresponding conductive layer 302A located at the same horizontal plane. Figure 3B (as shown in the diagram). Then, the lateral recess 1008 can be filled by depositing conductive material through the second contact hole to form... Figure 10E The lateral contact structure 206 is located within the second contact hole. One or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) can be used to deposit a conductive material (e.g., a metal layer). The deposition rate and / or duration can be controlled to ensure that the lateral contact structure 206 contacts the corresponding exposed conductive layer 302A at the same level as the lateral recess 1008. In other words, the second dielectric layer 222A exposed from the bottom of the second contact hole can be partially replaced by the corresponding lateral contact structure 206 in the dielectric portion 107 of the connection region 103, while other second dielectric layers 222 located at other levels in the dielectric portion 107 remain intact.

[0172] Refer again Figure 10EThe first conductor layer 212 may be formed over the first spacer 214 and the bottom of the first contact hole. The second conductor layer 202 may be formed over the second spacer 204 and the lateral contact structure 206. In some embodiments, the first conductor layer 212 and the second conductor layer 202 may be formed in the same process as forming the lateral contact structure 206 by using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to deposit conductive material not only into the lateral recess 1008 but also onto the sidewalls and bottom surfaces of the first and second contact holes.

[0173] refer to Figure 10F The remaining portion of the first contact hole can be filled with a first filler body 218. The remaining portion of the second contact hole can be filled with a second filler body 208. The first filler body 218 and the second filler body 208 (e.g., a dielectric layer) can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). Excess portions of the conductor layer and dielectric layer can be removed using chemical mechanical polishing (CMP).

[0174] refer to Figure 10G The first contact pad 220 may be formed on the first conductor layer 212 and the first filler body 218. The second contact pad 210 may be formed on the second conductor layer 202 and the second filler body 208. In some embodiments, the remaining portion of the semiconductor layer 201 located below the first contact hole may be removed, and contact pads 1050 may be formed to fill the space of the remaining portion of the semiconductor layer 201.

[0175] Figure 11 A block diagram of an exemplary system 1100 having a 3D memory device according to some aspects of this disclosure is shown. System 1100 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game controller, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 11 As shown, system 1100 may include a host 1108 and a memory system 1102 having one or more 3D memory devices 1104 and a memory controller 1106. The host 1108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 1108 may be configured to send data to or receive data from the 3D memory device 1104.

[0176] Memory device 1104 can be any 3D memory device disclosed herein. In some embodiments, memory device 1104 includes NAND flash memory.

[0177] According to some embodiments, a memory controller 1106 (also referred to as a controller circuit) is coupled to the memory device 1104 and the host 1108 and is configured to control the memory device 1104. For example, the memory controller 1106 may be configured to operate a multiple-channel structure via word lines. The memory controller 1106 may manage data stored in the memory device 1104 and communicate with the host 1108. In some embodiments, the memory controller 1106 is designed to operate in a low duty cycle environment, such as with a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1106 is designed to operate in a high duty cycle environment, such as with an SSD or an embedded multimedia card (eMMC), which is used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 1106 may be configured to control the operation of the memory device 1104 (e.g., read operations, erase operations, and programming operations). The memory controller 1106 may also be configured to manage various functions relating to data stored or to be stored in the memory device 1104, including but not limited to: bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 1104. The memory controller 1106 may also perform any other suitable function, such as formatting the memory device 1104. The memory controller 1106 may communicate with an external device (e.g., host 1108) according to a specific communication protocol. For example, the memory controller 1106 may communicate with an external device via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), FireWire, etc.

[0178] The memory controller 1106 and one or more 3D memory devices 1104 can be integrated into various types of memory devices, such as being included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 1102 can be implemented and packaged into different types of end electronic products. Figure 12A In one example shown, the memory controller 1106 and the single memory device 1104 can be integrated into the memory card 1202. The memory card 1202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1202 may also include a connection between the memory card 1202 and a host computer (e.g., Figure 11 The host 1108) is electrically coupled to the memory card connector 1204. In such a... Figure 12B In another example shown, the memory controller 1106 and multiple 3D memory devices 1104 can be integrated into the SSD 1206. The SSD 1206 may also include a connection between the SSD 1206 and a host (e.g., Figure 11 The host 1108 is electrically coupled to the SSD connector 1208. In some embodiments, the storage capacity and / or operating speed of the SSD 1206 is greater than the storage capacity and / or operating speed of the memory card 1202.

[0179] The descriptions of specific implementation methods described above can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance provided herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementation methods.

[0180] The breadth and scope of this disclosure should not be limited to any of the embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: Semiconductor layer; A stacked structure situated above the semiconductor layer and comprising alternating first layers and first dielectric layers, wherein the stacked structure includes a first portion and a second portion adjacent to the first portion, the first layer of the first portion comprising a second dielectric layer, and the first layer of the second portion comprising a conductive layer; A first contact structure extends through the first portion and the semiconductor layer; as well as A second contact structure extends through a portion of the first portion and connects to one of the conductive layers.

2. The semiconductor device according to claim 1, wherein: The first contact structure includes a first segment and a second segment connected to the first segment in a first direction. The first segment includes a first end that contacts the second segment, and the second segment includes a second end that contacts the first segment. In a second direction perpendicular to the first direction, the size of the first end is larger than the size of the second end.

3. The semiconductor device according to claim 2, wherein, The first segment further includes a third end remote from the first end, and the second segment further includes a fourth end remote from the second end, wherein, in the second direction, the size of the third end is larger than the size of the first end, and in the second direction, the size of the second end is larger than the size of the fourth end.

4. The semiconductor device according to claim 2, wherein, The first segment is located on the side of the second segment away from the semiconductor layer.

5. The semiconductor device according to claim 1, wherein: The second contact structure includes a vertical direct contact structure and a lateral contact structure connected to the vertical direct contact structure, wherein the vertical direct contact structure extends in the same direction as the first contact structure, and the lateral contact structure is connected to one of the conductive layers in the conductive layer.

6. The semiconductor device according to claim 5, wherein: The first contact structure includes a first engagement located in the first stack pair, and the vertical direct contact structure extends to the first stack pair, wherein the first stack pair is a pair including a first dielectric layer in the first dielectric layer and a first layer in the first layer that contacts the first dielectric layer in the first dielectric layer.

7. The semiconductor device of claim 6, further comprising a third contact structure extending through a portion of the first portion, wherein, The third contact structure is connected to the second stack pair, and the first contact structure includes a second joint located in the second stack pair.

8. The semiconductor device according to claim 1, wherein: The first contact structure includes a first conductor layer and a first spacer surrounding the first conductor layer; and The second contact structure includes a second conductor layer and a second spacer surrounding the second conductor layer, wherein the first spacer and the second spacer are made of the same material, and the first conductor layer and the second conductor layer are made of the same material.

9. The semiconductor device according to claim 8, wherein, The first contact structure also includes a first filler body surrounded by the first conductor layer.

10. The semiconductor device according to claim 9, wherein, The second contact structure further includes a second filler body surrounded by the second conductor layer, and the first filler body and the second filler body comprise the same material.

11. The semiconductor device of claim 1, further comprising a channel structure extending through the second portion into the semiconductor layer.

12. The semiconductor device according to claim 11, wherein: In the vertical direction, the length of the first contact structure is greater than the length of the channel structure.

13. The semiconductor device according to claim 11, wherein: The second part includes a first part and a second part spaced apart from the first part, wherein the first part connects the first part and the second part.

14. The semiconductor device according to claim 1, further comprising peripheral circuitry connected to the first contact structure.

15. The semiconductor device of claim 14, further comprising a first connection layer and a second connection layer, the first connection layer being connected to the first contact structure, and the second connection layer being connected to the peripheral circuit. in, The first connection layer is bonded to the second connection layer.

16. The semiconductor device according to claim 14, wherein, The peripheral circuit is disposed below the stacked structure, and the first contact structure extends through the semiconductor layer to connect with the peripheral circuit.

17. A method of forming a semiconductor device, comprising: A stacked structure is formed, the stacked structure including alternating first layers and first dielectric layers, wherein the stacked structure includes a first portion and a second portion adjacent to the first portion, the first layer of the first portion including a second dielectric layer, and the first layer of the second portion including a conductive layer; A first contact hole is formed, which extends through the stacked structure; During the formation of the first contact hole, a second contact hole is formed that extends through a portion of the stacked structure; A first contact structure is formed in the first contact hole; and A second contact structure is formed in the second contact hole. The second contact structure extends through a portion of the first portion and is connected to one of the conductive layers.

18. The method according to claim 17, wherein, Forming the first contact hole and forming the second contact hole during the formation of the first contact hole includes: The stacked structure is etched using a first mask to form a first opening extending into the stacked structure and one or more second openings, wherein the second contact hole includes the one or more second openings; and A second mask is used to etch the first opening to form a third opening that further extends through the stacked structure, wherein the first contact hole includes the first opening and the third opening.

19. The method according to claim 18, wherein, Forming the second contact hole further includes: A third mask is used to etch the stacked structure to form one or more fourth openings extending into the stacked structure, wherein the second contact hole further includes the one or more fourth openings.

20. The method of claim 17, further comprising: During the formation of the first contact structure, a second contact structure is formed in the second contact hole.

21. The method of claim 20, wherein: The first contact structure includes a first spacer, a first conductor layer surrounded by the first spacer, and a first filler body surrounded by the first conductor layer; and The second contact structure includes a second spacer, a second conductor layer surrounded by the second spacer, a transverse contact structure connected to the second conductor layer, and a second filler body surrounded by the second conductor layer.

22. The method according to claim 21, wherein, Forming the first contact structure and forming the second contact structure includes: Specifically, the first spacer is formed on the sidewall of the first contact hole, and the second spacer is formed on the sidewall of the second contact hole; The lateral contact structure of the second contact structure is formed below the bottom of the second contact hole; Specifically, a first conductor layer is formed over the bottom of the first spacer and the first contact hole, and a second conductor layer is formed over the second spacer and the lateral contact structure; and Specifically, the first filler body is used to fill the remaining portion of the first contact hole, and the second filler body is used to fill the remaining portion of the second contact hole.

23. The method according to claim 22, wherein, The lateral contact structure forming the second contact structure below the bottom of the second contact hole includes: The portions of the corresponding second dielectric layer exposed at the bottom of the second contact hole are removed to form a lateral recess; and The lateral contact structure is formed by depositing conductive material through the second contact hole to fill the lateral recesses.

24. The method according to claim 22, wherein, Forming the first contact structure and forming the second contact structure further includes: First contact pads are formed on the first conductor layer and the first filler body, respectively, and second contact pads are formed on the second conductor layer and the second filler body.

25. A semiconductor device, comprising: Semiconductor layer; A stacked structure, the stacked structure being situated above the semiconductor layer and comprising alternating conductive and dielectric layers; A first contact structure extends through the stacked structure and includes a first conductor layer and a first spacer surrounding the sidewalls of the first conductor layer; as well as The second contact structure extends through a portion of the stacked structure and includes a second conductor layer and a second spacer surrounding the sidewalls of the second conductor layer. The second conductor layer is connected to one of the conductive layers, and the first conductor layer is separated from the conductive layer by the first spacer.

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