Semiconductor device

Abstract

Provided are a semiconductor device having a large storage capacity, a semiconductor device capable of achieving miniaturization or high integration, a semiconductor device having high reliability, a semiconductor device having low power consumption, or a semiconductor device having a high operating speed. In the semiconductor device, in a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer provided in this order on the first conductive layer, an opening that reaches the first conductive layer is provided. A third insulating layer, a first charge accumulation layer, a fourth insulating layer, an oxide semiconductor layer, a fifth insulating layer, a second charge accumulation layer, a sixth insulating layer, and a fourth conductive layer are provided in this order from a side wall close to the opening, and the first conductive layer and the third conductive layer are respectively used as one and the other of a source electrode and a drain electrode of the transistor. The fourth conductive layer is used as a first control gate, and the second conductive layer is used as a second control gate.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device, a storage device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device and a storage device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. As an example of the technical field of one embodiment of the present invention, a display device, a light-emitting device, a power storage device, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), and a driving method or a manufacturing method of the above-mentioned device can be cited.

[0003] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device including the circuit, etc. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips with integrated circuits, and electronic components that contain chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves are semiconductor devices, and sometimes all include semiconductor devices. Background Art

[0004] In recent years, semiconductor devices have been developed, and LSI, CPU (Central Processing Unit), memory, etc. are mainly used for semiconductor devices. CPU is a collection of semiconductor elements including a semiconductor integrated circuit (including at least transistors and memory) processed into a chip by a semiconductor wafer and having electrodes as connection terminals. Semiconductor circuits (IC chips) such as LSI, CPU, memory, etc. are mounted on a circuit board, such as a printed wiring board, and are used as one of the components of various electronic devices.

[0005] In addition, the technology of forming a transistor by using a semiconductor film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and display devices. As a semiconductor film that can be applied to transistors, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have attracted attention.

[0006] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely small in the off state. For example, Patent Document 1 has disclosed a low-power CPU that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 discloses a storage device that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor to achieve long-term retention of stored content.

[0007] In recent years, with the miniaturization and lightness of electronic devices, the demand for further high density of integrated circuits has increased. In addition, it is required to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology in which a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film are stacked and a plurality of memory cells are arranged in an overlapping manner, thereby increasing the density of the integrated circuit. In addition, Patent Document 4 discloses a technology in which the channel of a transistor using an oxide semiconductor film is configured vertically to achieve high density of the integrated circuit.

[0008] In addition, CAAC-IGZO as a crystalline oxide semiconductor is disclosed in Non-Patent Document 2. In addition, Non-Patent Document 2 also discloses the growth mechanism of CAAC-IGZO and the like.

[0009] In addition, Patent Document 5 discloses a nonvolatile memory using a floating gate. In addition, Patent Document 6 discloses a nonvolatile memory including an oxide semiconductor layer. In addition, as shown in Patent Document 7, in a nonvolatile semiconductor memory device, a memory transistor can be arranged in a three-dimensional manner.

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187

[0011] [Patent Document 2] Japanese Patent Application Publication No. 2011-151383

[0012] [Patent Document 3] International Patent Application Publication No. 2021 / 053473

[0013] [Patent Document 4] Japanese Patent Application Publication No. 2013-211537

[0014] [Patent Document 5] Japanese Patent Application Publication No. 2009-295971

[0015] [Patent Document 6] Japanese Patent Application Publication No. 2011-124563

[0016] [Patent Document 7] Japanese Patent Application Publication No. 2007-266143

[0017] [Non-patent document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53

[0018] [Non-Patent Document 2] Noboru Kimizuka and Shunpei Yamazaki, “PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE SEMICONDUCTOR CAAC-IGZO: FUNDAMENTALS”, (USA), Wiley-SID Series in Display Technology, 2017, pp. 50-150 Summary of the invention

[0019] One of the purposes of one embodiment of the present invention is to provide a transistor, semiconductor device or storage device with large storage capacity. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor, semiconductor device or storage device that can achieve miniaturization or high integration. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor, semiconductor device or storage device with high reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor, semiconductor device or storage device with low power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor, semiconductor device or storage device with fast operating speed. In addition, one of the purposes of one embodiment of the present invention is to provide a novel transistor, semiconductor device or storage device. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing the above-mentioned transistor, semiconductor device or storage device.

[0020] Note that the description of these objectives does not prevent the existence of other objectives. One embodiment of the present invention does not need to achieve all of the above objectives. Objectives other than the above objectives can be extracted from the description of the specification, drawings, and claims.

[0021] One embodiment of the present invention is a semiconductor device comprising: a first conductive layer; a first insulating layer on the first conductive layer; a second conductive layer on the first insulating layer; a second insulating layer on the second conductive layer; a third conductive layer on the second insulating layer; an oxide semiconductor layer; a fourth conductive layer; a third insulating layer; a fourth insulating layer; a fifth insulating layer; a sixth insulating layer; a first charge accumulation layer; and a second charge accumulation layer, wherein the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have an opening that reaches the first conductive layer, the third insulating layer has a region that contacts the side wall of the opening of the first insulating layer, a region that contacts the side wall of the opening of the second conductive layer, and a region that contacts the top surface of the first conductive layer, and the first charge accumulation layer has a region that covers the side wall of the opening of the second conductive layer via the third insulating layer. domain, the fourth insulating layer has a region on the side wall of the opening portion covering the second conductive layer through the third insulating layer and the first charge accumulation layer, the fourth insulating layer has a region sandwiched between the oxide semiconductor layer and the first charge accumulation layer, the oxide semiconductor layer has a region in contact with the top surface of the first conductive layer, a region on the side wall of the opening portion covering the second conductive layer through the third insulating layer, the first charge accumulation layer and the fourth insulating layer, and a region in contact with the third conductive layer, the fourth conductive layer has a region located in the opening portion of the second conductive layer, the second charge accumulation layer has a region sandwiched between the oxide semiconductor layer and the fourth conductive layer, the fifth insulating layer has a region sandwiched between the oxide semiconductor layer and the second charge accumulation layer, and the sixth insulating layer has a region sandwiched between the second charge accumulation layer and the fourth conductive layer.

[0022] In the above embodiment, it is preferred that the fourth insulating layer and the fifth insulating layer include one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0023] In addition, in the above method, it is preferred that at least one of the first charge accumulation layer and the second charge accumulation layer contains one or more metal elements selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, or an alloy containing the above metal elements as components or an alloy combining the above metal elements.

[0024] Furthermore, in the above-described embodiment, it is preferable that at least one of the first charge accumulation layer and the second charge accumulation layer contains a metal nitride or a metal oxide.

[0025] Furthermore, in the above embodiment, it is preferable that at least one of the first charge accumulation layer and the second charge accumulation layer contains one or more selected from silicon and germanium.

[0026] Furthermore, in the above embodiment, it is preferable that at least one of the first charge accumulation layer and the second charge accumulation layer contains one or more selected from silicon nitride and silicon nitride oxide.

[0027] In addition, in the above method, preferably, the first conductive layer and the third conductive layer are respectively used as one and the other of the source electrode and the drain electrode of the transistor, the fourth conductive layer is used as the first control gate of the transistor, and the second conductive layer is used as the second control gate of the transistor.

[0028] According to one embodiment of the present invention, a transistor, semiconductor device or storage device with large storage capacity can be provided. In addition, according to one embodiment of the present invention, a transistor, semiconductor device or storage device capable of miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a transistor, semiconductor device or storage device with high reliability can be provided. In addition, according to one embodiment of the present invention, a transistor, semiconductor device or storage device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a transistor, semiconductor device or storage device with high operating speed can be provided. In addition, according to one embodiment of the present invention, a novel transistor, semiconductor device or storage device can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing the above-mentioned transistor, semiconductor device or storage device can be provided.

[0029] Note that the description of these effects does not prevent the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. Effects other than the above effects can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1A is a perspective view showing an example of a semiconductor device, Figure 1B is a plan view showing an example of a semiconductor device, Figure 1C is a cross-sectional view showing an example of a semiconductor device, Figure 1D is a circuit diagram of one embodiment of the present invention;

[0031] FIG. 2A to FIG. 2E is a cross-sectional view showing an example of a semiconductor device;

[0032] Figure 3A and Figure 3B is a cross-sectional view showing an example of a semiconductor device, Figure 3C is a perspective view showing an example of a semiconductor device;

[0033] Figure 4A is a plan view showing an example of a semiconductor device, Figure 4B and Figure 4C is a cross-sectional view showing an example of a semiconductor device;

[0034] Figure 5A is a cross-sectional view showing an example of a semiconductor device, Figure 5B is a plan view showing an example of a semiconductor device, Figure 5C and Figure 5D is a cross-sectional view showing an example of a semiconductor device;

[0035] Fig. 6A and Figure 6B is a cross-sectional view showing an example of a semiconductor device;

[0036] Fig. 7A and Figure 7B is a circuit diagram showing an example of a semiconductor device;

[0037] Fig. 8A is a circuit diagram showing an operating example of a semiconductor device, Figure 8B An example of an Id-Vgs curve of a semiconductor device is shown;

[0038] 9A to 9C is a timing chart showing an operation example of a semiconductor device;

[0039] Fig. 10A is a circuit diagram showing an operating example of a semiconductor device, Fig. 10B is a timing chart showing an operation example of a semiconductor device;

[0040] Fig.11A is a circuit diagram showing an operating example of a semiconductor device, Fig. 11B is a timing chart showing an operation example of a semiconductor device;

[0041] Fig.12 is a circuit diagram showing an operation example of a semiconductor device;

[0042] FIG. 13A to FIG. 13C is a timing chart showing an operation example of a semiconductor device;

[0043] Fig.14A and Fig. 14B is a timing chart showing an operation example of a semiconductor device;

[0044] Fig.15 is a circuit diagram showing an operation example of a semiconductor device;

[0045] FIG. 16A to FIG. 16C is a timing chart showing an operation example of a semiconductor device;

[0046] 17A to 17C is a timing chart showing an example of operation of a semiconductor device, Fig.17D is a diagram showing an example of an Id-Vgs curve;

[0047] 18A to 18D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0048] FIG. 19A to FIG. 19D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0049] FIG. 20A to FIG. 20C is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0050] Fig.21 is a cross-sectional view showing an example of a semiconductor device;

[0051] FIG. 22A to FIG. 22D is a cross-sectional view showing an example of a method for manufacturing an oxide semiconductor;

[0052] Figures 23A to 23D is a cross-sectional view showing an example of an oxide semiconductor;

[0053] Fig.24 is a block diagram illustrating a structural example of a semiconductor device;

[0054] Fig.25A and Fig.25B is a perspective view illustrating a structural example of a semiconductor device;

[0055] Fig.26 is a block diagram illustrating a CPU;

[0056] Fig.27A and Fig.27B is a three-dimensional diagram of a semiconductor device;

[0057] Fig.28A and Fig.28B is a three-dimensional diagram of a semiconductor device;

[0058] Fig.29A and Fig.29B is a diagram showing various levels of class storage devices;

[0059] Fig. 30A and Fig. 30B is a diagram showing an example of an electronic component;

[0060] FIG. 31A to FIG. 31C is a diagram showing an example of a large computer, Fig.31D is a diagram showing an example of a space device, Fig.31E is a diagram showing an example of a storage system that can be used in a data center. DETAILED DESCRIPTION

[0061] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0062] Note that in the invention structure described below, the same symbols are used in different drawings to represent the same parts or parts with the same function, and repeated description is omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without special additional symbols.

[0063] In addition, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent its actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0064] In this specification, etc., for the sake of convenience, ordinal numbers such as "first" and "second" are added, but they do not limit the number of components or the order of components (for example, process order or stacking order). In addition, the ordinal numbers added to components in one part of this specification may be inconsistent with the ordinal numbers added to the components in other parts of this specification or claims.

[0065] A transistor is a type of semiconductor element and can realize functions of amplifying current or voltage, controlling switching operations of conduction or non-conduction, etc. The transistor in this specification includes IGFET (Insulated Gate Field Effect Transistor) and thin film transistor (TFT: Thin Film Transistor).

[0066] In this specification, etc., a transistor using an oxide semiconductor or metal oxide for a semiconductor layer and a transistor including an oxide semiconductor or metal oxide in a channel formation region may be referred to as an OS transistor. Also, a transistor including silicon in a channel formation region may be referred to as a Si transistor.

[0067] In this specification, etc., a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region.

[0068] In addition, when transistors with different polarities are used or the direction of current changes during circuit operation, the functions of the source and the drain may be interchanged. Therefore, in this specification, the source and the drain may be interchanged.

[0069] Note that the impurities of a semiconductor refer to elements other than the main components that constitute the semiconductor. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity. When impurities are contained, for example, the defect state density of the semiconductor may increase or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, the impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specifically, for example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In addition, water sometimes acts as an impurity. In addition, for example, the mixing of impurities sometimes leads to oxygen vacancies (also recorded as V O )’s formation.

[0070] In this specification, etc., an oxynitride refers to a material containing more oxygen than nitrogen in its composition. An oxynitride refers to a material containing more nitrogen than oxygen in its composition.

[0071] For example, the content of hydrogen, oxygen, carbon, nitrogen and other elements in the film can be analyzed by secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). When the content ratio of the target element is high (for example, 0.5 atomic% or more or 1 atomic% or more), XPS is very suitable. On the other hand, when the content ratio of the target element is low (for example, 0.5 atomic% or less or 1 atomic% or less), SIMS is very suitable. When comparing the content of elements, it is more preferable to use a composite analysis using both SIMS and XPS analysis techniques.

[0072] In addition, depending on the situation or state, the "film" and the "layer" may be interchanged. For example, the "conductive layer" may be replaced with the "conductive film". In addition, the "insulating film" may be replaced with the "insulating layer".

[0073] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -20° and less than 20°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 70° and less than 110°.

[0074] In this specification, "electrical connection" includes connection through "an element having some kind of electrical function". Here, "an element having some kind of electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected objects. For example, "an element having some kind of electrical function" includes switching elements such as transistors, resistors, coils, and other elements having various functions in addition to electrodes and wiring.

[0075] In addition, in this specification, etc., unless otherwise specified, off-state current refers to the leakage current between the source and the drain when the transistor is in the off state (also called non-conducting state or blocking state). In n-channel transistors, the off state refers to the voltage V between the gate and the source. gs Below the threshold voltage V th (In a p-channel transistor, V gs Higher than V th ) status.

[0076] In this specification, etc., the normally-on characteristic refers to a state in which a channel exists and current flows through a transistor even when no voltage is applied to the gate. In addition, the normally-off characteristic refers to a state in which current does not flow through a transistor when no potential is applied to the gate or when a ground potential is supplied to the gate.

[0077] In this specification, etc., the top surface shape of a component refers to the outline shape of the component when viewed from a plane. In addition, viewed from a plane refers to the situation when viewed from the normal direction of the surface on which the component is formed or the surface of a support (such as a substrate) on which the component is formed.

[0078] In this specification, etc., "the top surface shapes are roughly consistent" means that at least a portion of the edges of each layer in the stack overlap. For example, it includes the case where the upper layer and the lower layer are processed by the same mask pattern or a portion of the same mask pattern. However, in reality, there are cases where the edges do not overlap, and sometimes the upper layer is located on the inner side of the lower layer or the upper layer is located on the outer side of the lower layer. In this case, it can also be said that "the top surface shapes are roughly consistent". When the top surface shapes are consistent or roughly consistent, it can also be said that the ends are aligned or roughly aligned, or the side ends are aligned or roughly consistent.

[0079] In this specification, etc., a tapered shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to a substrate surface or a formed surface. For example, it is preferred to have a region where the angle formed by the inclined side surface and the substrate surface or the formed surface (also referred to as a taper angle) is greater than 0 degrees and less than 90 degrees. Here, the side surface, substrate surface, and formed surface of a constituent element do not necessarily have to be completely flat, and may also be a substantially planar shape with a slight curvature or a substantially planar shape with fine concave-convex shapes.

[0080] In this specification and the like, when there is a description that "A is in contact with B", at least a part of A is in contact with B. Therefore, for example, A can be said to include a region in contact with B in other words.

[0081] In this specification and the like, when there is a description that “A is located on B”, at least a portion of A is located on B. Therefore, for example, A can be said to include a region located on B in other words.

[0082] In this specification and the like, when there is a description that A covers B, at least a portion of A covers B. Therefore, for example, A can be said to include a region covering B in other words.

[0083] In this specification and the like, when there is a description that "A overlaps with B", at least a part of A overlaps with B. Therefore, for example, A can be said to include a region overlapping with B in other words.

[0084] In this specification and the like, disconnection refers to a phenomenon in which a layer, a film, or an electrode is disconnected due to the shape of a formed surface (for example, a step, etc.).

[0085] Note that sometimes arrows indicating the X direction, Y direction, and Z direction are attached in the drawings and the like of this specification. In this specification and the like, the "X direction" refers to the direction along the X axis, and except for the case where it is clearly stated, sometimes the forward direction and the reverse direction are not distinguished. The same is true for the "Y direction" and the "Z direction". In addition, the X direction, the Y direction, and the Z direction are directions that intersect each other. For example, the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other.

[0086] Implementation Method 1

[0087] In this embodiment, a semiconductor device which is one embodiment of the present invention is described.

[0088] A semiconductor device according to one embodiment of the present invention includes a first conductive layer, a second conductive layer, and an oxide semiconductor layer.

[0089] The first insulating layer is located on the first conductive layer, and the second conductive layer is located on the first insulating layer. The first insulating layer has a first opening portion that reaches the first conductive layer. The oxide semiconductor layer covers the top surface of the first conductive layer and the side surface of the first insulating layer in the first opening portion. Note that the opening portion is also referred to as an opening.

[0090] The second conductive layer has a second opening that overlaps with the first opening, and the oxide semiconductor layer covers the side surfaces of the second conductive layer in the second opening.

[0091] Furthermore, a semiconductor device according to one embodiment of the present invention includes a third conductive layer, a fourth conductive layer, a first charge accumulation layer, and a second charge accumulation layer.

[0092] The third conductive layer overlaps the oxide semiconductor layer in the first opening via the first charge storage layer.

[0093] The fourth conductive layer is located on the first insulating layer and below the second conductive layer. The fourth conductive layer has a third opening overlapping the first opening. The oxide semiconductor layer overlaps the fourth conductive layer via the second charge accumulation layer in the third opening.

[0094] The first conductive layer is used as one of the source electrode and the drain electrode of the transistor. The second conductive layer is used as the other of the source electrode and the drain electrode of the transistor. The third conductive layer is used as the first gate electrode of the transistor, and the fourth conductive layer is used as the second gate electrode of the transistor.

[0095] The charge accumulation layer can store charges. In addition, the charge accumulation layer can release the stored charges. In addition, the charge accumulation layer can hold the stored charges.

[0096] The transistor included in the semiconductor device of one embodiment of the present invention can store information by storing charges in the charge accumulation layer. The transistor included in the semiconductor device of one embodiment of the present invention can be used as a storage device. In addition, because the transistor included in the semiconductor device of one embodiment of the present invention includes a plurality of charge accumulation layers, it can be used as a multi-value memory. Therefore, by using the transistor of one embodiment of the present invention, a semiconductor device with a large storage capacity can be realized. In a transistor of one embodiment of the present invention, a first charge accumulation layer for controlling the writing of information with a first gate electrode and a second charge accumulation layer for controlling the writing of information with a second gate electrode can increase the amount of information stored in each transistor.

[0097] A semiconductor device according to one embodiment of the present invention includes a transistor used as a storage element. A semiconductor device according to one embodiment of the present invention can retain data written to the semiconductor device for a long time even after the power supplied to the storage element is cut off. A semiconductor device according to one embodiment of the present invention can be represented as a non-volatile semiconductor device. In addition, a transistor included in a semiconductor device according to one embodiment of the present invention can rewrite written data. A transistor included in a semiconductor device according to one embodiment of the present invention is sometimes referred to as an EEPROM (Electrically Erasable Programmable Read Only Memory).

[0098] In this specification, the phrase "when viewed in section" may be used to describe the relationship between multiple components. For example, when describing the relationship between multiple components, the relationship when viewed in section from the same direction is described. In this case, the relationship between the multiple components can be described with reference to one cross-sectional view.

[0099] The source electrode and drain electrode of the transistor of one embodiment of the present invention are located at different heights (for example, the height in the direction perpendicular to the substrate surface or insulating plane on which the transistor is set), so the current flowing through the semiconductor layer flows in the height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction), so the transistor of one embodiment of the present invention can also be called VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, etc.

[0100] Since the source electrode, the semiconductor layer, and the drain electrode can be overlapped, the occupied area of ​​the transistor of one embodiment of the present invention can be made much smaller than that of a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0101] In this specification, etc., "ends are consistent" means that when viewed from a plane, at least a portion of the contours of the stacked layers overlap. For example, this includes the case where the upper layer and the lower layer are processed by the same mask pattern or a portion of the same mask pattern. However, strictly speaking, sometimes the contours do not overlap and the contour of the upper layer is located inside the contour of the lower layer or the contour of the upper layer is located outside the contour of the lower layer. These cases can also be said to be "ends consistent".

[0102] Note that, in general, it is sometimes difficult to clearly distinguish between “completely consistent” and “substantially consistent.” Therefore, in this specification, etc., “consistent” may include both completely consistent and substantially consistent.

[0103] <Structural Example 1 of Semiconductor Device>

[0104] Figure 1A is a perspective view of a semiconductor device including a transistor 500. In addition, Figure 1B Show Figure 1A A plan view of transistor 500 is shown, Figure 1C Shown corresponding to Figure 1B The cross section is shown as the dotted line C1-C2. Note that for the sake of clarity, Figure 1A Some components are omitted in the stereoscopic views shown in the figure.

[0105] The transistor 500 is used as a storage element. In particular, the transistor 500 can be used as a nonvolatile storage element. By configuring the storage cell including the transistor 500 in a matrix shape, a storage device capable of storing a large amount of data can be formed. The storage cell including the transistor 500 can be used as a NOR type storage cell, a NAND type storage cell, etc., for example. Note that the transistor 500 is sometimes referred to as a memory transistor. In addition, the transistor 500 can be represented as a nonvolatile memory. In addition, a semiconductor device including the transistor 500 is sometimes referred to as a nonvolatile semiconductor device or a nonvolatile storage device, etc.

[0106] The transistor 500 includes an oxide semiconductor layer 530, a charge accumulation layer 552, a conductive layer 560, a charge accumulation layer 555, and a conductive layer 114. The conductive layer 560 has a columnar shape. The charge accumulation layer 552 is provided so as to surround the conductive layer 560, the oxide semiconductor layer 530 is provided so as to surround the conductive layer 560 via the charge accumulation layer 552, the charge accumulation layer 555 is provided so as to surround the conductive layer 560 via the charge accumulation layer 552 and the oxide semiconductor layer 530, and the conductive layer 114 is provided so as to surround the conductive layer 560 via the charge accumulation layer 552, the oxide semiconductor layer 530, and the charge accumulation layer 555. The charge accumulation layer 552, the oxide semiconductor layer 530, the charge accumulation layer 555, and the conductive layer 114 all have a cylindrical shape.

[0107] exist Figures 1A to 1C In the embodiment, it can be expressed as follows: the conductive layer 560 has a cylindrical shape, and the charge accumulation layer 552, the oxide semiconductor layer 530, the charge accumulation layer 555, and the conductive layer 114 all have a hollow cylindrical shape. Here, the hollow cylindrical shape means that the first cylinder is hollowed out by the second cylinder, the centers of the first cylinder and the second cylinder are the same, and the diameter of the second cylinder is smaller than the diameter of the first cylinder. In addition, it can also be expressed as follows: the conductive layer 560 is arranged in the hollow part of the hollow cylindrical shape of the charge accumulation layer 552, the oxide semiconductor layer 530, the charge accumulation layer 555, and the conductive layer 114.

[0108] The conductive layer 560 and the conductive layer 114 have a region in which they overlap with each other with the oxide semiconductor layer 530 being interposed therebetween.

[0109] The charge accumulation layer 552 has a region sandwiched between the oxide semiconductor layer 530 and the conductive layer 560. The insulating layer 551 has a region sandwiched between the oxide semiconductor layer 530 and the charge accumulation layer 552. The insulating layer 553 has a region sandwiched between the charge accumulation layer 552 and the conductive layer 560.

[0110] In the transistor 500 , the oxide semiconductor layer 530 is used as a semiconductor layer, the conductive layer 560 is used as a first gate electrode, and the conductive layer 114 is used as a second gate electrode.

[0111] The conductive layer 560 and the conductive layer 114 are sometimes referred to as control gates or control gate electrodes. Here, the conductive layer 560 is referred to as a first control gate, and the conductive layer 114 is referred to as a second control gate. In addition, when the conductivity of the charge accumulation layer 552 is high, the charge accumulation layer 552 is referred to as a floating gate or a floating gate electrode. Similarly, when the conductivity of the charge accumulation layer 555 is high, the charge accumulation layer 555 is referred to as a floating gate or a floating gate electrode.

[0112] An insulating layer is provided between the charge accumulation layer and the semiconductor layer and between the charge accumulation layer and the control gate. Figure 1B and Figure 1C In FIG. 5 , insulating layers 551 and 554 are shown as insulating layers between the charge accumulation layer and the semiconductor layer, and insulating layers 553 and 556 are shown as insulating layers between the charge accumulation layer and the control gate. Figure 1B and Figure 1C In the figure, the boundaries between these insulating layers and the boundaries between these insulating layers and insulating layers in other regions (interlayer insulating layers, etc.) are not clearly shown.

[0113] The insulating layer 551, the charge storage layer 552, and the insulating layer 553 each have a region located between the oxide semiconductor layer 530 and the conductive layer 560. The insulating layer 551, the charge storage layer 552, and the insulating layer 553 are arranged in order from the closest to the oxide semiconductor layer 530.

[0114] The insulating layer 554, the charge accumulation layer 555, and the insulating layer 556 each have a region located between the oxide semiconductor layer 530 and the conductive layer 114. The insulating layer 554, the charge accumulation layer 555, and the insulating layer 556 are arranged in order from closest to the oxide semiconductor layer 530.

[0115] Figure 1D An example of a transistor that can adopt the structure of the above-described transistor 500 is shown.

[0116] Figure 1DThe transistor M1 shown includes a first control gate (denoted as CG1 in the figure) and a second control gate (denoted as CG2 in the figure). In addition, the transistor M1 includes a first charge accumulation layer (denoted as Ch1 in the figure) whose storage and release of charges are controlled by the first control gate, and a second charge accumulation layer (denoted as Ch2 in the figure) whose storage and release of charges are controlled by the second control gate. The first control gate, the second control gate, the first charge accumulation layer, and the second charge accumulation layer can all correspond to the conductive layer 560, the conductive layer 114, the charge accumulation layer 552, and the charge accumulation layer 555 included in the transistor 500. Alternatively, sometimes the first control gate, the second control gate, the first charge accumulation layer, and the second charge accumulation layer can also correspond to the conductive layer 114, the conductive layer 560, the charge accumulation layer 555, and the charge accumulation layer 552.

[0117] By injecting carriers into at least one of the charge accumulation layer 552 and the charge accumulation layer 555 or releasing carriers from at least one of the charge accumulation layer 552 and the charge accumulation layer 555, information can be written to the transistor 500. By injecting carriers into the charge accumulation layer or releasing carriers from the charge accumulation layer, the threshold of the transistor 500 can be changed, and the current value flowing between the source and the drain during reading can be changed. In addition, by utilizing the tunnel current flowing through the insulating layer 551 located between the oxide semiconductor layer 530 and the charge accumulation layer 552, carriers can be injected into or released from the charge accumulation layer 552. In addition, by utilizing the tunnel current flowing through the insulating layer 554 located between the oxide semiconductor layer 530 and the charge accumulation layer 555, carriers can be injected into or released from the charge accumulation layer 555. Sometimes the insulating layer 551 and the insulating layer 554 are each referred to as a tunnel insulating layer.

[0118] Notice, Figure 1C An example is shown in which the charge accumulation layer 555 and the conductive layer 114 are located at the same height, but the charge accumulation layer 555 may have one or both of a region higher than the conductive layer 114 (region with a large Z coordinate) and a region lower than the conductive layer 114 (region with a small Z coordinate). Figure 2A An example is shown in which the charge storage layer 555 has a region lower than the conductive layer 114. Figure 2B An example is shown in which the charge storage layer 555 has a region higher than the conductive layer 114 and a region lower than the conductive layer 114 .

[0119] In addition, if Figure 2C As shown, the charge storage layer 555 sometimes has a region sandwiched between the conductive layer 114 and the oxide semiconductor layer 530 and a region located on the conductive layer 114 .

[0120] In addition, if Figure 3A and Figure 3BAs shown, the transistor 500 preferably includes a conductive layer 520 and a conductive layer 540. The conductive layer 520 is used as one of a source electrode and a drain electrode, and the conductive layer 540 is used as the other of the source electrode and the drain electrode.

[0121] The oxide semiconductor layer 530 is preferably in contact with the conductive layer 520 and the conductive layer 540. Figure 3A In the structure shown, the oxide semiconductor layer 530 is in contact with the side surface of the conductive layer 520 and the side surface of the conductive layer 540. Figure 3B In the embodiment, the oxide semiconductor layer 530 has a region in contact with the top surface of the conductive layer 520 . Figure 3C Shown corresponding to Figure 3B A perspective view of the cross section shown.

[0122] Note that Figure 2D As shown, the oxide semiconductor layer 530 may be in contact with not only the side surface but also the top surface of the conductive layer 540. By adopting such a structure, the contact area can be increased and the contact resistance can be reduced.

[0123] In addition, Figure 2E In the illustrated structural example, the insulating layer 554 covers the side surfaces of the conductive layer 560. The oxide semiconductor layer 530 covers the side surfaces and the top surface of the conductive layer 540, but the insulating layer 554 is provided between the side surfaces, so that the oxide semiconductor layer 530 is in contact with the top surface but not with the side surfaces.

[0124] Reference FIG. 4A to FIG. 4C The structure of a semiconductor device according to one embodiment of the present invention will be described. Figure 4A is a plan view of a semiconductor device including a transistor 500 . Figure 4B It is along Figure 4A A cross-sectional view along the dashed line A1-A2 is shown. Figure 4C It is along Figure 4A A cross-sectional view along the dashed line A3-A4 is shown. Figure 5A yes Figure 4B Note that for clarity, Figure 4A Some components are omitted in the plan view of the previous figure. Sometimes some components are also omitted in the subsequent plan view.

[0125] FIG. 4A to FIG. 4C The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 500 on the insulating layer 210, an insulating layer 481 on the insulating layer 210, an insulating layer 482 on the insulating layer 481, an insulating layer 483 on the insulating layer 482, an insulating layer 283 on the transistor 500, and an insulating layer 285. The insulating layer 210, the insulating layer 481, the insulating layer 482, the insulating layer 483, the insulating layer 283, and the insulating layer 285 are used as interlayer films.

[0126] exist FIG. 4A to FIG. 4C , the transistor 500 includes a conductive layer 520, a conductive layer 540, an oxide semiconductor layer 530, an insulating layer 551, a charge accumulation layer 552, an insulating layer 553, a conductive layer 560, an insulating layer 554, a charge accumulation layer 555, an insulating layer 556, and a conductive layer 114. The conductive layer 520 and the conductive layer 540 are located at different heights. The insulating layer 481, the insulating layer 482, and the insulating layer 483 are located between the conductive layer 520 and the conductive layer 540.

[0127] In addition, the insulating layer 556 has a region overlapping with the top surface of the conductive layer 520. The insulating layer 556 in this region is sandwiched between the conductive layer 520 and the charge accumulation layer 555. Thus, the conductive layer 520 and the charge accumulation layer 555 can be prevented from directly contacting each other. When the conductive layer 520 and the charge accumulation layer 555 are in direct contact, charges retained in the charge accumulation layer 555 flow through the conductive layer 520.

[0128] The conductive layer 114 and the insulating layer 482 are provided over the insulating layer 481. The insulating layer 483 is provided over the conductive layer 114 and the insulating layer 482.

[0129] exist FIG. 4A to FIG. 4C and Figure 5A In the semiconductor device shown, the insulating layer 481 is located on the conductive layer 520, the conductive layer 114 is located on the insulating layer 481, the insulating layer 483 is located on the conductive layer 114, and the conductive layer 540 is located on the insulating layer 483. Openings (openings 590c, 590d, 590e, and 590f) that reach the conductive layer 520 are provided in the insulating layer 481, the conductive layer 114, the insulating layer 483, and the conductive layer 540.

[0130] The insulating layer 481 has an opening 590c that reaches the top surface of the conductive layer 520. In addition, the conductive layer 114 has an opening 590d. When viewed from a plane, the opening 590c overlaps with the opening 590d. In addition, the side surface of the opening 590c and the side surface of the opening 590d are preferably smoothly connected. Thus, when the side surface of the opening 590c to the side surface of the opening 590d is covered by an insulating layer, a conductive layer, a semiconductor layer, etc., the coverage can be improved.

[0131] The conductive layer 560 has at least a region located in the opening 590 e . The conductive layer 560 in the opening 590 e overlaps with the conductive layer 114 with the oxide semiconductor layer 530 interposed therebetween.

[0132] The insulating layer 556 covers the side surfaces of the opening 590c of the insulating layer 481 and the side surfaces of the opening 590d of the conductive layer 114. The insulating layer 556 is preferably in contact with the side surfaces of the opening 590c of the insulating layer 481 and the side surfaces of the opening 590d of the conductive layer 114. In addition, the charge storage layer 555 covers the side surfaces of the opening 590c of the insulating layer 481 and the side surfaces of the opening 590d of the conductive layer 114 via the insulating layer 556.

[0133] like Figure 4B and Figure 4C and Figure 5A As shown in FIG. 5 , the conductive layer 114 , the insulating layer 482 , the insulating layer 556 , and the charge storage layer 555 are preferably provided so that the heights of the top surfaces thereof are substantially the same.

[0134] The insulating layer 483 has an opening 590e. The opening 590e overlaps with the opening 590c when viewed from the top. In addition, it is preferable that the opening 590e is surrounded by the opening 590c when viewed from the top.

[0135] The conductive layer 540 has an opening 590f. The opening 590f overlaps with the opening 590c when viewed from the top. In addition, it is preferable that the opening 590f is surrounded by the opening 590c when viewed from the top.

[0136] In addition, the side surface of the opening 590e is preferably smoothly connected to the side surface of the opening 590f. Therefore, when the side surface of the opening 590e to the side surface of the opening 590f is covered by an insulating layer, a conductive layer, a semiconductor layer, etc., the coverage can be improved.

[0137] The insulating layer 554 covers the side surfaces of the opening 590e of the insulating layer 483 and the side surfaces of the opening 590f of the conductive layer 540. The insulating layer 554 is preferably in contact with the side surfaces of the opening 590e of the insulating layer 483 and the side surfaces of the opening 590f of the conductive layer 540. In addition, the insulating layer 554 covers the side surfaces of the opening 590c of the insulating layer 481 and the side surfaces of the opening 590d of the conductive layer 114 via the charge storage layer 555 and the insulating layer 556.

[0138] The oxide semiconductor layer 530 has a region in contact with the top surface of the conductive layer 520 in the opening 590c. The oxide semiconductor layer 530 also has a region in contact with the top surface of the conductive layer 540. The oxide semiconductor layer 530 covers the insulating layer 554 in the opening 590c, the opening 590d, the opening 590e, and the opening 590f.

[0139] The insulating layer 551 , the charge storage layer 552 , and the insulating layer 553 are provided in this order over the oxide semiconductor layer 530 . The conductive layer 560 is provided over the insulating layer 553 .

[0140] The conductive layer 560 has a region facing the conductive layer 114 with the oxide semiconductor layer 530 interposed therebetween in the opening 590 e .

[0141] exist FIG. 4A to FIG. 4C In the embodiment, the insulating layer 554 has a region overlapping with the top surface of the conductive layer 520 and has an opening 290c overlapping with the conductive layer 520. Since the opening 290c is provided in the insulating layer 554, the oxide semiconductor layer 530 can be in contact with the conductive layer 520 via the opening 290c.

[0142] In the semiconductor device of one embodiment of the present invention, a metal oxide serving as a semiconductor (also referred to as an oxide semiconductor) can be used as the oxide semiconductor layer 530 .

[0143] A region of the oxide semiconductor layer 530 that is in contact with the conductive layer 520 and the conductive layer 540 is preferably used as a low-resistance region.

[0144] The oxide semiconductor layer 530 is provided inside the opening 590c of the insulating layer 481, inside the opening 590d of the conductive layer 114, and inside the opening 590e of the insulating layer 483. In addition, one of the source electrode and the drain electrode of the transistor 500 (here, the conductive layer 520) is located below and the other of the source electrode and the drain electrode (here, the conductive layer 540) is located above, so that current flows in the up-down direction.

[0145] By changing the amount of charge stored in the charge accumulation layer, information can be written to the transistor 500. In addition, carriers such as electrons and holes can be stored in the charge accumulation layer. As the charge accumulation layer, for example, a conductor can be used. When a conductor is used as the charge accumulation layer, it is preferable to surround the conductor with an insulator. Alternatively, as the charge accumulation layer, for example, an insulator having a function of capturing carriers can be used. For example, a positive high potential is applied to the gate with reference to the source or the drain, whereby electrons are injected from the oxide semiconductor layer 530 into the charge accumulation layer through the insulating layer between the oxide semiconductor layer and the charge accumulation layer and stored. In addition, for example, a negative high potential is applied to the gate with reference to the source or the drain, whereby electrons are released from the charge accumulation layer to the oxide semiconductor layer 530 through the insulating layer. In addition, the charge accumulation layer can retain the stored charge.

[0146] In this way, by making the oxide semiconductor layer 530 contact not only the side surface but also the top surface of the conductive layer 540, for example, compared with the case where the oxide semiconductor layer 530 contacts the side surface but not the top surface of the conductive layer 540, the area in which the oxide semiconductor layer 530 contacts the conductive layer 540 can be increased. Therefore, the contact resistance between the oxide semiconductor layer 530 and the conductive layer 540 can be reduced.

[0147] In addition, in the transistor 500, the side surface and the top surface of the conductive layer 540 are covered by the charge accumulation layer 552, and the area of ​​the conductive layer 540 covered by the charge accumulation layer 552 can be increased compared to the case where only one of the side surface or the top surface is covered. When data is written to the transistor 500, when carriers are injected from the oxide semiconductor layer 530 into the charge accumulation layer 552 due to the electric field between the gate and the drain, the area of ​​the conductive layer 540 covered by the charge accumulation layer 552 is increased to improve the writing efficiency. The transistor of one embodiment of the present invention can improve the writing efficiency compared to the planar transistor.

[0148] In addition, in a planar transistor having a semiconductor layer formed in an island shape, the boundary between the channel forming region and the drain forming region has an end of the island-shaped semiconductor layer. When the current flowing through the transistor causes heat, etc., the end of the channel width direction of the island-shaped semiconductor layer may be significantly affected by the heat. Such heat generation may lead to a reduction in withstand voltage, and its influence is sometimes more significant because the amount of current in a transistor with a large channel width is large. On the other hand, in transistor 500, since the semiconductor layer can be arranged along the side wall of the opening of the insulating layer, the semiconductor layer may not have an end at the boundary between the channel forming region and the drain forming region. Thus, the tolerance of the source and drain of the transistor can be improved. In addition, the withstand voltage between the gate and the drain or between the gate and the source can also be improved. Therefore, when a high electric field is applied between the drain and the source, between the gate and the source, between the gate and the drain, etc. during writing and deleting, the degradation of the transistor can be suppressed and the reliability of the storage element can be improved.

[0149] exist FIG. 4A to FIG. 4C In the semiconductor device shown, Figure 4C The end of the charge accumulation layer 552 in the cross section shown is located outside the end of the conductive layer 560. That is, the end of the charge accumulation layer 552 is arranged outside the end of the conductive layer 560 in the direction along the Y axis, and the top surface of the charge accumulation layer 552 has an area not covered by the conductive layer 560. By adopting Figure 4C In the structure shown in the figure, the insulating layer 551, the charge storage layer 552, and the insulating layer 553 are interposed between the conductive layer 560 and the conductive layer 540, whereby leakage current between the conductive layer 560 and the conductive layer 540 can be suppressed.

[0150] On the other hand, Figure 4B In the illustrated cross section, the end of the charge accumulation layer 552 is located inside the end of the conductive layer 560. This is because the conductive layer 560 extends in the direction along the X-axis.

[0151] Note that the end of the charge accumulation layer 552 may be located inside the end of the conductive layer 560 in the direction along the Y axis. By adopting such a structure, the overlapping area of ​​the charge accumulation layer 552 and the conductive layer 560 can be increased, and the capacitance value between the charge accumulation layer 552 and the conductive layer 560 can be increased. By increasing the capacitance value, the voltage required for writing can be reduced, thereby improving the writing efficiency of the memory element.

[0152] The occupied area of ​​the transistor 500, specifically, the area of ​​the transistor when viewed from above, is roughly determined by the width of the opening 590c of the insulating layer 481, the width of the opening 590e of the insulating layer 483, etc. In the transistor 500, the channel formation region, the source region, and the drain region can be arranged at different heights, thereby reducing the occupied area compared to a transistor in which the semiconductor layer is arranged on a plane to arrange the channel formation region, the source region, and the drain region on a plane. Thus, high integration of semiconductor devices can be achieved. In addition, by using a semiconductor device of one embodiment of the present invention in a storage device, the storage capacity per unit area can be increased.

[0153] In addition, in the transistor 500, the conductive layer 520 used as one of the source electrode and the drain electrode and the conductive layer 540 used as the other of the source electrode and the drain electrode are arranged at different heights. In addition, the conductive layer 520 can be used in common in a plurality of transistors 500, and similarly, the conductive layer 540 can be used in common in a plurality of transistors 500. The conductive layer used in common in a plurality of transistors can also be extended and used as wiring.

[0154] In the semiconductor device of one embodiment of the present invention, since the conductive layer 520 and the conductive layer 540 are arranged at different heights, even when the conductive layer 520 and the conductive layer 540 are extended and used as wiring, the wiring using the conductive layer 520 and the wiring using the conductive layer 540 can be arranged crosswise without short-circuiting them. Therefore, the area of ​​the memory cell can be reduced.

[0155] Figure 5B The cross section of the XY plane including the insulating layer 481 is shown. The oxide semiconductor layer 530 surrounds the entire periphery of the conductive layer 560 via the insulating layer 551, the charge storage layer 552, and the insulating layer 553. When a gate electric field is applied through the conductive layer 560, a channel formation region of the transistor 500 may be formed in the entire oxide semiconductor layer 530 surrounding the periphery of the conductive layer 560. Note that Figure 5B It can also be said that it is a cross-sectional view taken along the XY plane including the channel formation region of the oxide semiconductor layer 530 .

[0156] The conductive layer 114 surrounds the periphery of the oxide semiconductor layer 530 via the insulating layer 554, the charge storage layer 555, and the insulating layer 556. A channel formation region of the transistor 500 when a gate electric field is applied via the conductive layer 114 may be formed in the entire oxide semiconductor layer 530 surrounded by the conductive layer 114.

[0157] Figure 5A Show Figure 4B The channel length of transistor 500 is the distance between the source region and the drain region. In other words, it can be said that the channel length of transistor 500 is determined by the sum of the thicknesses of insulating layer 481, insulating layer 483, and conductive layer 114 on conductive layer 520. Figure 5A The double-headed dotted arrow in FIG. 5 shows a channel length L of the transistor 500. In cross-sectional view, the channel length L is a distance between an end of a region where the oxide semiconductor layer 530 and the conductive layer 520 are in contact with each other and an end of a region where the oxide semiconductor layer 530 and the conductive layer 540 are in contact with each other. That is, in cross-sectional view, the channel length L is approximately equal to the sum of the length of the side surface of the opening 590 c of the insulating layer 481, the length of the side surface of the opening 590 d of the conductive layer 114, the length of the side surface of the opening 590 e of the insulating layer 483, and the length of the side surface of the opening 590 f of the conductive layer 540.

[0158] The width of the opening 590c is width D. In addition, the width of the opening 590e is width D2. Width D and width D2 sometimes vary in the depth direction. For example, it can be the width of the upper end of the opening of the insulating layer. Or, it can be the width of the lower end. Or, it can be the width of half the depth of the opening in the insulating layer.

[0159] The side walls of the openings 590c and 590e are preferably shaped to be perpendicular or nearly perpendicular to the top surface of the formed surface of the layer where the opening is provided (when the top surface of the formed surface has unevenness, the top surface of the layer below it with smaller unevenness or the top surface of the substrate surface). Since the opening has such a shape, the occupied area of ​​the transistor 500 can be reduced. Therefore, miniaturization of the semiconductor device can be achieved.

[0160] The angle formed by the top surface of the conductive layer 520 (or the top surface of the insulating layer 210, the top surface of the substrate) and the side wall of the opening 590c of the insulating layer 481 is defined as angle θ481. In addition, the angle formed by the top surface of the conductive layer 520 (or the top surface of the insulating layer 210, the top surface of the substrate, the top surface of the conductive layer 114) and the side wall of the opening 590e of the insulating layer 483 is defined as angle θ483. θ481 and θ483 are preferably angles of 90 degrees or approximately 90 degrees. For example, θ481 and θ483 are preferably not less than 75 degrees and not more than 90 degrees.

[0161] In addition, θ481 and θ483 may be less than 75 degrees, less than 70 degrees, less than 65 degrees, or less than 60 degrees. By forming the side wall of the opening into a tapered shape, coverage of the film formed on the side wall of the opening can be improved.

[0162] In a planar transistor, the minimum value of the channel length is limited by the exposure accuracy of the photolithography method, and it is difficult to further achieve miniaturization. However, in a transistor included in a semiconductor device of one embodiment of the present invention, since the channel length corresponds to the thickness of the insulating layer 481, the insulating layer 483, etc., the channel length can be less than the minimum value limited by the exposure accuracy of the photolithography method (for example, less than 60nm, less than 50nm, less than 40nm, less than 30nm, less than 20nm, or less than 10nm and more than 0.1nm, more than 1nm, or more than 5nm). As a result, the on-state current of the transistor 500 increases, and the response speed of the storage element can be improved.

[0163] Since the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is determined by the thickness of the insulating layer 481, the insulating layer 483, etc. on the conductive layer 520, for example, when the channel length is set to 60nm or more, the occupied area of ​​the transistor, specifically, the area of ​​the transistor when viewed from above, is also roughly determined by the width of the opening provided in the insulating layer 481, the insulating layer 483, etc. As described later, the width D2 of the opening 590e is preferably 5nm or more, 10nm or more, or 20nm or more and 100nm or less, 60nm or less, 50nm or less, 40nm or less, or 30nm or less. As an example, when the channel length is set to 150nm, the width of the opening 590e can also be made less than 150nm. That is, a transistor whose width of the opening is narrower than the channel length can be formed, the occupied area of ​​the transistor can be reduced, and high integration of the semiconductor device can be achieved. By increasing the channel length, the withstand voltage between the source and the drain when writing to the storage element and the reliability can be improved.

[0164] In addition, by setting the channel length of the transistor to, for example, less than 1 μm, less than 500 nm, or less than 300 nm, productivity and yield can be improved in the formation of the insulating layer 481 and the insulating layer 483, the formation of openings in the insulating layer 481 and the insulating layer 483, and the like.

[0165] Therefore, the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more and 1 μm or less, 500 nm or less, or 300 nm or less.

[0166] In addition, when writing and deleting data, a high voltage is sometimes applied between the drain and source of transistor 500. Therefore, the channel length of transistor 500 is preferably long enough to withstand the high voltage between the drain and the source. Therefore, the channel length of transistor 500 may be, for example, more than 10 nm, more than 20 nm, or more than 30 nm. As described above, the area occupied by transistor 500 is roughly determined by the width of opening 590 c, etc., and when the channel length is extended, the area occupied by the transistor is hardly affected. Therefore, transistor 500 can achieve high withstand voltage and integration.

[0167] In addition, if Figure 5B As shown, the oxide semiconductor layer 530 and the conductive layer 560 are arranged in a concentric circle shape. Therefore, the side surface of the conductive layer 560 arranged in the center is opposite to the side surface of the oxide semiconductor layer 530. In other words, the periphery of the oxide semiconductor layer 530 as a whole becomes a channel formation region when viewed from a plane. At this time, for example, the channel width of the transistor 500 is determined by the length of the periphery of the oxide semiconductor layer 530. In other words, the channel width of the transistor 500 is determined by the size of the width of the opening 590e, the opening 590f, etc. (the diameter when the opening shape is circular when viewed from a plane). Figure 5B The double-pointed arrow indicates the channel width W of the transistor 500. By increasing the width D2 of the opening 590e, the channel width per unit area can be increased, thereby increasing the on-state current.

[0168] When the opening is formed by photolithography, the minimum value of the width D2 of the opening 590e is limited by the exposure accuracy of the photolithography. The width D2 of the opening 590e is preferably 5 nm or more, 10 nm or more, or 20 nm or more and 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening is circular when viewed from a plane, the width D2 of the opening is equivalent to the diameter of the opening, and the channel width W can be calculated as "D2×π". In addition, Figure 5B In the above description, the width D of the opening 590 c is a value obtained by adding twice the thickness of the charge storage layer 555 and twice the thickness of the insulating layer 556 to the width D2.

[0169] Furthermore, by making the channel length L of the transistor 500 smaller than the channel width W of the transistor 500 , the current driving capability of the transistor can be improved. Therefore, for example, the writing speed of the memory element can be improved.

[0170] Furthermore, by making the channel length L of the transistor 500 larger than the channel width W of the transistor 500 , the withstand voltage between the source and the drain of the transistor can be increased. Therefore, for example, the rewrite resistance of the memory element can be improved.

[0171] In addition, the openings 590c, 590f, and 590e are formed in a circular shape when viewed from a plane, so that the oxide semiconductor layer 530 and the conductive layer 560 are arranged in a concentric shape. Thus, the electric field from the conductive layer 560 can be applied to the oxide semiconductor layer 530 in a substantially uniform manner. In addition, the opening 590f is formed in a circular shape, so that the openings of the oxide semiconductor layer 530 and the conductive layer 114 are arranged in a concentric shape. Thus, the electric field from the conductive layer 114 can be applied to the oxide semiconductor layer 530 in a substantially uniform manner.

[0172] Although the example in which the openings 590c, 590f, and 590e are circular when viewed from a plane is shown in this embodiment, the present invention is not limited thereto. For example, the shape of the opening when viewed from a plane may be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle have an arc shape. By making the opening shape a shape without corners such as a circle or an ellipse or making the corners of a polygon have an arc shape, the electric field from the conductive layer 560 and the conductive layer 114 can be suppressed from being concentrated at the corners of the oxide semiconductor layer 530.

[0173] In addition, if Figure 5C As shown, the conductive layer 520 may also have a recessed portion. Figure 5C In the embodiment, the conductive layer 520 has a concave portion overlapping with the opening 590c. The opening 590c and the concave portion of the conductive layer 520 form a continuous opening. The oxide semiconductor layer 530 is arranged along the bottom and side of the concave portion of the conductive layer 520. Therefore, the electric field of the drain can be received from the bottom direction and the side direction. Therefore, the writing efficiency can be improved.

[0174] also, Figure 5D FIG. 5 shows an example in which the recessed portion of the conductive layer 520 is deeper. Figure 5D In the concave portion, the oxide semiconductor layer 530, the insulating layer 551, the charge storage layer 552, the insulating layer 553, and at least a portion of the conductive layer 560 are formed. With this structure, the gate electric field of the conductive layer 560 can be easily applied to the oxide semiconductor layer 530 near the conductive layer 520.

[0175] In addition, Figure 5D In the embodiment, the conductive layer 520 and the conductive layer 560 have a region overlapping each other, and the oxide semiconductor layer 530, the insulating layer 551, the charge accumulation layer 552, and the insulating layer 553 are sandwiched therebetween. Therefore, for example, the gate electric field easily reaches the channel formation region of the oxide semiconductor layer 530, so that the write voltage of the memory element can sometimes be reduced. As a result, the power consumption of the semiconductor device can sometimes be reduced.

[0176] By reducing the thickness of the insulating layer 551, the voltage of the first control gate when writing to the transistor 500 can be reduced. Similarly, by reducing the thickness of the insulating layer 554, the voltage of the second control gate when writing to the transistor 500 can be reduced. By reducing the voltage, the power consumption of the memory device can be reduced and the writing time can be shortened. Thus, the operating speed of the memory device can be increased.

[0177] On the other hand, when the thickness of the insulating layer 551 is too thin, there is a concern that the number of carriers stored in the charge accumulation layer 552 may decrease due to leakage current. Similarly, when the thickness of the insulating layer 554 is too thin, there is a concern that the number of carriers stored in the charge accumulation layer 555 may decrease due to leakage current. When the number of carriers decreases due to leakage current, the retention characteristics of the memory device decrease.

[0178] Therefore, the thickness of the insulating layer 551 and the insulating layer 554 can be, for example, greater than or equal to 1 nm and less than or equal to 20 nm. Note that as the insulating layer 551 and the insulating layer 554, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, or the like is preferably used.

[0179] In addition, for example, the thickness of the insulating layer 553 is preferably thicker than the thickness of the insulating layer 551. As a result, the tunnel current flowing through the insulating layer 553 is reduced, and the charge of the charge accumulation layer 552 can be suppressed from being transferred to the first control gate side. Similarly, for example, the thickness of the insulating layer 556 is preferably thicker than the thickness of the insulating layer 554. The thickness of the insulating layer 553 and the insulating layer 556 can be, for example, not less than 8 nm and not more than 30 nm. As the insulating layer 553 and the insulating layer 556, for example, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or the like is preferably used.

[0180] Materials that can be used for the charge accumulation layer 552 and the charge accumulation layer 555 will be described later.

[0181] <Variation Example 1 of Semiconductor Device>

[0182] Fig. 6A Show Figure 4C Deformation example. Fig. 6A An example is shown in which the insulating layer 554 is provided mainly along the side walls of the opening 590 c , the opening 590 d , the opening 590 e , and the opening 590 f . Fig. 6A The insulating layer 554 shown may be formed, for example, using anisotropic etching. Fig. 6A The insulating layer 554 shown may be referred to as a sidewall or sidewall insulating layer.

[0183] In addition, if Fig. 6AAs shown, the height of the upper end of the insulating layer 554 may be lower than the top surface of the conductive layer 540. By adopting this structure, the oxide semiconductor layer 530 can be in contact not only with the top surface of the conductive layer 540 but also with the side surface thereof.

[0184] In addition, Figure 4B , Figure 4C , Fig. 6A In the structure shown in FIG. 1 , the height of the upper end of the charge storage layer 555 is substantially equal to the height of the upper end of the conductive layer 114. Therefore, the charge storage layer 555 is provided in a region sandwiched between the conductive layer 114 and the oxide semiconductor layer 530 and is not provided in other regions.

[0185] <Variation Example 2 of Semiconductor Device>

[0186] On the other hand, Figure 6B As shown in FIG. 1 , the following structure may be adopted: the height of the upper end of the charge accumulation layer 555 is not substantially consistent with the height of the upper end of the conductive layer 114, and the charge accumulation layer 555 is included on the conductive layer 114. Figure 6B In the example shown, the insulating layer 482 is also not provided.

[0187] exist Figure 4C In the embodiment, the top surfaces of the conductive layer 114, the charge accumulation layer 555, the insulating layer 556, and the insulating layer 482 are arranged in a manner such that their top surfaces are roughly aligned, and Figure 6B In FIG. 5 , the charge storage layer 555 and the insulating layer 556 have a region covering the top surface of the conductive layer 114. Figure 6B In the embodiment, there is a step between the side wall of the charge accumulation layer 555 and the side wall of the insulating layer 483.

[0188] Since there is no need for a process of forming the insulating layer 482, there is no need for a process of processing the conductive layer 114, the charge accumulation layer 555, the insulating layer 556, and the top surface of the insulating layer 482 in a substantially aligned manner, and there is no need for a process of minimizing the step between the side wall of the charge accumulation layer 555 and the side wall of the insulating layer 483, Figure 6B In the structure shown, the manufacturing process can be simplified to reduce the manufacturing cost. Figure 4C In the structure shown in the figure, the charge accumulation layer 555 is provided in a region sandwiched between the conductive layer 114 and the oxide semiconductor layer 530 and not in other regions, and the electric field from the conductive layer 114 is easily and uniformly applied to the charge accumulation layer 555, thereby improving the reliability of the storage element.

[0189] <Structural Example of Memory Cell Array>

[0190] Reference Fig. 7A and Figure 7BAn application example of a memory cell including the transistor 500 will be described.

[0191] Fig. 7A An example of a circuit diagram of a memory cell array 601 including a plurality of NOR memory cells 602 is shown. The memory cell 602 includes a transistor M1. The transistor M1 may be the transistor 500 described above or the like.

[0192] In the memory cell 602, one of the source and the drain of the transistor M1 is connected to the wiring BL, and the other is connected to the wiring SL. In addition, the first control gate of the transistor M1 is connected to the wiring WL1, and the second control gate is connected to the wiring WL2. The wiring WL1 and the wiring WL2 are used as word lines, and the wiring BL is used as a bit line.

[0193] The memory cell array 601 includes a plurality of wirings BL, a plurality of wirings SL, a plurality of wirings WL1, and a plurality of wirings WL2. One wiring BL is connected to each transistor M1 included in a plurality of memory cells 602 arranged in the same column. One wiring SL is connected to each transistor M1 included in a plurality of memory cells 602 arranged in the same row. One wiring WL1 is connected to each transistor M1 included in a plurality of memory cells 602 arranged in the same row. One wiring WL2 is connected to each transistor M1 included in a plurality of memory cells 602 arranged in the same row.

[0194] In addition, in the transistors M1 included in the plurality of memory cells 602 arranged in the same row, the same signal can be simultaneously supplied to the control gate and one of the source and the drain. When the transistor M1 is an n-channel transistor, for example, by supplying a negative potential to one of the source and the drain with respect to the control gate, data can be deleted simultaneously in the plurality of memory cells 602 arranged in the same row.

[0195] Figure 7B An example of a circuit diagram of a memory cell array 611 including a plurality of NAND memory cells 612 is shown. The memory cell 612 includes transistors M[0] to M

[31] , a transistor S1, and a transistor S2 connected in series. The transistor 500 described above can be used as the transistors M[0] to M

[31] .

[0196] In each of transistors M[0] to transistor M

[31] , transistor S1, and transistor S2, one of the source and the drain is referred to as the first terminal, and the other of the source and the drain is referred to as the second terminal. The first terminal of transistor M[k] is connected to the second terminal of transistor M[k-1], and the second terminal of transistor M[k] is connected to the first terminal of transistor M[k+1]. Here, k is an integer greater than 2 and less than 30.

[0197] The first terminal of the transistor S1 is connected to the wiring SL, and the second terminal is connected to the first terminal of the transistor M[0]. The first terminal of the transistor S2 is connected to the second terminal of the transistor M

[31] , and the second terminal is connected to the wiring BL.

[0198] The memory cell array 611 includes a plurality of wirings BL. One wiring BL is connected to one memory cell 612. The memory cell array 611 also includes wirings SG1, SG2, wirings WL1[0] to WL1

[31] , and wirings WL2[0] to WL2

[31] .

[0199] Wiring SG1 is connected to the gate of each transistor S1 of the plurality of memory cells 612. Wiring SG2 is connected to the gate of each transistor S2 of the plurality of memory cells 612. Wiring WL1[0] to wiring WL1

[31] are connected to the first gate of each transistor M[0] to transistor M

[31] of the plurality of memory cells 612. Wiring WL2[0] to wiring WL2

[31] are connected to the second gate of each transistor M[0] to transistor M

[31] of the plurality of memory cells 612.

[0200] The wiring SG1 and the wiring SG2 are used as wiring for selecting the memory cell 612 when performing operations such as writing, reading, and erasing.

[0201] Fig. 6A and Figure 6B Although an example in which one memory cell 612 is connected to one wiring is shown, one embodiment of the present invention is not limited to this.

[0202] <Working Example 1-1 of Semiconductor Device>

[0203] Reference FIG. 8A to FIG. 17D An operation example of the semiconductor device according to one embodiment of the present invention will be described.

[0204] Fig. 8A 4 states of the storage unit 602 are shown. Specifically, these four states refer to the state in which any one of the four data of data D_11, data D_01, data D_10, and data D_00 is stored. Figure 8B An example of an Id-Vgs curve of transistor M1 in the case of storing four data is shown. The drain current Id is the drain current of transistor M1, and the voltage Vgs is the voltage between the gate and the source of transistor M1. The threshold of the transistor changes according to the stored data. Therefore, when the voltage Vgs between the gate and the source is a specified value ( Figure 8B When Vr is Vr in the figure, the drain current Id changes according to the storage state. By reading the drain current Id, the stored data can be identified.

[0205] also, 9A to 9CA timing diagram corresponding to the operation of the memory cell 602 is shown.

[0206] First, refer to Fig. 8A and Fig. 9A An operation example of the semiconductor device will be described.

[0207] Fig. 8A In the memory cell 602 shown in the figure, the first control gate (represented as CG1 in the figure) is connected to the wiring WL1, and the second control gate (represented as CG2 in the figure) is connected to the wiring WL2. In addition, one of the source and the drain is connected to the wiring BL, and the other of the source and the drain is connected to the wiring SL.

[0208] [Data D_11]

[0209] exist Fig. 9A At the time t0 shown, when the state of the data D_11 is saved, the wire WL1, the wire WL2, and the wire BL are supplied with the low potential L, the low potential L, and the potential V2, respectively. In addition, the wiring SL is in a floating state. The state at the time t0 corresponds to Fig. 8A The state where the data D_11 in the memory cell 602 is stored (the memory cell 602 shown in the upper left). At this time, no charge is stored in the charge accumulation layer (hereinafter referred to as the first charge accumulation layer) located between the first control gate and the semiconductor layer. In addition, no charge is stored in the charge accumulation layer (hereinafter referred to as the second charge accumulation layer) located between the second control gate and the semiconductor layer.

[0210] [Work Wr1_1: Data D_01]

[0211] Then, in Fig. 9A At the time t1 shown, by changing the potential supplied to the wiring WL1 from the low potential L to the high potential H, changing the potential supplied to the wiring BL from the potential V2 to the potential V1, and supplying the low potential L to the wiring SL, the state of storing the data D_11 can be changed to storing the data D_01 ( Fig. 8A The data D_01 is a state in which charges are stored in the first charge accumulation layer. Hereinafter, the charges stored in the charge accumulation layer are, for example, electrons.

[0212] [Work Wr1_2: Data D_00]

[0213] Then, in Fig. 9A At the time t2 shown in the figure, by changing the potential supplied to the wiring WL2 from the low potential L to the high potential H, the state of storing the data D_01 can be changed to storing the data D_00 ( Fig. 8AThe data D_00 is the state of the storage unit 602 shown in the lower right of FIG. 1 (operation Wr1_2). The data D_00 is the state of the charges stored in the first charge accumulation layer and the second charge accumulation layer.

[0214] <Working Example 1-2 of Semiconductor Device>

[0215] Fig. 9A In the example shown, charges are stored in the first charge accumulation layer and the second charge accumulation layer in this order, but it is also possible to store Fig. 9B In the operation shown, charges are stored in the second charge accumulation layer and the first charge accumulation layer in this order.

[0216] [Data D_11]

[0217] and Fig. 9A At the time t0 shown, Fig. 9B The time t10 shown is a state where the data D_11 is stored.

[0218] [Work Wr2_1: Data D_10]

[0219] exist Fig. 9B At time t11 shown, by changing the potential supplied to the wiring WL2 from the low potential L to the high potential H, changing the potential supplied to the wiring BL from the potential V2 to the potential V1, and supplying the low potential L to the wiring SL, the state of storing data D_11 can be changed to storing data D_10 ( Fig. 8A The data D_10 is in a state where charges are stored in the second charge accumulation layer.

[0220] [Work Wr2_2: Data D_00]

[0221] Then, in Fig. 9B At the time t12 shown, by changing the potential supplied to the wiring WL1 from the low potential L to the high potential H, the state storing the data D_10 can be changed to the state storing the data D_00 (work Wr2_2).

[0222] <Working Example 1-3 of Semiconductor Device>

[0223] Fig. 9A and Fig. 9B The example of supplying charges to the first charge accumulation layer and the second charge accumulation layer at different operation timings is shown, but it is also possible to Fig. 9C In the operation shown, charges are stored in the first charge accumulation layer and the second charge accumulation layer by the same operation.

[0224] [Data D_11]

[0225] and Fig. 9AAt the time t0 shown, Fig. 9C The time t20 shown is a state where the data D_11 is stored.

[0226] [Work Wr3: Data D_00]

[0227] exist Fig. 9C At the time t21 shown, by changing the potential supplied to the wiring WL1 and the wiring WL2 from the low potential L to the high potential H, changing the potential supplied to the wiring BL from the potential V2 to the potential V1, and supplying the low potential L to the wiring SL, the state of storing data D_11 can be changed to the state of storing data D_00 (work Wr3).

[0228] In addition, Fig. 8A , Fig. 9A , Fig. 9B , Fig. 9C In the examples of voltages, the low potential L, the high potential H, the potential V1 and the potential V2 are 0 V, 10 V, 5 V and 10 V, respectively, but the voltages are not limited thereto.

[0229] Furthermore, in the transistor M1, when charges are stored in the charge accumulation layer, the Id-Vgs curve shifts toward the positive voltage side. That is, when charges are stored in the charge accumulation layer, the voltage required for writing also increases.

[0230] In addition, when the above transistor 500 is used as the transistor M1, for example, the conductive layer 560 can be used as the control gate CG1, and the conductive layer 114 can be used as the control gate CG2. In addition, the area where the conductive layer 560 overlaps with the oxide semiconductor layer 530 is larger than the area where the conductive layer 114 overlaps with the oxide semiconductor layer 530. Therefore, by performing writing using the control gate CG1, the writing efficiency can be improved.

[0231] Therefore, after writing using control gate CG2, when the voltage required for writing becomes higher due to the drift of the Id-Vgs curve, it is preferable to use control gate CG1 with higher writing efficiency for writing. That is, from the perspective of efficiency, it is sometimes preferable to perform work Wr2-1 and work Wr2-2 in this order rather than performing work Wr1-1 and work Wr1-2 in this order.

[0232] <Working Example 2-1 of Semiconductor Device>

[0233] In addition, if Fig. 10A and Fig. 10B and Fig.11A and Fig. 11BAs shown, after the charges are stored in the charge accumulation layer, the voltage applied to the control gate is reduced to such an extent that the stored charges do not disappear, thereby reducing the power consumption of the semiconductor device. In addition, the life of the memory cell 602 can sometimes be extended.

[0234] Fig. 10A A circuit diagram corresponding to the operation of the memory cell 602 is shown. Fig. 10B Shown corresponding to Fig. 10A The timing diagram of the operation is shown.

[0235] [Data D_11]

[0236] and Fig. 10A At the time t0 shown, Fig. 10B The time t30 shown is a state where the data D_11 is stored.

[0237] [Data D_01]

[0238] Then, in Fig. 10B At the time t31 shown in FIG. 1 , the state of storing data D_11 changes to the state of storing data D_01. For the description of the time t30 to the time t31, please refer to the description of Fig. 9A Description of the time from t0 to t1.

[0239] [Data D_00]

[0240] Then, in Fig. 10B At the time t32 shown, by changing the potential supplied to the wiring WL2 from the low potential L to the high potential H, the state of storing the data D_01 can be changed to the state of storing the data D_00. At this time, by changing the potential supplied to the wiring WL1 from the high potential H to the low potential L, the power consumption of the semiconductor device can be reduced. Here, the potential difference between the wiring WL1 and the wiring BL (the difference between the voltage of the low potential L and the voltage of the potential V1) can be a value at which the charge stored in the first charge accumulation layer is not released (not deleted), that is, a value at which the stored data is not rewritten.

[0241] <Working Example 2-2 of Semiconductor Device>

[0242] Fig.11A A circuit diagram corresponding to the operation of the memory cell 602 is shown. Fig. 11B Shown corresponding to Fig.11A The operating timing diagram is shown.

[0243] [Data D_11]

[0244] and Fig. 9B At time t10 shown, Fig. 11B The time t40 shown is a state where the data D_11 is stored.

[0245] [Data D_10]

[0246] Then, in Fig. 11B At the time t41 shown in FIG. 1 , the state of storing data D_11 changes to the state of storing data D_10. For the description of the time t40 to the time t41, please refer to the description of Fig. 9B Description of the time from t10 to t11.

[0247] [Data D_00]

[0248] Then, in Fig. 11B At the time t42 shown, by changing the potential supplied to the wiring WL1 from the low potential L to the high potential H, the state of storing the data D_10 can be changed to the state of storing the data D_00. At this time, by changing the potential supplied to the wiring WL2 from the high potential H to the low potential L, the power consumption of the semiconductor device can be reduced. Here, the potential difference between the wiring WL2 and the wiring BL (the difference between the voltage of the low potential L and the voltage of the potential V1) is a value at which the charge stored in the second charge accumulation layer is not released (not deleted), that is, a value at which the stored data is not rewritten.

[0249] <Working Example 3-1 of Semiconductor Device>

[0250] Fig.12 4 states of the memory cell 602 are shown (states storing data D_11, data D_01, data D_10, and data D_00, respectively). FIG. 13A to FIG. 13C 602. Fig.12 and FIG. 13A to FIG. 13C The operation shown is sometimes called an erasing operation because the charges stored in the charge accumulation layer are released.

[0251] In addition, although the release of electrons is described here, holes may be stored in addition to the release of electrons, or holes may be stored without releasing electrons.

[0252] First, refer to Fig.12 and Fig.13A An example of the operation of the semiconductor device will be described.

[0253] [Data D_00]

[0254] Fig.13A The time t50 shown is the state where data D_00 is stored. FIG. 8A to FIG. 11B The above work can save the data.

[0255] [Work Er1_1: Data D_01]

[0256] Then, in Fig.13A At the time t51 shown, by changing the potential supplied to the wiring WL2 from the high potential H to the low potential L, changing the potential supplied to the wiring BL from the potential V1 to the potential V2, and making the wiring SL in a floating state, the charge of the second charge accumulation layer can be released, and the state of storing the data D_00 can be changed to the state of storing the data D_01 (at the time t52). Fig.12 Storage unit 602 shown in the upper right corner of (working Er1_1).

[0257] [Work Er1_2: Data D_11]

[0258] Then, in Fig.13A At time t52 shown in FIG. 1 , by changing the potential supplied to the wiring WL1 from the high potential H to the low potential L, the charge of the first charge accumulation layer can be released, and the state of storing the data D_01 can be changed to the state of storing the data D_11 (at the time t53). Fig.12 Storage unit 602 shown in the lower right corner) (working Er1_2).

[0259] <Working Example 3-2 of Semiconductor Device>

[0260] Fig.13A In the example shown, the second charge accumulation layer and the first charge accumulation layer are released in this order, but it is also possible to Fig. 13B In the operation shown, charges are released in the order of the first charge accumulation layer and the second charge accumulation layer.

[0261] [Data D_00]

[0262] and Fig.13A At time t50 shown, Fig. 13B The time t60 shown is a state where the data D_00 is stored.

[0263] [Work Er2_1: Data D_10]

[0264] exist Fig. 13B At the time t61 shown, by changing the potential supplied to the wiring WL1 from the high potential H to the low potential L, changing the potential supplied to the wiring BL from the potential V1 to the potential V2, and making the wiring SL in a floating state, the charge of the first charge accumulation layer can be released, and the state of storing the data D_00 can be changed to the state of storing the data D_10 (at the time t62). Fig.12 The storage unit 602 shown in the lower left) (working Er2_1).

[0265] [Work Er2_2: Data D_11]

[0266] Then, in Fig. 13BAt time t62 shown, by changing the potential supplied to the wiring WL2 from high potential H to low potential L, the charge stored in the second charge accumulation layer can be released, and the state storing data D_10 is changed to the state storing data D_11 (operation Er2_2).

[0267] <Working Example 3-3 of Semiconductor Device>

[0268] Fig.13A and Fig. 13B The example of releasing charges from the first charge accumulation layer and the second charge accumulation layer at different operation timings is shown, but it is also possible to Fig. 13C In the operation shown, charges are released from the first charge accumulation layer and the second charge accumulation layer by the same operation.

[0269] [Data D_00]

[0270] and Fig.13A At time t50 shown, Fig. 13C The time t70 shown is a state where the data D_00 is stored.

[0271] [Work Er3: Data D_00]

[0272] exist Fig. 13C At the time t71 shown, by changing the potential supplied to the wiring WL1 and the wiring WL2 from the high potential H to the low potential L, changing the potential supplied to the wiring BL from the potential V1 to the potential V2, and making the wiring SL in a floating state, it is possible to change from the state of storing data D_00 to the state of storing data D_11 (operation Er3).

[0273] <Working Example 4-1 of Semiconductor Device>

[0274] The above description is an example of rewriting the data in the state of the saved data D_00. Fig.14A and Fig. 14B The timing chart shown shows an example of an operation of rewriting data in the state where data D_01 and data D_10 are stored.

[0275] Next, Fig.14A The timing diagram is used to illustrate this.

[0276] [Data D_01]

[0277] At time t80, data D_01 is stored. 8A to 9C The above work can save the data.

[0278] [Data D_11]

[0279] Next, at time t81, by changing the potential supplied to the wiring WL1 from high potential H to low potential L, changing the potential supplied to the wiring BL from potential V1 to potential V2, and making the wiring SL in a floating state, the state storing data D_01 can be changed to the state storing data D_11.

[0280] [Data D_10]

[0281] Next, at time t82, the state of storing data D_11 changes to the state of storing data D_10. For the description of time t81 to time t82, please refer to the description of Fig. 9B Description of the time from t10 to t11.

[0282] <Working Example 4-2 of Semiconductor Device>

[0283] Next, Fig. 14B The timing diagram is used to illustrate this.

[0284] [Data D_10]

[0285] At time t90, data D_10 is stored. 8A to 9C The above work can save the data.

[0286] [Data D_11]

[0287] Next, at time t91, by changing the potential supplied to the wiring WL2 from high potential H to low potential L, changing the potential supplied to the wiring BL from potential V1 to potential V2, and making the wiring SL in a floating state, the state storing data D_10 can be changed to the state storing data D_11.

[0288] [Data D_01]

[0289] Next, at time t92, the state of storing data D_11 changes to the state of storing data D_01. For the description of time t91 to time t92, refer to the description of Fig. 9A Description of the time from t0 to t1.

[0290] <Working Example 5-1 of Semiconductor Device>

[0291] Fig.15 and Fig.16A and Fig. 16C The working example shown is Fig.12 and FIG. 13A to FIG. 13C The main difference is that the potential of the wiring SL is used to change the stored data. By using the wiring SL, the data of the memory cells 602 arranged in the same row can be changed at the same time. Sometimes this work is called a simultaneous erasing work.

[0292] First, refer to Fig.15 and Fig.16A An example of the operation of the semiconductor device will be described.

[0293] [Data D_00]

[0294] Fig.16A The time t100 shown is the state where data D_00 is stored (in Fig.15 The storage unit 602 shown in the upper left of FIG. FIG. 8A to FIG. 11B The above work can save the data.

[0295] [Work Er4_1: Data D_01]

[0296] Then, in Fig.16A At the time t101 shown, by changing the potential supplied to the wiring WL2 from the high potential H to the low potential L, changing the potential supplied to the wiring SL from the low potential L to the high potential H, and making the wiring BL in a floating state, the charge of the second charge accumulation layer can be released, and the state of storing the data D_00 can be changed to the state of storing the data D_01 (at the time t102). Fig.15 The memory cell 602 shown in the upper right of FIG4 (operation Er4_1). Through the above operation, the data of all the memory cells 602 connected to the same wiring WL2 and the same wiring SL can be changed.

[0297] [Work Er4_2: Data D_11]

[0298] Then, in Fig.16A At time t102 shown in FIG. 102 , by changing the potential supplied to the wiring WL1 from the high potential H to the low potential L, the charge of the first charge accumulation layer can be released, and the state of storing the data D_01 can be changed to the state of storing the data D_11 (at Fig.15 The memory cell 602 shown in the lower right of FIG4 (operation Er4_2). By the above operation, the data of all the memory cells 602 connected to the same wiring WL1 and the same wiring SL can be changed.

[0299] <Working Example 5-2 of Semiconductor Device>

[0300] Fig.16A In the example shown, the second charge accumulation layer and the first charge accumulation layer are released in this order, but it is also possible to Fig. 16B In the operation shown, charges are released in the order of the first charge accumulation layer and the second charge accumulation layer.

[0301] [Data D_00]

[0302] and Fig.16A At time t100 shown, Fig. 16BThe time t110 shown is a state where data D_00 is stored.

[0303] [Work Er5_1: Data D_10]

[0304] exist Fig. 16B At the time t111 shown, by changing the potential supplied to the wiring WL1 from the high potential H to the low potential L, changing the potential supplied to the wiring SL from the low potential L to the high potential H, and making the wiring BL in a floating state, the charge of the first charge accumulation layer can be released, and the state of storing the data D_00 can be changed to the state of storing the data D_10 (at the time t112). Fig.15 The memory cell 602 shown in the lower left of FIG5 (operation Er5_1). By the above operation, the data of all the memory cells 602 connected to the same wiring WL1 and the same wiring SL can be changed.

[0305] [Work Er5_2: Data D_11]

[0306] Then, in Fig. 16B At the time t112 shown, by changing the potential supplied to the wiring WL2 from the high potential H to the low potential L, the charge stored in the second charge accumulation layer can be released, and the state of storing data D_10 is changed to the state of storing data D_11 (operation Er5_2). Through the above operation, the data of all the memory cells 602 connected to the same wiring WL2 and the same wiring SL can be changed.

[0307] <Working Example 5-3 of Semiconductor Device>

[0308] Fig.16A and Fig. 16B The example of releasing charges from the first charge accumulation layer and the second charge accumulation layer at different operation timings is shown, but it is also possible to Fig. 16C In the operation shown, charges are released from the first charge accumulation layer and the second charge accumulation layer by the same operation.

[0309] [Data D_00]

[0310] and Fig.16A At time t100 shown, Fig. 16C The time t120 shown is a state where data D_00 is stored.

[0311] [Work Er6: Data D_11]

[0312] exist Fig. 16CAt the time t121 shown, by changing the potential supplied to the wiring WL1 and the wiring WL2 from the high potential H to the low potential L, changing the potential supplied to the wiring SL from the low potential L to the high potential H, and making the wiring BL in a floating state, the state storing the data D_00 can be changed to the state storing the data D_11 (operation Er6). Through the above operations, the data of all the memory cells 602 connected to the same wiring WL1, the same wiring WL2, and the same wiring SL can be changed.

[0313] <Working Example 6-1 of Semiconductor Device>

[0314] In the operation of changing the stored data by using the potential change of the wiring SL, an example of the operation of rewriting the state of the stored data D_00 is described above. Fig.17A and Fig. 17B The timing chart shown shows an example of an operation of rewriting data in the state where data D_01 and data D_10 are stored.

[0315] Next, Fig.17A The timing diagram is used to illustrate this.

[0316] [Data D_01]

[0317] At time t130, data D_01 is stored. Fig. 9C The above work can save the data.

[0318] [Data D_11]

[0319] Next, at time t131, by changing the potential supplied to the wiring WL1 from high potential H to low potential L, changing the potential supplied to the wiring SL from low potential L to high potential H, and making the wiring BL in a floating state, the state storing data D_01 can be changed to the state storing data D_11.

[0320] [Data D_10]

[0321] Next, at time t132, by changing the potential supplied to wiring WL2 from low potential L to high potential H, changing the potential supplied to wiring SL from high potential H to low potential L, and setting the potential supplied to wiring BL to potential V1, the state of storing data D_11 can be changed to the state of storing data D_10.

[0322] <Working Example 6-2 of Semiconductor Device>

[0323] Next, Fig. 17B The timing diagram is used to illustrate this.

[0324] [Data D_10]

[0325] At time t140, data D_10 is stored. Fig. 9C The above work can save the data.

[0326] [Data D_11]

[0327] Next, at time t141, by changing the potential supplied to the wiring WL2 from high potential H to low potential L, changing the potential supplied to the wiring SL from low potential L to high potential H, and making the wiring BL in a floating state, the state storing data D_10 can be changed to the state storing data D_11.

[0328] [Data D_01]

[0329] Next, at time t142, by changing the potential supplied to wiring WL1 from low potential L to high potential H, changing the potential supplied to wiring SL from high potential H to low potential L, and changing the potential supplied to wiring BL to potential V1, the state of storing data D_11 can be changed to the state of storing data D_01.

[0330] <Operation Example of Semiconductor Device: Readout>

[0331] Reference Fig. 17C The timing chart shown in FIG. 1 illustrates an example of the operation of reading data stored in the memory cell 602 .

[0332] First, at time t161 , the low potential L is supplied to the wiring WL1 , the wiring WL2 , the wiring BL, and the wiring SL.

[0333] Next, the stored data is read out by changing the potential of the wiring WL1. The threshold of the transistor M1 included in the memory cell 602 changes according to the stored data. Fig.17D An example of an Id-Vgs curve of transistor M1 is shown (the curve is shown again Figure 8B By changing the read potential (indicated as read potential Vread in the figure), the current flowing through the transistor can be changed. By changing the read potential Vread and reading the current of the transistor, the data stored in the transistor M1 can be identified.

[0334] Hereinafter, an example will be described in which the potential supplied to the wiring WL1 is changed to Vr1 , Vr2 , and Vr3 in sequence as the read potential Vread to perform reading.

[0335] First, at time t162, the potential Vd is supplied to the wiring BL as a predetermined potential. When the potential of the wiring WL1 is changed to the potential Vr1, if the data D_11 is stored in the memory cell 602, current flows between the wiring BL and the wiring SL.

[0336] Next, at time t163 , when the potential of the wiring WL1 is changed to the potential Vr2 , if the data D_10 is stored in the memory cell 602 , current flows between the wiring BL and the wiring SL.

[0337] Next, at time t164, when the potential of the wiring WL1 is changed to the potential Vr3, when the data D_01 is stored in the memory cell 602, current flows between the wiring BL and the wiring SL. Note that when the data D_00 is stored in the memory cell 602, current does not flow between the wiring BL and the wiring SL. In this way, by measuring the current flowing between the wiring BL and the wiring SL, the stored data can be read.

[0338] <Materials Constituting Semiconductor Devices>

[0339] Materials that can be used for the semiconductor device of this embodiment are described below. Note that a layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked-layer structure.

[0340] [Conductive layer]

[0341] As the conductive layer (conductive layer 520, conductive layer 540, conductive layer 560, etc.) included in the semiconductor device, it is preferred to use a metal element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy with the above metal elements as a component, or an alloy combining the above metal elements, etc. In addition, nitrides or oxides of the above metal elements can also be used. In addition, as an alloy with the above metal elements as a component, a nitride of the alloy or an oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, ruthenium nitride, nitride containing molybdenum, nitride containing tungsten, titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Alternatively, a semiconductor having high conductivity, such as polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

[0342] In addition, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing ruthenium, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum, etc., a conductive material containing oxygen, such as ruthenium oxide, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel, and a material containing metal elements such as titanium, tantalum or ruthenium are conductive materials that are not easily oxidized, conductive materials that have the function of inhibiting oxygen diffusion, or materials that absorb oxygen and maintain conductivity, so they are preferred. As a conductive material containing oxygen, indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide added with silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide, etc. can be cited. In this specification, etc., a conductive film deposited using a conductive material containing oxygen is sometimes referred to as an oxide conductive film.

[0343] A conductive material mainly composed of tungsten, copper or aluminum is preferred because of its high conductivity.

[0344] In addition, a plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used.

[0345] In addition, when a metal oxide is used in the channel formation region of a transistor, a stacked structure of a material containing the above-mentioned metal element and a conductive material containing oxygen is preferably used as a conductive layer used as a gate electrode. In this case, the conductive material containing oxygen can be arranged on one side of the channel formation region. By arranging the conductive material containing oxygen on one side of the channel formation region, oxygen separated from the conductive material can be easily supplied to the channel formation region.

[0346] As the conductive material containing a metal element and nitrogen, for example, tantalum nitride, titanium nitride, ruthenium nitride, nitride containing molybdenum, nitride containing tungsten, titanium and aluminum, nitride containing tantalum and aluminum, etc. can be used. In addition, as the conductive material containing a metal element and oxygen, for example, ruthenium oxide, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. can be used.

[0347] In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon may also be used. In addition, indium gallium zinc oxide containing nitrogen may also be used.

[0348] Titanium, tantalum, ruthenium, and materials containing one or more of these metal elements are preferred because they are conductive materials that are not easily oxidized, conductive materials that have the function of suppressing oxygen diffusion, or materials that can maintain conductivity even when absorbing oxygen.

[0349] The conductive layer 520 and the conductive layer 540 are conductive layers in contact with the oxide semiconductor layer, so it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, an oxide conductive material, or a conductive material having a function of inhibiting oxygen diffusion. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer.

[0350] As the conductive material containing oxygen, for example, ITO, ITSO, IZO (registered trademark) or the like is preferably used.

[0351] Note that when the conductive layer 520 has a stacked-layer structure, a conductive material containing nitrogen and a conductive material containing oxygen may be used as an upper conductive layer in contact with the oxide semiconductor layer.

[0352] In addition, when the conductive layer 540 has a stacked structure, for example, the lower layer may use a material having higher conductivity than the upper layer, and the upper layer may use a conductive material containing nitrogen, a conductive material containing oxygen, a conductive material that is not easily oxidized, a conductive material having a function of inhibiting the diffusion of oxygen, or a material that maintains conductivity even when absorbing oxygen, etc.

[0353] Specifically, for example, it is preferred that ruthenium, tungsten, titanium nitride or tantalum nitride be used as the lower layer and ITO or ITSO be used as the upper layer as the conductive layer 540. In this case, ITO or ITSO is in contact with the oxide semiconductor layer. By adopting such a structure, conductivity can be maintained even if the conductive layer is in contact with the oxide semiconductor layer. In addition, by using a material having a higher conductivity than the upper layer as the lower layer, the conductivity of the conductive layer can be improved.

[0354] Note that when the conductive layer has a two-layer stacked structure, a material with high conductivity may be used for the upper layer, and a conductive material containing nitrogen, a conductive material containing oxygen, a conductive material that is not easily oxidized, a conductive material having a function of suppressing the diffusion of oxygen, or a material that maintains conductivity even when absorbing oxygen may be used for the lower layer. In this case, for example, by adopting a structure in which the oxide semiconductor layer is in contact with the top surface of the conductive layer, the contact resistance between the conductive layer and the oxide semiconductor layer can be reduced.

[0355] [Insulation layer]

[0356] As the insulating layer (insulating layer 210, insulating layer 481, insulating layer 482, insulating layer 483, insulating layer 283, insulating layer 285, insulating layer 551, insulating layer 553, etc.) included in the semiconductor device, an inorganic insulating film is preferably used. As the inorganic insulating film, for example, an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film can be cited. As the oxide insulating film, for example, a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminum oxide film can be cited. As the nitride insulating film, for example, a silicon nitride film and an aluminum nitride film can be cited. As the oxynitride insulating film, for example, an oxynitride silicon film, an oxynitride aluminum film, an oxynitride gallium film, an oxynitride yttrium film, and an oxynitride hafnium film can be cited. Examples of the oxynitride insulating film include a silicon oxynitride film and an aluminum oxynitride film. Alternatively, an organic insulating film may be used as an insulating layer included in a semiconductor device.

[0357] In addition, by surrounding a transistor using a metal oxide with an insulating layer having a function of suppressing the transmission of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulating layer having a function of suppressing the transmission of impurities and oxygen, for example, a single layer or a stack of insulating layers containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium and tantalum can be used. Specifically, as a material for an insulating layer having a function of suppressing the transmission of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0358] Specifically, it is preferable to use an insulating layer that blocks impurities such as water and hydrogen, and oxygen.

[0359] In this specification, etc., a barrier insulating layer refers to an insulating layer having barrier properties. In addition, barrier properties refer to properties that a corresponding substance does not diffuse easily, properties that a corresponding substance does not permeate easily, properties that a corresponding substance has low permeability, functions to inhibit diffusion of a corresponding substance, or functions to inhibit permeation of a corresponding substance. In addition, hydrogen, which is recorded as a corresponding substance, refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH. - In addition, unless otherwise specified, the impurity recorded as the corresponding substance refers to an impurity in the channel formation region or in the semiconductor layer, for example, at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, oxygen recorded as the corresponding substance refers to at least one of oxygen atoms, oxygen molecules, etc.

[0360] As the insulating layer having the function of inhibiting the permeation of impurities such as water and hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide can be cited. For example, an oxide containing aluminum and hafnium (hafnium aluminate) can be cited. In addition, for example, nitrides such as aluminum nitride, silicon oxynitride and silicon nitride can be cited.

[0361] In addition, an insulating layer such as a gate insulating layer in contact with the oxide semiconductor layer or an insulating layer provided near the oxide semiconductor layer preferably has a region containing oxygen (hereinafter sometimes referred to as excess oxygen) released by heating. For example, by making the insulating layer having a region containing excess oxygen contact the oxide semiconductor layer or be located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. As an insulating layer that easily forms a region containing excess oxygen, silicon oxide, silicon oxynitride, or silicon oxide with vacancies can be cited.

[0362] For example, as the miniaturization and high integration of transistors progress, problems such as leakage current sometimes occur due to the thin filming of the gate insulating layer. By using a material with a high relative dielectric constant (high-k) for the gate insulating layer, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT: Equivalent Oxide Thickness) of the gate insulating layer can be reduced. In addition, by using a material with a high relative dielectric constant for the dielectric layer of the capacitor, a component with a larger capacitance value can be achieved. On the other hand, by using a material with a low relative dielectric constant for the insulating layer used as an interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, the material can be selected according to the function of the insulating layer. In addition, a material with a low relative dielectric constant is also a material with a high dielectric strength.

[0363] Examples of materials having a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0364] As materials with low relative dielectric constant, for example, resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate and acrylic resin can be cited. In addition, as inorganic insulating materials with low relative dielectric constant other than the above, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen can be cited. In addition, silicon oxide with holes can be cited. In addition, these silicon oxides can also contain nitrogen.

[0365] For example, inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide can be used for both layers such as gate insulating layers to which materials with high relative dielectric constants are applied and layers such as interlayer films to which materials with low relative dielectric constants are applied. These materials have relatively low relative dielectric constants compared to high-k materials such as hafnium oxide, and therefore are sometimes described as materials with low relative dielectric constants in this specification and the like.

[0366] In addition, a material having ferroelectricity may be used as an insulating layer included in a semiconductor device. Examples of the material having ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and other metal oxides. In addition, as a material that can have ferroelectricity, a material obtained by adding an element J1 to hafnium oxide (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) can be cited. Here, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be appropriately set. For example, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, a material obtained by adding an element J2 to zirconium oxide (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) can be cited. In addition, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be appropriately set. For example, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectric properties, piezoelectric ceramics with a perovskite structure, such as lead titanate (PbTiOX), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, can also be used.

[0367] In addition, as a material that can have ferroelectricity, a metal nitride containing an element M1, an element M2 and nitrogen can be cited. Here, the element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the atomic number ratio of the element M1 to the element M2 can be appropriately set. In addition, a metal oxide containing the element M1 and nitrogen sometimes has ferroelectricity even if it does not contain the element M2. In addition, as a material that can have ferroelectricity, a material in which the element M3 is added to the above-mentioned metal nitride can be cited. Note that the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. In addition, the atomic number ratio of the element M1, the element M2 and the element M3 can be appropriately set.

[0368] In addition, as materials that can have ferroelectricity, there can be mentioned perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 of κ-type alumina.

[0369] Note that the materials described above that can have ferroelectricity include metal oxides and metal nitrides, but are not limited thereto. For example, metal oxynitrides obtained by adding nitrogen to the above metal oxides or metal nitride oxides obtained by adding oxygen to the above metal nitrides may also be used.

[0370] In addition, as a material that can have ferroelectricity, for example, a mixture or compound composed of a plurality of materials selected from the above materials can be used. In addition, the insulating layer can have a stacked structure composed of a plurality of materials selected from the above materials. Note that the crystal structure (properties) of the materials listed above may change not only depending on the deposition conditions but also depending on various processes, and thus in this specification, etc., a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material that can have ferroelectricity.

[0371] Even when the metal oxide containing one or both of hafnium and zirconium is processed into a thin film of several nm, it can have ferroelectricity. In addition, even when the area of ​​the metal oxide containing one or both of hafnium and zirconium is small, it can have ferroelectricity. Therefore, by using the metal oxide containing one or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0372] In this specification, etc., a material that can have ferroelectricity formed in a layer is sometimes referred to as a ferroelectric layer. In addition, in this specification, etc., a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0373] In addition, ferroelectricity is considered to be exhibited because oxygen or nitrogen of the crystals contained in the ferroelectric layer is displaced by the action of an external electric field. In addition, the exhibiting of ferroelectricity is presumed to depend on the structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer to exhibit ferroelectricity, the insulating layer needs to contain crystals. In particular, the insulating layer preferably has crystals with an orthorhombic crystal structure, thereby exhibiting ferroelectricity. The crystal structure of the crystals contained in the insulating layer is any one or more selected from the group consisting of an isometric system, a tetragonal system, an orthorhombic system, a monoclinic system and a hexagonal system. In addition, the insulating layer may also have an amorphous structure. At this time, the insulating layer may also have a composite structure of an amorphous structure and a crystal structure.

[0374] In the insulating layer of one embodiment of the present invention, the concentration of impurities such as water and hydrogen is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer.

[0375] The insulating layer 481, the insulating layer 482, and the insulating layer 483 preferably include a hydrogen barrier insulating layer. The insulating layer 481, the insulating layer 482, and the insulating layer 483 are provided so as to surround the oxide semiconductor layer. The insulating layer 481, the insulating layer 482, and the insulating layer 483 provided outside the oxide semiconductor layer have hydrogen barrier properties, so that hydrogen diffusion into the oxide semiconductor layer can be suppressed. For example, the insulating layer 481, the insulating layer 482, and the insulating layer 483 are preferably made of a silicon nitride film.

[0376] In addition, silicon nitride has an oxygen barrier property. Therefore, by using silicon nitride for the insulating layer 481, the insulating layer 482, and the insulating layer 483, formation of excessive oxygen vacancies in the oxide semiconductor layer due to oxygen desorption from the oxide semiconductor layer can be suppressed.

[0377] In addition, by using silicon nitride for the insulating layers 481, 482, and 483, excessive oxygen can be prevented from being supplied to the oxide semiconductor layer. Therefore, excessive oxygen in a channel formation region of the oxide semiconductor layer can be prevented, so that reliability of the transistor can be improved.

[0378] Note that the insulating layer 481 , the insulating layer 482 , and the insulating layer 483 preferably include the above-described oxide insulating film, the oxynitride insulating film, or an insulating layer having a region containing excess oxygen.

[0379] Note that the concentration of impurities such as water and hydrogen in the insulating layer 481, the insulating layer 482, and the insulating layer 483 is preferably reduced. Thus, mixing of impurities such as water and hydrogen into a channel formation region of the oxide semiconductor layer can be suppressed.

[0380] The insulating layer 481 , the insulating layer 482 , and the insulating layer 483 may have a stacked-layer structure.

[0381] For example, the insulating layer may have a three-layer stacked structure in which the second insulating layer is sandwiched between the first insulating layer and the third insulating layer. Note that a structure that does not include either the first insulating layer or the third insulating layer may also be employed.

[0382] The second insulating layer preferably has a region containing more oxygen than at least one of the first insulating layer and the third insulating layer. By increasing the oxygen content of the second insulating layer, an i-type region is easily formed in the oxide semiconductor layer near the second insulating layer.

[0383] As the second insulating layer, it is more preferable to use a film that releases oxygen by heating. Oxygen is released from the insulating layer due to heat applied in the manufacturing process of the transistor, so that oxygen can be supplied to the oxide semiconductor layer. By supplying oxygen to the oxide semiconductor layer, especially to the channel formation region of the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer and V OH, a transistor with good electrical characteristics and high reliability can be realized.

[0384] In addition, in the insulating layer 481 and the insulating layer 483, the oxygen content in the region in contact with the source region and the drain region of the oxide semiconductor layer 530 is preferably low. Since the oxygen content is low, the amount of oxygen supplied to the oxide semiconductor layer is reduced, and the resistance of the oxide semiconductor layer can be easily reduced. Therefore, among the first insulating layer and the third insulating layer sandwiching the second insulating layer, the oxygen content of the insulating layer on the side in contact with the conductive layer 520 and the insulating layer on the side in contact with the conductive layer 540 is preferably lower than that of the second insulating layer.

[0385] In addition, as the second insulating layer, it is preferable to use a material with a low relative dielectric constant. This can reduce the parasitic capacitance generated between wirings. For example, silicon oxide or silicon oxynitride can be used.

[0386] As the first insulating layer and the third insulating layer, an oxygen blocking insulating layer is preferably used. Thus, oxidation of the conductive layer 520 and the conductive layer 114 can be suppressed, and the resistance of the conductive layer increases.

[0387] By using an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer and the third insulating layer, the diffusion of hydrogen in the oxide semiconductor layer can be suppressed, and hydrogen contained in the oxide semiconductor layer can be captured or fixed. For example, magnesium oxide, aluminum oxide, hafnium oxide, or an oxide containing hafnium and silicon can be used. In addition, for example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide can also be used.

[0388] [Insulating layer 551, insulating layer 553, insulating layer 554, insulating layer 556, charge accumulation layer 552, charge accumulation layer 555]

[0389] The above-described materials can be used as appropriate for the insulating layer 551 , the insulating layer 553 , the insulating layer 554 , and the insulating layer 556 .

[0390] When writing to the transistor 500, it is not preferable that charges are trapped in the following regions other than the charge accumulation layer, specifically, for example, in the films of the insulating layer 551, the insulating layer 553, the insulating layer 554, and the insulating layer 556, at the interface between the insulating layer 551 and the semiconductor layer, at the interface between the insulating layer 554 and the semiconductor layer, etc. This is because, due to the capture of charges in such regions, the captured charges cannot be released at a desired voltage, resulting in an increase in power consumption required for the operation of the memory element, the captured charges are easily released due to leakage current, etc., and information cannot be retained, or the reliability of the transistor 500 is reduced due to the capture of charges.

[0391] From the above viewpoints, the insulating layer 551, the insulating layer 553, the insulating layer 554, and the insulating layer 556 are preferably films having fewer defects that may cause leakage current or charge trapping. In particular, the insulating layer 551 having a thin thickness is preferably one with fewer defects.

[0392] Note that as the insulating layer 551 and the insulating layer 554 , silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, or the like is preferably used.

[0393] The thickness of the insulating layer 551 and the insulating layer 554 can be, for example, greater than or equal to 1 nm and less than or equal to 20 nm.

[0394] When a highly conductive material is used as the charge accumulation layer 552, the thickness of the insulating layer 551 can be, for example, 5 nm to 20 nm, more preferably 6 nm to 15 nm. In addition, when a highly insulating material is used as the charge accumulation layer 552, the thickness of the insulating layer 551 can be, for example, 1 nm to 6 nm, more preferably 1.5 nm to 4.5 nm.

[0395] When a highly conductive material is used as the charge accumulation layer 555, the thickness of the insulating layer 554 can be, for example, 5 nm to 20 nm, more preferably 6 nm to 15 nm. In addition, when a highly insulating material is used as the charge accumulation layer 555, the thickness of the insulating layer 554 can be, for example, 1 nm to 6 nm, more preferably 1.5 nm to 4.5 nm.

[0396] For example, the thickness of the insulating layer 553 is preferably thicker than the thickness of the insulating layer 551. Furthermore, for example, the thickness of the insulating layer 556 is preferably thicker than the thickness of the insulating layer 554.

[0397] The thickness of the insulating layer 553 and the insulating layer 556 can be, for example, greater than or equal to 8 nm and less than or equal to 30 nm.

[0398] The materials exemplified as the above insulating layers can be used for the insulating layer 553 and the insulating layer 556. Alternatively, a stacked layer of a plurality of materials may be used. For example, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or the like is preferably used for the insulating layer 553.

[0399] As the charge accumulation layer 552 and the charge accumulation layer 555, a material with high conductivity can be used. For example, the materials exemplified as the above-mentioned conductive layer can be appropriately used. Specifically, for example, one or more metal elements selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, or an alloy with the above-mentioned metal elements as a component or an alloy combining the above-mentioned metal elements can be used. In addition, nitrides or oxides of the above-mentioned metal elements can be used. In addition, as alloys with the above-mentioned metal elements as components, nitrides of the alloys or oxides of the alloys can also be used.

[0400] Alternatively, a semiconductor material such as silicon or germanium can be used for the charge accumulating layer 552 and the charge accumulating layer 555. When a semiconductor material is used, for example, a layer whose resistance is reduced by implantation of impurities can be used.

[0401] In addition, a material with high insulation properties can be used as the charge accumulation layer 552 and the charge accumulation layer 555. For example, the materials exemplified as the above-mentioned insulating layer can be used for the insulating layer containing charge traps. Specifically, for example, silicon nitride, silicon oxynitride, etc. can be used. In addition, a layer in which conductive nanodots are dispersed in an insulating layer can also be used.

[0402] By having an amorphous structure in the insulating layer, the formation of grain boundaries in the layer can be suppressed. By suppressing the formation of grain boundaries, the flatness of the insulating layer can be improved. As a result, the thickness distribution of the insulating layer becomes uniform, and the extremely thin portion can be reduced, thereby improving the withstand voltage of the insulating layer. In addition, the thickness distribution of the film provided on the insulating layer can be made uniform. In addition, by suppressing the formation of grain boundaries in the insulating layer, the leakage current caused by the defect state of the grain boundaries can be reduced. As a result, the insulating layer can be used as an insulating film with less leakage current. Therefore, the insulating layer used for the insulating layer 551, the insulating layer 553, etc., for example, preferably has an amorphous structure.

[0403] The gate insulating layer of the transistor has the function of trapping and fixing hydrogen, which can reduce the V in the channel formation region. O H, and the channel formation region can be made i-type or substantially i-type.

[0404] In addition, when the gate insulating layer of the transistor includes the hydrogen blocking insulating layer, diffusion of hydrogen into the oxide semiconductor layer can be suppressed.

[0405] Furthermore, by including a thermally stable insulating layer such as silicon oxide or silicon oxynitride in the gate insulating layer of the transistor, the characteristics of the transistor can be stabilized.

[0406] In addition, by using the oxygen blocking insulating layer as the gate insulating layer of the transistor, it is possible to suppress diffusion of oxygen in the oxide semiconductor layer into the surrounding layers to form oxygen vacancies in the oxide semiconductor layer.

[0407] [Substrate]

[0408] As a substrate for forming a transistor, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, etc. can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. can be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, etc. can also be cited. As a conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can be cited. In addition, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, etc. can also be cited. Alternatively, a substrate having elements provided on these substrates can also be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0409] <Oxide Semiconductor Layer>

[0410] In the transistor 500, a metal oxide serving as a semiconductor is preferably contained in the oxide semiconductor layer 530 having a channel formation region. That is, the transistor 500 is preferably an OS transistor.

[0411] In addition, transistors using other semiconductor materials in the channel formation region may also be used in the semiconductor device of this embodiment. As the other semiconductor material, for example, a semiconductor composed of a single element or a compound semiconductor may be cited. As a semiconductor composed of a single element, for example, silicon or germanium may be cited. As a compound semiconductor, for example, gallium arsenide and silicon germanium may be cited. In addition, as a compound semiconductor, for example, an organic semiconductor and a nitride semiconductor may be cited. The above-mentioned oxide semiconductor is also a type of compound semiconductor. These semiconductor materials may also contain impurities as dopants.

[0412] Examples of silicon that can be used as a semiconductor material for transistors include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon).

[0413] In addition, the semiconductor layer of the transistor may also include a layered material used as a semiconductor. Layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals bonding forces that are weaker than covalent bonds and ionic bonds. The layered material has high conductivity in a unit layer, that is, has high two-dimensional conductivity. By using a material used as a semiconductor and having high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0414] As the above-mentioned layered material, for example, graphene, silicene, chalcogenides, etc. can be cited. Chalcogenides are compounds containing oxygen group elements (belonging to group 16 elements). In addition, as chalcogenides, transition metal chalcogenides, group 13 chalcogenides, etc. can be cited. As transition metal chalcogenides that can be used for the semiconductor layer of the transistor, specifically, molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited.

[0415] Next, oxide semiconductor layers that can be used as the oxide semiconductor layer 530 are described.

[0416] As the oxide semiconductor layer 530 , the oxide semiconductor layer 30 described in the following embodiment can be used.

[0417] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. As the structure of the crystalline metal oxide, for example, a CAAC (c-axis aligned crystal) structure, a polycrystalline (Poly-crystal) structure, and a microcrystalline (nc: nano-crystal) structure can be cited. By using a crystalline metal oxide for the oxide semiconductor layer, the defect state density in the oxide semiconductor layer can be reduced. Therefore, the reliability of the transistor using the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of the semiconductor device equipped with the transistor can be improved.

[0418] The oxide semiconductor layer of one embodiment of the present invention particularly preferably contains a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of crystallites (typically, a plurality of crystallites having a hexagonal crystal structure) have a c-axis orientation and the plurality of crystallites are connected without orientation on the ab plane. When a cross-section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM: Transmission Electron Microscope) image, it can be confirmed that the metal atoms are arranged in layers in the crystal part. Therefore, it can also be said that the oxide semiconductor layer having a CAAC structure has a layered crystal part. In the cross-section of the oxide semiconductor layer observed using a TEM image, metal atoms arranged in layers can be observed as bright spots.

[0419] The CAAC structure is formed, for example, in a manner such that the c-axis is perpendicular or approximately perpendicular to the formed surface. In the CAAC structure, metal atoms are arranged in layers in a direction parallel or approximately parallel to the formed surface. In the region having the CAAC structure, the angle formed by the c-axis and the formed surface is preferably within 90°±20° (above 70° and below 110°), more preferably within 90°±15° (above 75° and below 105°), further preferably within 90°±10° (above 80° and below 100°), and further preferably within 90°±5° (above 85° and below 95°).

[0420] The polycrystalline structure has a grain boundary. In addition, when a heat treatment is performed after the oxide semiconductor layer of the polycrystalline structure is formed, a tiny gap (also called nanocrack or microcrack) or a tiny space (also called nanospace or microspace) may be formed between the crystal parts. If a tiny gap or a tiny space is formed in the oxide semiconductor layer, the resistance of the oxide semiconductor layer becomes higher. This is because the resistance of the tiny gap or the tiny space is very high, for example, the resistance is infinite. When an oxide semiconductor layer with a tiny gap or a tiny space is used in the channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of the source electrode and the drain electrode becomes higher. Therefore, this will have a negative impact on the initial characteristics or reliability of the transistor. The CAAC structure does not observe a clear grain boundary on the ab plane, so a semiconductor device with high reliability can be realized. In addition, since there are few grain boundaries, the barrier to carrier conduction in the channel of the transistor is small, and an increase in the on-state current can be expected.

[0421] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED), or a combination of a plurality of the above methods.

[0422] When electron diffraction is performed on an oxide semiconductor layer having a CAAC structure, spots (bright spots) indicating c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to the normal vector of the formed surface of the oxide semiconductor layer or the normal vector of the surface of the oxide semiconductor layer.

[0423] Furthermore, an FFT pattern obtained by performing a fast Fourier transform (FFT) process on a TEM image reflects the same reciprocal spatial information as the electron diffraction pattern.

[0424] By obtaining a cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure and performing FFT processing on each region in the cross-sectional TEM image to produce an FFT pattern, the crystal axis direction of each region can be calculated based on the produced FFT pattern. Specifically, in the spots observed in the produced FFT pattern, the direction of the line segment connecting two spots with high brightness and approximately equal distances from the center is the crystal axis direction. The angle of the direction of the crystal axis of each region calculated from the FFT pattern relative to the formed surface is preferably 70° or more and 110° or less (within 90°±20°), more preferably 75° or more and 105° or less (within 90°±15°), more preferably 80° or more and 100° or less (within 90°±10°), and further preferably 85° or more and 95° or less (within 90°±5°) The region is regarded as a CAAC structure.

[0425] When the oxide semiconductor layer having the CAAC structure is observed from a direction perpendicular to the formed surface using a TEM image, a triangular or hexagonal atomic arrangement is observed on the ab plane and has crystallinity. In addition, in the Voronoi map produced by image analysis of the TEM image of the oxide semiconductor layer having the CAAC structure observed from a direction perpendicular to the formed surface, pentagonal, hexagonal and heptagonal Voronoi regions are mainly observed, and hexagonal Voronoi regions are typically observed. For example, in the Voronoi region observed in the Voronoi map, the proportion of hexagonal Voronoi regions is greater than 30% and less than 100%.

[0426] The following is a method for making a Voronoi diagram. First, when performing image analysis on a TEM image, after FFT processing, only a certain range of information is left through filtering, and a fast Fourier inverse transform is performed to make an FFT filtered image. Lattice points are extracted from the produced FFT filtered image to make perpendicular bisectors of line segments connecting adjacent lattice points. The point where three perpendicular bisectors intersect is a Voronoi point, and the polygonal area surrounded by the line segments connecting the Voronoi points is a Voronoi area. In this way, a Voronoi diagram can be made.

[0427] Note that, as an example of the observation range of the TEM when preparing the Voronoi plot, a rectangular region with a vertical side length of 50 nm and a horizontal side length of 50 nm may be observed. Note that the observation range is not limited to this.

[0428] In addition, when the distribution of the direction of the hexagonal lattice was analyzed using the lattice points extracted by image analysis of the planar TEM image, it was observed that the difference in the direction of the hexagonal lattice was small at the boundary of the two structures with different directions of the hexagonal lattice, the boundary was blurred, and the two structures were connected in a mutually entangled manner. In other words, no clear boundary was observed in the CAAC structure.

[0429] Note that the direction of the hexagonal lattice can be calculated from the direction of a hexagon formed by the six lattice points closest to each lattice point.

[0430] There is no particular restriction on the crystallinity of the semiconductor material included in the oxide semiconductor layer. For example, the oxide semiconductor layer sometimes includes one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a partially crystalline region). When the oxide semiconductor layer has crystallinity, the degradation of transistor characteristics can sometimes be suppressed.

[0431] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as the main component. Here, the metal oxide may contain indium as the main component, and may further contain element M. In addition, the metal oxide preferably contains two or three selected from indium, element M and zinc, and particularly preferably contains indium and zinc as the main components. Here, the metal oxide may contain indium and zinc as the main components, and may further contain element M. Note that element M is a metal element or a semi-metal element with a high bond energy with oxygen, for example, a metal element or a semi-metal element with a higher bond energy with oxygen than indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains any one or more selected from indium, gallium and zinc. In this specification, etc., metal elements and semi-metal elements are sometimes collectively referred to as "metal elements", and the "metal elements" described in this specification, etc. sometimes include semi-metal elements.

[0432] In the cross section of the oxide semiconductor layer observed using the TEM image, it is confirmed that the metal atoms are arranged in layers in a direction parallel or approximately parallel to the formed surface. The metal atoms are observed as bright spots in the TEM image. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. In addition, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0433] As a metal oxide according to one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide (also referred to as ITSO) containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be cited. In addition, as a metal oxide according to one embodiment of the present invention, indium oxide can be used. In addition, as a metal oxide according to one embodiment of the present invention, gallium oxide, zinc oxide, etc. can be used.

[0434] When the ratio of the number of indium atoms to the total number of atoms of all metal elements in the metal oxide is increased, the transistor can obtain a large on-state current and a high frequency characteristic.

[0435] Note that the metal oxide may also contain one or more metal elements with a large periodic number in the periodic table instead of indium. Alternatively, the metal oxide may also contain one or more metal elements with a large periodic number in the periodic table in addition to indium. There is a tendency that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large periodic number in the periodic table, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large periodic number in the periodic table, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0436] In addition, the metal oxide may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field effect mobility of the transistor may sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0437] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the metal oxide can be made highly crystalline, thereby suppressing the diffusion of impurities in the metal oxide. This can suppress the variation of the electrical characteristics of the transistor and improve reliability.

[0438] In addition, by increasing the atomic number ratio of the element M relative to the total atomic number of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers due to oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0439] In this embodiment, In—Ga—Zn oxide is sometimes described as an example of a metal oxide.

[0440] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using two deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using a first deposition method and a second deposition method. The oxide semiconductor layer formed using two deposition methods can also be referred to as Hybrid OS.

[0441] The oxide semiconductor layer of one embodiment of the present invention has crystallinity. In addition, the oxide semiconductor layer of one embodiment of the present invention preferably has a CAAC structure.

[0442] In the manufacture of the oxide semiconductor layer of one embodiment of the present invention, a metal oxide having crystallinity is deposited using a first deposition method. The metal oxide deposited at this time preferably has a CAAC structure. For example, a metal oxide film deposited using a sputtering method tends to have crystallinity.

[0443] When the metal oxide is formed using the first deposition method, a mixed layer is sometimes formed at the interface between the metal oxide and the layer as the formed surface. For example, when the sputtering method is used as the first deposition method, the mixed layer is sometimes formed due to particles released from a target material or the like (also referred to as sputtered particles) or energy supplied to the substrate side by sputtered particles or the like. The mixed layer may block the crystallization of the metal oxide.

[0444] For example, when an insulating layer containing silicon, such as silicon oxide, is used as a formation surface, when a metal oxide is formed on the silicon oxide using the first deposition method, silicon may be mixed into the metal oxide. The impurities such as silicon mixed into the metal oxide may block the crystallization of the metal oxide.

[0445] Therefore, in one embodiment of the present invention, before forming the metal oxide using the first deposition method, the metal oxide is formed using the second deposition method. That is, after forming the metal oxide as the first layer using the second deposition method, the metal oxide is formed as the second layer on the first layer using the first deposition method. At this time, as the second deposition method, it is preferred to use a deposition method that causes less damage to the formed surface than the first deposition method. By using a deposition method that causes less damage to the formed surface as the second deposition method, it is possible to suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer that is the formed surface of the oxide semiconductor layer. In addition, in the second layer, the mixing of impurities such as silicon can be suppressed, so it is possible to further improve the crystallinity. For example, compared with the sputtering method, the atomic layer deposition (ALD: Atomic Layer Deposition) method and the chemical vapor deposition (CVD: Chemical Vapor Deposition) method can suppress damage to the formed surface, so it is suitable as the second deposition method.

[0446] In addition, as the first layer, for example, a metal oxide having a microcrystalline structure or an amorphous structure whose crystallinity is lower than that of the CAAC structure is sometimes formed. By forming a second layer with high crystallinity on the first layer with low crystallinity or performing a heat treatment after forming the second layer, the crystallinity of the first layer is sometimes improved with the second layer as the core. As a result, the crystallinity of the entire oxide semiconductor layer including the vicinity of the interface with the formed surface can sometimes be improved.

[0447] In the oxide semiconductor layer of one embodiment of the present invention, it is preferred that the metal oxide is first formed on the surface to be formed by using the second deposition method, and then the metal oxide is formed thereon by using the first deposition method.

[0448] Examples of the first deposition method include a sputtering method and a pulsed laser deposition (PLD: Pulsed Laser Deposition) method.

[0449] As the second deposition method, for example, ALD method, plasma CVD (PECVD: Plasma EnhancedCVD) method, thermal CVD (TCVD: Thermal CVD) method, photo CVD (Photo CVD) method, metal organic CVD (MOCVD: MetalOrganic CVD) method, molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, etc. can be cited. The MBE method is a deposition method for growing a thin film having a crystal structure reflecting the crystal system of the substrate, and can be said to be one of the deposition methods with less damage to the formed surface. In addition, as the second deposition method, a wet method can be used. The wet method is one of the deposition methods with less damage to the formed surface. As a wet method, for example, a spray coating method can be cited.

[0450] As an example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer using a second deposition method and then forming a metal oxide as a second layer using a first deposition method. Specifically, the ALD method can be used as the second deposition method, and the sputtering method can be used as the first deposition method. In addition, the metal oxide formed using the first deposition method preferably has a CAAC structure.

[0451] In addition, a third layer may also be formed on the second layer. Since the second layer has high crystallinity, the third layer can be crystallized with the crystals of the second layer as nuclei or seeds. Therefore, even if a deposition method that is easy to have crystallinity is not used as a deposition method for the third layer, the third layer can be crystallized. Here, for example, by using a deposition method with higher coverage than the second layer as a deposition method for the third layer, the entire oxide semiconductor layer can have both high crystallinity and high coverage. In addition, for example, by using a deposition method that causes less damage than the second layer as a deposition method for the third layer, damage to the second layer can be reduced, so that the entire oxide semiconductor layer can have high crystallinity.

[0452] Furthermore, by providing the first layer to reduce the influence of the formed surface, the crystallinity of the second layer is improved, thereby obtaining extremely excellent crystallinity. Therefore, it can be expected that the third layer crystallized with the second layer as a core or seed will also form a layer with extremely excellent crystallinity.

[0453] In addition, the third layer is the uppermost layer of the oxide semiconductor layer. When the oxide semiconductor layer is used as a semiconductor layer of a transistor described later, the third layer is, for example, a layer in contact with a gate insulating layer. By improving the crystallinity of the layer in contact with the gate insulating layer, the carrier mobility when the transistor is in an on state can be improved.

[0454] As an example, an oxide semiconductor layer of one embodiment of the present invention can be manufactured by the following steps: after forming a metal oxide as a first layer using a second deposition method, forming a metal oxide as a second layer using a first deposition method, and forming a metal oxide as a third layer using a second deposition method. Specifically, the ALD method can be used as the second deposition method, and the sputtering method can be used as the first deposition method. In addition, the metal oxide formed using the first deposition method preferably has a CAAC structure. The ALD method is a deposition method having higher coverage than the sputtering method. By using the ALD method as the deposition method for the first layer and the third layer, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be used to well cover steps and openings with high aspect ratios.

[0455] As a sputtering method, there can be cited an RF sputtering method in which a high-frequency power supply is used as a power supply for sputtering, a DC sputtering method using a direct current power supply, and a pulsed DC sputtering method in which the voltage applied to the electrode is changed in a pulsed manner. In addition, there is an RF superposition DC sputtering method in which RF and DC are superimposed. In the deposition using an insulating target material, the RF sputtering method is preferably used. The DC sputtering method is mainly used when a conductive target material is used for deposition. In addition, a conductive film can be formed during the DC sputtering method, and an insulating film can be formed when a reactive sputtering using a pulsed DC sputtering method is performed. Specifically, the pulsed DC sputtering method can be used when compounds such as oxides, nitrides, and carbides are deposited using a reactive sputtering method. The RF superposition DC sputtering method can control the ion energy during deposition and the potential on one side of the target material. Therefore, compared with the RF sputtering method, the damage caused by the deposition can be reduced. In addition, a film of good quality can be obtained.

[0456] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant react using only thermal energy and a plasma ALD (PEALD: Plasma Enhanced ALD) method using a reactant excited by plasma.

[0457] The ALD method can deposit atoms layer by layer, and thus has the following effects: it can deposit very thin films; it can deposit on structures with high aspect ratios or surfaces with large steps; it can deposit in a manner with few defects such as pinholes; it can deposit with high coverage; it can deposit at low temperatures, etc. In addition, in the PEALD method, deposition can be performed at a lower temperature by using plasma, so it is sometimes preferred. In addition, the precursor used in the ALD method sometimes contains elements such as carbon or chlorine. Therefore, the film set using the ALD method sometimes contains more elements such as carbon or chlorine than the film set using other deposition methods. In addition, the quantification of these elements can be performed using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy) or SIMS. Note that the deposition method of the metal oxide as one embodiment of the present invention uses the ALD method, but due to the use of one or both of the conditions of high substrate temperature during deposition and impurity removal treatment, the amount of carbon and chlorine contained in the film is sometimes less than when the ALD method is used without the above conditions.

[0458] Unlike a deposition method in which particles released from a target material are deposited, the ALD method is a deposition method in which a film is formed by a reaction on the surface of the object being processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object being processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for forming a film that covers the surface of an opening with a high aspect ratio.

[0459] By using the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since no plasma is used, the thermal CVD method is a deposition method that can reduce plasma damage to the object being processed. In addition, in the thermal CVD method, no plasma damage is generated during deposition, so a film with fewer defects can be obtained.

[0460] In addition, when the CVD method is used, a film of any composition can be deposited by adjusting the flow ratio of the source gas. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of the source gas while performing deposition. When deposition is performed while changing the flow ratio of the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where formation is performed using a plurality of deposition chambers. Therefore, the productivity of the semiconductor device can sometimes be improved.

[0461] [Method for producing oxide semiconductor layer]

[0462] The oxide semiconductor layer 30 can be manufactured, for example, by the following method: an oxide semiconductor layer 30a is formed on the layer 229 as the formed surface using the ALD method, an oxide semiconductor layer 30b is formed on the oxide semiconductor layer 30a using the sputtering method, and an oxide semiconductor layer 30c is formed on the oxide semiconductor layer 30b using the ALD method. Furthermore, after the oxide semiconductor layer 30 is formed, heat treatment is preferably performed. By performing heat treatment, the crystallinity of the oxide semiconductor layer 30 can be improved. Here, the heat treatment is not limited to heat treatment. For example, it can also be heat applied in the manufacturing process. Layer 229 is an insulating film, for example, an insulating film of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, etc. In addition, as layer 229, a film of an insulator included in the semiconductor device described later can be used.

[0463] Alternatively, the layer 229 may be a conductive film. For example, the oxide semiconductor layer 30 may be formed over a conductive film that serves as an electrode of a semiconductor device.

[0464] The layer 229 may not have crystallinity. In other words, the layer 229 may have an amorphous structure. In addition, when the layer 229 has crystallinity, it may have a crystal structure with low lattice matching with the metal oxide included in the oxide semiconductor layer 30 .

[0465] Reference FIG. 22A to FIG. 23D An example of a method for manufacturing the oxide semiconductor layer 30 is described.

[0466] First, an oxide semiconductor layer 30a ( Fig.22A Next, an oxide semiconductor layer 30b is formed on the oxide semiconductor layer 30a ( Fig. 22B ).

[0467] The oxide semiconductor layer 30 b is preferably formed by sputtering. In addition, the oxide semiconductor layer 30 b preferably has a composition suitable for forming a CAAC structure.

[0468] It is preferable to form the oxide semiconductor layer 30a by a deposition method that causes less damage to the surface to be formed than by a deposition method for the oxide semiconductor layer 30b. Here, the oxide semiconductor layer 30a is formed by an ALD method.

[0469] In the case of depositing a metal oxide film using a sputtering method, alloying of the components contained in the metal oxide film and the components contained in the layer of the formed surface sometimes occurs due to damage to the formed surface. In the case of alloying, it is difficult to improve the crystallinity of the alloyed region even when performing the heat treatment described later. In addition, there is the following concern: by using an oxide semiconductor layer having an alloyed region for a transistor, a negative impact is brought to the initial characteristics or reliability of the transistor. Therefore, it is preferred to suppress the alloying of the components contained in the metal oxide film and the components contained in the layer as the formed surface.

[0470] In the method for manufacturing an oxide semiconductor layer of one embodiment of the present invention, an oxide semiconductor layer 30a is formed on the layer 229, and then an oxide semiconductor layer 30b is formed by a sputtering method. At this time, the oxide semiconductor layer 30a is preferably formed by a deposition method that causes little damage to the formed surface. By forming the oxide semiconductor layer 30a between the oxide semiconductor layer 30b and the layer 229 using a deposition method that causes little damage to the formed surface, alloying of the components contained in the oxide semiconductor layer 30 and the components contained in the layer 229 can be suppressed, thereby further improving the crystallinity of the oxide semiconductor layer 30.

[0471] By adopting the above structure, the thickness of the alloyed region can be reduced or reduced to the extent that the alloyed region cannot be observed. For example, the thickness of the alloyed region can be greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, more preferably greater than 0 nm and less than 1 nm, and further preferably greater than 0 nm and less than 0.3 nm. In addition, Fig.22A and Fig. 22B An example is shown in which no alloyed region is formed between the layer 229 and the oxide semiconductor layer 30 a .

[0472] In addition, the thickness of the alloyed region can be calculated by performing a line analysis of the composition of the region and its periphery using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0473] For example, the EDX line analysis is performed on the above-mentioned region and its periphery with the direction perpendicular to the formed surface of the oxide semiconductor layer 30a as the depth direction. Then, in the distribution of the quantitative values ​​of each element relative to the depth direction obtained by the analysis, the depth at which the quantitative value of the metal (In when the oxide semiconductor layer 30a contains In) which is the main component of the oxide semiconductor layer 30a but not the main component of the layer as the formed surface (here, layer 229) reaches half value is defined as the depth (position) of the interface between the above-mentioned region and the oxide semiconductor layer 30a. In addition, the depth at which the quantitative value of the element (e.g., Si) which is the main component of the layer as the formed surface but not the main component of the oxide semiconductor layer 30a reaches half value is defined as the depth (position) of the interface between the above-mentioned region and the layer as the formed surface. Through the above steps, the thickness of the alloyed region can be calculated.

[0474] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed using EDX analysis, for example, its thickness is greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, more preferably greater than 0 nm and less than 1 nm, and further preferably greater than 0 nm and less than 0.3 nm.

[0475] For example, when a silicon oxide layer is used as the layer 229 and the oxide semiconductor layer 30 formed on the layer 229 is subjected to SIMS analysis, the depth at which the concentration of silicon reaches 50% of the maximum concentration in the layer 229 is defined as the interface, and the depth at which the silicon concentration decreases to 1.0×10 21 atoms / cm 3 , preferably 5.0×10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm 3 The distance between the depth of and the interface is thickness t_s2. Thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0476] By setting the thickness t_s2 to a value within the above range, the thickness of the alloyed region can be reduced, so that the thickness t_s2 can be set to a value within the above range.

[0477] In addition, by reducing the alloying area, a CAAC structure can be formed near the formed surface. Here, near the formed surface refers to, for example, a region greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, and more preferably greater than 1 nm and less than 2 nm in a substantially vertical direction from the formed surface of the oxide semiconductor layer 30.

[0478] Note that a CAAC structure may be observed near the formed surface by TEM observation. For example, when a cross section of the oxide semiconductor layer 30 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface may be observed near the formed surface.

[0479] Alternatively, a diagram showing the crystal orientation can sometimes be used to evaluate the CAAC structure near the formed surface. For example, a cross-sectional TEM image is obtained, and each region in the cross-sectional TEM image is subjected to FFT processing to produce an FFT pattern, and the crystal axis direction of each region is calculated, so that a diagram showing the crystal orientation can be obtained. The FFT pattern reflects the same reciprocal spatial information as the electron diffraction pattern. For example, the angle of the calculated crystal axis direction of each region relative to the formed surface is preferably 70° or more and 110° or less (within 90°±20°), more preferably 75° or more and 105° or less (within 90°±15°), more preferably 80° or more and 100° or less (within 90°±10°), and further preferably 85° or more and 95° or less (within 90°±5°) The region is regarded as a CAAC structure.

[0480] In addition, when the oxide semiconductor layer 30a is formed by the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure whose crystallinity is lower than that of the CAAC structure may be formed. Fig.22A In the manufacturing stage shown, the oxide semiconductor layer 30 a sometimes includes a region whose crystallinity is lower than that of the oxide semiconductor layer 30 b .

[0481] Here, a method of forming an In-M-Zn oxide by using the ALD method as the oxide semiconductor layer 30a is described. In addition, the details of forming a metal oxide by using the ALD method will be described later.

[0482] First, a source gas including a precursor containing indium is introduced into the chamber to be adsorbed onto the surface of the layer 229. Here, the substrate heating temperature is preferably a temperature corresponding to the decomposition temperature of the precursor.

[0483] Next, the introduction of the source gas is stopped, the chamber is purged, and the remaining precursors and reaction products are discharged from the chamber. Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than indium are separated while indium is adsorbed on the substrate, thereby forming a layer formed by bonding indium and oxygen. As the oxidant, ozone, oxygen, water, etc. can be used. Next, the introduction of the oxidant is stopped, the chamber is purged, and the remaining reactants and reaction products are discharged from the chamber.

[0484] Next, a source gas including a precursor containing the element M is introduced into the chamber and adsorbed onto the layer formed by bonding indium and oxygen. Here, the substrate heating temperature is preferably a temperature corresponding to the decomposition temperature of the precursor.

[0485] Next, the introduction of the source gas is stopped, the chamber is purged, and the remaining precursors and reaction products are exhausted from the chamber. Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than the element M are desorbed while the element M is adsorbed on the substrate, thereby forming a layer in which the element M and oxygen are bonded. Next, the introduction of the oxidant is stopped, the chamber is purged, and the remaining reactants and reaction products are exhausted from the chamber.

[0486] Next, a source gas including a precursor containing zinc is introduced into the chamber so as to be adsorbed to the layer formed by bonding the element M and oxygen. Here, the substrate heating temperature is preferably a temperature corresponding to the decomposition temperature of the precursor.

[0487] Here, in a thermal ALD method using triethylindium as a precursor containing indium, triethylgallium as a precursor containing gallium, and diethylzinc as a precursor containing zinc, for example, the substrate heating temperature is 100°C to 350°C, preferably 150°C to 300°C.

[0488] Next, the introduction of source gas is stopped, the chamber is purged, and the remaining precursors and reaction products are discharged from the chamber. Next, an oxidant is introduced into the chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than zinc are desorbed while zinc is adsorbed on the substrate, thereby forming a layer formed by bonding zinc and oxygen. Next, the introduction of the oxidant is stopped, the chamber is purged, and the remaining reactants and reaction products are discharged from the chamber.

[0489] Next, a layer formed by bonding indium and oxygen is formed again on the layer formed by bonding zinc and oxygen by the above method. By repeating the above method, an In-M-Zn oxide can be formed as the oxide semiconductor layer 30a on the layer 229 by the ALD method.

[0490] The ALD method can control the composition of the obtained film according to the amount of source gas introduced. For example, when the ALD method is used, a film of any composition can be deposited by adjusting the amount of source gas introduced, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse time). In addition, for example, when the ALD method is used, a film whose composition changes continuously can be deposited by changing the source gas while performing deposition. When deposition is performed while changing the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0491] After the oxide semiconductor layer 30 a is formed by the ALD method, an In—M—Zn oxide is formed as the oxide semiconductor layer 30 b on the oxide semiconductor layer 30 a by the sputtering method.

[0492] Here, when the oxide semiconductor layer 30b is formed by sputtering, the mixed layer 231 is formed on the surface or near the surface of the oxide semiconductor layer 30a. In addition, due to sputtered particles or energy supplied to the substrate side by the sputtered particles when the oxide semiconductor layer 30b is formed, a tiny crystal region may be formed in the mixed layer 231. In the subsequent heat treatment process, at least a part of the oxide semiconductor layer 30a may be crystallized using the mixed layer 231 or the tiny crystal region formed in the mixed layer 231 as a nucleus.

[0493] As a target material for the sputtering method, In-M-Zn oxide can be used. For example, when a metal oxide is formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the deposited oxide film can be increased.

[0494] In some cases, a metal oxide with higher crystallinity can be formed as the flow rate ratio of the oxygen gas to the entire deposition gas used in the formation (hereinafter also referred to as the oxygen flow rate ratio) is higher.

[0495] In the case of forming a metal oxide by sputtering, an oxygen-excess metal oxide can sometimes be formed by depositing under the condition that the proportion of oxygen contained in the sputtering gas is higher than 30% and lower than 100%, preferably higher than 70% and lower than 100%. A transistor using an oxygen-excess oxide semiconductor layer in a channel formation region can obtain higher reliability. Note that one embodiment of the present invention is not limited to this. An oxygen-deficient metal oxide is formed by depositing under the condition that the proportion of oxygen contained in the sputtering gas is higher than 1% and lower than 30%, preferably higher than 5% and lower than 20%. A transistor using an oxygen-deficient metal oxide in a channel formation region can have a higher field effect mobility.

[0496] When the metal oxide is formed by sputtering, the composition of the metal oxide after formation may be different from that of the sputtering target. In particular, the zinc content of the metal oxide after formation may be reduced to about 50% of the zinc content in the sputtering target.

[0497] When the oxide semiconductor layer 30b is deposited by sputtering, the substrate is preferably heated. When a metal oxide is formed, a metal oxide with high crystallinity can sometimes be formed by increasing the substrate temperature (stage temperature) when the metal oxide is formed. When the oxide semiconductor layer 30b is deposited by sputtering, the substrate heating temperature is preferably, for example, 100°C or more and 400°C or less, and more preferably 200°C or more and 300°C or less.

[0498] Through the above process, Fig. 22B As shown, an oxide semiconductor layer 30 a and an oxide semiconductor layer 30 b on the oxide semiconductor layer 30 a may be formed on the layer 229 .

[0499] Next, an oxide semiconductor layer 30c is formed on the oxide semiconductor layer 30b ( Fig. 22C Here, the oxide semiconductor layer 30c is formed by the ALD method. The formation method of the oxide semiconductor layer 30a can be referred to for the formation of the oxide semiconductor layer 30c by the ALD method.

[0500] When the oxide semiconductor layer 30c having a CAAC structure and having lower crystallinity than that of the CAAC structure is formed by the ALD method on the oxide semiconductor layer 30b having the CAAC structure, the oxide semiconductor layer 30c is sometimes epitaxially grown with the oxide semiconductor layer 30b as a core. Therefore, when the oxide semiconductor layer 30c is formed, the oxide semiconductor layer 30c sometimes includes the region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed in the entire oxide semiconductor layer 30c.

[0501] Next, a heat treatment step may be performed.

[0502] The heat treatment temperature can be, for example, above 100°C and below 800°C, preferably above 250°C and below 650°C, and more preferably above 350°C and below 550°C. Typically, it can be 400°C±25°C (above 375°C and below 425°C). In addition, the treatment time can be below 10 hours, above 1 minute and below 5 hours, or above 1 minute and below 2 hours. In addition, when using an RTA (Rapid Thermal Anneal) device, the treatment time can be, for example, above 1 second and below 5 minutes. Through this heat treatment, it can be expected that the voids in the atomic-level crystalline portion of the CAAC structure of the oxide semiconductor layer 30b are repaired by the oxide semiconductor layer 30c (in other words, each crystalline molecule formed using the ALD method).

[0503] There is no particular limitation on the heating device used for heat treatment, and there may be a device that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device may be used. The LRTA device is a device that heats the object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment.

[0504] Through this heat treatment process, the crystallinity of the region having the CAAC structure in the oxide semiconductor layer 30c is sometimes improved. In addition, after deposition using the ALD method, when the region is formed only below the oxide semiconductor layer 30c, the region sometimes expands upward due to the heat treatment process ( Fig.22D ) That is, by performing this heat treatment, a region having a CAAC structure may be formed in the entire oxide semiconductor layer 30c.

[0505] In addition, by this heat treatment step, the oxide semiconductor layer 30 b may be further repaired by the oxide semiconductor layer 30 c (in other words, each crystal molecule formed by the ALD method) filling the gaps between the atomic-level crystal parts of the CAAC structure of the oxide semiconductor layer 30 b.

[0506] In addition, it is preferred that at least a portion of the oxide semiconductor layer 30a is converted into CAAC by the heat treatment step ( Fig.22D ). It can be expected that CAAC formation is easily caused by using the mixed layer 231 formed in the oxide semiconductor layer 30a when the oxide semiconductor layer 30b is deposited as a core or a seed. The CAAC formation region in the oxide semiconductor layer 30a is preferably large, preferably reaching the vicinity of the layer 229.

[0507] In addition, since CAAC is formed from the upper part to the lower part of the oxide semiconductor layer 30a, it is possible to reach the vicinity of the layer 229 without being limited by the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the oxide semiconductor layer 30a with high crystallinity can be formed. Therefore, the method for manufacturing an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where the layer to be formed has an amorphous structure.

[0508] FIG. 22A to FIG. 22D : is a cross-sectional view illustrating a method for depositing a metal oxide according to one embodiment of the present invention. FIG. 22A to FIG. 22D It can also be regarded as a schematic diagram showing a film formation model of a metal oxide according to one embodiment of the present invention. FIG. 22A to FIG. 22D As shown, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c respectively use the oxide semiconductor layer 30b with high crystallinity as a core or a seed to improve crystallinity. Specifically, the crystallinity of the oxide semiconductor layer 30a is sometimes improved by heat treatment when the oxide semiconductor layer 30b is deposited or after the oxide semiconductor layer 30c is deposited. In addition, the crystallinity of the oxide semiconductor layer 30c is sometimes improved by heat treatment when the oxide semiconductor layer 30c is deposited or after the oxide semiconductor layer 30c is deposited. In addition, the above-mentioned heat treatment plays an auxiliary role in improving crystallinity.

[0509] Thus, in a metal oxide deposition method of one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (here, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c) can be improved by using the highly crystalline oxide semiconductor layer 30b (i.e., CAAC) as a core or seed. Thus, the crystallinity of the entire oxide semiconductor can be improved. In other words, the upper and lower oxide semiconductors are solid-phase grown using the oxide semiconductor layer 30b as a core or seed, thereby forming an oxide semiconductor with high crystallinity. The oxide semiconductor formed using the above-mentioned deposition method, in this CAAC film, can be referred to as axial growth (Axial Growth) CAAC (AG CAAC).

[0510] In the entire oxide semiconductor layer 30 including the oxide semiconductor layer 30 a and the oxide semiconductor layer 30 c , a region having a CAAC structure preferably exists widely throughout the entire layer. Fig.23A The oxide semiconductor layer 30a, the oxide semiconductor layer 30b, and the oxide semiconductor layer 30c are all shown to be crystallized. The crystals in the region having the CAAC structure in the oxide semiconductor layer 30a are connected to the crystals in the region having the CAAC structure in the oxide semiconductor layer 30b. The crystals in the region having the CAAC structure in the oxide semiconductor layer 30c are connected to the crystals in the region having the CAAC structure in the oxide semiconductor layer 30b. As a result, sometimes the boundary between the oxide semiconductor layer 30a and the oxide semiconductor layer 30b is not observed. In addition, sometimes the boundary between the oxide semiconductor layer 30b and the oxide semiconductor layer 30c is not observed. Sometimes the oxide semiconductor layer 30 can be described as a layer in which no clear interface is observed. Sometimes the oxide semiconductor layer 30 can be described as a single layer.

[0511] In the region having the CAAC structure in each of the oxide semiconductor layer 30a, the oxide semiconductor layer 30b, and the oxide semiconductor layer 30c, bright spots arranged in a direction parallel to the formed surface are confirmed in cross-sectional observation using, for example, a high-resolution TEM. In addition, the c-axis of the CAAC structure of each of the oxide semiconductor layer 30a, the oxide semiconductor layer 30b, and the oxide semiconductor layer 30c is preferably substantially parallel to the normal direction of the formed surface of the oxide semiconductor layer.

[0512] In addition, a part of the oxide semiconductor layer 30 a or the oxide semiconductor layer 30 c may not be crystallized. Fig. 23B As an example, a case is described in which the oxide semiconductor layer 30 a is not crystallized in the vicinity of the interface with the layer 229 . Fig.23C This shows a case where the oxide semiconductor layer 30 c is not crystallized near the surface. Fig.23D This shows a case where the vicinity of the interface between the oxide semiconductor layer 30 a and the layer 229 and the vicinity of the surface of the oxide semiconductor layer 30 c are not crystallized.

[0513] By improving the crystallinity of the oxide semiconductor layer, the resistance increase of the semiconductor layer of the transistor using the oxide semiconductor layer is suppressed or the initial characteristics of the transistor (especially the on-state current) are improved, thereby realizing a transistor suitable for high-speed driving. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0514] According to the method for manufacturing an oxide semiconductor layer of one embodiment of the present invention, the crystallinity of metal oxides located above and below the metal oxide having the CAAC structure can be improved, so that the entire oxide semiconductor layer has high crystallinity.

[0515] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity as a whole. Therefore, in the oxide semiconductor layer 30, the boundaries between the stacked films in the oxide semiconductor layer 30a, the oxide semiconductor layer 30b, and the oxide semiconductor layer 30c are sometimes not confirmed. In particular, after heat treatment, it is sometimes difficult to confirm the boundaries between the stacked films. For example, the presence or absence of the boundaries between the stacked films can be confirmed using cross-sectional TEM, cross-sectional STEM, etc.

[0516] As described above, by using a metal oxide with a high In content ratio for a transistor, the field effect mobility of the transistor can be improved. On the other hand, an oxide semiconductor with a high In content ratio has a tendency to polycrystallize. When a metal oxide with a polycrystalline structure is used for a transistor, it has a negative impact on the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content ratio for one or both of the oxide semiconductor layer 30a and the oxide semiconductor layer 30c, a crystal reflecting the orientation of the crystal contained in the oxide semiconductor layer 30b is formed, thereby suppressing polycrystallization.

[0517] In addition, the lattice mismatch between the crystals included in the oxide semiconductor layer 30b and the crystals included in the oxide semiconductor layer 30a or the oxide semiconductor layer 30c is preferably small. Thus, the oxide semiconductor layer 30a or the oxide semiconductor layer 30c can form a crystal that reflects the orientation of the crystals included in the oxide semiconductor layer 30b. At this time, for example, when the oxide semiconductor layer 30 is observed in cross section using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface are confirmed in the oxide semiconductor layer 30a or the oxide semiconductor layer 30c.

[0518] As long as the lattice mismatch between the crystals included in the oxide semiconductor layer 30b and the crystals included in the oxide semiconductor layer 30a or the oxide semiconductor layer 30c is small, there is no particular limitation on the crystal structure of the oxide semiconductor layer 30a or the oxide semiconductor layer 30c. The crystal structure of the oxide semiconductor layer 30a or the oxide semiconductor layer 30c may be any one of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.

[0519] [Composition of Oxide Semiconductor Layer]

[0520] The composition of the oxide semiconductor layer 30a is preferably different from the composition of the oxide semiconductor layer 30b. In addition, the composition of the oxide semiconductor layer 30c is preferably different from the composition of the oxide semiconductor layer 30b. In addition, the oxide semiconductor layer 30a can use the same composition as the oxide semiconductor layer 30c. Alternatively, the composition of the oxide semiconductor layer 30a can also be different from the composition of the oxide semiconductor layer 30c.

[0521] As described above, the composition of the oxide semiconductor layer 30b is preferably suitable for forming a CAAC structure. The oxide semiconductor layer 30b can be formed using a sputtering method, for example. The oxide semiconductor layer 30b preferably contains zinc, for example. By containing zinc, a metal oxide with high crystallinity can be obtained. In addition, the oxide semiconductor layer 30b preferably contains element M in addition to zinc. By making the oxide semiconductor layer 30b contain element M, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of the transistor using the oxide semiconductor layer can be improved. As the oxide semiconductor layer 30b, specifically, a metal oxide having the following composition can be used: In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, or In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto. In addition, the nearby composition includes a range of ±30% of the desired atomic ratio. As the element M, one or more of gallium, aluminum, and tin are preferably used.

[0522] The oxide semiconductor layer 30b may not contain the element M. For example, In-Zn oxide may also be used. Specifically, it may be a composition of In:Zn=1:1 [atomic ratio] or a composition near it, a composition of In:Zn=2:1 [atomic ratio] or a composition near it, or a composition of In:Zn=4:1 [atomic ratio] or a composition near it. Alternatively, indium oxide may also be used. In addition, a trace amount of element M may also be contained. For example, it may be a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition near it, or a composition of In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition near it. In addition, for example, it may be a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition near it, or a composition of In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition near it.

[0523] The oxide semiconductor layer 30a and the oxide semiconductor layer 30c can use a metal oxide with a high In ratio. The oxide semiconductor layer 30a and the oxide semiconductor layer 30c can be formed, for example, using an ALD method. In addition, it is particularly preferred to use a metal oxide with a higher In ratio than the element M. By using a metal oxide with a high In ratio, when the oxide semiconductor layer is used for a transistor, the on-state current can be increased and the frequency characteristics can be improved.

[0524] In addition, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c may not contain the element M. For example, In-Zn oxide may also be used. Specifically, it may be a composition of In:Zn=1:1 [atomic ratio] or a composition close thereto, In:Zn=2:1 [atomic ratio] or a composition close thereto, or In:Zn=4:1 [atomic ratio] or a composition close thereto. Alternatively, indium oxide may also be used. In addition, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c may also contain a trace amount of the element M. Specifically, it may be a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition close thereto, In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition close thereto, In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition close thereto, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition close thereto.

[0525] Alternatively, the oxide semiconductor layer 30 a and the oxide semiconductor layer 30 c may use a metal oxide having a higher In content than that of the oxide semiconductor layer 30 b .

[0526] For example, as the oxide semiconductor layer 30a and the oxide semiconductor layer 30c, a metal oxide having a higher Ga ratio than the oxide semiconductor layer 30b may be used. For example, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c preferably use a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereof, a metal oxide having a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition thereof, or a metal oxide having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition thereof. By increasing the Ga ratio, for example, the band gaps of the oxide semiconductor layer 30a and the oxide semiconductor layer 30c can sometimes be made larger than the oxide semiconductor layer 30b. As a result, the oxide semiconductor layer 30b is sandwiched by the oxide semiconductor layer 30a and the oxide semiconductor layer 30c having a large band gap, and the oxide semiconductor layer 30b is mainly used as a current path (channel). By sandwiching the oxide semiconductor layer 30b by the oxide semiconductor layer 30a and the oxide semiconductor layer 30c, the trap energy levels at the interface of the oxide semiconductor layer 30b and its vicinity can be reduced. Thus, a buried channel transistor with a channel away from the insulating layer interface can be realized, thereby improving the field effect mobility. In addition, the influence of the interface energy level formed on the back channel side is reduced, and the light degradation of the transistor (for example, light negative bias degradation) can be suppressed, thereby improving the reliability of the transistor.

[0527] Alternatively, one of the oxide semiconductor layer 30 a and the oxide semiconductor layer 30 c may include a metal oxide having a higher In ratio than that of the oxide semiconductor layer 30 b , and the other may include a metal oxide having a higher Ga ratio than that of the oxide semiconductor layer 30 b .

[0528] Alternatively, a plurality of layers having the above composition may be stacked in the oxide semiconductor layer 30a, the oxide semiconductor layer 30b, and the oxide semiconductor layer 30c. For example, the oxide semiconductor layer 30c may have a structure in which a metal oxide having a high In content is stacked on a metal oxide having a high Ga content.

[0529] In addition, in the oxide semiconductor layer of one embodiment of the present invention, even if the oxide semiconductor layer 30a and the oxide semiconductor layer 30c have a composition that does not easily form a CAAC structure when formed as a single layer, the entire oxide semiconductor layer including the oxide semiconductor layer 30a and the oxide semiconductor layer 30c can have a CAAC structure by causing crystal growth using the oxide semiconductor layer 30b as a core. Alternatively, the region including at least a portion of each of the oxide semiconductor layer 30a and the oxide semiconductor layer 30c to the region of the oxide semiconductor layer 30b can have a CAAC structure.

[0530] In particular, when the oxide semiconductor layer 30a and the oxide semiconductor layer 30c have a composition with a high ratio of In, the crystallinity of the semiconductor layer suitable for the transistor can also be obtained. In the oxide semiconductor layer of one embodiment of the present invention, the reliability can be improved by adopting a CAAC structure with high crystallinity while increasing the ratio of In to improve the turn-on characteristics of the transistor.

[0531] Alternatively, the oxide semiconductor layer 30 a and the oxide semiconductor layer 30 c may use a metal oxide having the same composition as that of the oxide semiconductor layer 30 b . Using the same composition may facilitate CAAC formation after heat treatment.

[0532] In addition, compared with an oxide semiconductor layer with a CAAC structure formed using one deposition method, any one or more of the relative dielectric constant, film density, and film hardness of the oxide semiconductor layer with a CAAC structure formed using the above-mentioned two deposition methods is sometimes higher.

[0533] By using an oxide semiconductor layer having a CAAC structure formed using the two deposition methods described above for the channel formation region of a transistor, a transistor having excellent characteristics (for example, a transistor with a large on-state current, a transistor with a high field effect mobility, a transistor with a small S value, a transistor with a high frequency characteristic (also called f characteristic) , a transistor with high reliability, etc.) can be realized.

[0534] The composition of the metal oxide used for the oxide semiconductor layer 30 can be analyzed using, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry). Alternatively, a combination of multiple of the above methods can be used for analysis. Note that elements with low content ratios are sometimes affected by the accuracy of analysis, and the actual content ratio is different from the content ratio obtained by analysis. For example, when the content ratio of element M is low, the content ratio of element M obtained by analysis is sometimes lower than the actual content ratio.

[0535] The oxide semiconductor layer according to one embodiment of the present invention includes a metal oxide.

[0536] Metal oxides sometimes have lattice defects. Lattice defects refer to point defects such as atomic vacancies and foreign atoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. In addition, the main causes of lattice defects include differences in the number ratio of atoms of constituent elements (excess or deficiency of constituent atoms) and impurities.

[0537] When a metal oxide is used for a semiconductor layer of a transistor, lattice defects in the metal oxide may lead to generation or capture of carriers, etc. Therefore, when a metal oxide with many lattice defects is used for a semiconductor layer of a transistor, the electrical characteristics of the transistor may be unstable. Therefore, it is preferred that the metal oxide used for the semiconductor layer of the transistor has fewer lattice defects.

[0538] The type of lattice defects that are likely to exist in the metal oxide and the amount of the lattice defects that exist vary depending on the structure of the metal oxide, the method of depositing the metal oxide, and the like.

[0539] Therefore, it is preferred to use a metal oxide with high crystallinity for the semiconductor layer of the transistor. For example, it is preferred to use a metal oxide with a CAAC structure or a metal oxide with a single crystal structure. By using the metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a transistor with high reliability can be realized.

[0540] In addition, the channel formation region of the transistor preferably uses a metal oxide that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, it is preferred to increase the mobility of the metal oxide used for the transistor. In order to increase the mobility of the metal oxide, it is necessary to increase the transmission of carriers (electrons in the case of n-channel transistors) or reduce the scattering factors that affect the transmission of carriers. In addition, carriers flow from the source to the drain through the channel formation region. Therefore, by setting a channel formation region where carriers easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0541] [Impurities in oxide semiconductors]

[0542] Here, the influence of each impurity in the oxide semiconductor is described.

[0543] In the channel formation region of a transistor using an oxide semiconductor as a semiconductor layer, it is preferred that the channel formation region has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source region and the drain region. O ) and impurities, the electrical properties are easily changed and reliability may be reduced. In addition, hydrogen near the oxygen vacancy forms V O H may generate electrons that become carriers. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor has a normally-on characteristic. Therefore, in the channel formation region, V O H is also preferably reduced. Thus, the channel formation region of the transistor is a high resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0544] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. As impurities, hydrogen, carbon, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to elements other than the main components of oxide semiconductors. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity.

[0545] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, a defect state is formed in the oxide semiconductor. Thus, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS was set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 the following.

[0546] In addition, when the oxide semiconductor contains nitrogen, electrons as carriers are generated, which increases the carrier concentration and is easily converted to n-type. As a result, transistors using oxide semiconductors containing nitrogen as semiconductors tend to have normally-on characteristics. Alternatively, when the oxide semiconductor contains nitrogen, trap states are sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0547] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, so oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferred to reduce the hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , and more preferably less than 5×10 18 atoms / cm 3 , and further preferably less than 1×10 18 atoms / cm 3 , and further preferably less than 1×10 17 atoms / cm 3 .

[0548] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to generate carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0549] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0550] The carrier concentration of the oxide semiconductor in the region serving as the channel formation region is preferably 1×10 18 cm -3 Below, more preferably below 1×10 17 cm -3 , and more preferably less than 1×10 16 cm -3 , and more preferably less than 1×10 13 cm -3 , more preferably less than 1×10 12 cm -3Note that the lower limit of the carrier concentration of the oxide semiconductor in the region serving as the channel formation region is not particularly limited, and can be set to 1×10 -9 cm -3 .

[0551] [c-axis orientation]

[0552] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. For example, the crystal orientation can be used to evaluate the crystallinity of the oxide semiconductor layer of one embodiment of the present invention.

[0553] By performing FFT processing on the TEM image, the crystal orientation can be obtained from the FFT pattern. Specifically, the crystal axis direction can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects the same reciprocal spatial information as the electron diffraction pattern.

[0554] By performing FFT processing on each region in the TEM image of the oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation of each region within a certain area, a graph showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of the region having the layered crystal part. The crystal axis direction of the region can be obtained from the angle of the line segment connecting the two spots.

[0555] By calculating the proportion of the c-axis oriented region in the diagram showing the crystal orientation, the c-axis orientation degree can be calculated. Here, the c-axis oriented region refers to a region whose orientation is consistent with the c-axis, and the difference between the c-axis and the c-axis is preferably within 20°, more preferably within 15°, further preferably within 10°, and further preferably within 5°. Here, the angle of the c-axis is the angle relative to the formed surface.

[0556] In the oxide semiconductor layer of one embodiment of the present invention, for example, a cross-sectional or planar TEM observation of the oxide semiconductor layer can be performed, and the c-axis orientation degree can be calculated using the above-mentioned diagram showing the crystal orientation. In addition, the region where FFT is performed (also referred to as the FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0557] When analyzing using a cross-sectional TEM image, for example, the observation range of the cross-sectional TEM image may be set to a region having a vertical direction perpendicular to the formed surface and a width of 100 nm in the horizontal direction. Note that the observation range is not limited to this.

[0558] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, further preferably 80% or more, further preferably 90% or more, further preferably 95% or more. Here, the c-axis orientation is preferably calculated as the proportion of the region within 20° of the c-axis difference, for example.

[0559] In addition, the c-axis orientation degrees of the region deposited as the oxide semiconductor layer 30a, the region deposited as the oxide semiconductor layer 30b, and the region deposited as the oxide semiconductor layer 30c are Rc1, Rc2, and Rc3, respectively. Rc2 is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, further preferably 80% or more, further preferably 90% or more, further preferably 95% or more. In addition, Rc3 is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, further preferably 80% or more, further preferably 90% or more, further preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. In addition, Rc2 / Rc1 is preferably greater than 1. Here, the c-axis orientation degree is preferably calculated, for example, as the proportion of the region whose difference from the c-axis is within 20°.

[0560] Sometimes, after the oxide semiconductor layer 30 is manufactured, the boundaries among the oxide semiconductor layers 30 a , 30 b , and 30 c are not observed.

[0561] The oxide semiconductor layer 30 of one embodiment of the present invention can be divided into three regions, namely, a first region, a second region, and a third region in order from the layer 229 side. Each region is a layered region.

[0562] The first region, the second region and the third region all have a CAAC structure. In addition, the c-axis orientation of the third region is preferably higher than that of the first region. In addition, the c-axis orientation of the second region is preferably higher than that of the first region. In addition, the c-axis orientation of the third region is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, further preferably 80% or more, further preferably 90% or more, further preferably 95% or more. In addition, the c-axis orientation of the second region is preferably 50% or more, more preferably 60% or more, further preferably 70% or more, further preferably 80% or more, further preferably 90% or more, further preferably 95% or more. Here, the c-axis orientation is preferably calculated, for example, as the proportion of the region whose difference with the c-axis is within 20°.

[0563] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor layer 30 .

[0564] Alternatively, the thickness of the layer in each region is, for example, substantially equal.

[0565] <Example 1 of Method for Manufacturing Semiconductor Device>

[0566] Reference FIG. 18A to FIG. 20C A method for manufacturing a semiconductor device will be described. Note that regarding the materials and formation methods of each component, the same parts as those already described may be omitted.

[0567] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed by sputtering, CVD, vacuum deposition, PLD, ALD, or the like.

[0568] As a sputtering method, there can be cited an RF sputtering method in which a high-frequency power supply is used as a power supply for sputtering, a DC sputtering method using a direct current power supply, and a pulsed DC sputtering method in which the voltage applied to the electrode is changed in a pulsed manner. In addition, there is an RF superposition DC sputtering method in which RF and DC are superimposed. In the deposition using an insulating target material, the RF sputtering method is preferably used. The DC sputtering method is mainly used when a conductive target material is used for deposition. In addition, a conductive film can be formed during the DC sputtering method, and an insulating film can be formed when a reactive sputtering using a pulsed DC sputtering method is performed. Specifically, the pulsed DC sputtering method can be used when compounds such as oxides, nitrides, and carbides are deposited using a reactive sputtering method. The RF superposition DC sputtering method can control the ion energy during deposition and the potential on one side of the target material. Therefore, compared with the RF sputtering method, the damage caused by the deposition can be reduced. In addition, a film of good quality can be obtained.

[0569] As the sputtering method, for example, an ionized sputtering method, a long-throw sputtering method, etc. can be used. The ionized sputtering method is a method in which sputtered particles generated from a target material are ionized by RF or the like, and deposition is performed anisotropically by self-bias or the like. In addition, in the long-throw sputtering method, anisotropic deposition can be performed by increasing the distance between the sputtering target material and the substrate.

[0570] Note that the CVD method can be classified into PECVD method, thermal CVD method using heat, photoCVD method using light, etc. Furthermore, it can be classified into metal CVD (MCVD: Metal CVD) method and organic metal CVD method according to the source gas used.

[0571] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used, the thermal CVD method is a deposition method that can reduce plasma damage to the object being processed. For example, the wiring, electrodes, components (transistors, capacitors, etc.) included in the semiconductor device sometimes generate charge accumulation due to receiving charges from plasma. At this time, the wiring, electrodes, components, etc. included in the semiconductor device are sometimes damaged due to the stored charge. On the other hand, since the above-mentioned plasma damage does not occur in the case of the thermal CVD method without using plasma, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage during deposition is not generated, so a film with fewer defects can be obtained.

[0572] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD (Plasma Enhanced ALD) method using a reactant excited by plasma, and the like are used.

[0573] The ALD method can deposit atoms of each layer, thereby producing effects such as being able to deposit extremely thin films, being able to deposit structures with high aspect ratios, being able to deposit in a manner with fewer defects such as pinholes, being able to deposit with excellent coverage, and being able to deposit at low temperatures. In addition, in the PEALD method, deposition can be performed at lower temperatures by utilizing plasma, so it is sometimes preferred. In addition, the precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, a film set using the ALD method sometimes contains more impurities such as carbon than a film set using other deposition methods. In addition, quantification of impurities can be performed using XPS or SIMS. Note that the ALD method is used as a deposition method for metal oxides as one embodiment of the present invention, but due to the use of one or both of the conditions of a high substrate temperature during deposition and the impurity removal process, the amount of carbon and chlorine contained in the film is sometimes less than when the ALD method is used without the above conditions.

[0574] The CVD method and the ALD method are different from the deposition method of the particles released from the target material, etc., and are deposition methods that form a film due to the reaction on the surface of the processed object. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the processed object and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for forming a film on the surface of the opening portion with a high aspect ratio. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferably used in combination with other deposition methods such as sputtering or CVD methods with fast deposition rates. For example, when a metal oxide has a laminated structure of a first metal oxide and a second metal oxide, a method of depositing the first metal oxide using a sputtering method and depositing the second metal oxide using an ALD method on the first metal oxide can be cited. For example, in the case where the above-mentioned first metal oxide has a crystalline portion, the above-mentioned second metal oxide sometimes grows crystals with the crystalline portion as a core.

[0575] The CVD method and the ALD method can control the composition of the obtained film by adjusting the flow ratio of the source gases. For example, when the CVD method and the ALD method are used, a film of any composition can be deposited according to the flow ratio of the source gases. In addition, for example, when the CVD method and the ALD method are used, a film whose composition continuously changes can be formed by changing the flow ratio of the source gases while performing deposition. When deposition is performed while changing the flow ratio of the source gases, since the time required for conveying and adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0576] In addition, when the ALD method is used, a film of any composition can be deposited by adjusting the amount of source gas introduced, the number of introductions (also referred to as the number of pulses), and the time required for one pulse (also referred to as the pulse time), etc. When the ALD method is used, a film of any composition can be deposited by simultaneously introducing a plurality of different precursors. Alternatively, when introducing a plurality of different precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor.

[0577] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be formed using wet deposition methods such as spin coating, dipping, spraying, inkjet, dispenser, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, or doctor knife coating.

[0578] In addition, when processing a thin film constituting a semiconductor device, photolithography or the like can be used. Alternatively, the thin film can be processed by nanoimprinting, sandblasting, lift-off, etc. In addition, an island-shaped thin film can be directly formed by a deposition method using a shielding mask such as a metal mask.

[0579] There are two typical methods of photolithography. One is to form a resist mask on the thin film to be processed, process the thin film by etching, etc., and remove the resist mask. The other is to deposit a photosensitive thin film, then expose and develop it, and process the thin film into a desired shape.

[0580] In the photolithography method, as the light used for exposure, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm) or a mixture of these lights can be used. In addition, ultraviolet light, KrF laser or ArF laser, etc. can also be used. In addition, liquid immersion exposure technology can also be used for exposure. In addition, as the light used for exposure, extreme ultraviolet (EUV: Extreme Ultra-violet) light or X-rays can also be used. In addition, instead of the light used for exposure, an electron beam can also be used. When extreme ultraviolet light, X-rays or electron beams are used, extremely fine processing can be performed, so it is preferred. Note that when exposure is performed by scanning with a light beam such as an electron beam, a photomask is not required.

[0581] As etching of the thin film, dry etching, wet etching, sand blasting, or the like can be used.

[0582] First, a conductive layer 520 is formed on the conductive layer 210. Next, an insulating layer 481 is formed on the conductive layer 520 and the insulating layer 210. Then, a conductive layer 114 and an insulating layer 482 are formed on the insulating layer 481. Fig.18A ).

[0583] The conductive layer 114 is provided so as to be embedded in the opening of the insulating layer 482. The top surfaces of the conductive layer 114 and the insulating layer 482 are preferably planarized by a chemical mechanical polishing (CMP) method or the like (also referred to as CMP treatment).

[0584] Next, openings (opening 590c and opening 590d) reaching the conductive layer 520 are formed in the conductive layer 114 and the insulating layer 481, respectively. Fig.18B ). The opening 590d and the opening 590c can be formed using the same mask.

[0585] Next, an insulating layer 556 and a charge storage layer 555 are formed in the opening 590c and the opening 590d. Fig. 18C ).

[0586] For example, the insulating layer 556 and the charge accumulation layer 555 can be formed as follows. First, an insulating film to be the insulating layer 556 is formed in the opening 590c, in the opening 590d, on the insulating layer 482, and on the conductive layer 114. Next, a film to be the charge accumulation layer 555 is formed on the insulating film to be the insulating layer 556. The film to be the charge accumulation layer 555 is formed so as to be embedded in the opening 590c and the opening 590d. In addition, the charge accumulation layer 555 and the insulating layer 556 can be formed by removing a region located on the insulating layer 482 and the conductive layer 114 in the film to be the charge accumulation layer 555 and the insulating film to be the insulating layer 556.

[0587] Next, an insulating layer 483 is formed over each of the charge storage layer 555, the insulating layer 556, the conductive layer 114, and the insulating layer 482. Next, a conductive layer 540 ( Fig.18D ).

[0588] Next, openings ( Fig.19A ). The opening provided in the conductive layer 540 is referred to as an opening 590f. The opening provided in the insulating layer 483 is referred to as an opening 590e. By forming each opening using the same mask, a shape in which the side walls of the above-mentioned openings located above and below are smoothly connected can be achieved. In addition, the opening of the upper layer can be used as a hard mask to provide the opening.

[0589] Next, an insulating layer 554 is formed so as to be in contact with the side walls of the openings provided in the conductive layer 540, the insulating layer 483, the charge storage layer 555, and the insulating layer 556, the top surface of the conductive layer 520, and the top surface of the conductive layer 540. Fig.19B ).

[0590] Next, in the insulating layer 554, the region located on the conductive layer 540 is removed. In addition, an opening 290c ( Fig.19C ).

[0591] For example, the area of ​​the insulating layer 554 located on the conductive layer 540 may be removed by planarization. Alternatively, etching may be performed using a mask. Fig.19D As shown, when a mask is used, a portion of the insulating layer 554 located on the conductive layer 540 may remain. Thus, for example, the oxide semiconductor layer 530 covers the end portion of the conductive layer 540 on the opening 590f side via the insulating layer 554. Thus, the coverage of the oxide semiconductor layer 530 may be improved.

[0592] Next, an oxide semiconductor layer 530 is formed to cover the top surface of the conductive layer 520, the top surface of the insulating layer 554, and the top surface of the conductive layer 540. Then, an insulating layer 551, a charge accumulation layer 552, an insulating layer 553, a conductive layer 560, an insulating layer 283, and an insulating layer 285 are sequentially formed to produce a semiconductor device. FIG. 4A to FIG. 4C The semiconductor device shown.

[0593] Note that the insulating layer 554 may be provided as a side wall insulating layer on the side walls of the openings of the conductive layer 540, the insulating layer 483, the charge storage layer 555, and the insulating layer 556. Fig. 6A The semiconductor device shown.

[0594] Heat treatment may be performed after any one or more steps from the formation of the insulating layer 481 to the formation of the conductive layer 560. The heat treatment may be performed at, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. For example, the treatment may be performed at a temperature of 350° C. to 550° C. for 1 minute to 1 hour or 10 minutes to 30 minutes.

[0595] Heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or an atmosphere containing an oxidizing gas of more than 10 ppm, more than 1%, or more than 10%. For example, when heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas is preferably set to about 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can also be performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere containing an oxidizing gas of more than 10 ppm, more than 1%, or more than 10% to compensate for the oxygen that has been separated. Preferably, heat treatment is performed before depositing the oxide semiconductor layer 530 to reduce impurities such as water contained in the insulating layer, etc.

[0596] The gas used in the heat treatment is preferably highly purified. For example, the water content in the gas used in the above-mentioned heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. By using a highly purified gas for heat treatment, it is possible to prevent moisture and the like from being absorbed by the insulating layer and the like as much as possible. In addition, by performing heat treatment after forming the oxide semiconductor layer 530, the crystallinity of the oxide semiconductor layer 530 can be improved.

[0597] <Example 2 of Method for Manufacturing Semiconductor Device>

[0598] Reference FIG. 20A to FIG. 20C illustrate Figure 6B A method for manufacturing a semiconductor device is shown. Figure 6BThe semiconductor device shown does not include the insulating layer 482 .

[0599] First, the conductive layer 520 is formed over the insulating layer 210 . Next, the insulating layer 481 is formed over the conductive layer 520 and the insulating layer 210 . Next, the conductive layer 114 is formed over the insulating layer 481 .

[0600] Next, openings ( Fig. 20A ).

[0601] Next, an insulating layer 556 and a charge storage layer 555 are formed in this order so as to cover the side walls of the conductive layer 114 and the insulating layer 481, the top surface of the conductive layer 520, the top surface of the conductive layer 114, and the top surface of the insulating layer 481. Next, an insulating layer 483 and a conductive layer 540 ( Fig. 20B ).

[0602] Next, openings are provided in the conductive layer 540 and the insulating layer 483. The openings provided in the conductive layer 540 and the insulating layer 483 can be formed using the same mask.

[0603] Next, openings are provided in the insulating layer 556 and the charge storage layer 555 to expose the top surface of the conductive layer 520 ( Fig. 20C ).exist Fig. 20C In the illustrated example, the width of the openings of the insulating layer 556 and the charge storage layer 555 is smaller than the openings of the conductive layer 540 and the insulating layer 483. Although not illustrated, the openings of the insulating layer 556 and the charge storage layer 555 are included in the openings of the conductive layer 540 and the insulating layer 483, for example, when viewed from a plan view.

[0604] Next, the insulating layer 554 is formed to cover the side walls of the opening of the conductive layer 540, the side walls of the opening of the insulating layer 483, the top surface of the conductive layer 520, the charge storage layer 555, and the side surfaces of the insulating layer 556. Next, the oxide semiconductor layer 530, the insulating layer 551, the charge storage layer 552, the insulating layer 553, the conductive layer 560, the insulating layer 283, and the insulating layer 285 are sequentially formed to produce a semiconductor device. Figure 6B The semiconductor device shown.

[0605] <Semiconductor Device Structure Example 2>

[0606] like Fig.21 As shown, in a semiconductor device according to one embodiment of the present invention, a memory cell can be stacked on a layer including a circuit for driving the memory cell.

[0607] exist Fig.21 In the embodiment, transistor 500 is disposed above transistor 300 .

[0608] The transistor 300 can be used as, for example, a transistor included in a sense amplifier described later.

[0609] about Fig.21 The transistor 500 shown can be referred to Figure 4B etc.

[0610] The transistor 300 is provided on a substrate 311 and includes a conductive layer 316 used as a gate, an insulating layer 315 used as a gate insulator, a semiconductor region 313 formed by a portion of the substrate 311, and a low resistance region 314a and a low resistance region 314b used as a source region or a drain region. The transistor 300 may be a p-channel transistor or an n-channel transistor.

[0611] Here, in Fig.21 In the transistor 300 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, a conductive layer 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulating layer 315. In addition, a material that adjusts the work function can also be used for the conductive layer 316. Because the convex portion of the semiconductor substrate is utilized, this transistor 300 is also referred to as a FIN-type transistor. In addition, an insulating layer used as a mask for forming the convex portion can also be provided in a manner that contacts the upper portion of the convex portion. In addition, although a portion of the semiconductor substrate is processed to form a convex portion is shown here, an SOI substrate can also be processed to form a semiconductor film having a convex shape.

[0612] Notice, Fig.21 The structure of the transistor 300 shown is just an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or driving method.

[0613] A wiring layer including an interlayer film, wiring, and plugs may also be provided between each structure. In addition, the wiring layer may be provided in multiple layers according to the design. Here, in a conductive layer having the function of a plug or wiring, the same symbol is sometimes used to represent multiple structures. In addition, in this specification, wiring and a plug electrically connected to the wiring may also be a constituent element. That is, a part of the conductive layer is sometimes used as wiring, and a part of the conductive layer is sometimes used as a plug.

[0614] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are sequentially stacked as interlayer films over the transistor 300. Furthermore, a conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. Furthermore, the conductive layer 328 and the conductive layer 330 are used as plugs or wirings.

[0615] In addition, the insulating layer used as an interlayer film can also be used as a planarization film to cover the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulating layer 322, the top surface can also be planarized by a planarization process such as a CMP method.

[0616] Alternatively, a wiring layer may be formed over the insulating layer 326 and the conductive layer 330. Fig.21 In the illustrated structural example, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. In addition, a conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 is used as a plug or a wiring.

[0617] The insulating layer 352 and the insulating layer 354 used as an interlayer film can refer to the description of the insulating layer that can be used in the above-mentioned semiconductor device.

[0618] As conductive layers used as plugs or wirings, for example, the conductive layer 328, the conductive layer 330, and the conductive layer 356, the description of the conductive layers that can be used in the above-mentioned semiconductor devices can be referred to.

[0619] The transistor 300 is in contact with a circuit including the transistor 500 via the conductive layer 356 and a conductive layer embedded in the insulating layer 648 .

[0620] This embodiment mode can be combined with other embodiment modes as appropriate.

[0621] Implementation Method 2

[0622] This embodiment mode describes a semiconductor device according to one embodiment of the present invention. A semiconductor device according to one embodiment of the present invention can be used as a memory device.

[0623] Fig.24 is a block diagram showing a structural example of a semiconductor device 900 . Fig.24 The semiconductor device 900 shown includes a driving circuit 910 and a memory cell array 920 .

[0624] As the memory cell array 920 , the memory cell array 601 , the memory cell array 611 , or the like described in the above embodiment can be used.

[0625] The memory cell array 920 includes one or more memory cells 950. As the memory cell 950, the memory cell 602, the memory cell 612, or the like described in the above embodiment mode can be used.

[0626] The driving circuit 910 includes a PSW 931 (power switch), a PSW 932 , and a peripheral circuit 915 . The peripheral circuit 915 includes a peripheral circuit 911 , a control circuit 912 , and a voltage generating circuit 928 .

[0627] In the semiconductor device 900, the above-mentioned circuits, signals and voltages can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1 and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0628] In addition, the signal BW, the signal CE, and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are power gating control signals. In addition, the signals PON1 and PON2 can also be generated in the control circuit 912.

[0629] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 to execute the above operation mode. The control circuit 912 may also have a function of performing error detection and correction (also called ECC: Error Check and Correct) when reading data from the memory cell array 920.

[0630] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0631] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0632] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting a row to be connected to the row specified by the row decoder 941. The column driver 924 has the following functions: a function of writing data to the memory cell 950; a function of reading data from the memory cell 950; a function of holding the read data, etc.

[0633] The input circuit 925 has a function of holding a signal WDA. The data held in the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is the data (Din) written to the memory cell 950. The data (Dout) read out from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data signal output from the output circuit 926 is a signal RDA.

[0634] PSW931 has the function of controlling the supply of V to the peripheral circuit 915 DD PSW932 has the function of controlling the supply of V to the row driver 923. HM Here, the high power supply voltage of the semiconductor device 900 is V DD , the low power supply voltage is GND (ground potential). In addition, V HM is V DD A higher voltage is used as a potential applied during writing and erasing. The on / off of PSW931 is controlled by the signal PON1, and the on / off of PSW932 is controlled by the signal PON2. Fig.24 In the peripheral circuit 915, V DD The number of power domains is 1, but may be multiple. In this case, a power switch may be provided for each power domain.

[0635] The driving circuit and the memory cell array 920 of the semiconductor device 900 are arranged on the same plane. Fig.25A As shown, the driving circuit may also overlap with the memory cell array 920. By overlapping the driving circuit with the memory cell array 920, the signal transmission distance may be shortened.

[0636] In order to facilitate understanding of the structure of the semiconductor device 900, Fig.25A 9 and 910. In FIG. 9, a layer in which a driving circuit 910 is provided and a layer in which a memory cell array 920 is provided are separately shown.

[0637] In addition, if Fig.25B As shown, a plurality of memory cell arrays 920 may be stacked on the driving circuit.

[0638] [Processing device]

[0639] Next, an example of a calculation processing device that may include a semiconductor device such as the above-mentioned storage device will be described.

[0640] Fig.26 It is a block diagram of the computing device 960 . Fig.26 The computing device 960 shown can be used, for example, for a CPU (Central Processing Unit). In addition, the computing device 960 can also be used for a processor such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit) that includes more (tens or hundreds) processor cores capable of parallel processing than a CPU.

[0641] Fig.26 The computing device 960 shown has an ALU 991 (ALU: Arithmetic logic unit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. A semiconductor substrate, an SOI substrate, a glass substrate, etc. can be used as the substrate 990. A rewritable ROM and a ROM interface can also be included. The cache 999 and the cache interface 989 can also be set on different chips.

[0642] The cache memory 999 is connected to a main memory provided on a different chip via a cache interface 989. The cache interface 989 has a function of supplying a part of the data stored in the main memory to the cache memory 999. In addition, the cache interface 989 has a function of outputting a part of the data held in the cache memory 999 to the ALU 991, the register 996, or the like via a bus interface 998.

[0643] As described later, the memory cell array 920 may be provided in a stacked manner on the computing device 960. The memory cell array 920 may be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory cell array 920 to the cache 999. In addition, in this case, it is preferable that a driving circuit 910 is included in a portion of the cache interface 989.

[0644] Note that the cache memory 999 may not be provided and only the memory cell array 920 may be used as a cache memory.

[0645] Fig.26 The computing device 960 shown is only an example of a simplified structure, so the actual computing device 960 has various structures depending on its use. For example, it is preferable to use a computing device including Fig.26 The structure of the computing device 960 shown is a so-called multi-core structure in which one core is provided with a plurality of the cores and the cores are made to work simultaneously. The more cores there are, the higher the computing performance can be. The more cores there are, the more preferred it is, for example, preferably 2, more preferably 4, further preferably 8, further preferably 12, and further preferably 16 or more. In addition, when very high computing performance is required, such as when used in a server, it is preferred to adopt a multi-core structure including 16 or more cores, preferably 32 or more, and more preferably 64 or more cores. In addition, the number of bits that can be processed in the internal computing circuit, data bus, etc. of the computing device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0646] The instructions input to the operation device 960 through the bus interface 998 are input to the instruction decoder 993 and decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995.

[0647] The ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995 perform various controls according to the decoded instructions. Specifically, the ALU controller 992 generates a signal for controlling the operation of the ALU 991. In addition, when executing the program of the computing device 960, the interrupt controller 994 determines the interrupt request from the external input / output device, peripheral circuit, etc. according to its priority, mask status, etc. and processes the request. The register controller 997 generates the address of the register 996 and reads and writes the register 996 according to the state of the computing device 960.

[0648] In addition, the timing controller 995 generates signals for controlling the operation timing of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 has an internal clock generator that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the above-mentioned various circuits.

[0649] exist Fig.26In the illustrated operation device 960, the register controller 997 selects the holding operation in the register 996 according to the instruction of the ALU 991. In other words, the register controller 997 selects whether the data is held by the flip-flop or by the capacitor in the storage unit of the register 996. When the flip-flop is selected to hold the data, the power supply potential is supplied to the storage unit in the register 996. When the capacitor is selected to hold the data, the data is rewritten to the capacitor, and the supply of the power supply potential to the storage unit in the register 996 can be stopped.

[0650] The memory cell array 920 and the computing device 960 may be arranged to overlap. Fig.27A and Fig.27B 970A. The semiconductor device 970A includes a layer 930 on which a memory cell array is disposed on a computing device 960. The layer 930 includes a memory cell array 920L1, a memory cell array 920L2, and a memory cell array 920L3. The computing device 960 and the memory cell arrays have overlapping regions. Fig.27B The computing device 960 and the layer 930 are shown separately in FIG.

[0651] By overlapping the layer 930 including the memory cell array and the computing device 960, the connection distance between the two can be shortened. Thus, the communication speed between the two can be increased. In addition, since the connection distance is short, power consumption can be reduced.

[0652] As a stacking method of the layer 930 including the memory cell array and the computing device 960, the following methods can be adopted: directly stacking the layer 930 including the memory cell array on the computing device 960 (also called monolithic stacking); or forming the computing device 960 and the layer 930 on different substrates, bonding the two substrates together, and electrically connecting them using a perforated or conductive film bonding technology (Cu-Cu bonding, etc.). In the former method, there is no need to consider the misalignment during bonding, so it is possible to reduce the chip size and manufacturing cost.

[0653] Here, the storage cell arrays 920L1, 920L2, and 920L3 that do not include the cache 999 in the computing device 960 and are disposed in the layer 930 can all be used as caches. At this time, for example, the storage cell array 920L1, the storage cell array 920L2, and the storage cell array 920L3 can be used as L1 cache (also called first-level cache), L2 cache (also called second-level cache), and L3 cache (also called third-level cache), respectively. Among the three storage cell arrays, the storage cell array 920L3 has the largest capacity and the lowest access frequency. In addition, the storage cell array 920L1 has the smallest capacity and the highest access frequency.

[0654] Note that when the cache 999 provided in the computing device 960 is used as an L1 cache, each memory cell array provided in the layer 930 can be used as a lower level cache or a main memory. The main memory is a memory having a larger capacity and a lower access frequency than the cache.

[0655] In addition, if Fig.27B As shown, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory cell array 920L1 via the connecting electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory cell array 920L2 via the connecting electrode 940L2, and the driving circuit 910L3 is connected to the memory cell array 920L3 via the connecting electrode 940L3.

[0656] Note that although the case where three memory cell arrays are used as a cache is shown here, the number may be one, two, or four or more.

[0657] When the memory cell array 920L1 is used as a cache, the driver circuit 910L1 may also be used as a part of the cache interface 989, and the driver circuit 910L1 may also be connected to the cache interface 989. Similarly, the driver circuit 910L2 and the driver circuit 910L3 may also be used as a part of the cache interface 989 or connected to a part of the cache interface 989.

[0658] Whether the memory cell array 920 is used as a cache or a main memory depends on the control circuit 912 included in each driver circuit 910. The control circuit 912 can use part of the plurality of memory cells 950 included in the semiconductor device 900 as a RAM according to a signal supplied from the operation device 960.

[0659] In the semiconductor device 900, part of the plurality of storage units 950 can be used as a cache and the other part can be used as a main memory. That is, the semiconductor device 900 can have a function as a cache and a function as a main memory. The semiconductor device 900 according to one embodiment of the present invention can be used as a general-purpose memory, for example.

[0660] Alternatively, a layer 930 including one memory cell array 920 may be provided so as to overlap with the computing device 960 . Fig.28A It is a perspective view of the semiconductor device 970B.

[0661] In the semiconductor device 970B, one memory cell array 920 can be divided into a plurality of regions and different functions can be assigned to the regions for use. Fig.28A An example is shown in which the area L1, the area L2, and the area L3 are used as an L1 cache, an L2 cache, and an L3 cache, respectively.

[0662] In addition, in the semiconductor device 970B, the capacity of each of the regions L1 to L3 can be changed according to the situation. For example, the capacity of the L1 cache can be increased by increasing the area of ​​the region L1. By adopting this structure, the efficiency of the operation processing can be improved and the processing speed can be increased.

[0663] Alternatively, a plurality of memory cell arrays may be stacked. Fig.28B It is a perspective view of a semiconductor device 970C.

[0664] The semiconductor device 970C is stacked with a layer 930L1 including a memory cell array 920L1, a layer 930L2 including a memory cell array 920L2 thereon, and a layer 930L3 including a memory cell array 920L3 thereon. The memory cell array 920L1 physically closest to the computing device 960 can be used as an upper cache and the memory cell array 920L3 farthest from the computing device 960 can be used as a lower cache or a main memory. By adopting this structure, the capacity of each memory cell array can be increased, and thus the processing capability can be further improved.

[0665] This embodiment mode can be combined with other embodiment modes as appropriate.

[0666] Implementation 3

[0667] In this embodiment, an application example of a storage device which is one embodiment of the present invention will be described.

[0668] Generally speaking, in semiconductor devices such as computers, various storage devices are used according to their uses. Fig.29AVarious storage devices used in semiconductor devices are shown in a hierarchical manner. The higher the storage device, the faster the operating speed is required, and the lower the storage device, the larger the storage capacity and the higher the recording density is required. Fig.29A In the example, from the top layer, it includes the memory installed together as registers in the CPU and other arithmetic processing devices, L1 cache, L2 cache, L3 cache, main memory, storage, etc. Note that although the example including up to L3 cache is shown here, it can also include lower level caches.

[0669] Since the memory installed together with the register in the CPU and other processing devices is used for temporary storage of the calculation results, the access frequency from the processing devices is high. Therefore, the operation speed is required to be faster than the storage capacity. In addition, the register has the function of holding the setting information of the processing device.

[0670] The cache has the function of copying and retaining a portion of the data held in the main memory. By copying frequently used data to the cache, the speed of access to the data can be increased. The storage capacity required for the cache is less than that of the main memory, but the operating speed required for the cache is higher than that of the main memory. In addition, the data rewritten in the cache is copied and supplied to the main memory.

[0671] The main memory has a function of holding programs, data, and the like read from the storage.

[0672] Storage has the function of storing data that needs to be stored for a long time and various programs used by the computing processing device. Therefore, compared with faster working speed, storage requires larger storage capacity and higher recording density. For example, large-capacity non-volatile storage devices such as 3D NAND can be used.

[0673] A storage device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. Specifically, as the OS memory, for example, the DOSRAM, NOSRAM, OS-SRAM, etc. shown in the above embodiment can be used. Fig.29A As shown, a storage device according to one embodiment of the present invention can be used in both a hierarchy including a cache and a hierarchy including a main memory. In addition, a storage device according to one embodiment of the present invention can also be used in a hierarchy including storage. For example, a storage device using the transistor 500 shown in the above embodiment can be used in a hierarchy including storage.

[0674] also, Fig.29B An example is shown in which an SRAM is used for a part of the cache and an OS memory according to one embodiment of the present invention is used for the other part.

[0675] The cache at the lowest level can be called LLC (Last Level cache). LLC does not need to work faster than its upper level cache, but is required to have a larger storage capacity. The OS memory of one embodiment of the present invention has a fast working speed and can retain data for a long time, so it can be suitable for LLC. Note that the OS memory of one embodiment of the present invention can also be used for FLC (Final Level cache).

[0676] For example, Fig.29B As shown, SRAM can be used for upper cache (L1 cache, L2 cache, etc.) and the OS memory of one embodiment of the present invention can be used for LLC. Fig.29B As shown, in the main memory, DRAM can be used in addition to the OS memory.

[0677] This embodiment mode can be combined with other embodiment modes as appropriate.

[0678] Implementation 4

[0679] In this embodiment, an application example of a semiconductor device which is one embodiment of the present invention is described.

[0680] For example, a semiconductor device of one embodiment of the present invention can be used in electronic components, electronic devices, large computers, space equipment, data centers (also referred to as DCs), and various electronic devices. By using a semiconductor device of one embodiment of the present invention, low power consumption and high performance of electronic components, large computers, space equipment, data centers, and various electronic devices can be achieved.

[0681] Furthermore, a display device including a semiconductor device according to one embodiment of the present invention can be used in a display portion of various electronic devices. A display device including a semiconductor device according to one embodiment of the present invention can easily achieve high definition and high resolution.

[0682] Electronic devices include, for example, television sets, desktop or notebook personal computers, displays for computers, etc., digital signage, large-scale game consoles such as pinball machines, and other electronic devices with larger screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, sound reproduction devices, and the like.

[0683] The electronic device of this embodiment may also include a sensor (the sensor has the function of sensing, detecting, and measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared).

[0684] The electronic device of this embodiment may have various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of executing various software (programs); a function of wireless communication; a function of reading programs or data stored in a storage medium; etc.

[0685] [Electronic components]

[0686] Fig. 30A A perspective view of a substrate (circuit board 704 ) on which an electronic component 700 is mounted is shown. Fig. 30A The electronic component 700 shown includes a semiconductor device 710 within a mold 711. Fig. 30A 700 is partially omitted to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 through the lead 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of these electronic components and electrically connecting them on the printed circuit board 702, a circuit board 704 is completed.

[0687] In addition, the semiconductor device 710 includes a driving circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driving circuit layer 715 and the storage layer 716 are stacked can be a monolithic stacked structure. In the monolithic stacked structure, it is possible to connect the layers without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When there is a monolithic stacked structure with the driving circuit layer 715 and the storage layer 716, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0688] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to the technology using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0689] In addition, it is preferred that multiple memory cell arrays in the storage layer 716 are formed using OS transistors, and the multiple memory cell arrays are stacked in a monolithic manner. When the multiple memory cell arrays have a monolithic stacking structure, one or both of the bandwidth of the memory and the access delay of the memory can be improved. The bandwidth refers to the amount of data transmitted per unit time, and the access delay refers to the time between accessing and starting the exchange of data. When Si transistors are used in the storage layer 716, it is more difficult to adopt a monolithic stacking structure compared to OS transistors. Therefore, in a monolithic stacking structure, OS transistors are superior to Si transistors.

[0690] In addition, the semiconductor device 710 may be referred to as a bare chip. In this specification, etc., a bare chip refers to a chip obtained by forming a circuit pattern on a disc-shaped substrate (also called a wafer) or the like in the manufacturing process of a semiconductor chip, and cutting it into rectangular small pieces. As semiconductor materials that can be used for bare chips, for example, silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) can be cited. For example, a bare chip obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon chip.

[0691] then, Fig. 30B The electronic component 730 is a perspective view. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0692] The electronic component 730 shows an example of using the semiconductor device 710 as a high bandwidth memory (HBM). In addition, the semiconductor device 735 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0693] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0694] The interposer 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the interposer 731 has the function of electrically connecting the integrated circuit disposed on the interposer 731 to the electrode disposed on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the interposer 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, in the case of using a silicon interposer, TSV can also be used as a through electrode.

[0695] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0696] In addition, in SiP and MCM using silicon interposers, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not easy to occur. In addition, since the surface flatness of the silicon interposer is high, the connection between the integrated circuit arranged on the silicon interposer and the silicon interposer is not easy to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and configured on the interposer.

[0697] On the other hand, when a plurality of integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSV, etc., a space such as the width of the terminal pitch is required. Therefore, when the size of the electronic component 730 is to be reduced, the width of the terminal pitch becomes a problem, and it is sometimes difficult to set up more wiring required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner can also be used.

[0698] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0699] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig. 30BAn example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive needles. By arranging conductive needles in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0700] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0701] [Mainframe computer]

[0702] then, Fig.31A A perspective view of a mainframe computer 5600 is shown. Fig.31A In the illustrated mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0703] Computer 5620 may have, for example, Fig.31B The structure of the stereogram is shown. Fig.31B In the embodiment, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0704] Fig. 31C The personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Fig. 31CSemiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0705] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe and the like.

[0706] The connection terminals 5623, 5624, and 5625 can be used as interfaces for supplying power to the personal computer card 5621 or inputting signals, for example. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621, for example. Examples of the specifications of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when video signals are output from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark) and the like can be cited as the specifications.

[0707] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal. By inserting the terminal into a socket (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0708] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. Examples of the semiconductor device 5627 include FPGA, GPU, and CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0709] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. As the semiconductor device 5628, for example, a memory device can be cited. As the semiconductor device 5628, for example, the electronic component 700 can be used.

[0710] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0711] [Space Equipment]

[0712] The semiconductor device according to one embodiment of the present invention can be applied to space equipment.

[0713] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The electrical characteristics of the OS transistor change little due to exposure to radiation. In other words, the OS transistor has high resistance to radiation, so it can be appropriately used in an environment where radiation may be incident. For example, an OS transistor can be appropriately used when used in outer space. Specifically, an OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron radiation. Note that outer space refers to, for example, an altitude of 100 km or more, but the outer space shown in this specification may also include one or more of the thermosphere, mesosphere, and stratosphere.

[0714] exist Fig.31D In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.31D An example of a planet 6804 in outer space is shown.

[0715] In addition, although Fig.31D Although not shown in the figure, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the above-mentioned battery management system or battery control circuit, power consumption is low and high reliability is achieved even in outer space, so it is preferable.

[0716] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0717] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

[0718] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0719] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is composed of, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, as the control device 6807, a semiconductor device including an OS transistor of one embodiment of the present invention is preferably used. Compared with Si transistors, the electrical characteristics of OS transistors due to irradiation with radiation are less changed. Therefore, OS transistors have high reliability and can be appropriately used even in an environment where radiation may be incident.

[0720] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0721] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.

[0722] As described above, OS transistors have superior effects compared to Si transistors, such as being able to achieve a wider memory bandwidth and having high radiation resistance.

[0723] [Data Center]

[0724] For example, a semiconductor device according to one embodiment of the present invention can be applied to a storage system used in a data center or the like. A data center is required to manage data over a long period of time by ensuring data invariance. When managing data over a long period of time, it is necessary to enlarge facilities, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply to maintain data, or ensuring cooling equipment required for maintaining data.

[0725] By using a semiconductor device of one embodiment of the present invention in a storage system used in a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device for retaining data. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for retaining data, and reduce the scale of cooling equipment. As a result, it is possible to save space in the data center.

[0726] In addition, the power consumption of the semiconductor device of one embodiment of the present invention is low, so the heat generation of the circuit can be reduced. As a result, the negative impact of the heat generation on the circuit itself, the peripheral circuits and the modules can be reduced. In addition, by using the semiconductor device of one embodiment of the present invention, a data center that can operate stably even in a high temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0727] Fig.31E A storage system that may be used in a data center is shown. Fig.31E The storage system 7010 shown includes a plurality of servers 7001sb as a host 7001 (shown as a host computer). In addition, it includes a plurality of storage devices 7003md as storage 7003 (shown as storage). The host 7001 and the storage 7003 are shown to be connected via a storage area network 7004 (shown as SAN: Storage Area Network) and a storage control circuit 7002 (shown as a storage controller).

[0728] The host 7001 is equivalent to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0729] In the storage 7003, the access speed of data is shortened by using a flash memory, that is, the time required for data storage and output is shortened, but this time is much longer than the time required for DRAM which can be used as a cache memory in the storage. In the storage system, in order to solve the problem of the long access speed of the storage 7003, a cache memory is generally provided in the storage to shorten the time required for data storage and output.

[0730] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003 and then output to the host 7001 or the storage 7003.

[0731] When an OS transistor is used as a transistor for storing data in the cache memory to hold a potential corresponding to the data, the refresh frequency can be reduced to reduce power consumption. In addition, miniaturization can be achieved by stacking memory cell arrays.

[0732] Note that by using a semiconductor device of one embodiment of the present invention for any one or more selected from electronic components, large computers, space equipment, data centers, and electronic devices, the effect of reducing power consumption can be expected. Therefore, it is currently believed that as the energy demand for high performance or high integration of semiconductor devices increases, the emission of greenhouse gases represented by carbon dioxide (CO2) can also be reduced by using a semiconductor device of one embodiment of the present invention. In addition, a semiconductor device of one embodiment of the present invention has low power consumption, so it is also effective as a measure against global warming.

[0733] This embodiment mode can be combined with other embodiment modes as appropriate.

Claims

1. A semiconductor device comprising: a first conductive layer; a first insulating layer on the first conductive layer; a second conductive layer on the first insulating layer; a second insulating layer on the second conductive layer; a third conductive layer on the second insulating layer; an oxide semiconductor layer; a fourth conductive layer; A third insulating layer; a fourth insulating layer; a fifth insulating layer; a sixth insulating layer; a first charge accumulation layer; as well as The second charge accumulation layer, The first insulating layer, the second conductive layer, the second insulating layer and the third conductive layer all have openings that reach the first conductive layer. The third insulating layer has a region in contact with the side wall of the opening of the first insulating layer, a region in contact with the side wall of the opening of the second conductive layer, and a region in contact with the top surface of the first conductive layer. The first charge storage layer has a region covering the side wall of the opening of the second conductive layer via the third insulating layer. The fourth insulating layer has a region covering the side wall of the opening of the second conductive layer via the third insulating layer and the first charge accumulation layer. the fourth insulating layer has a region sandwiched between the oxide semiconductor layer and the first charge accumulation layer, The oxide semiconductor layer includes a region in contact with the top surface of the first conductive layer, a region covering the side wall of the opening of the second conductive layer via the third insulating layer, the first charge accumulation layer, and the fourth insulating layer, and a region in contact with the third conductive layer. The fourth conductive layer has a region located within the opening of the second conductive layer, the second charge accumulation layer has a region sandwiched between the oxide semiconductor layer and the fourth conductive layer, the fifth insulating layer has a region sandwiched between the oxide semiconductor layer and the second charge accumulation layer, Furthermore, the sixth insulating layer has a region sandwiched between the second charge accumulation layer and the fourth conductive layer.

2. The semiconductor device according to claim 1, The fourth insulating layer and the fifth insulating layer each include at least one selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride and aluminum oxide.

3. The semiconductor device according to claim 1, At least one of the first charge accumulation layer and the second charge accumulation layer contains one or more metal elements selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, or an alloy containing the above metal elements or an alloy combining the above metal elements.

4. The semiconductor device according to claim 1, At least one of the first charge accumulation layer and the second charge accumulation layer comprises a metal nitride or a metal oxide.

5. The semiconductor device according to claim 1, At least one of the first charge accumulation layer and the second charge accumulation layer includes one or more selected from silicon and germanium.

6. The semiconductor device according to claim 1, At least one of the first charge accumulation layer and the second charge accumulation layer includes one or more selected from silicon nitride and silicon nitride oxide.

7. The semiconductor device according to claim 1, wherein the first conductive layer is used as one of a source electrode and a drain electrode of a transistor, The third conductive layer is used as the other of the source electrode and the drain electrode of the transistor, The fourth conductive layer is used as a first control gate of the transistor, And the second conductive layer is used as a second control gate of the transistor.

Images