ETOX NOR type flash memory device and preparation method thereof

Abstract

The invention provides an ETOX NOR type flash memory device and a preparation method thereof, and the preparation method comprises the steps: forming a cap layer on a control gate material layer, then forming a first deep trench and a second deep trench, filling a sacrificial oxide layer in the first deep trench and the second deep trench, and flattening the sacrificial oxide layer, etching the sacrificial oxide layer in the first deep trench and forming a source line ion implantation region through an ion implantation process; according to the method, the sacrificial oxide layer is adopted to fill the first deep groove, the situation that in a traditional SAS technology, residual photoresist on the side wall of the deep groove subsequently causes adverse effects on the performance of a device is avoided, the performance of the device is improved, and further miniature integration of the size of a storage unit is facilitated.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an ETOX NOR flash memory device and a preparation method thereof. Background Art

[0002] The source line region of the current mainstream ETOX NOR flash memory device (flash) architecture adopts a SAS (Self-Aligned Source) structure. By etching a shallow trench isolation structure (STI) in the substrate between the control gates and performing ion implantation, a source line ion implantation region is formed in the substrate, and a source line polysilicon material layer is formed on the substrate surface on the side of the source line ion implantation region. The doped ions in the source line ion implantation region are conductive, connecting the source line ion implantation region and the source line polysilicon material layer in series, thereby forming a serpentine source line in the substrate and on the substrate surface in an alternating manner.

[0003] As the size of storage cells is further miniaturized and integrated, the SAS structure-related processes are the main obstacles to further miniaturization of storage cells. The main reasons are: (1) In the lithography process of the SAS structure, deep trenches for preparing source lines, word lines, etc. are formed in the stacked floating gate, ONO dielectric layer and control gate. Before ion implantation is performed at the bottom of the source line deep trench, a layer of photoresist needs to be coated on the entire surface of the wafer, so all deep trenches are filled with photoresist. Then, the deep trench where the source line is located is opened through exposure, development and other processes to perform source line ion implantation on the substrate at the bottom of the deep trench. However, since the deep trench line width of the source line is small and the stacked floating gate, ONO dielectric layer and control gate of the storage unit are high, after the photoresist is filled into the deep trench, the SAS lithography process window is small, which is not conducive to the development of the photoresist and is prone to produce photoresist residues in the deep trenches, thereby generating impurity residual defects that affect the electrical performance of the device; (2) The etching process of the SAS structure will mistakenly etch the top corners of the control gate on both sides of the deep trench of the source line, making the top corners of the control gate rounded, which is not conducive to further thinning of the control gate; (3) In the ion implantation process of the SAS structure, a shallow trench isolation (STI) structure is etched in the substrate between the control gates and ions are implanted into the substrate. The lateral diffusion of the doped ions in the source line ion implantation region (source end) is twice that of the doped ions in the bit line ion implantation region (drain end), which shortens the effective channel of the storage cell and affects the electrical performance of the device. Summary of the invention

[0004] The present application provides an ETOX NOR flash memory device and a preparation method thereof, which can solve at least one of the following problems: the mainstream source line SAS technology of the ETOX NOR flash memory device is used to prepare the source line with residual photoresist in the deep trench, thereby affecting the electrical performance of the device; the etching step in the SAS technology is prone to mistakenly etching the top corners of the control gate on both sides of the deep trench of the source line; the doped ions in the source line ion implantation region are severely diffused laterally in the substrate, thereby shortening the effective channel of the storage unit.

[0005] On the one hand, an embodiment of the present application provides a method for preparing an ETOX NOR flash memory device, comprising: A substrate is provided, the substrate comprising a storage area and a peripheral logic area, wherein a gate oxide layer, a floating gate material layer, an ONO dielectric layer and a control gate material layer are formed on the substrate of the storage area, and a pad oxide layer and a control gate material layer are formed on the substrate of the peripheral logic area; Thinning the control gate material layer of the storage area to a certain thickness; forming a capping layer, wherein the capping layer covers the control gate material layer of the storage area; Etching the remaining thickness of the control gate material layer, the ONO dielectric layer, the floating gate material layer and the gate oxide layer of the storage area to form a plurality of first deep trenches and a plurality of second deep trenches, wherein the first deep trenches and the second deep trenches are arranged in a staggered manner; forming an anti-reflection layer, wherein the anti-reflection layer fills the first deep trench and covers the control gate material layer of the peripheral logic region; Etching the control gate material layer and the pad oxide layer of the peripheral logic region to form a plurality of third deep trenches; forming a first spacer material layer and a second spacer material layer, wherein the first spacer material layer covers the sidewalls and bottom walls of the first deep trench, the second deep trench and the third deep trench, and the second spacer material layer covers the first spacer material layer; forming a sacrificial oxide layer, wherein the sacrificial oxide layer covers the second spacer material layer and fills the first deep trench, the second deep trench and the third deep trench; Planarizing the sacrificial oxide layer to the surface of the second spacer material layer; Coating a photoresist layer on the flat surfaces of the sacrificial oxide layer and the second spacer material layer; By photolithography and etching processes, the sacrificial oxide layer in the first deep trench of the storage area and the second spacer material layer and the first spacer material layer on the bottom wall of the first deep trench are etched away; Forming a source line ion implantation region in the substrate at the bottom of the first deep trench by an ion implantation process; forming a source line material layer, wherein the source line material layer fills the first deep trench; Etching and removing the sacrificial oxide layer in the second deep trench of the storage area and the sacrificial oxide layer in the third deep trench of the peripheral logic area; forming a third spacer material layer, wherein the third spacer material layer fills the second deep trench and the third deep trench; Etching a portion of the third spacer material layer in the second deep trench, the second spacer material layer and the first spacer material layer on the bottom wall of the second deep trench to obtain a storage area spacer structure, and etching a portion of the third spacer material layer in the third deep trench, the second spacer material layer and the first spacer material layer on the bottom wall of the third deep trench to obtain a peripheral logic area spacer structure; Forming a bit line ion implantation region in the substrate at the bottom of the second deep trench and a source / drain region in the substrate at the bottom of the third deep trench by ion implantation processes respectively; Forming a metal silicide layer on the surface of the bit line ion implantation region, the surface of the source line material layer, the surface of the control gate material layer, and the surface of the source / drain region of the peripheral logic region through a self-aligned metal silicide process; and An interlayer insulating dielectric layer is formed, which fills the second deep trench and the third deep trench and covers the cap layer, the metal silicide layer on the top of the source line material layer and the metal silicide layer on the top of the control gate material layer of the peripheral logic area.

[0006] Optionally, in the method for preparing the ETOX NOR flash memory device, the step of etching and removing the sacrificial oxide layer in the first deep trench of the storage area and the second spacer material layer and the first spacer material layer on the bottom wall of the first deep trench by photolithography and etching processes comprises: By means of exposure and development processes, an opening pattern is defined on the photoresist layer at the top of the first deep trench; Through the opening pattern, a sacrificial oxide layer in the first deep trench of the storage area is removed by a wet etching process; and The second spacer material layer and the first spacer material layer are removed from the bottom wall of the first deep trench by a wet etching process.

[0007] Optionally, in the method for preparing the ETOX NOR flash memory device, after forming a source line ion implantation region in the substrate at the bottom of the first deep trench by an ion implantation process and before forming a source line material layer, the method for preparing the ETOX NOR flash memory device further comprises: The photoresist layer is removed by ashing.

[0008] Optionally, in the preparation method of the ETOX NOR flash memory device, while etching part of the third sidewall material layer in the second deep trench, the second sidewall material layer and the first sidewall material layer at the bottom wall of the second deep trench to obtain the storage area sidewall structure, and etching part of the third sidewall material layer in the third deep trench, the second sidewall material layer and the first sidewall material layer at the bottom wall of the third deep trench to obtain the peripheral logic area sidewall structure, the second sidewall material layer and the first sidewall material layer at the top of the cap layer of the storage area are etched, and the second sidewall material layer and the first sidewall material layer at the top of the control gate material layer of the peripheral logic area are etched.

[0009] Optionally, in the preparation method of the ETOX NOR flash memory device, the material of the cap layer is silicon nitride; the material of the first sidewall material layer is silicon dioxide; the material of the second sidewall material layer is silicon nitride; and the material of the third sidewall material layer is silicon dioxide.

[0010] Optionally, in the method for preparing the ETOX NOR flash memory device, after forming the interlayer insulating dielectric layer, the method for preparing the ETOX NOR flash memory device further comprises: A first conductive plug, a second conductive plug and a third conductive plug are formed, wherein the first conductive plug penetrates the interlayer insulating dielectric layer and contacts the metal silicide layer on the surface of the bit line ion implantation region, the second conductive plug penetrates the interlayer insulating dielectric layer and contacts the metal silicide layer on the top of the source line material layer, and the third conductive plug penetrates the interlayer insulating dielectric layer and contacts the metal silicide layer on the surface of the source / drain region.

[0011] Optionally, in the method for preparing the ETOX NOR flash memory device, after etching the control gate material layer and the pad oxide layer of the peripheral logic region to form a plurality of third deep trenches, and before forming the first spacer material layer and the second spacer material layer, the method for preparing the ETOX NOR flash memory device further includes: The anti-reflection layer is removed.

[0012] On the other hand, the embodiment of the present application further provides an ETOX NOR flash memory device, including: A substrate, the substrate comprising a storage area and a peripheral logic area, wherein a gate oxide layer, a floating gate material layer, an ONO dielectric layer and a control gate material layer are formed on the substrate of the storage area, and a pad oxide layer and a control gate material layer are formed on the substrate of the peripheral logic area; A capping layer, wherein the capping layer covers the control gate material layer of the storage area; A first deep trench and a second deep trench, wherein the first deep trench and the second deep trench are located in the control gate material layer, the ONO dielectric layer, the floating gate material layer and the gate oxide layer of the storage area and are arranged alternately; a third deep trench, the third deep trench being located in the control gate material layer and the liner oxide layer of the peripheral logic region; a source line ion implantation region, the source line ion implantation region being located in the substrate at the bottom of the first deep trench; a source line material layer, wherein the source line material layer fills the first deep trench; A storage area sidewall structure, wherein the storage area sidewall structure covers a sidewall of the second deep trench; A peripheral logic area sidewall structure, wherein the peripheral logic area sidewall structure covers the sidewall of the third deep trench; a bit line ion implantation region, the bit line ion implantation region being located in the substrate at the bottom of the second deep trench; a source / drain region, the source / drain region being located in the substrate at the bottom of the third deep trench; A metal silicide layer, the metal silicide layer covers the surface of the bit line ion implantation region and the source line material layer of the storage region, and the surface of the control gate material layer and the source / drain region of the peripheral logic region; and An interlayer insulating dielectric layer fills the second deep trench and the third deep trench and covers the cap layer, the metal silicide layer on the top of the source line material layer and the metal silicide layer on the top of the control gate material layer of the peripheral logic area.

[0013] The technical solution of this application has at least the following advantages: First, the present application uses a sacrificial oxide layer to fill the first deep trench, etches away the sacrificial oxide layer in the first deep trench, and forms a source line ion implantation region in the substrate at the bottom of the first deep trench through an ion implantation process; then forms a source line material layer for filling the first deep trench, thereby avoiding the situation in which residual photoresist on the sidewall of the deep trench in the process of preparing a serpentine source line by a traditional SAS process subsequently causes adverse effects on device performance, improves device performance, and is also conducive to further miniaturization and integration of storage units; Second, after forming the control gate material layer, the present application directly thins the control gate material layer of the storage area to a certain thickness, and then forms a cap layer on the thinned control gate material layer. In this way, in the subsequent etching process to form the first deep trench and the second deep trench, the presence of the cap layer can avoid the top corner of the control gate material layer from being mistakenly etched, thereby ensuring that the morphology and contour of the control gate material layer are intact. Because the process of thinning the control gate material layer is advanced, there is no need to thin the control gate material layer again in the subsequent process. Third, the present application utilizes a source line material layer to connect the source line ion implantation area of ​​the storage area in series, eliminating the traditional etching and ion implantation process based on SAS technology. The source line ion implantation and word line ion implantation of the present application are symmetrical, which in disguise expands the effective channel of the storage unit and improves the device performance.

[0014] In addition, the preparation method of the ETOX NOR flash memory device provided in the present application can straighten the control gate in the integrated circuit layout, eliminate the elbow design in the traditional process, make OPC (optical proximity correction) simpler, and improve the subsequent photolithography overlay accuracy; at the same time, all line width dimensions of the active area of ​​the storage area array (source line ion implantation area, word line ion implantation area, etc.) can be further reduced and kept consistent, making the OPC of this area simple, and the subsequent CAA etching process is also simpler, improving the subsequent photolithography overlay accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1-Figure 23 It is a schematic diagram of the semiconductor structure in each process step of preparing an ETOX NOR flash memory device according to an embodiment of the present invention; The reference numerals are described as follows: 10-substrate, 11-source line ion implantation region, 12-word line ion implantation region 1, 13-word line ion implantation region 2, 14-source / drain region, 21-gate oxide layer, 22-high voltage oxide layer, 23-low voltage oxide layer, 30-floating gate layer, 40-ONO dielectric layer, 50-control gate layer, 61-photoresist layer 1, 62-photoresist layer 2, 63-photoresist layer 3, 64-anti-reflection layer, 65-photoresist layer 4, 66-photoresist layer 5, 7 0-cap layer, 71-first deep trench, 72-second deep trench, 73-third deep trench, 81-first spacer material layer, 82-second spacer material layer, 83-third spacer material layer, 91-sacrificial oxide layer, 92-source line material layer, 93-metal silicide layer, 94-interlayer insulating dielectric layer, 95-first conductive plug, 96-second conductive plug, 98-third conductive plug, 97-fourth conductive plug, 99-fifth conductive plug. DETAILED DESCRIPTION

[0017] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0018] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0019] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0020] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0021] The present application embodiment provides a method for preparing an ETOX NOR flash memory device, referring to Figure 1-Figure 23 , the preparation method of the ETOXNOR type flash memory device comprises: First, refer to Figure 1 , Figure 1 It is a schematic diagram of a semiconductor structure after a control gate material layer is formed in an embodiment of the present application, and a substrate 10 is provided, wherein the substrate 10 includes a storage area and a peripheral logic area, wherein a gate oxide layer 21, a floating gate material layer 30, an ONO dielectric layer 40 and a control gate material layer 50 are formed on the substrate of the storage area, and a pad oxide layer and a control gate material layer 50 are formed on the substrate of the peripheral logic area.

[0022] The peripheral logic region includes a high-voltage MOS device region and a low-voltage MOS device region, so the pad oxide layer of the high-voltage device region is a high-voltage oxide layer 22 ; the pad oxide layer of the low-voltage device region is a low-voltage oxide layer 23 .

[0023] Furthermore, the control gate material layer 50 of the peripheral logic region is subsequently used as a gate of a high-voltage MOS device and a gate of a low-voltage MOS device in the peripheral logic region.

[0024] Then, refer to Figure 2 , Figure 2 This is a schematic diagram of the semiconductor structure after the control gate material layer of the storage area is thinned to a certain thickness according to an embodiment of the present application. A photoresist layer 61 is coated on the control gate material layer 50 of the storage area and the control gate material layer 50 of the peripheral logic area. The control gate material layer 50 of the storage area to a certain thickness is etched using the photoresist layer 61 as a mask, thereby thinning the control gate material layer 50 of the storage area to a certain thickness.

[0025] Next, refer to Figure 3 , Figure 3 It is a schematic diagram of the semiconductor structure after forming a cap layer according to an embodiment of the present application, wherein a cap layer 70 is formed, and the cap layer 70 covers the control gate material layer 50 of the storage area and the control gate material layer 50 of the peripheral logic area.

[0026] In this embodiment, the cap layer 50 is made of silicon nitride.

[0027] Next, refer to Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the cap layer of the peripheral logic area is etched away in an embodiment of the present application. A second photoresist layer 62 is coated on the cap layer 70 of the storage area and the cap layer 70 of the peripheral logic area. The cap layer 70 of the peripheral logic area is etched away using the second photoresist layer 62 as a mask.

[0028] For further reference, Figure 5 and Figure 6 , Figure 5 is a schematic diagram of a semiconductor structure after coating a photoresist layer three in an embodiment of the present application, Figure 6 1 is a schematic diagram of a semiconductor structure after forming a plurality of first deep trenches and a plurality of second deep trenches according to an embodiment of the present application, wherein a photoresist layer 63 is coated on the cap layer 70 of the storage area and the control gate material layer 50 of the peripheral logic area, and the control gate material layer 50, the ONO dielectric layer 40, the floating gate material layer 30 and the gate oxide layer 21 of the storage area are etched to form a plurality of first deep trenches 71 and a plurality of second deep trenches 72, wherein the first deep trenches 71 and the second deep trenches 72 are alternately arranged.

[0029] In the present application, after forming the control gate material layer, the control gate material layer of the storage area is directly thinned to a certain thickness, and then a cap layer is formed on the thinned control gate material layer. In this way, in the subsequent etching process to form the first deep trench and the second deep trench, the presence of the cap layer can avoid mistaken etching of the top corners of the control gate material layer, thereby ensuring that the morphology and contour of the control gate material layer are intact. Since the process of thinning the control gate material layer is advanced, there is no need to thin the control gate material layer again later.

[0030] Next, refer to Figure 7 , Figure 7 It is a schematic diagram of the semiconductor structure after the anti-reflection layer is formed in an embodiment of the present application, wherein the anti-reflection layer 64 is formed, and the anti-reflection layer 64 fills the first deep trench 71 and covers the control gate material layer 50 of the peripheral logic region.

[0031] For further reference, Figure 8 and Fig. 9 , Figure 8 is a schematic diagram of a semiconductor structure after coating a photoresist layer 4 in an embodiment of the present application, Fig. 9 It is a schematic diagram of the semiconductor structure after forming a plurality of third deep trenches in an embodiment of the present application. A photoresist layer 65 is coated on the anti-reflective layer 64, and the control gate material layer 50 and the high-voltage oxide layer 22 and the low-voltage oxide layer 23 of the peripheral logic area are etched to form a plurality of third deep trenches 73.

[0032] In this embodiment, after etching the control gate material layer 50 and the high-voltage oxide layer 22 and the low-voltage oxide layer 23 of the peripheral logic area to form a plurality of third deep trenches 73, and before forming the first sidewall material layer 81 and the second sidewall material layer 82, the preparation method of the ETOX NOR flash memory device may further include: removing the photoresist layer 65 and the anti-reflective layer 64.

[0033] Next, refer to Fig.10 , Fig.10 It is a schematic diagram of the semiconductor structure after the first spacer material layer and the second spacer material layer are formed in an embodiment of the present application, wherein the first spacer material layer 81 and the second spacer material layer 82 are formed, wherein the first spacer material layer 81 covers the side walls and bottom walls of the first deep trench 71, the second deep trench 72 and the third deep trench 73, and the second spacer material layer 82 covers the first spacer material layer 81.

[0034] In this embodiment, the material of the first spacer material layer 81 is silicon dioxide; the material of the second spacer material layer 82 is silicon nitride.

[0035] For further reference, Fig.11 , Fig.11It is a schematic diagram of the semiconductor structure after forming a sacrificial oxide layer in an embodiment of the present application, forming a sacrificial oxide layer 91, the sacrificial oxide layer 91 covers the second sidewall material layer 82 and fills the first deep trench 71, the second deep trench 72 and the third deep trench 73.

[0036] Next, refer to Fig.12 , Fig.12 It is a schematic diagram of the semiconductor structure after the sacrificial oxide layer is planarized to the surface of the second spacer material layer according to an embodiment of the present application, and the sacrificial oxide layer 91 is planarized to the surface of the second spacer material layer 82 of the storage area.

[0037] Furthermore, a photoresist layer 66 is coated on the flat surfaces of the sacrificial oxide layer 91 and the second spacer material layer 82 .

[0038] Next, the sacrificial oxide layer 91 in the first deep trench 71 of the storage area and the second spacer material layer 82 and the first spacer material layer 81 on the bottom wall of the first deep trench 71 are removed by etching through photolithography and etching processes.

[0039] In this embodiment, the step of etching and removing the sacrificial oxide layer 91 in the first deep trench 71 of the storage area and the second spacer material layer 82 and the first spacer material layer 81 on the bottom wall of the first deep trench 71 by photolithography and etching processes may specifically include: 1) Reference Fig.13 , Fig.13 1 is a schematic diagram of a semiconductor structure after an opening pattern is defined on the photoresist layer five at the top of the first deep trench according to an embodiment of the present application. An opening pattern is defined on the photoresist layer five 66 at the top of the first deep trench 71 through exposure and development processes; 2) Reference Fig.14 , Fig.14 is a schematic diagram of a semiconductor structure after the sacrificial oxide layer in the first deep trench of the storage area is etched away according to an embodiment of the present application, wherein the sacrificial oxide layer 91 in the first deep trench 71 of the storage area is etched away by a wet etching process through the opening pattern; and 3) Reference Fig.15 , Fig.15 This is a schematic diagram of the semiconductor structure after the second sidewall material layer and the first sidewall material layer on the bottom wall of the first deep trench are etched away in an embodiment of the present application. The second sidewall material layer 81 and the first sidewall material layer 82 on the bottom wall of the first deep trench 71 are etched away by a wet etching process.

[0040] For further reference, Fig.16 , Fig.16Schematic diagram of the semiconductor structure after the source line ion implantation region is formed in the embodiment of the present application. The source line ion implantation region 11 is formed in the substrate 10 at the bottom of the first deep trench 71 by an ion implantation process.

[0041] In this embodiment, after forming a source line ion implantation region 11 in the substrate 10 at the bottom of the first deep trench 71 by an ion implantation process, and before forming a source line material layer 92, the method for preparing the ETOX NOR flash memory device may further include: removing the photoresist layer 5 66 by ashing.

[0042] Next, refer to Fig.17 and Fig.18 , Fig.17 is a schematic diagram of a semiconductor structure after a source line material layer is formed in an embodiment of the present application, Fig.18 1 is a schematic diagram of the semiconductor structure after the source line material layer beyond the upper surface of the sacrificial oxide layer is ground according to an embodiment of the present application, to form a source line material layer 92, wherein the source line material layer 92 fills the first deep trench 71 and covers the sacrificial oxide layer 91, and then the source line material layer 92 beyond the upper surface of the sacrificial oxide layer is ground using a CMP (chemical mechanical polishing) process, leaving only the source line material layer 92 in the first deep trench 71.

[0043] In the present application, a sacrificial oxide layer is used to fill the first deep trench, the sacrificial oxide layer in the first deep trench is etched away, and a source line ion implantation region is formed in the substrate at the bottom of the first deep trench through an ion implantation process; then a source line material layer for filling the first deep trench is formed, thereby avoiding the situation in which residual photoresist on the side wall of the deep trench in the process of preparing a serpentine source line by a traditional SAS process subsequently causes adverse effects on device performance, thereby improving device performance and facilitating further miniaturization and integration of storage units.

[0044] For further reference, Fig.19 , Fig.19 This is a schematic diagram of the semiconductor structure after the sacrificial oxide layer in the second deep trench of the storage area and the sacrificial oxide layer in the third deep trench of the peripheral logic area are etched away in an embodiment of the present application, and the sacrificial oxide layer 91 in the second deep trench 72 of the storage area and the sacrificial oxide layer 91 in the third deep trench 73 of the peripheral logic area are etched away.

[0045] Next, a third spacer material layer 83 is formed, and the third spacer material layer 83 fills the second deep trench 72 and the third deep trench 73 .

[0046] In this embodiment, the third spacer material layer 83 is made of silicon dioxide.

[0047] For further reference, Fig. 20 , Fig. 20It is a schematic diagram of the semiconductor structure after the storage area sidewall structure and the peripheral logic area sidewall structure are formed in an embodiment of the present application, and a portion of the third sidewall material layer 83 in the second deep trench 72, the second sidewall material layer 82 and the first sidewall material layer 81 on the bottom wall of the second deep trench 72 are etched to obtain the storage area sidewall structure, and a portion of the third sidewall material layer 83 in the third deep trench 73, the second sidewall material layer 82 and the first sidewall material layer 81 on the bottom wall of the third deep trench 73 are etched to obtain the peripheral logic area sidewall structure.

[0048] It is worth noting that while etching part of the third sidewall material layer 83 in the second deep trench 72, the second sidewall material layer 82 and the first sidewall material layer 81 on the bottom wall of the second deep trench 72 to obtain the storage area sidewall structure, and etching part of the third sidewall material layer 83 in the third deep trench 73, the second sidewall material layer 82 and the first sidewall material layer 81 on the bottom wall of the third deep trench 73 to obtain the peripheral logic area sidewall structure, the second sidewall material layer 82 and the first sidewall material layer 81 on the top of the cap layer 70 of the storage area are etched, and the second sidewall material layer 82 and the first sidewall material layer 81 on the top of the control gate material layer 50 of the peripheral logic area are etched.

[0049] Next, refer to Fig.21 , Fig.21 It is a schematic diagram of the semiconductor structure after the bit line ion implantation region and the source / drain region are formed in an embodiment of the present application. Through the ion implantation process, a bit line ion implantation region 12 and a bit line ion implantation region 13 are formed in the substrate 10 at the bottom of the second deep trench 72, and a source / drain region 14 is formed in the substrate at the bottom of the third deep trench 73.

[0050] For further reference, Fig. 22 , Fig. 22 It is a schematic diagram of the semiconductor structure after the metal silicide layer is formed in an embodiment of the present application. Through a self-aligned metal silicide process, a metal silicide layer 93 is formed on the surface of the bit line ion implantation area 12, the surface of the bit line ion implantation area 2 13, the surface of the source line material layer 92 in the storage area, and the surface of the control gate material layer 50 and the surface of the source / drain area 14 in the peripheral logic area.

[0051] Finally, reference Fig.23 , Fig.23 It is a schematic diagram of the semiconductor structure after the interlayer insulating dielectric layer is formed in an embodiment of the present application, forming an interlayer insulating dielectric layer 94, wherein the interlayer insulating dielectric layer 94 fills the second deep trench 72 and the third deep trench 73 and covers the cap layer 70, the metal silicide layer 93 at the top of the source line material layer 92 and the metal silicide layer 93 at the top of the control gate material layer 50 of the peripheral logic area.

[0052] For further information, please refer to Fig.23 After forming the interlayer insulating dielectric layer 94, the method for preparing the ETOX NOR flash memory device may further include: forming a first conductive plug 95, a second conductive plug 96, a third conductive plug 97, a fourth conductive plug 98, and a fifth conductive plug 99, wherein the first conductive plug 95 penetrates the interlayer insulating dielectric layer 94 and contacts the metal silicide layer on the surface of the bit line ion implantation region 12, the fourth conductive plug 98 penetrates the interlayer insulating dielectric layer 94 and contacts the metal silicide layer 93 on the surface of the bit line ion implantation region 2 13, the second conductive plug 96 penetrates the interlayer insulating dielectric layer 94 and contacts the metal silicide layer 93 on the top of the source line material layer 92, the third conductive plug 97 penetrates the interlayer insulating dielectric layer 94 and contacts the metal silicide layer 93 on the surface of the source / drain region 14; and the fifth conductive plug 99 penetrates the interlayer insulating dielectric layer 94 and contacts the metal silicide layer 93 on the top of the control gate material layer 50 of the peripheral logic region.

[0053] In the present application, the source line material layer is used to connect the source line ion implantation area of ​​the storage area in series, and the traditional etching and ion implantation process based on SAS technology is eliminated. The source line ion implantation and word line ion implantation of the present application are symmetrical, which enlarges the effective channel of the storage unit in disguise and improves the device performance. In addition, the preparation method of the ETOX NOR flash memory device provided by the present application can straighten the control gate in the integrated circuit layout, eliminate the elbow design in the traditional process, make OPC (optical proximity correction) simpler, and improve the subsequent photolithography overlay accuracy; at the same time, all the line width dimensions of the active area of ​​the storage area array (source line ion implantation area, word line ion implantation area, etc.) can be further reduced and kept consistent, making the OPC of this area simple, and the subsequent CAA etching process is also simpler, which improves the subsequent photolithography overlay accuracy.

[0054] Based on the same inventive concept, the present application embodiment also provides an ETOX NOR flash memory device, referring to Fig.23 , the ETOX NOR flash memory device comprises: A substrate 10, wherein the substrate 10 comprises a storage area and a peripheral logic area, wherein a gate oxide layer 20, a floating gate material layer 30, an ONO dielectric layer 40 and a control gate material layer 50 are formed on the substrate 10 of the storage area, and a pad oxide layer and a control gate material layer 50 are formed on the substrate 10 of the peripheral logic area; A capping layer 70, wherein the capping layer 70 covers the control gate material layer 50 of the storage region; A first deep trench 71 and a second deep trench 72, wherein the first deep trench 71 and the second deep trench 72 are located in the cap layer 70, the control gate material layer 50, the ONO dielectric layer 40, the floating gate material layer 30 and the gate oxide layer 20 of the storage area and are arranged alternately; A third deep trench 73, wherein the third deep trench 73 is located in the control gate material layer 50 and the liner oxide layer of the peripheral logic region; A source line ion implantation region 11, wherein the source line ion implantation region 11 is located in the substrate at the bottom of the first deep trench 71; A source line material layer 92 , wherein the source line material layer 92 fills the first deep trench 71 ; A storage area sidewall structure, wherein the storage area sidewall structure covers the sidewall of the second deep trench 72; A peripheral logic area sidewall structure, wherein the peripheral logic area sidewall structure covers the sidewall of the third deep trench 73; A first bit line ion implantation region 12 and a second bit line ion implantation region 13, wherein the first bit line ion implantation region 12 and the second bit line ion implantation region 13 are located in the substrate at the bottom of the second deep trench 72; A source / drain region 14, wherein the source / drain region 14 is located in the substrate 10 at the bottom of the third deep trench 73; A metal silicide layer 93, the metal silicide layer 93 covers the surface of the bit line ion implantation region 12 and the bit line ion implantation region 2 13 of the storage region, the surface of the source line material layer 92, and the surface of the control gate material layer 50 and the surface of the source / drain region 14 of the peripheral logic region; and An interlayer insulating dielectric layer 94 fills the second deep trench 72 and the third deep trench 73 and covers the cap layer 70, the metal silicide layer 93 at the top of the source line material layer 92 and the metal silicide layer 93 at the top of the control gate material layer 50 of the peripheral logic area.

[0055] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing an ETOX NOR flash memory device, characterized in that: include: A substrate is provided, the substrate comprising a storage area and a peripheral logic area, wherein a gate oxide layer, a floating gate material layer, an ONO dielectric layer and a control gate material layer are formed on the substrate of the storage area, and a pad oxide layer and a control gate material layer are formed on the substrate of the peripheral logic area; Thinning the control gate material layer of the storage area to a certain thickness; forming a capping layer, wherein the capping layer covers the control gate material layer of the storage area; Etching the remaining thickness of the control gate material layer, the ONO dielectric layer, the floating gate material layer and the gate oxide layer of the storage area to form a plurality of first deep trenches and a plurality of second deep trenches, wherein the first deep trenches and the second deep trenches are arranged in a staggered manner; forming an anti-reflection layer, wherein the anti-reflection layer fills the first deep trench and covers the control gate material layer of the peripheral logic region; Etching the control gate material layer and the pad oxide layer of the peripheral logic region to form a plurality of third deep trenches; forming a first spacer material layer and a second spacer material layer, wherein the first spacer material layer covers the sidewalls and bottom walls of the first deep trench, the second deep trench and the third deep trench, and the second spacer material layer covers the first spacer material layer; forming a sacrificial oxide layer, wherein the sacrificial oxide layer covers the second spacer material layer and fills the first deep trench, the second deep trench and the third deep trench; Planarizing the sacrificial oxide layer to the surface of the second spacer material layer; Coating a photoresist layer on the flat surfaces of the sacrificial oxide layer and the second spacer material layer; By photolithography and etching processes, the sacrificial oxide layer in the first deep trench of the storage area and the second spacer material layer and the first spacer material layer on the bottom wall of the first deep trench are etched away; forming a source line ion implantation region in the substrate at the bottom of the first deep trench by an ion implantation process; forming a source line material layer, wherein the source line material layer fills the first deep trench; Etching and removing the sacrificial oxide layer in the second deep trench of the storage area and the sacrificial oxide layer in the third deep trench of the peripheral logic area; forming a third spacer material layer, wherein the third spacer material layer fills the second deep trench and the third deep trench; Etching a portion of the third spacer material layer in the second deep trench, the second spacer material layer and the first spacer material layer on the bottom wall of the second deep trench to obtain a storage area spacer structure, and etching a portion of the third spacer material layer in the third deep trench, the second spacer material layer and the first spacer material layer on the bottom wall of the third deep trench to obtain a peripheral logic area spacer structure; Forming a bit line ion implantation region in the substrate at the bottom of the second deep trench and a source / drain region in the substrate at the bottom of the third deep trench by ion implantation processes respectively; Forming a metal silicide layer on the surface of the bit line ion implantation region, the surface of the source line material layer, the surface of the control gate material layer, and the surface of the source / drain region of the peripheral logic region through a self-aligned metal silicide process; and An interlayer insulating dielectric layer is formed, which fills the second deep trench and the third deep trench and covers the cap layer, the metal silicide layer on the top of the source line material layer and the metal silicide layer on the top of the control gate material layer of the peripheral logic area.

2. The method for preparing the ETOX NOR flash memory device according to claim 1, characterized in that: The step of etching and removing the sacrificial oxide layer in the first deep trench of the storage area and the second spacer material layer and the first spacer material layer on the bottom wall of the first deep trench by photolithography and etching processes comprises: By means of exposure and development processes, an opening pattern is defined on the photoresist layer at the top of the first deep trench; Through the opening pattern, a sacrificial oxide layer in the first deep trench of the storage area is removed by a wet etching process; and The second spacer material layer and the first spacer material layer are removed from the bottom wall of the first deep trench by a wet etching process.

3. The method for preparing the ETOX NOR flash memory device according to claim 1, characterized in that: After forming a source line ion implantation region in the substrate at the bottom of the first deep trench by an ion implantation process and before forming a source line material layer, the method for preparing the ETOX NOR flash memory device further includes: The photoresist layer is removed by ashing.

4. The method for preparing the ETOX NOR flash memory device according to claim 1, characterized in that: While etching part of the third sidewall material layer in the second deep trench, the second sidewall material layer and the first sidewall material layer on the bottom wall of the second deep trench to obtain the storage area sidewall structure, and etching part of the third sidewall material layer in the third deep trench, the second sidewall material layer and the first sidewall material layer on the bottom wall of the third deep trench to obtain the peripheral logic area sidewall structure, the second sidewall material layer and the first sidewall material layer on the top of the cap layer of the storage area are etched, and the second sidewall material layer and the first sidewall material layer on the top of the control gate material layer of the peripheral logic area are etched.

5. The method for preparing the ETOX NOR flash memory device according to claim 1, characterized in that: The material of the capping layer is silicon nitride; the material of the first sidewall material layer is silicon dioxide; the material of the second sidewall material layer is silicon nitride; and the material of the third sidewall material layer is silicon dioxide.

6. The method for preparing the ETOX NOR flash memory device according to claim 1, characterized in that: After forming the interlayer insulating dielectric layer, the method for preparing the ETOX NOR flash memory device further comprises: A first conductive plug, a second conductive plug and a third conductive plug are formed, wherein the first conductive plug penetrates the interlayer insulating dielectric layer and contacts the metal silicide layer on the surface of the bit line ion implantation region, the second conductive plug penetrates the interlayer insulating dielectric layer and contacts the metal silicide layer on the top of the source line material layer, and the third conductive plug penetrates the interlayer insulating dielectric layer and contacts the metal silicide layer on the surface of the source / drain region.

7. The method for preparing the ETOX NOR flash memory device according to claim 1, characterized in that: After etching the control gate material layer and the liner oxide layer of the peripheral logic region to form a plurality of third deep trenches, and before forming the first spacer material layer and the second spacer material layer, the method for preparing the ETOX NOR flash memory device further includes: The anti-reflection layer is removed.

8. An ETOX NOR flash memory device, characterized in that: include: A substrate, the substrate comprising a storage area and a peripheral logic area, wherein a gate oxide layer, a floating gate material layer, an ONO dielectric layer and a control gate material layer are formed on the substrate of the storage area, and a pad oxide layer and a control gate material layer are formed on the substrate of the peripheral logic area; A capping layer, wherein the capping layer covers the control gate material layer of the storage area; A first deep trench and a second deep trench, wherein the first deep trench and the second deep trench are located in the control gate material layer, the ONO dielectric layer, the floating gate material layer and the gate oxide layer of the storage area and are arranged alternately; a third deep trench, the third deep trench being located in the control gate material layer and the liner oxide layer of the peripheral logic region; a source line ion implantation region, the source line ion implantation region being located in the substrate at the bottom of the first deep trench; a source line material layer, wherein the source line material layer fills the first deep trench; A storage area sidewall structure, wherein the storage area sidewall structure covers a sidewall of the second deep trench; A peripheral logic area sidewall structure, wherein the peripheral logic area sidewall structure covers the sidewall of the third deep trench; a bit line ion implantation region, the bit line ion implantation region being located in the substrate at the bottom of the second deep trench; a source / drain region, the source / drain region being located in the substrate at the bottom of the third deep trench; A metal silicide layer, the metal silicide layer covers the surface of the bit line ion implantation region and the source line material layer of the storage region, and the surface of the control gate material layer and the source / drain region of the peripheral logic region; and An interlayer insulating dielectric layer fills the second deep trench and the third deep trench and covers the cap layer, the metal silicide layer on the top of the source line material layer and the metal silicide layer on the top of the control gate material layer of the peripheral logic area.

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