Manufacturing method of flash memory device
During the manufacturing process of SONOS flash memory devices, the top oxide layer and intermediate nitride layer of the ONO layer were removed by combining dry and wet etching, and the remaining ONO layer was removed by hydrofluoric acid treatment, which solved the problem of depressing the edge of the ONO layer and the residue of the HK dielectric layer, ensuring the normal operation of the flash memory device.
Patent Information
- Application Number
- CN202510039649.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-09
- Publication Date
- 2025-05-06
AI Technical Summary
During the manufacturing process of SONOS flash memory devices, the gate oxide layer in the IO device region is easily affected by wet etching of the ONO layer during the etching process, resulting in side depressions forming edges of the ONO layer, which in turn causes the HK dielectric layer to remain, affecting the normal operation of the device.
By depositing the first gate oxide layer on the semiconductor substrate layer, an ONO layer is formed, and the top oxide layer is removed by dry etching with the intermediate nitride layer as the etching stop layer. Then, the intermediate nitride layer is removed by wet etching, the remaining ONO layer is coated with hydrofluoric acid removal, forming a compensation oxide layer, and depositing the HK dielectric layer, and finally making and etching the gate polysilicon layer.
This method corrects the problem of side-extraction at the edge of the ONO layer, prevents the HK dielectric layer from remaining during the etching process, and ensures the normal operation of the flash memory device.
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Figure CN119947112A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing a flash memory device. Background Art
[0002] SONOS is the acronym for Silicon-Oxide-Nitride-Oxide-Silicon, which is a non-volatile memory that is closely related to flash memory. It differs from mainstream flash memory in that it uses silicon nitride instead of polysilicon as the storage material. One of its offshoots is SHINOS (Silicon-High Dielectric-Nitride-Oxide-Silicon). SONOS allows lower programming voltage and higher program-erase cycles than polysilicon flash memory, and is a relatively active development and research hotspot.
[0003] Embedded flash (E-Flash) is formed by embedding flash memory into CMOS (Complementary Metal-Oxide-Semiconductor Transistor). Embedded SONOS flash memory is based on the existing logic platform and embeds SONOS flash memory into the logic platform. It is widely praised by the market for its good process compatibility and low cost advantages.
[0004] SONOS flash memory uses a 2T structure (select-gate and cell-gate). Usually, the operating voltage of SONOS flash memory requires the input-output (IO) device voltage to be 3 to 6V, and the thickness of the gate oxide layer in the IO device area is much higher than the thickness of the top gate oxide layer of the ONO in the storage area. In order to ensure that the gate oxide layer is not damaged by ONO etching, the ONO layer is usually etched by dry etching the top oxide layer of the ONO first, and then wet etching the silicon nitride layer. A high dielectric constant material layer (High-k, HK) is used on the gate oxide layer at process nodes of 28nm and below. During gate etching, due to the isotropy of the wet etching of the ONO silicon nitride layer, the ONO layer will be undercut, resulting in the formation of a "C"-shaped HK layer residue at the edge of the ONO, which pollutes the machine.
[0005] Figure 8 FIG. 1 shows a schematic cross-sectional structure diagram of a SONOS flash memory device manufactured in the related art, from Figure 8 It can be seen that the SONOS flash memory device includes a storage device 10 formed in a storage area and an IO device area 20 formed between two adjacent storage devices 10. The IO device area 20 of the SONOS flash memory manufactured by the related art has the problem of "C"-type HK layer residue 21. Summary of the invention
[0006] The present application provides a method for manufacturing a flash memory device, which can solve the problem of abnormal operation in the related art.
[0007] In order to solve the technical problem in the background technology, the present application provides a method for manufacturing a flash memory device, and the method for manufacturing a flash memory device comprises the following steps:
[0008] providing a semiconductor substrate layer;
[0009] depositing a first gate oxide layer on the semiconductor substrate layer;
[0010] Depositing an ONO layer on the first gate oxide layer, the ONO layer comprising a bottom oxide layer, a middle nitride layer and a top oxide layer stacked in sequence from bottom to top;
[0011] Using the middle nitride layer as an etching stop layer, dry-etching the ONO layer to at least remove the top oxide layer in the ONO layer;
[0012] removing the intermediate nitride layer by wet etching;
[0013] Applying hydrofluoric acid to remove the lateral protrusions formed by the top oxide layer due to the side-digging of the remaining ONO layer by the wet etching;
[0014] Growing a compensation oxide layer on the remaining first gate oxide layer and the top oxide layer;
[0015] Deposition to form a HK dielectric layer;
[0016] A gate polysilicon layer is formed and the HK dielectric layer is etched.
[0017] Optionally, the step of dry etching the ONO layer using the middle nitride layer as an etch stop layer to remove at least a top oxide layer in the ONO layer comprises:
[0018] Using the intermediate nitride layer as an etching stop layer, with an etching stop surface located in the intermediate nitride layer, dry etching the ONO layer to remove the top oxide layer in the ONO layer and the upper portion of the intermediate nitride layer;
[0019] The step of removing the intermediate nitride layer by wet etching comprises:
[0020] The intermediate nitride layer remaining after the dry etching is removed by wet etching.
[0021] Optionally, in the step of using the intermediate nitride layer as an etch stop layer, with the etch stop surface located in the intermediate nitride layer, dry etching the ONO layer to remove the top oxide layer in the ONO layer and the upper portion of the intermediate nitride layer, dry etching the ONO layer to remove the upper portion accounting for one half to two thirds of the total thickness of the intermediate nitride layer.
[0022] Optionally, the step of dry etching the ONO layer using the middle nitride layer as an etch stop layer to remove at least a top oxide layer in the ONO layer comprises:
[0023] Using the middle nitride layer as an etching stop layer, with the etching stop surface located at the upper surface of the middle nitride layer, dry etching the ONO layer to remove the top oxide layer in the ONO layer;
[0024] The step of removing the intermediate nitride layer by wet etching comprises:
[0025] The intermediate nitride layer remaining after the dry etching is removed by wet etching.
[0026] Optionally, the step of removing the intermediate nitride layer by wet etching includes rinsing the intermediate nitride layer with 70% to 85% concentration phosphoric acid at a temperature of 155° C. to 170° C. for 50 seconds to 200 seconds to etch away the intermediate nitride layer.
[0027] Optionally, the step of applying hydrofluoric acid to remove the lateral protrusions of the top oxide layer formed by the side-digging of the remaining ONO layer by the wet etching includes: cleaning the top oxide layer with hydrofluoric acid at a concentration of 200:1 to 100:1 to remove the lateral protrusions of the top oxide layer formed by the side-digging of the remaining ONO layer by the wet etching.
[0028] Optionally, the step of growing a compensation oxide layer on the remaining first gate oxide layer and the top oxide layer comprises:
[0029] A compensation oxide layer is grown on the remaining first gate oxide layer and the top oxide layer through an in-situ water vapor oxidation process at a temperature of 950° C. to 1100° C. and a pressure of 5 bar to 10 bar.
[0030] Optionally, the thickness of the compensation oxide layer grown on the remaining first gate oxide layer and the top oxide layer is 10 angstroms to 30 angstroms.
[0031] The technical solution of the present application has at least the following advantages: the present application corrects the problem of side recesses formed at the edge of the remaining ONO layer, thereby preventing the HK dielectric layer from remaining during the etching process of the gate polysilicon and the HK dielectric layer thereunder. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0033] Figure 1 A flow chart of a method for manufacturing a flash memory device provided by an embodiment of the present application is shown;
[0034] Figure 2 A schematic diagram of the cross-sectional structure of the device after step S2 is completed is shown;
[0035] Figure 3 A schematic diagram of the cross-sectional structure of the device after step S3 is completed is shown;
[0036] Figure 4 Shown in Figure 3 A schematic diagram of a cross-sectional structure of a device with a patterned photoresist layer formed on the device structure shown;
[0037] Figure 5 It shows a schematic diagram of the cross-sectional structure of an ideal device after step S5 is completed;
[0038] Figure 6 A schematic diagram of the cross-sectional structure of the device after step S8 is completed is shown;
[0039] Figure 7 A schematic diagram of the cross-sectional structure of the device after step S9 is completed is shown;
[0040] Figure 8 FIG. 4 is a schematic cross-sectional structure diagram of a SONOS flash memory device manufactured in the related art. DETAILED DESCRIPTION
[0041] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0042] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0043] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0044] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0045] Figure 1 FIG. 1 shows a flow chart of a method for manufacturing a flash memory device provided by an embodiment of the present application. The method for manufacturing a flash memory device is used to manufacture a SONOS flash memory device. Figure 2 It can be seen that the manufacturing method of the flash memory device includes the following steps:
[0046] Step S1: providing a semiconductor substrate layer.
[0047] The semiconductor substrate layer includes a storage region for forming a storage device in a subsequent step, and an IO device region for forming an IO device in a subsequent step.
[0048] Step S2: depositing a first gate oxide layer on the semiconductor substrate layer.
[0049] Reference Figure 2 , which shows a schematic diagram of the cross-sectional structure of the device after step S2 is completed, from Figure 2 As can be seen in FIG. 1 , a first gate oxide layer 200 is deposited on the semiconductor substrate layer 100 . The first gate oxide layer 200 covers the storage area 101 and the IO device area 102 of the semiconductor substrate layer 100 .
[0050] Exemplarily, the thickness of the first gate oxide layer is 80 angstroms to 90 angstroms.
[0051] Step S3: depositing and forming an ONO layer on the first gate oxide layer, wherein the ONO layer comprises a bottom oxide layer, a middle nitride layer and a top oxide layer stacked in sequence from bottom to top.
[0052] Reference Figure 3 , which shows a schematic diagram of the cross-sectional structure of the device after step S3 is completed, from Figure 3 As can be seen in FIG. 1 , a bottom oxide layer 310 , a middle nitride layer 320 and a top oxide layer 330 having an ONO layer 300 are sequentially deposited on the first gate oxide layer 200 .
[0053] Exemplarily, the thickness of the bottom oxide layer 310 is 0.5 angstroms to 5 angstroms, and the thickness of the top oxide layer 330 is 30 angstroms to 60 angstroms.
[0054] Step S4: using the middle nitride layer as an etching stop layer, dry-etching the ONO layer to at least remove the top oxide layer in the ONO layer.
[0055] Step S5: removing the middle nitride layer by wet etching.
[0056] Before performing step S4, a patterned photoresist layer is formed on the ONO layer through a photolithography process. Figure 4 Shown in Figure 3 A schematic diagram of a device cross-sectional structure in which a patterned photoresist layer is formed on the device structure shown in FIG. Figure 4 It can be seen that the ONO layer 300 at the storage area 101 is covered with a photoresist layer 400 , and the ONO layer 300 at the IO device area 102 is covered with a photoresist layer 400 , forming an etching window 410 .
[0057] Can be based on this Figure 4 The pattern of the photoresist layer 400 is shown, and the ONO layer 300 is dry-etched to remove at least the top oxide layer 330 in the ONO layer 300 .
[0058] Exemplarily, when implementing step S4, based on the Figure 4 The pattern of the photoresist layer 400 is shown, with the middle nitride layer as an etch stop layer, the etch stop surface is located at the upper surface of the middle nitride layer, and the ONO layer is dry-etched to remove the top oxide layer in the ONO layer.
[0059] During the dry etching process, the middle nitride layer is not removed, and the middle nitride layer can be removed by a subsequent wet etching process in step S5.
[0060] When implementing step S4, based on the Figure 4The pattern of the photoresist layer 400 is shown, with the middle nitride layer as an etch stop layer, the etch stop surface is located in the middle nitride layer, and the ONO layer is dry-etched to remove the top oxide layer and part of the middle nitride layer in the ONO layer.
[0061] The remaining middle nitride layer that has not been dry-etched is used to protect the bottom oxide layer. The remaining middle nitride layer that has not been dry-etched can be wet-removed in the subsequent wet etching process in step S5.
[0062] Exemplarily, the wet etching solution for wet-removing the intermediate nitride layer in step S5 includes phosphoric acid with a concentration of 70% to 85% and a temperature of 150° C. to 170° C. The phosphoric acid is used to rinse the intermediate nitride layer for 50 seconds to 200 seconds, and the intermediate nitride layer is etched and removed. The phosphoric acid does not react with silicon oxide, and thus can protect the bottom oxide and the first gate oxide layer located at the lower side of the intermediate nitride layer.
[0063] Reference Figure 5 , which shows a schematic diagram of the cross-sectional structure of an ideal device after step S5 is completed. Figure 5 It can be seen that, ideally, the top oxide layer 330 and the middle nitride layer 320 of the ONO layer 300 at the position of the etching window 410 are etched away, and the edge of the remaining ONO layer 300 is smooth.
[0064] However, due to the isotropy of wet etching, the wet etching in step S5 not only etches the middle nitride layer vertically, but also causes a certain degree of lateral erosion to the middle nitride layer, thereby forming a side-digging depression at the edge of the remaining ONO layer, and the top oxide layer at the edge extends and protrudes from the side-digging position. The top oxide layer extending from the edge of the ONO layer is likely to cause HK dielectric layer residues during the subsequent HK dielectric layer deposition and etching process. To solve this problem, the following steps can be performed:
[0065] Step S6: applying hydrofluoric acid to remove the lateral protrusions formed on the top oxide layer due to the undercutting of the remaining ONO layer by the wet etching.
[0066] Reference Figure 5 , which shows a schematic diagram of the structure of the lateral protrusion formed on the top oxide layer due to the wet etching of the remaining ONO layer. Figure 5 It can be seen that the wet etching causes a certain degree of lateral erosion on the middle nitride layer, forming a side recess 500 at the edge of the remaining ONO layer 300, and the top oxide layer 330 at the edge extends and protrudes from the side recess 500 to form a lateral protrusion 331.
[0067] Exemplarily, hydrofluoric acid with a concentration of 200:1 and 100:1 can be used to remove the lateral protrusion 331 due to the wet etching to eliminate the undercut recess 500 formed at the edge of the remaining ONO layer 300, so that the edge of the remaining ONO layer 300 tends to be vertical.
[0068] After completing step S6, the device surface may be cleaned with deionized water to prevent hydrofluoric acid residue.
[0069] Step S7: growing a compensation oxide layer on the remaining first gate oxide layer and the top oxide layer.
[0070] Since step S6 applies hydrofluoric acid, in the process of removing the lateral protrusion formed by the top oxide layer due to the side digging of the remaining ONO layer by the wet etching, the hydrofluoric acid will also consume the first gate oxide layer and the top oxide layer, so after step S6 is completed, step S7 is performed to compensate for the consumed oxide layer. At the same time, the top oxide layer at the edge position of the ONO layer can be prevented from forming a lateral protrusion.
[0071] Exemplarily, in step S7, a compensation oxide layer can be grown on the remaining first gate oxide layer and the top oxide layer by an in-situ water vapor oxidation process at a temperature of 950° C. to 1100° C. and a pressure environment of 5 bar to 10 bar, and the thickness of the formed compensation oxide layer is 10 angstroms to 30 angstroms.
[0072] Step S8: depositing to form a HK dielectric layer, wherein the HK dielectric layer is a material with a high dielectric constant, usually a material layer with a dielectric constant greater than 3.9, for example, the material of the HK dielectric layer is titanium nitride.
[0073] Wherein, the HK dielectric layer covers the first gate oxide layer and the ONO layer.
[0074] In other embodiments, according to the thickness requirements of the gate oxide layer for different devices, a second gate oxide layer may be deposited again and etched according to the thickness requirements, and then deposited again to form an HK dielectric layer.
[0075] Figure 6 The schematic diagram of the cross-sectional structure of the device after step S8 is completed is shown. Figure 6 It can be seen that Figure 5 The lateral protrusion 331 formed by the top oxide layer 330 extending from the side recess 500 is etched away, and the edge position of the remaining ONO layer 300 tends to be vertical. Figure 6A region in the middle. Therefore, the HK dielectric layer 600 covering the first gate oxide layer 200 and the ONO layer 300 will not have an etch shielding area blocked. If the side-cut recess 500 formed at the edge of the remaining ONO layer 300 is not eliminated, the HK dielectric layer 600 will also be deposited on the surface of the side-cut recess 500, and the top oxide layer 330 extends and protrudes from the side-cut recess 500 to form a lateral protrusion 331, which causes etching shielding for the HK dielectric layer 600 covering the surface of the side-cut recess 500, that is, the HK dielectric layer 600 located on the surface of the side-cut recess 500 is an etching shielding area, so that when the subsequent etching process is carried out, the HK dielectric layer 600 on the surface of the side-cut recess 500 remains.
[0076] Step S9: forming a gate polysilicon layer and etching the HK dielectric layer.
[0077] For example, a blanket deposition of gate polysilicon may be performed on the HK dielectric layer, and then an etching pattern may be defined on the gate polysilicon by a photolithography process, and then the gate polysilicon may be etched based on the etching pattern to open the gate polysilicon not covered by the photoresist. During the etching of the gate polysilicon, the HK dielectric layer under the etched gate polysilicon is also etched and removed.
[0078] Figure 7 The schematic diagram of the cross-sectional structure of the device after step S9 is completed is shown. Figure 7 It can be seen that, since the above steps correct the problem of undercutting at the edge of the remaining ONO layer 300, the HK dielectric layer will not remain during the etching process of the gate polysilicon and the HK dielectric layer thereunder.
[0079] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A method for manufacturing a flash memory device, characterized in that: The method for manufacturing the flash memory device comprises the following steps: providing a semiconductor substrate layer; depositing a first gate oxide layer on the semiconductor substrate layer; Depositing an ONO layer on the first gate oxide layer, the ONO layer comprising a bottom oxide layer, a middle nitride layer and a top oxide layer stacked in sequence from bottom to top; Using the middle nitride layer as an etching stop layer, dry-etching the ONO layer to at least remove the top oxide layer in the ONO layer; removing the intermediate nitride layer by wet etching; Applying hydrofluoric acid to remove the lateral protrusions formed by the top oxide layer due to the side-digging of the remaining ONO layer by the wet etching; Growing a compensation oxide layer on the remaining first gate oxide layer and the top oxide layer; Deposition to form a HK dielectric layer; A gate polysilicon layer is formed and the HK dielectric layer is etched.
2. The method for manufacturing a flash memory device according to claim 1, wherein: The step of dry etching the ONO layer using the intermediate nitride layer as an etching stop layer to remove at least the top oxide layer in the ONO layer comprises: Using the intermediate nitride layer as an etching stop layer, with an etching stop surface located in the intermediate nitride layer, dry etching the ONO layer to remove the top oxide layer in the ONO layer and the upper portion of the intermediate nitride layer; The step of removing the intermediate nitride layer by wet etching comprises: The intermediate nitride layer remaining after the dry etching is removed by wet etching.
3. The method for manufacturing a flash memory device according to claim 2, wherein: In the step of using the intermediate nitride layer as an etching stop layer, the etching stop surface being located in the intermediate nitride layer, dry etching the ONO layer, and removing the top oxide layer in the ONO layer and the upper portion of the intermediate nitride layer, the ONO layer is dry-etched to remove the upper portion accounting for one-half to two-thirds of the total thickness of the intermediate nitride layer.
4. The method for manufacturing a flash memory device according to claim 1, wherein: The step of dry etching the ONO layer using the intermediate nitride layer as an etching stop layer to remove at least the top oxide layer in the ONO layer comprises: Using the middle nitride layer as an etching stop layer, with the etching stop surface located at the upper surface of the middle nitride layer, dry etching the ONO layer to remove the top oxide layer in the ONO layer; The step of removing the intermediate nitride layer by wet etching comprises: The intermediate nitride layer remaining after the dry etching is removed by wet etching.
5. The method for manufacturing a flash memory device according to any one of claims 1 to 4, characterized in that: The step of removing the intermediate nitride layer by wet etching includes washing the intermediate nitride layer with 70% to 85% concentration phosphoric acid at a temperature of 155° C. to 170° C. for 50 seconds to 200 seconds to etch away the intermediate nitride layer.
6. The method for manufacturing a flash memory device according to claim 1, wherein: The step of applying hydrofluoric acid to remove the lateral protrusions formed on the top oxide layer due to the side-digging of the remaining ONO layer by the wet etching comprises: cleaning the top oxide layer with hydrofluoric acid at a concentration of 200:1 to 100:1 to remove the lateral protrusions formed on the top oxide layer due to the side-digging of the remaining ONO layer by the wet etching.
7. The method for manufacturing a flash memory device according to claim 1, wherein: The step of growing a compensation oxide layer on the remaining first gate oxide layer and the top oxide layer comprises: A compensation oxide layer is grown on the remaining first gate oxide layer and the top oxide layer through an in-situ water vapor oxidation process at a temperature of 950° C. to 1100° C. and a pressure of 5 bar to 10 bar.
8. The method for manufacturing a flash memory device according to claim 1 or 7, wherein: A compensation oxide layer having a thickness of 10 angstroms to 30 angstroms is grown on the remaining first gate oxide layer and the top oxide layer.