Three-dimensional memory devices and methods of manufacturing the same

Abstract

This document discloses a three-dimensional memory device and a method for manufacturing the same. A semiconductor structure includes multiple layers of transistors stacked vertically. Each transistor layer includes: a first transistor array sharing a first common first-type terminal line; and a second transistor array sharing a second common first-type terminal line. The first transistor array and the second transistor array share a common second-type terminal line. The semiconductor structure also includes a first common first-type terminal contact structure coupled to the first common first-type terminal line in a first first-type terminal contact region; a second common first-type terminal contact structure coupled to the second common first-type terminal line in a second first-type terminal contact region; and a common second-type terminal contact structure coupled to the common second-type terminal line in a common second-type terminal contact region.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology, and more specifically, to a three-dimensional (3D) random access memory (RAM) device and a method of manufacturing the same. Background Technology

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells. Summary of the Invention

[0003] Embodiments of 3D memory devices and manufacturing methods are described in this disclosure.

[0004] One aspect of this disclosure provides a semiconductor structure comprising: a plurality of transistors stacked in a vertical direction, each transistor layer comprising: a first transistor array sharing a first common first type terminal line; a second transistor array sharing a second common first type terminal line, wherein the first transistor array and the second transistor array share a common second type terminal line; and a plurality of contact structures comprising: a first common first type terminal contact structure coupled to the first common first type terminal line in a first first type terminal contact region located on a first lateral side of the first transistor array away from the second transistor array; a second common first type terminal contact structure coupled to the second common first type terminal line in a second first type terminal contact region located on a second lateral side of the second transistor array away from the first transistor array; and a common second type terminal contact structure coupled to the common second type terminal line in a common second type terminal contact region located between the first transistor array and the second transistor array.

[0005] In some implementations, the transistor is a ferroelectric field-effect transistor (FeFET).

[0006] In some implementations, each FeFET includes: a channel layer, a ferroelectric layer having ferroelectric properties and surrounded by the channel layer in a horizontal plane, and a gate surrounded by the ferroelectric layer in a horizontal plane.

[0007] In some implementations, the channel layer comprises a metal-oxide-semiconductor material.

[0008] In some implementations, the channel layer of each FeFET has an elliptical ring shape in the horizontal plane.

[0009] In some embodiments, a first portion of the channel layer at the second end of the long diameter of the elliptical shape contacts a first common first type terminal line or a second common first type terminal line; and a second portion of the channel layer at the first end of the long diameter of the elliptical shape contacts a common second type terminal line.

[0010] In some embodiments, the first common first type terminal line includes a first U-shaped portion located between adjacent rows of the first transistor array and having a first opening facing away from the second transistor array; the second common first type terminal line includes a second U-shaped portion located between adjacent rows of the second transistor array and having a second opening facing away from the first transistor array.

[0011] In some implementations, the first type terminal is a drain terminal; the second type terminal is a source terminal; a first common first type terminal contact structure is connected to the first bit line; a second common first type terminal contact structure is connected to the second bit line; and a common second type terminal contact structure is connected to the source line.

[0012] In some embodiments, each of the plurality of contact structures is located in a dielectric stack within a first type of terminal contact region, a second type of terminal contact region, or a common second type of terminal contact region.

[0013] In some embodiments, the first common first type terminal lines of the multiple layers of the transistor overlap in the vertical direction; the second common first type terminal lines of the multiple layers of the transistor overlap in the vertical direction; and the common second type terminal lines of the multiple layers of the transistor overlap in the vertical direction.

[0014] In some embodiments, a contact structure of the intermediate stack of transistors includes: a conductive via extending vertically in a dielectric stack above the intermediate stack of transistors; a dielectric layer laterally surrounding the conductive via to isolate the contact structure from terminal lines of an upper transistor located above the intermediate stack of transistors; and an enlarged conductive end that is laterally electrically contacting a corresponding terminal line of the intermediate stack of transistors.

[0015] In some embodiments, the semiconductor structure further includes: a first isolation wall located between a first type terminal contact region and a first transistor array to isolate a first common type terminal line from a common type terminal line; and a second isolation wall located between a second type terminal contact region and a second transistor array to isolate a second common type terminal line from a common type terminal line.

[0016] Another aspect of this disclosure provides a semiconductor structure comprising: a plurality of vertically stacked layers of transistors, each layer of transistors including: a first transistor array sharing a first common first type terminal line; a second transistor array sharing a second common first type terminal line, wherein the first transistor array and the second transistor array share a common second type terminal line; and a plurality of contact structures, each of the plurality of contact structures being coupled to the first common first type terminal line, the second common first type terminal line, or the common second type terminal line; wherein each of the plurality of contact structures electrically coupled to an intermediate stack of transistors extends through a dielectric stack located above the intermediate stack of transistors.

[0017] In some implementations, the transistor is a ferroelectric field-effect transistor (FeFET).

[0018] In some implementations, each FeFET includes: a channel layer, a ferroelectric layer having ferroelectric properties and surrounded by the channel layer in a horizontal plane, and a control gate surrounded by the ferroelectric layer in a horizontal plane.

[0019] In some implementations, the channel layer comprises a metal-oxide-semiconductor material.

[0020] In some implementations, the channel layer of each FeFET cell has an elliptical ring shape in the horizontal plane.

[0021] In some embodiments, a first portion of the channel layer at the second end of the long diameter of the elliptical shape contacts a first common first type terminal line or a second common first type terminal line; and a second portion of the channel layer at the first end of the long diameter of the elliptical shape contacts a common second type terminal line.

[0022] In some embodiments, the first common first type terminal line includes a first U-shaped portion located between adjacent rows of the first transistor array and having a first opening facing away from the second transistor array; the second common first type terminal line includes a second U-shaped portion located between adjacent rows of the second transistor array and having a second opening facing away from the first transistor array.

[0023] In some embodiments, a plurality of contact structures include: a first common first type terminal contact structure coupled to a first common first type terminal line in a first first type terminal contact region located on a first lateral side of the first transistor array away from the second transistor array; a second common first type terminal contact structure coupled to a second common first type terminal line in a second first type terminal contact region located on a second lateral side of the second transistor array away from the first transistor array; and a common second type terminal contact structure coupled to a common second type terminal line in a common second type terminal contact region located between the first transistor array and the second transistor array.

[0024] In some implementations, the first type terminal is a drain terminal; the second type terminal is a source terminal; a first common first type terminal contact structure is connected to the first bit line; a second common first type terminal contact structure is connected to the second bit line; and a common second type terminal contact structure is connected to the source line.

[0025] In some embodiments, each contact structure includes: a conductive via extending vertically in a dielectric stack above an intermediate stack of transistors; a dielectric layer laterally surrounding the conductive via to isolate the contact structure from terminal lines of an upper transistor above the intermediate stack of transistors; and an enlarged conductive end that is laterally electrically contacting a corresponding terminal line of the intermediate stack of transistors.

[0026] In some embodiments, the first common first type terminal lines of the multiple layers of the transistor overlap in the vertical direction; the second common first type terminal lines of the multiple layers of the transistor overlap in the vertical direction; and the common second type terminal lines of the multiple layers of the transistor overlap in the vertical direction.

[0027] In some embodiments, the semiconductor structure further includes: a first isolation wall located between a first type terminal contact region and a first transistor array to isolate a first common type terminal line from a common type terminal line; and a second isolation wall located between a second type terminal contact region and a second transistor array to isolate a second common type terminal line from a common type terminal line.

[0028] Another aspect of this disclosure provides a method for forming a semiconductor structure, comprising: forming a dielectric stack comprising a plurality of first dielectric layers and second dielectric layers alternately stacked in a vertical direction; forming a plurality of vias in the dielectric stack; forming a plurality of sacrificial through-hole structures in the plurality of vias; replacing portions of the second dielectric layers with conductive lines; replacing the plurality of sacrificial through-hole structures with a plurality of transistor structures; and forming a plurality of contact structures, each of the plurality of contact structures being coupled to a corresponding conductive line and penetrating the remaining portion of the dielectric stack above the corresponding conductive line.

[0029] In some embodiments, forming multiple sacrificial through-hole structures includes: removing portions of the second dielectric layer exposed by the multiple vias to form multiple recesses on the sidewalls of the multiple vias; and depositing sacrificial material to fill the multiple recesses and the multiple vias.

[0030] In some embodiments, replacing multiple sacrificial punch-through structures with multiple transistor structures includes: removing multiple sacrificial punch-through structures from multiple recesses and multiple vias; forming multiple channel layers in the multiple recesses; forming a ferroelectric layer on the sidewall of each via, wherein the ferroelectric layer is ferroelectric and is laterally surrounded by the channel layers; and forming a gate structure in each via, wherein the gate structure is laterally surrounded by the ferroelectric layer.

[0031] In some embodiments, the channel layer comprises a metal-oxide-semiconductor material in direct contact with the conductive layer.

[0032] In some implementations, the metal oxide semiconductor material is indium gallium zinc oxide (IGZO).

[0033] In some embodiments, replacing portions of the second dielectric layer with conductive lines includes: forming a plurality of gaps through the dielectric stack; removing portions of the second dielectric layer from the plurality of gaps to form a plurality of horizontal openings; forming conductive lines in the plurality of horizontal openings; and filling the plurality of gaps with a dielectric material.

[0034] In some embodiments, forming a plurality of through holes includes forming each through hole having an elliptical shape in a horizontal plane.

[0035] In some embodiments, the method further includes: forming an isolation wall that extends vertically through the dielectric stack, such that conductive lines formed in each stack are divided by the isolation wall to include: a first common first type terminal line shared by a first array of ferroelectric field-effect transistor (FeFET) cells in the layer; a second common first type terminal line shared by a second transistor array in the layer; and a common second type terminal line shared by the first transistor array and the second transistor array.

[0036] In some embodiments, a first portion of the channel layer at the first end of the long diameter of the elliptical shape is formed to contact a common second type terminal line; and a second portion of the channel layer at the second end of the long diameter of the elliptical shape is formed to contact a first common first type terminal line or a second common first type terminal line.

[0037] In some embodiments, the first common first type terminal line is formed to include a first U-shaped portion located between adjacent rows of the first transistor array and having a first opening facing away from the second transistor array; the second common first type terminal line is formed to include a second U-shaped portion located between adjacent rows of the second transistor array and having a second opening facing away from the second transistor array.

[0038] In some embodiments, a plurality of contact structures are formed, including: forming a first common first type terminal contact structure coupled to a first common first type terminal line and located on a first lateral side of the first transistor array away from the second transistor array; forming a second common first type terminal contact structure coupled to a second common first type terminal line and located on a second lateral side of the second transistor array away from the first transistor array; and forming a common second type terminal contact structure coupled to a common second type terminal line and located between the first transistor array and the second transistor array.

[0039] In some embodiments, forming one of a plurality of contact structures includes: forming a contact hole that extends through the upper portion of the remainder of the dielectric stack and stops at a second dielectric layer located at the same horizontal plane as a corresponding conductive line; forming a dielectric fill structure to fill the contact hole; performing a punch etching to remove a portion of the dielectric fill structure to expose a portion of a second dielectric layer adjacent to a corresponding conductive line; removing a portion of a second dielectric layer to expose a corresponding conductive line; and depositing a conductive material in the contact hole to form a contact structure such that the contact structure is isolated from the conductive line above the corresponding conductive line and is electrically contacted with the corresponding conductive line in the lateral direction.

[0040] In some embodiments, first common first type terminal lines in multiple layers of conductive wire are formed to overlap in the vertical direction; second common first type terminal lines in multiple layers of conductive wire are formed to overlap in the vertical direction; and common second type terminal lines in multiple layers of conductive wire are formed to overlap in the vertical direction.

[0041] Other aspects of this disclosure will be understood by those skilled in the art based on the specification, claims, and drawings. Attached Figure Description

[0042] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0043] Figure 1 A schematic cross-section of a FeFET according to some embodiments of the present disclosure is shown.

[0044] Figure 2 The charge distribution in the storage film of a 3D FeFET RAM cell during erase and programming operations is shown according to some embodiments of the present disclosure.

[0045] Figure 3 A schematic top view of a 3D FeFET according to some embodiments of the present disclosure is shown.

[0046] Figure 4 A schematic top view of a patterned design of a 3D storage array structure according to some embodiments of the present disclosure is shown.

[0047] Figure 5 Some embodiments according to this disclosure are shown, such as Figure 4 The diagram shows a schematic circuit design of the 3D storage array structure.

[0048] Figures 6A-6C A schematic top view of a patterned design of a 3D memory structure according to some embodiments of the present disclosure is shown.

[0049] Figure 7 Some embodiments according to this disclosure are shown, such as Figures 6A-6C A schematic circuit diagram of another pattern design of the 3D storage array structure shown.

[0050] Figure 8 A flowchart of a method for forming a 3D memory structure according to some embodiments of the present disclosure is shown.

[0051] Figure 9A Some embodiments according to this disclosure are shown in Figure 8 A schematic cross-sectional side view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0052] Figure 9B Some embodiments according to this disclosure are shown in Figure 8 A schematic top view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0053] Figure 10 Some embodiments according to this disclosure are shown in Figure 8A schematic cross-sectional side view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0054] Figure 11A Some embodiments according to this disclosure are shown in Figure 8 A schematic cross-sectional side view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0055] Figure 11B Some embodiments according to this disclosure are shown in Figure 8 A schematic top view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0056] Figure 12A Some embodiments according to this disclosure are shown in Figure 8 A schematic cross-sectional side view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0057] Figure 12B Some embodiments according to this disclosure are shown in Figure 8 A schematic top view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0058] Figure 13A Some embodiments according to this disclosure are shown in Figure 8 A schematic cross-sectional side view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0059] Figure 13B Some embodiments according to this disclosure are shown in Figure 8 A schematic top view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0060] Figure 14A Some embodiments according to this disclosure are shown in Figure 8 A schematic cross-sectional side view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0061] Figure 14B Some embodiments according to this disclosure are shown in Figure 8 A schematic top view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0062] Figure 15A Some embodiments according to this disclosure are shown in Figure 8 A schematic cross-sectional side view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0063] Figure 15B Some embodiments according to this disclosure are shown in Figure 8 A schematic top view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0064] Figure 16A Some embodiments according to this disclosure are shown in Figure 8 A schematic cross-sectional side view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0065] Figure 16B Some embodiments according to this disclosure are shown in Figure 8 A schematic top view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0066] Figure 17A Some embodiments according to this disclosure are shown in Figure 8 A schematic cross-sectional side view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0067] Figure 17B Some embodiments according to this disclosure are shown in Figure 8 A schematic top view of the 3D memory structure at a specific manufacturing stage of the method shown.

[0068] The features and advantages of the invention will become more apparent when viewed in conjunction with the accompanying drawings, in which similar reference numerals identify corresponding elements. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The first appearance of an element in the drawing is indicated by the leftmost (or more) numerals in the corresponding reference numerals.

[0069] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0070] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other constructions and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0071] Note that references to "one embodiment," "implementation," "exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment must include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0072] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, again depending at least partly on the context, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described.

[0073] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on something,” but also includes the meaning of “on something” with an intermediate feature or layer between them. Furthermore, “above” or “on top of” not only means “above something” or “on top of something,” but can also include the meaning of “above something” or “on top of something” without an intermediate feature or layer between them (i.e., directly on something).

[0074] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another (or more) shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the equipment during use or process steps. The equipment may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0075] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore, the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0076] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper overlay structure, or may have a range smaller than that of the lower or upper overlay structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnect lines, and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0077] In this disclosure, for ease of description, the term "tier" is used to refer to elements having substantially the same height in the vertical direction. For example, a word line and a lower gate dielectric layer can be referred to as a "tier", a word line and a lower insulating layer can be referred to together as a "tier", word lines having substantially the same height can be referred to as a "tier of word lines", and so on.

[0078] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter set for a component or process step during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may be due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates the value of a given quantity that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate the value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0079] In this disclosure, the terms "horizontal / horizontally / laterally" mean nominally parallel to the lateral surface of the substrate, and the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0080] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having a string of vertically oriented memory cell transistors (referred to herein as a “memory string”) on a laterally oriented substrate, such that the memory string extends in a vertical direction relative to the substrate.

[0081] In 3D NAND flash memory, memory cells can be programmed for data storage based on charge trapping technology. The stored information in a memory cell depends on the amount of charge trapped in the storage layer. Although 3D NAND flash memory can be high-density and cost-effective, it suffers from low write speeds and high power consumption at the system level due to the required peripheral devices (e.g., charge pumps). On the other hand, phase-change memories generally have large leakage currents and high power consumption. Therefore, there is a need to develop a new type of high-speed and high-density storage-class memory (SCM).

[0082] Ferroelectric field-effect transistor (FeFET) random access memory (RAM) is a high-performance and low-power non-volatile memory that combines the advantages of conventional non-volatile memories (e.g., flash memory and EEPROM) and high-speed RAMs (e.g., SRAM and DRAM). FeFET RAM can outperform existing memories such as EEPROM and flash memory, offering lower power consumption, faster response times, and greater robustness to multiple read / write operations. Traditional planar FeFET RAM is difficult to scale down. By replacing the charge-trapping storage layer in 3D NAND flash memory with a ferroelectric material (e.g., Si:HfO2), FeFET RAM with a similar 3D NAND architecture can achieve scalable dimensions without performance loss. However, due to the small size of the source and drain contacts in existing 3D FeFET RAM architectures, it is difficult to separate the source and drain leads to enable individual access to each memory cell. Therefore, the development of a novel 3D architecture for FeFET RAM is desired.

[0083] Figure 1 A schematic cross-section of a FeFET 100 according to some embodiments of the present disclosure is shown. The FeFET 100 may include a control gate 110, a storage film 120, a channel layer 130, and source / drain electrodes 140.

[0084] In the FeFET 100, a storage film 120 may be located between a control gate 110 and a channel layer 130, and may include a barrier layer 122, a ferroelectric layer 124, an electrode layer 126, and an interface layer 128. In some embodiments, the barrier layer 122 is located between the control gate 110 and the ferroelectric layer 124. The control gate 110 may be a metal layer or a polysilicon layer. The barrier layer 122 may be used to block the interaction between the ferroelectric layer 124 and the control gate 110. The barrier layer 122 may have a thickness in the range of about 5 nm to about 50 nm. The barrier layer may include titanium nitride (TiN), silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2O2N), high-k dielectric materials (e.g., HfO2, Al2O3), and / or any combination thereof. The barrier layer 122 may be formed by any suitable physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0085] In some embodiments, the ferroelectric layer 124 may comprise a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). In some embodiments, the ferroelectric layer 124 may comprise a high-k (i.e., high dielectric constant) dielectric material, which may comprise transition metal oxides, such as hafnium zirconium oxide (HZO), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (Ta2O5), tungsten oxide (WO3), molybdenum oxide (MO3), vanadium oxide (V2O3), lanthanum oxide (La2O3), and / or any combination thereof. In some embodiments, the high-k dielectric material may be doped to improve ferroelectric properties. For example, the ferroelectric layer 124 may be HZO or HfO2 doped with silicon (Si), (yttrium)y, gadolinium (Gd), lanthanum (La), zirconium (Zr), or aluminum (Al), or any combination thereof. In some embodiments, the ferroelectric layer 124 may include zirconium titanate (PZT), strontium bismuth tantalate (SrBi2Ta2O9), barium titanate (BaTiO3), PbTiO3, and BLT ((Bi,La)4Ti3O9). 12 (or any combination thereof).

[0086] In some embodiments, the ferroelectric layer 124 can be formed by chemical vapor deposition (CVD) (e.g., metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma-enhanced chemical vapor deposition (HDP-CVD), etc.). The ferroelectric layer 124 can also be formed by atomic layer deposition (ALD), sputtering, evaporation, or any combination thereof. In some embodiments, the ferroelectric layer 124 can have a thickness in the range of 5 nm to 100 nm.

[0087] In some embodiments, the interface layer 128 may be located between the ferroelectric layer 124 and the channel layer 130. The interface layer 128 can be used to reduce the possibility of material mixing between the ferroelectric layer 124 and the channel layer 130. In this example, the effective gate dielectric of the FeFET is a combination of the ferroelectric layer 124 and the interface layer 128. A thinner effective gate dielectric can provide better control over the channel layer 130 from the control gate 110. Therefore, the thickness of the interface layer 128 can be in the range of about 5 nm to about 50 nm. In some embodiments, the interface layer 128 may be silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials (e.g., HfO2, HfAlO, Al2O3) and / or any combination thereof. The interface layer 128 can be formed by any suitable film deposition technique, such as ALD, CVD, sputtering, evaporation and / or any combination thereof. The interface layer 128 can also be formed by oxidation, nitriding and / or combinations thereof.

[0088] In some embodiments, the storage film 120 may further include an electrode layer 126 located between the ferroelectric layer 124 and the interface layer 128. Thus, the control gate 110, the ferroelectric layer 124, and the electrode layer 126 form a metal-insulator-metal (MIM) capacitor 161, which is connected in series with a floating gate transistor (FG-MOSFET) 163 in which the electrode layer 126 serves as a floating gate and the interface layer 128 serves as a gate dielectric.

[0089] In some embodiments, the channel layer 130 may comprise amorphous silicon, polycrystalline silicon, monocrystalline silicon, and / or any combination thereof. The channel layer 130 may be formed using any suitable thin-film deposition technique (e.g., ALD, CVD, sputtering, etc.). In some embodiments, portions of the channel layer 130 may be doped to form source / drain electrodes 140 on each side of the channel layer 130, respectively. In other embodiments, the source / drain electrodes 140 may be a metal layer formed on the channel layer 130.

[0090] refer to Figure 2 This illustrates the charge distribution in the storage film of a FeFET during erase and programming operations according to some embodiments of the present disclosure. It should be noted that, for simplicity, in Figure 3 The barrier layer 222, electrode layer 226, and interface layer 228 of the FeFET are omitted.

[0091] In such Figure 2 During the programming operation shown in the left figure, the programming voltage V applied to the control gate 210 p Provides a positive voltage (V) greater than the coercive voltage across the ferroelectric film 224. p >V cFerroelectric film 224 can have positive remanent polarization P r The charge direction is from the control gate 210 towards the channel layer 230. As a result, the top surface charge near the control gate 210 is negative, while the bottom surface charge near the channel layer 230 is positive. The positive bottom surface charge near the channel layer 230 can reduce the transistor's threshold voltage V. th Therefore, the corresponding capacitor control performed by the FeFET can be programmed to operate at a low threshold voltage V. th_L And it is set to logical state "1".

[0092] In such Figure 2 During the erase operation shown in the right figure, the erase voltage -V p A negative voltage (e.g.) is applied to the control gate 210, the magnitude of which is greater than the reverse coercive voltage (i.e., |-V) p |>|-V c |), the ferroelectric film 224 can be negatively polarized to have a reverse residual polarization -P r The charge direction is from the channel layer 230 to the control gate 210. The top surface charge near the control gate 210 is positive, while the bottom surface charge near the channel layer 230 is negative. The negative bottom surface charge near the channel layer 230 can increase the threshold voltage V of the transistor. th Therefore, the corresponding capacitor control performed by the FeFET can be programmed to a high threshold voltage V. th_H And it is reset to logical state "0".

[0093] It should be pointed out that the coercive field E c Coercive voltage V c Programming voltage V p and residual polarization P r It is not necessarily symmetric around zero. Positive and negative values ​​can have different magnitudes. To simplify the following discussion, it is assumed that they are the same size in opposite directions. Those skilled in the art should be able to apply the following method to general conditions.

[0094] As discussed above, by applying an appropriate voltage pulse to the control gate 210, the polarization direction of the ferroelectric film 224 can be switched, and the threshold voltage of the FeFET can be changed. This affects the conductivity of the channel layer 230 and the on / off state of the FeFET. The corresponding logic state (or stored data) controlled by the FeFET's capacitor can be determined accordingly.

[0095] In some implementations, during the read operation (in Figure 2During (not shown), by applying a read voltage Vread to the control gate 210, the conductance of the channel layer 230 can be measured from the source / drain electrodes 240 of the FeFET. The corresponding DRAM memory cell including the FeFET and the logic state or threshold voltage controlled by the corresponding capacitor of the FeFET can be verified. Compared to conventional NAND cells that operate based on charge trapping in the storage film, FeFET RAM cells can instead be controlled by polarization in the ferroelectric film 224.

[0096] It should be pointed out that, Figure 1 The electrode layer 126 shown can be optional. During FeFET operation, the voltage of electrode layer 126 is determined by the amount of charge on the bottom surface of ferroelectric films 124 / 224. By switching the polarization direction in ferroelectric layers 124 / 224, the amount of charge on the bottom surface can be changed, and the voltage of electrode layer 126 can be changed accordingly. Therefore, the threshold voltage of FeFET can be changed. Electrode layer 126 in FeFET can provide functionality similar to the floating gate in a conventional NAND memory cell, except that the voltage of electrode layer 126 is controlled by the polarization of ferroelectric layers 124 / 224. The voltage applied to control gates 110 / 210 is distributed between MIM capacitor 161 and FG-MOSFET 163. As a result, a relatively large voltage is required to switch the polarization of ferroelectric layers 124 / 224. To reduce the write voltage, a thinner ferroelectric layer 124 / 224 can be used in some embodiments. By scaling the thickness of the ferroelectric layers 124 / 224, the MIM capacitor 161 can have a larger capacitance, allowing a larger portion of the applied voltage to be dropped across the MIM capacitor 161.

[0097] refer to Figure 3 This diagram illustrates a schematic top view of a 3D FeFET according to some embodiments of the present disclosure. The 3DFeFET 300 may include a control gate 310, a barrier layer 322, a ferroelectric film 324, an interface layer 328, a channel layer 330, and source / drain electrodes 340. It should be noted that the source and drain electrodes 340 are separated by an insulating layer, which is omitted for simplicity. The channel layer 330 may be in physical contact with the source / drain electrodes 340 and may surround the interface layer 328 in the XY plane of cross-section. The interface layer 328 may surround the ferroelectric film 324 in the XY plane of cross-section. The ferroelectric film 324 may surround the barrier layer 322 in the XY plane of cross-section. The barrier layer 322 may surround the control gate 310 in the XY plane of cross-section.

[0098] In some embodiments, the control gate 310, barrier layer 322, ferroelectric film 324, interface layer 328, and channel layer 330 can form a through-structure 380 located in a via extending in a vertical direction perpendicular to the horizontal XY plane. The cross-section of the via in the horizontal XY plane can be as follows: Figure 4 The elliptical shape is shown. In some embodiments, the ratio between the long diameter L1 and the short diameter L2 of the through-structure 380 is greater than 1. In some embodiments, the long diameter L1, the short diameter L2, and the ratio L1 / L2 can be determined based on the total number of 3D FeFET RAM cells in the vertical direction in each memory string. For example, as the total number of 3D FeFET RAM cells in each memory string increases, the dimensions of the long diameter L1 and the short diameter L2, as well as the ratio L1 / L2, can be increased. In some embodiments, the long diameter L1 of the through-structure 380 can provide an option for increased contact area and / or multiple contact regions for landing control gate contacts. This enhances the gate control capability of the 3D memory device.

[0099] refer to Figure 4 This diagram shows a schematic top view of a patterned design of a 3D storage array structure 400 according to some embodiments of the present disclosure. In the XY plane, the 3D storage array structure 400 may include a plurality of through-structures 480 arranged in an array. Similar to Figure 3 As shown, each of the multiple through-structures 480 can have an elliptical shape in cross-section in the horizontal XY plane. The short diameter of each through-structure 480 can be along a first lateral direction (e.g., the X direction), and the long diameter of each through-structure 480 can be along a second lateral direction (e.g., the Y direction). The array of through-structures 480 can share a common source line 442 and a common bit line 444. It should be noted that in Figure 4 For illustrative purposes and for simplicity, five through-structures 480 are shown in each row. In some implementations, the number "n" of through-structures 480 in each row can be greater than five to increase storage capacity.

[0100] like Figure 4As shown, both source line 442 and bit line 444 may include trunks (also referred to as "common source trunks" and "common bit trunks") extending along the Y direction and located on each side of the array of through-structures 480, respectively, and may also include multiple branches (also referred to as "common source branches" and "common bit branches") located in an alternating manner between adjacent rows of through-structures 480. In some embodiments, each branch of source line 442 or bit line 444 may have a U-shaped portion or a single stripe shape and extend along the X direction. That is, both source line 442 and bit line 444 may have a comb shape and may be placed face-to-face by alternating single stripe teeth. Source line 442 and bit line 444 are separated by insulating layer 434.

[0101] Each row of through-structures 480 is arranged between adjacent branches of source line 442 and bit line 444. That is, there is a common source branch and a common bit branch between adjacent rows of through-structures 480. The lower ends of multiple through-structures 480 in each row can jointly contact one branch of source line 442, and the upper ends of multiple through-structures 480 in each row can jointly contact an adjacent branch of source line 442. In this way, the channel layer of multiple through-structures 480 in the same row (e.g., as shown in Figure 444) Figure 3 The channel layer 330 shown can be in physical contact with the common source line 442 and the common potential line 444.

[0102] In addition, such as Figure 4 As shown, the 3D memory array structure 400 may include a plurality of gate lines 416 (also referred to as “word lines”) arranged parallel to each other and extending along a second lateral direction (e.g., the Y direction). Since there are two rows of through-structures 480 in each finger, two gate lines 416 can be arranged for each column of two through-structures 480, one of which can be connected via a first control gate contact 412 to the control gate of the through-structure 480 in the first row (e.g., as shown). Figure 3 The control gate 310 shown is shown, and another gate line 416 can be connected to the control gate of the through-structure 480 in the second row via a second control gate contact 414. As described above... Figure 3 The elliptical shape of the through-structure 480 in the XY plane, as discussed, can provide an option for increased contact area and / or multiple contact regions for landing the first control gate contact 412 or the second control gate contact 414.

[0103] Figure 5 As shown Figure 4The schematic circuit diagram 500 shows a pattern design of the 3D memory array structure 400. It should be noted that the schematic circuit diagram 500 corresponds to a 3D FeFET RAM cell in one layer of a 3D memory array structure in the XY plane. Figure 5 As shown, each row of FeFETs includes n FeFETs. The array of FeFETs shares a common source line SL_1 and a common bit line BL_1. Gate lines GL_1, ..., GL_2n, numbered 2n, can each be connected to their respective FeFETs, allowing independent control of the 2n FeFETs. Therefore, each memory cell of the 3D memory array structure 500 can be randomly accessed.

[0104] refer to Figure 6A A schematic top view 600A of a patterned design of a 3D memory structure according to some embodiments of the present disclosure is shown. Reference Figure 6B The diagram illustrates some embodiments of the present disclosure along line AA'. Figure 6A A schematic cross-sectional side view 600B of the 3D memory structure shown. (Reference) Figure 6C The diagram illustrates some embodiments of the present disclosure along the BB' line, or the CC' line, or the DD' line. Figure 6A The 3D memory structure shown is a cross-sectional side view 600C.

[0105] like Figure 6B As shown, the 3D memory array structure includes a substrate 610 and a film stack 620 located on the substrate 610. In some embodiments, the substrate 610 can be any suitable semiconductor substrate having any suitable structure, such as a single-layer silicon substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polycrystalline silicon and metal multilayer substrate, etc. In a vertical direction (i.e., the Z direction) perpendicular to the top surface of the substrate 610, the film stack 620 may include alternately stacked first dielectric layers 622 and second dielectric layers 624. Figures 6A-6C As shown, a plurality of conductive lines 640 (including 642, 644, and 646) may be located on the same horizontal plane as the second dielectric layer 624. The conductive lines 640 and the second dielectric layer 624 are sandwiched between adjacent first dielectric layers 622.

[0106] In the first lateral direction (i.e., the X direction), the 3D memory array structure includes a first contact region 671 located on the first lateral side of the 3D memory array structure, a second contact region 673 located on the second lateral side of the 3D memory array structure, and a third contact region 675 located in the middle of the 3D memory array structure. The 3D memory array structure also includes a first transistor array 691 located between the first contact region 671 and the third contact region 675, and a second transistor array 699 located between the second contact region 673 and the third contact region 675.

[0107] In the vertical direction (i.e., the Z-direction), the first transistor array 691 and the second transistor array 699 include multiple memory strings formed in multiple vias extending through the film stack 620, respectively. The vias can be formed by removing portions of the first dielectric layer 622, the second dielectric layer 624, and the conductive lines 640, exposing the inner sidewalls of the first dielectric layer 622, the second dielectric layer 624, and the conductive lines 640. A through-structure 680 can be formed in each via. In some embodiments, the through-structure 680 may include a channel layer on the sidewall of the via, a memory film on the sidewall of the channel layer, and a core control gate surrounded by the memory film. Thus, the through-structure 680 and the multiple conductive lines 640 in the film stack 620 can form a row of 3D FeFETs stacked in the vertical direction (Z-direction).

[0108] like Figure 6A As shown, each FeFET layer in the lateral XY plane may include a first transistor array 691 sharing a first common first-type terminal line 642 extending into a first contact region 671, and a second transistor array 699 sharing a second common first-type terminal line 644 extending into a second contact region 673. The first transistor array 691 and the second transistor array 699 may share a common second-type terminal line 646 extending into a third contact region 675. In some embodiments, a first portion of the channel layer located at the second end of the long diameter of the elliptical through-structure 680 contacts either the first common first-type terminal line 642 or the second common first-type terminal line 644. A second portion of the channel layer located at the first end of the long diameter of the elliptical through-structure 680 contacts the common second-type terminal line 646. The second-type terminal may be a source terminal, therefore, as... Figure 6A As shown, the common second-type terminal line can serve as the common source line for each row of transistors.

[0109] In some embodiments, the first common first-type terminal line 642 includes a first U-shaped portion located between adjacent rows of the first transistor array 691 and having a first opening facing away from the second transistor array 699. The second common first-type terminal line 644 includes a second U-shaped portion located between adjacent rows of the second transistor array 699 and having a second opening facing away from the first transistor array 691. In some embodiments, the first-type terminal may be a drain terminal, therefore the first common first-type terminal line 642 can be used as a common drain line of the first transistor array 691, and the second common first-type terminal line 644 can be used as a common drain line of the second transistor array 699.

[0110] like Figure 6B As shown, the first common first type terminal lines 642 of the transistor's multiple layers overlap in the vertical direction, and the second common first type terminal lines 644 of the transistor's multiple layers overlap in the vertical direction. Although not shown, the common second type terminal lines 646 of the transistor's multiple layers overlap in the vertical direction.

[0111] like Figures 6A-6C As shown, the 3D memory array structure includes multiple contact structures 650 (including 652, 654, and 656). A first common first-type terminal contact structure 652 can be coupled to a first common first-type terminal line 642 and is located in a first first-type terminal contact region 671, which is located on a first lateral side of the first transistor array 691 away from the second transistor array 699. A second common first-type terminal contact structure 654 can be coupled to a second common first-type terminal line 644 and is located in a second first-type terminal contact region 673, which is located on a second lateral side of the second transistor array 699 away from the first transistor array 691. A common second-type terminal contact structure 656 can be coupled to a common second-type terminal line 646 and is located in a common second-type terminal contact region 675, which is located between the first transistor array 691 and the second transistor array 699.

[0112] In some embodiments, each first common first type terminal contact structure 652 coupled to a corresponding first common first type terminal line 642 may be connected between a first bit line (not shown) and the drain terminal of a first transistor array 691 in the same layer as the corresponding first common first type terminal line 642. Each second common first type terminal contact structure 654 coupled to a corresponding second common first type terminal line 644 may be connected between a second bit line (not shown) and the drain terminal of a second transistor array 699 in the same layer as the corresponding second common first type terminal line 644. Each common second type terminal contact structure 656 coupled to a corresponding common second type terminal line 646 may be connected between a source line (not shown) and the source terminal of a row of transistors in the same layer as the corresponding second common first type terminal line 646.

[0113] like Figure 6C As shown, the contact structure 650 may include a conductive via extending vertically within the membrane stack 620. The conductive via may include a conductive layer 674 located on the sidewalls and bottom surface of the contact via, and a conductive fill structure 676 filling the contact via. The conductive via may also include an enlarged conductive end 679 that is laterally electrically contacting a corresponding terminal line 640. The contact structure 650 may also include a spacer layer 672 laterally surrounding the conductive via to isolate the conductive via from other terminal lines 640.

[0114] In some implementations, such as Figures 6A-6B As shown, the 3D memory array structure also includes a first isolation wall 629 located between the first first-type terminal contact region 671 and the first transistor array 691 to isolate the first common first-type terminal line 642 from the common second-type terminal line 646. The 3D memory array structure also includes a second isolation wall 649 located between the second first-type terminal contact region 673 and the second transistor array 699 to isolate the second common first-type terminal line 644 from the common second-type terminal line 646.

[0115] Figure 7 It is shown that, according to, Figures 6A-6C The schematic circuit diagram 700 shows a patterned 3D memory array structure. It should be noted that schematic circuit diagram 700 corresponds to a 3DFeFET in one layer of a 3D memory array structure in the XY plane. Figure 7As shown, the FeFETs in the first row share the first common source line SL_1, and the FeFETs in the second row share the second common source line SL_2. The array of FeFETs on the left shares the first common bit line BL_1, and the array of FeFETs on the right shares the second common bit line BL_2. Gate lines GL_1, ..., GL_2n, numbered "2n", can each be connected to their respective FeFETs, allowing independent control of the "2n" FeFETs in adjacent rows. Therefore, each FeFET in the 3D memory array structure can be randomly accessed.

[0116] Figure 8 A flowchart of a method 800 for forming a 3D memory structure according to some embodiments of the present disclosure is shown. Figures 9A-9B , Figure 10 , Figures 11A-11B , Figures 12A-12B , Figures 13A-13B , Figures 14A-14B , Figures 15A-15B , Figures 16A-16B and Figures 17A-17B Some embodiments according to this disclosure are shown in Figure 8 The diagram shows a schematic cross-sectional view and / or top view of the 3D memory structure at a specific manufacturing stage of method 800. It should be understood that the operations shown in method 800 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of these operations may be performed simultaneously or in conjunction with... Figure 8 The different sequences shown are executed in order.

[0117] like Figure 8 As shown, method 800 begins with operation 802, wherein a dielectric stack can be formed on a substrate, and a plurality of vias and slots can be formed in the dielectric stack. Figure 9A The following are some embodiments according to this disclosure. Figure 9B A schematic cross-sectional view of the 3D memory structure after operation 802, showing the FF' line. Figure 9B The following are some embodiments according to this disclosure. Figure 9A A schematic top view of the 3D memory structure after operation 802, showing the EE' line.

[0118] In some embodiments, substrate 910 can be any suitable semiconductor substrate having any suitable structure, such as a single-layer silicon substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polycrystalline silicon and metal multilayer substrate, etc. In such embodiments, dielectric stack 920 can be formed directly on semiconductor substrate 910. In some other embodiments, substrate 910 can be a carrier substrate, which can include any suitable semiconductor material or a non-conductive material such as glass, plastic, or sapphire wafer. In such embodiments, dielectric stack 920 can be formed directly on a temporary substrate, and a flipping process will be performed in a subsequent operation to form carrier substrate 910 in dielectric stack 920, and then the temporary substrate can be removed.

[0119] According to some implementation methods, such as Figure 9A As shown, a dielectric stack 920 comprising multiple dielectric layer pairs can be formed on substrate 910. Each dielectric layer pair of the dielectric stack 920 may include an alternating stack of a first dielectric layer 922 and a second dielectric layer 924 different from the first dielectric layer 922. In some embodiments, portions of the first dielectric layer 922 and the second dielectric layer 924 may be used as insulating layers, while other portions of the second dielectric layer 924 may be used as sacrificial layers to be removed in subsequent processes.

[0120] Multiple first dielectric layers 922 and second dielectric layers 924 extend in a lateral direction parallel to the surface of the substrate 910. In some embodiments, the dielectric stack 920 contains more layers than pairs of dielectric layers made of different materials and having different thicknesses. The dielectric stack 920 can be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0121] In some embodiments, the first dielectric layer 922 may be an oxide layer, and the second dielectric layer 924 may be a nitride layer. That is, the dielectric stack 920 may include multiple oxide / nitride layer pairs. It should be noted that the oxide layer 922 and / or the nitride layer 924 may include any suitable oxide material and / or nitride material. In some embodiments, the oxide layer may be a silicon oxide layer, and the nitride layer may be a silicon nitride layer. The multiple oxide / nitride layer pairs are also referred to herein as an "oxide / nitride stack". That is, in the dielectric stack 920, the multiple oxide layers 922 and the multiple nitride layers 924 alternate in the vertical direction. In other words, apart from the top and bottom layers of the given alternating oxide / nitride stack, each of the other oxide layers 922 may be sandwiched between two adjacent nitride layers 924, and each nitride layer 924 may be sandwiched between two adjacent oxide layers 922.

[0122] The oxide layers 922 may each have the same thickness or different thicknesses. For example, the thickness of each oxide layer may be in the range of about 10 nm to about 150 nm. Similarly, the nitride layers 924 may each have the same thickness or different thicknesses. For example, the thickness of each nitride layer may be in the range of about 10 nm to about 150 nm. In some embodiments, the total thickness of the dielectric stack 920 may be greater than 1000 nm. It should be noted that the thickness ranges are provided for illustrative purposes and should not be construed as limiting the scope of the appended claims.

[0123] The dielectric stack 920 may include an oxide layer 922 and a nitride layer 924 of any suitable number. In some embodiments, the total number of oxide layers 922 and nitride layers 924 in the dielectric stack 920 is equal to or greater than 16. That is, the number of oxide / nitride layer pairs may be equal to or greater than 8. In some embodiments, alternating oxide / nitride stacks include more oxide layers or more nitride layers having a different material and / or thickness than the oxide / nitride layer pairs. For example, the bottom and top layers in the dielectric stack 920 may be oxide layers 922.

[0124] like Figures 9A-9B As shown, a plurality of vias 940 may be formed in the dielectric stack 920. In some embodiments, a first array of vias 940 may be formed in a first array region 991 of the dielectric stack 920, and a second array of vias 940 may be formed in a second array region 994 of the dielectric stack 920. Each via 940 may extend vertically through the dielectric stack 920 and expose the substrate 910. In some embodiments, the vias 940 may have a high aspect ratio and may be formed by etching the dielectric stack 920 and subsequent cleaning processes. The etching process for forming the vias 940 may include wet etching, dry etching, or a combination thereof. In some embodiments, each via 940 may be elliptical in the XY plane. The long diameter of each via 940 may be along a second lateral direction (e.g., the Y direction), and the short diameter of each via 940 may be along a first lateral direction (e.g., the X direction).

[0125] like Figure 9BAs shown, a plurality of first slots 928 may be formed on both sides of a plurality of vias 940. Each slot 928 may extend laterally along a second lateral direction (e.g., the Y direction) and vertically through the dielectric stack 920 and expose the substrate 910. In some embodiments, the first slots 928 may have a high aspect ratio and may be formed by etching the dielectric stack 920 and a subsequent cleaning process. The etching process for forming the first slots 928 may include wet etching, dry etching, or a combination thereof. In some embodiments, the vias 940 and the first slots 928 may be formed simultaneously in the same process.

[0126] refer to Figure 8 Method 800 proceeds to operation 804, wherein a sacrificial through-hole structure can be formed in the through hole and an isolation wall can be formed in the gap. Figure 10 The following are some embodiments according to this disclosure. Figure 9B A schematic cross-sectional view of the 3D memory structure during an intermediate step of operation 802, showing the FF' line. Figure 11A The following are some embodiments according to this disclosure. Figure 11B A schematic cross-sectional view of the 3D memory structure after operation 804, showing the FF' line. Figure 11B The following are some embodiments according to this disclosure. Figure 11A A schematic top view of the 3D memory structure after operation 804, showing the EE' line.

[0127] like Figure 10 As shown, operation 804 may include a recess etching process to remove portions of the second dielectric layer 924 of the dielectric stack 920 that are exposed by the plurality of vias 940. This allows a plurality of recesses 1040 to be formed on the sidewalls of each via 940.

[0128] In some embodiments, portions of the second dielectric layer 924 of the dielectric stack 920 on the sidewalls of each via 940 can be removed using any suitable etching process (e.g., isotropic dry etching or wet etching). The etching process can have sufficiently high etch selectivity for the material of the second dielectric layer 924 relative to the material of the first dielectric layer 922, such that the etching process has minimal impact on the first dielectric layer 922. Isotropic dry etching and / or wet etching can remove portions of the second dielectric layer 924 exposed by the multiple vias 940. This allows multiple recesses 1040 to be formed on the sidewalls of each via 940.

[0129] In some embodiments, each recess 1040 may have a horizontal, hollow annular shape, with its outer sidewall being a second dielectric layer 924 and its top and bottom walls being adjacent first dielectric layers 922. That is, after the recess etching process, each via 940 may have uneven sidewalls. In some embodiments, the size of the etch-back of the second dielectric layer 924 may be in the range of about 5 nm to about 20 nm.

[0130] like Figure 11A As shown, operation 804 may further include a deposition process to form a plurality of sacrificial through-hole structures 1140 in the via 940. In some embodiments, the sacrificial through-hole structures 1140 may be formed to fill the via 940 and a plurality of recesses 1040 on the sidewalls of the via 940. In some embodiments, forming the sacrificial through-hole structures 1140 may include filling the via 940 with a sacrificial material (e.g., polysilicon) using any suitable deposition process (e.g., ALD, CVD, PVD, etc.).

[0131] like Figure 11B As shown, operation 804 may further include a deposition process to form a plurality of isolation walls 1133 in the first gap 928. In some embodiments, the sacrificial isolation walls 1133 may comprise any suitable insulating material (e.g., silicon oxide) and may be formed to fill the first gap 928 by using any suitable deposition process (e.g., ALD, CVD, PVD, etc.).

[0132] refer to Figure 8 Method 800 proceeds to operation 806, in which multiple conductive lines can be formed. Figure 12A The following are some embodiments according to this disclosure. Figure 12B A schematic cross-sectional view of the 3D memory structure between the first intermediate steps of operation 806 and the FF' line. Figure 12B The following are some embodiments according to this disclosure. Figure 12A A schematic top view of the 3D memory structure between the first intermediate steps of operation 806, showing the EE' line. Figure 13A The following are some embodiments according to this disclosure. Figure 13B A schematic cross-sectional view of the 3D memory structure between the second intermediate steps of operation 806 and the FF' line. Figure 13B The following are some embodiments according to this disclosure. Figure 13A A schematic top view of the 3D memory structure between the second intermediate steps of operation 806 and the EE' line. Figure 14A The following are some embodiments according to this disclosure. Figure 14B A schematic cross-sectional view of the 3D memory structure after operation 806, showing the FF' line. Figure 14B The following are some embodiments according to this disclosure. Figure 14A A schematic top view of the 3D memory structure after operation 806, showing the EE' line.

[0133] like Figures 12A-12B As shown, operation 806 may include removing a portion of the dielectric stack 920 to form a plurality of slots 1260. The pattern of the second slots 1260 in the transverse XY plane may be predetermined by conductive lines formed in subsequent steps. In the vertical direction (e.g., the Z direction), the second slots 1260 may be formed to penetrate the dielectric stack 920. In some embodiments, the second slots 1260 may be formed by forming a mask layer (not shown) over the dielectric stack 920 and patterning the mask layer using, for example, photolithography to form openings corresponding to the plurality of slots in the patterned mask layer. Suitable etching processes, such as dry etching and / or wet etching, may be performed to remove the portions of the dielectric stack 920 exposed by the openings until the slots 1260 expose the substrate 910. The mask layer may be removed after the plurality of slots 1260 have been formed.

[0134] like Figures 13A-13B As shown, operation 806 may further include replacing the portion of the second dielectric layer 924 of the dielectric stack 920 exposed by the plurality of second slots 1260 with conductive lines 1320 (including 1322, 1324, 1326). In some embodiments, the portion of the second dielectric layer 924 of the dielectric stack 920 exposed by the plurality of slots 1260 may be removed to form a plurality of horizontal trenches (not shown). In some embodiments, the exposed portion of the second dielectric layer 924 may be removed by using any suitable recess etching process (e.g., isotropic dry etching or wet etching). The etching process may have sufficiently high etch selectivity for the material of the second dielectric layer 924 relative to the material of the first dielectric layer 922 and the sacrificial through-structure 1140 of the dielectric stack 920, such that the etching process has minimal impact on the first dielectric layer 922 and the sacrificial through-structure 1140.

[0135] In some embodiments, the recess etching process can remove portions of the second dielectric layer 924 in various directions through multiple slots 1260. In this way, multiple horizontal trenches (not shown) can then be formed extending horizontally to specific depths recessed from the sidewalls of the multiple slots 1260. After the portions of the second dielectric layer 924 have been removed, the multiple slots 1260 and the multiple horizontal trenches can be cleaned using any suitable cleaning process.

[0136] Following the cleaning process, in some implementations, it can be done as follows: Figures 13A-13BConductive lines 1320 (including 1322, 1324, 1326) are formed in the plurality of horizontal trenches shown. The conductive lines 1320 (including 1322, 1324, 1326) can be formed by filling the plurality of horizontal trenches with any suitable conductive material (e.g., tungsten, aluminum, copper, cobalt, or any combination thereof). The conductive material can be deposited into the horizontal trenches using suitable deposition methods (e.g., CVD, PVD, plasma-enhanced CVD (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), and / or ALD). In some embodiments, according to some embodiments of this disclosure, the formed conductive lines 1320 (including 1322, 1324, 1326) can be used as source and drain terminals of a FeFET formed in a subsequent process. In some embodiments, such as Figure 13B As shown, the first / second common first type terminal line 1322 / 1324 can be isolated from the common second type terminal line 1326 through the isolation wall 1133.

[0137] like Figures 14A-14B As shown, operation 806 may further include forming a fill structure 1462 to fill the plurality of second gaps 1260. In some embodiments, after forming the conductive lines 1320 (including 1322, 1324, 1326), the plurality of second gaps 1260 may be filled with a dielectric material using any suitable deposition method (e.g., CVD, PVD, and / or ALD). In some embodiments, the dielectric material of the fill structure 1462 may be a low-temperature oxide material. In some embodiments, the dielectric material of the fill structure 1462 may include the same dielectric material as the first dielectric layer 922, such as silicon oxide.

[0138] refer to Figure 8 Method 800 can proceed to operation 808, in which multiple contact structures can be formed in the contact area. Figure 15A The following are some embodiments according to this disclosure. Figure 15B A schematic cross-sectional view of the 3D memory structure after operation 808, showing the GG' line. Figure 15B The following are some embodiments according to this disclosure. Figure 15A A schematic top view of the 3D memory structure after operation 808, showing the EE' line.

[0139] like Figures 15A-15BAs shown, multiple contact structures 1580 (including 1582, 1584, and 1586) can be formed in contact areas 1501, 1503, and 1505. A first common first-type terminal contact structure 1582 can be formed to contact a first common first-type terminal line 1322 and is located in a first first-type terminal contact area 1501, which is located on a first lateral side of the first array area 991 away from the second array area 999. A second common first-type terminal contact structure 1584 can be formed to contact a second common first-type terminal line 1324 and is located in a second first-type terminal contact area 1503, which is located on a second lateral side of the second array area 999 away from the first array area 991. The common second type terminal contact structure 1586 can be formed to contact the common second type terminal line 1326 and be located in the common second type terminal contact area 1505, which is located between the first array area 991 and the second array area 999.

[0140] like Figure 15A As shown, forming the contact structure 1580 may include forming a plurality of contact holes, each penetrating the upper portion of the dielectric stack 920 and ending at a corresponding second dielectric layer 924. A dielectric fill structure can be formed to fill each contact hole using any suitable deposition process. A punching etching process can be performed to remove a portion of the dielectric fill structure to expose a corresponding second dielectric layer 924 in each contact hole. The remaining portion of the dielectric fill structure forms a spacer layer 1572 on the sidewall of each contact hole. A portion of the corresponding second dielectric layer 924 can be removed using any suitable etching process to expose a corresponding conductive line 1320 located at the same horizontal plane as the corresponding second dielectric layer 924. A conductive layer 1574 can be formed using any suitable thin-film deposition process to cover the spacer layer 1572 and the bottom surface of each contact hole, and to contact a corresponding conductive line 1320 in the lateral direction. A second conductive material can then be filled into the contact holes to form a conductive fill structure 1576. The conductive layer 1574 and the conductive fill structure 1576 can form a conductive via that is isolated from other conductive lines 1320 by the spacer layer 1572.

[0141] refer to Figure 8 Method 800 can proceed to operation 810, in which multiple sacrificial punch-through structures can be replaced by multiple transistor structures. Figure 16A The following are some embodiments according to this disclosure. Figure 16B A schematic cross-sectional view of the 3D memory structure between intermediate steps of operation 810, showing the FF' line. Figure 16BThe following are some embodiments according to this disclosure. Figure 16A A schematic top view of the 3D memory structure between intermediate steps of operation 810, showing the EE' line. Figure 17A The following are some embodiments according to this disclosure. Figure 17B A schematic cross-sectional view of the 3D memory structure after operation 810, showing the FF' line. Figure 17B The following are some embodiments according to this disclosure. Figure 17A A schematic top view of the 3D memory structure after operation 810, showing the EE' line.

[0142] like Figures 16A-16B As shown, operation 810 may include removing the sacrificial through-structure 1140 to reopen the plurality of vias 940 and the plurality of recesses 1040 on the sidewalls of the vias 940. In some embodiments, the sacrificial through-structure 1140 may be removed by using any suitable etching process (e.g., isotropic dry etching or wet etching). The etching process may have sufficiently high etch selectivity for the material of the sacrificial through-structure 1140 relative to the materials of the first dielectric layer 922 and the conductive lines 1320, such that the etching process has minimal impact on the first dielectric layer 922 and the conductive lines 1320. After removing the sacrificial through-structure 1140, the plurality of vias 940 and the plurality of recesses 1040 on the sidewalls of the vias 940 may be reformed. That is, as Figure 16A As shown, the new through-hole 1640 may have uneven sidewalls and expose the conductive line 1320.

[0143] like Figures 17A-17B As shown, operation 810 may further include forming a transistor structure 1740 in the new via 1640. In some embodiments, the transistor structure 1740 may include a control gate 1730 extending vertically through the new via 1640, a ferroelectric layer 1720 laterally surrounding the control gate 1730, and a plurality of channel layers 1710 laterally surrounding the ferroelectric layer 1720.

[0144] The channel layer 1710 may be formed in a plurality of recesses 1040 in each new via 1640. In some embodiments, forming the channel layer 1710 may include a deposition process of forming a silicon layer to cover the sidewalls of the plurality of new vias 1640. The silicon layer may be an amorphous silicon layer or a polycrystalline silicon layer formed using a thin-film deposition process (e.g., ALD, CVD, PVD, or any other suitable process). In some embodiments, forming the channel layer 1710 may further include an etching process of removing portions of the silicon layer attached to the sidewalls of the first dielectric layer 922. Thus, as Figure 17A As shown, the remaining portion of the silicon layer in the plurality of recesses 1040 can form the channel layer 1710.

[0145] In some implementations, such as Figure 17B As shown, each layer in the channel layer 1710 can contact the first / second common first type terminal line 1322 / 1324 and the common second type terminal line 1326. The first / second common first type terminal lines 1322 / 1324 can contact the channel layer 1710 at one end of the long diameter of each through-structure 1770 (e.g., the lower end of the through-structure 1770 in the first row and the upper end of the through-structure 1770 in the second row). The common second type terminal line 1326 can contact the channel layer 1710 of each through-structure 1770 at the other end of the long diameter of each through-structure 1770 (e.g., the upper end of the through-structure 1770 in the first row and the lower end of the through-structure 1770 in the second row). Therefore, the first / second common first type terminal lines 1322 / 1324 and the common second type terminal line 1326 can be used as a common bit line and a common source line, respectively.

[0146] In some embodiments, a storage film may be formed in each new via 1640. In some embodiments, the storage film may include a barrier layer (not shown), a ferroelectric layer 1720, and an interface layer (not shown).

[0147] In some embodiments, an interface layer 1668 may be formed on the sidewalls and bottom of each new via 1640. The sidewalls of the interface layer may contact the first dielectric layer 922 and the channel layer 1710. The bottom side of the interface layer may contact the substrate 910. The interface layer may be used to reduce the possibility of material mixing between the ferroelectric layer 1720 and the channel layer 1710. In some embodiments, the interface layer may be silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material (e.g., HfO2, HfAlO, Al2O3), and / or any combination thereof. The interface layer may be formed by any suitable film deposition technique (e.g., ALD, CVD, sputtering, evaporation, and / or any combination thereof), or by oxidation, nitriding, and / or a combination thereof. The thickness of the interface layer may be in the range of about 5 nm to about 50 nm.

[0148] In some embodiments, the ferroelectric layer 1720 may be formed to cover the interface layer. In some embodiments, the ferroelectric layer 124 may comprise a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). In some embodiments, the ferroelectric layer 1720 may comprise a high-k (i.e., high dielectric constant) dielectric material, which may comprise transition metal oxides, such as hafnium zirconium oxide (HZO), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (Ta2O5), tungsten oxide (WO3), molybdenum oxide (MO3), vanadium oxide (V2O3), lanthanum oxide (La2O3), and / or any combination thereof.

[0149] In some embodiments, the ferroelectric layer 1720 can be formed by chemical vapor deposition (CVD) (e.g., metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma-enhanced chemical vapor deposition (HDP-CVD), etc.). The ferroelectric layer 1720 can also be formed by atomic layer deposition (ALD), sputtering, evaporation, or any combination thereof. In some embodiments, the ferroelectric layer 1720 can have a thickness in the range of 5 nm to 100 nm.

[0150] In some embodiments, to improve ferroelectric properties, the high-k dielectric material of the ferroelectric layer 1720 can be doped. For example, the ferroelectric layer 1720 can be HZO or HfO2 doped with silicon (Si), (yttrium)y, gadolinium (Gd), lanthanum (La), zirconium (Zr), or aluminum (Al), or any combination thereof. In some embodiments, the ferroelectric film 224 can include zirconium titanate (PZT), strontium bismuth tantalate (SrBi₂Ta₂O₉), barium titanate (BaTiO₃), PbTiO₃, and BLT ((Bi,La)₄Ti₃O₉). 12 (or any combination thereof).

[0151] In some embodiments, a barrier layer may be formed to cover the ferroelectric layer 1720. The barrier layer can be used to block the interaction between the ferroelectric layer 1720 and a control gate formed in a subsequent process. The barrier layer may include titanium nitride (TiN), silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2O2N), high-k dielectric materials (e.g., HfO2, Al2O3), and / or any combination thereof. The barrier layer may be formed by any suitable physical vapor deposition (PVD) or chemical vapor deposition (CVD). The barrier layer may have a thickness in the range of about 5 nm to about 50 nm.

[0152] In some implementations, such as Figure 17AAs shown, a control gate 1730 may be formed in each new via 1640 to cover the memory film and fill the new via 1640. In some embodiments, the control gate 1730 may be a metal-filled structure or a polysilicon-filled structure formed using any suitable deposition process (e.g., ALD, CVD, PVD, etc.). In some embodiments, a subsequent chemical mechanical planarization (CMP) process may be performed to remove the memory film and portions of the control gate 1730 located outside the new via 1640.

[0153] Accordingly, this disclosure describes a three-dimensional (3D) ferroelectric field-effect transistor (FeFET) random access memory (RAM) device and a method for manufacturing the same. The disclosed 3D FeFET RAM device is a high-speed, high-density non-volatile memory that uses ferroelectric polarity to change the threshold voltage and store data. The pattern of the memory cell can be designed as an ellipse to increase the gate length, thereby improving gate control capability while increasing storage density. Furthermore, a common source line and a common drain line can be formed to enable random access to each memory cell. The source and drain lines of each layer can be electrically connected using through-contacts, which simplifies the source-drain contact process. The drain / source electrodes of the FeFET can be connected to the common drain / source line to reduce the step area. Ferroelectric materials such as IGZO can be filled into the vias from either the front or back side as the channel material for the FeFET, thereby improving the reliability of the ferroelectric material.

[0154] The foregoing description of specific embodiments so fully reveals the general nature of this disclosure that others can readily modify and / or adapt such specific embodiments for various applications by applying knowledge within the scope of the art, without excessive experimentation, and without departing from the overall concept of this disclosure. Therefore, based on the disclosure and guidance provided herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It will be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes, and that the terminology or terminology of this specification will be interpreted by those skilled in the art based on the disclosure and guidance.

[0155] The embodiments of this disclosure have been described above using functional building blocks that illustrate implementations of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries may be defined as long as the specified functions and their relationships are properly performed.

[0156] The summary and abstract may set forth one or more, but not all, embodiments of this disclosure conceived by (a plurality of) inventors, and therefore are not intended to limit this disclosure and the appended claims in any way.

[0157] The breadth and scope of this disclosure should not be limited to any of the embodiments described above, but should be defined only by the following claims and their equivalents.

Claims

1. A semiconductor structure, comprising: A transistor comprising multiple layers stacked vertically, each layer comprising: A first transistor array, wherein the first transistor array shares a first common first type terminal line; A second transistor array, the second transistor array sharing a second common first type terminal line, wherein the first transistor array and the second transistor array share a common second type terminal line; and Multiple contact structures, the multiple contact structures including: A first common first type terminal contact structure is coupled to a first common first type terminal line in a first first type terminal contact area, and the first first type terminal contact area is located on a first lateral side of the first transistor array away from the second transistor array. A second common first-type terminal contact structure is coupled to a second common first-type terminal line in a second first-type terminal contact region. The second first-type terminal contact region is located on a second lateral side of the second transistor array away from the first transistor array. A common second type terminal contact structure is provided, wherein the common second type terminal contact structure is coupled to the common second type terminal line in the common second type terminal contact area, and the common second type terminal contact area is located between the first transistor array and the second transistor array.

2. The semiconductor structure according to claim 1, wherein, The transistor is a ferroelectric field-effect transistor (FeFET).

3. The semiconductor structure according to claim 2, wherein, Each FeFET includes: Channel layer; A ferroelectric layer, the ferroelectric layer being ferroelectric and surrounded by the channel layer in a horizontal plane; and A gate, which is surrounded by the ferroelectric layer in the horizontal plane.

4. The semiconductor structure according to claim 3, wherein, The channel layer comprises a metal oxide semiconductor material.

5. The semiconductor structure according to claim 3, wherein, The channel layer of each FeFET has an elliptical ring shape in the horizontal plane.

6. The semiconductor structure according to claim 5, wherein: The first portion of the channel layer located at the second end of the long diameter of the outer periphery of the elliptical ring shape contacts the first common first type terminal line or the second common first type terminal line. and The second portion of the channel layer located at the first end of the long diameter of the outer periphery of the elliptical ring shape contacts the common second type terminal line.

7. The semiconductor structure according to claim 1, wherein: The first common first type terminal line includes a first U-shaped portion located between adjacent rows of the first transistor array and having a first opening facing away from the second transistor array; and The second common first type terminal line includes a second U-shaped portion located between adjacent rows of the second transistor array and having a second opening facing away from the first transistor array.

8. The semiconductor structure according to claim 1, wherein: The first type of terminal is a drain terminal; The second type of terminal is the source terminal; The first common first type terminal contact structure is connected to the first bit line; The second common first type terminal contact structure is connected to the second bit line; and The common second type terminal contact structure is connected to the source line.

9. The semiconductor structure according to claim 1, wherein: Each of the plurality of contact structures is located in a dielectric stack within the first type of terminal contact area, the second type of terminal contact area, or the common second type of terminal contact area.

10. The semiconductor structure according to claim 9, wherein: The first common first type terminal lines of the multiple layers of the transistor overlap in the vertical direction; The second common first type terminal lines of the multiple layers of the transistor overlap in the vertical direction; and The common second type terminal lines of the multiple layers of the transistor overlap in the vertical direction.

11. The semiconductor structure according to claim 10, wherein, A contact structure of the intermediate stack of transistors includes: A conductive via, the conductive via extending vertically in the dielectric stack located above the intermediate stack of the transistor; A dielectric layer laterally surrounding the conductive via to isolate the contact structure from the terminal lines of an upper transistor located above the intermediate stack of the transistors; and An enlarged conductive terminal is laterally electrically contacted with the corresponding terminal line of the intermediate stack of the transistor.

12. The semiconductor structure according to claim 9, further comprising: A first isolation wall is located between the first type of terminal contact area and the first transistor array to isolate the first common first type of terminal line from the common second type of terminal line; as well as A second isolation wall is located between the second first type terminal contact area and the second transistor array to isolate the second common first type terminal line from the common second type terminal line.

13. A semiconductor structure comprising: A transistor comprising multiple layers stacked vertically, each layer comprising: A first transistor array, wherein the first transistor array shares a first common first type terminal line; A second transistor array, the second transistor array sharing a second common first type terminal line, wherein the first transistor array and the second transistor array share a common second type terminal line; and Multiple contact structures, each of the multiple contact structures being coupled to the first common first type terminal line, the second common first type terminal line, or the common second type terminal line; Each of the plurality of contact structures electrically coupled to the intermediate stack of the transistor extends through a dielectric stack located above the intermediate stack of the transistor.

14. The semiconductor structure according to claim 13, wherein, The transistor is a ferroelectric field-effect transistor (FeFET).

15. The semiconductor structure according to claim 14, wherein, Each FeFET includes: Channel layer; A ferroelectric layer, the ferroelectric layer being ferroelectric and surrounded by the channel layer in a horizontal plane; and A control gate, which is surrounded by the ferroelectric layer in the horizontal plane.

16. The semiconductor structure according to claim 15, wherein, The channel layer comprises a metal oxide semiconductor material.

17. The semiconductor structure according to claim 15, wherein, The channel layer of each FeFET cell has an elliptical ring shape in the horizontal plane.

18. The semiconductor structure according to claim 17, wherein: The first portion of the channel layer located at the second end of the long diameter of the outer periphery of the elliptical ring shape contacts the first common first type terminal line or the second common first type terminal line. and The second portion of the channel layer located at the first end of the long diameter of the outer periphery of the elliptical ring shape contacts the common second type terminal line.

19. The semiconductor structure according to claim 13, wherein: The first common first type terminal line includes a first U-shaped portion located between adjacent rows of the first transistor array and having a first opening facing away from the second transistor array; and The second common first type terminal line includes a second U-shaped portion located between adjacent rows of the second transistor array and having a second opening facing away from the first transistor array.

20. The semiconductor structure according to claim 13, wherein, The plurality of contact structures include: A first common first type terminal contact structure is coupled to a first common first type terminal line in a first first type terminal contact area, and the first first type terminal contact area is located on a first lateral side of the first transistor array away from the second transistor array. A second common first-type terminal contact structure is coupled to a second common first-type terminal line in a second first-type terminal contact region. The second first-type terminal contact region is located on a second lateral side of the second transistor array away from the first transistor array. A common second type terminal contact structure is provided, wherein the common second type terminal contact structure is coupled to the common second type terminal line in the common second type terminal contact area, and the common second type terminal contact area is located between the first transistor array and the second transistor array.

21. The semiconductor structure according to claim 20, wherein: The first type of terminal is a drain terminal; The second type of terminal is the source terminal; The first common first type terminal contact structure is connected to the first bit line; The second common first type terminal contact structure is connected to the second bit line; and The common second type terminal contact structure is connected to the source line.

22. The semiconductor structure according to claim 13, wherein, Each contact structure includes: A conductive via, the conductive via extending vertically in the dielectric stack located above the intermediate stack of the transistor; A dielectric layer laterally surrounding the conductive via to isolate the contact structure from the terminal lines of an upper transistor located above the intermediate stack of the transistors; and An enlarged conductive terminal is laterally electrically contacted with the corresponding terminal line of the intermediate stack of the transistor.

23. The semiconductor structure according to claim 13, wherein: The first common first type terminal lines of the multiple layers of the transistor overlap in the vertical direction; The second common first type terminal lines of the multiple layers of the transistor overlap in the vertical direction; and The common second type terminal lines of the multiple layers of the transistor overlap in the vertical direction.

24. The semiconductor structure according to claim 20, further comprising: A first isolation wall is located between the first type of terminal contact area and the first transistor array to isolate the first common first type of terminal line from the common second type of terminal line; as well as A second isolation wall is located between the second first type terminal contact area and the second transistor array to isolate the second common first type terminal line from the common second type terminal line.

25. A method for forming a semiconductor structure, comprising: A dielectric stack is formed, the dielectric stack comprising a plurality of first dielectric layers and second dielectric layers alternately stacked in a vertical direction; Multiple through-holes are formed in the dielectric stack; Multiple sacrificial through-hole structures are formed in the plurality of through holes; A portion of the second dielectric layer is replaced with a conductive wire; The plurality of sacrificial punch-through structures are replaced with a plurality of transistor structures; as well as Multiple contact structures are formed. The conductive wire is formed to include: A first common first type terminal line, which is shared by a first transistor array; A second common first-type terminal line, shared by a second transistor array; and A common second type terminal line, which is shared by the first transistor array and the second transistor array. Each of the plurality of contact structures is coupled to a corresponding first common first type terminal line, second common first type terminal line, or common second type terminal line, and extends through the remaining portion of the dielectric stack above the corresponding conductive line.

26. The method of claim 25, wherein, Forming the plurality of sacrificial through-structures includes: Remove the portion of the second dielectric layer exposed by the plurality of vias to form a plurality of recesses on the sidewalls of the plurality of vias; and Deposit sacrificial material to fill the plurality of depressions and the plurality of through holes.

27. The method according to claim 26, wherein, Replacing the plurality of sacrificial punch-through structures with multiple transistor structures includes: Remove the plurality of sacrificial through-structures from the plurality of recesses and the plurality of through-holes; Multiple channel layers are formed in the multiple depressions; A ferroelectric layer is formed on the sidewall of each via, wherein the ferroelectric layer is ferroelectric and is laterally surrounded by the channel layer; and A gate structure is formed in each via, wherein the gate structure is laterally surrounded by the ferroelectric layer.

28. The method according to claim 27, wherein, The channel layer comprises a metal oxide semiconductor material that is in direct contact with the conductive layer.

29. The method according to claim 28, wherein, The metal oxide semiconductor material is indium gallium zinc oxide (IGZO).

30. The method according to claim 25, wherein, Replacing the portion of the second dielectric layer with the conductive line includes: Multiple gaps are formed that penetrate the dielectric stack; The portion of the second dielectric layer is removed from the plurality of gaps to form a plurality of horizontal openings; The conductive lines are formed in the plurality of horizontal openings; and The multiple gaps are filled with a dielectric material.

31. The method according to claim 25, wherein, Forming the plurality of through holes includes: forming each through hole having an elliptical shape in a horizontal plane.

32. The method of claim 29, further comprising: An isolation wall is formed vertically through the dielectric stack, such that the conductive lines formed in each stack are divided by the isolation wall to include the first common first type terminal line, the second common first type terminal line, and the common second type terminal line.

33. The method according to claim 32, wherein: Forming the plurality of through holes includes: forming each through hole having an elliptical shape in a horizontal plane; The first portion of the channel layer at the first end of the long diameter of the elliptical shape is formed to contact the common second type terminal line; and The second portion of the channel layer located at the second end of the long diameter of the elliptical shape is formed to contact the first common first type terminal line or the second common first type terminal line.

34. The method according to claim 32, wherein: The first common first type terminal line is formed to include a first U-shaped portion located between adjacent rows of the first transistor array and having a first opening facing away from the second transistor array; and The second common first type terminal line is formed to include a second U-shaped portion located between adjacent rows of the second transistor array and having a second opening facing away from the second transistor array.

35. The method according to claim 32, wherein, Forming the plurality of contact structures includes: A first common first type terminal contact structure is formed that is coupled to the first common first type terminal line and is located on the first lateral side of the first transistor array away from the second transistor array; Forming a second common first-type terminal contact structure coupled to the second bit line and located on the second lateral side of the second transistor array away from the first transistor array; and A common second type terminal contact structure is formed that is coupled to the common second type terminal line and located between the first transistor array and the second transistor array.

36. The method according to claim 25, wherein, One of the multiple contact structures includes: A contact hole is formed, which penetrates the upper portion of the remaining portion of the dielectric stack and stops at a second dielectric layer located at the same horizontal plane as the corresponding conductive line; A dielectric filling structure is formed to fill the contact hole; Perform punching etching to remove a portion of the dielectric filling structure to expose a portion of the second dielectric layer adjacent to the corresponding conductive line; Remove the portion of the second dielectric layer to expose the corresponding conductive line; and Conductive material is deposited in the contact hole to form the contact structure, such that the contact structure is isolated from the conductive line located above the corresponding conductive line and is in electrical contact with the corresponding conductive line in the lateral direction.

37. The method according to claim 32, wherein: The first common first type terminal line in the multiple layers of the conductive wire is formed to overlap in the vertical direction; The second common first type terminal wire in the multiple layers of the conductive wire is formed to overlap in the vertical direction; and The common second type terminal wires in the multiple layers of the conductive wire are formed to overlap in the vertical direction.

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