Integrated circuit and phase change memory device

Abstract

The invention provides an integrated circuit, a phase change memory device, and a method, a device and equipment for managing a phase change material in the memory device. In one aspect, an integrated circuit (e.g., a memory element) includes a first electrode, a second electrode, and a matrix of phase change material coupled between the first electrode and the second electrode. The phase change material comprises Si < x > Sb < y > Tez, wherein x, y and z respectively represent the atomic ratios of Si, Sb and Te in the composition. The bulk stoichiometry of the matrix of phase change material includes a Si atom concentration in a range from about 7% to about 12%.

Description

Technical Field

[0001] The present disclosure relates to phase change materials, which may be suitable for use in memory devices, for example. Background Art

[0002] Phase change materials, such as chalcogenide-based materials and other similar materials, can be changed between an amorphous phase and a crystalline phase by the application of electrical current at various levels suitable for implementation in integrated circuits. The bulk amorphous phase is characterized by a higher electrical resistivity than the bulk crystalline phase, which can be easily sensed to indicate data. These properties have the advantage of using programmable impedance materials to form nonvolatile memory circuits, which can be read or written with random access. Summary of the invention

[0003] The present disclosure describes methods, circuits, devices, systems and techniques for managing phase change materials in memory devices, such as those used in analog artificial intelligence (AI) systems.

[0004] One aspect of the present disclosure is characterized by an integrated circuit, comprising: a first electrode; a second electrode; and a body of a phase change material coupled between the first electrode and the second electrode. The phase change material comprises Si x Sb y Te z , wherein x, y and z represent the atomic ratios of the compositions Si (silicon), Sb (antimony) and Te (tellurium), respectively, and the bulk stoichiometry of the matrix of the phase change material includes a Si atomic concentration in the range from about 7% to about 12%.

[0005] In some embodiments, the bulk stoichiometry of the matrix of the phase change material includes a Sb atomic concentration in a range from about 27% to about 42% and a Te atomic concentration in a range from about 40% to about 60%.

[0006] In some embodiments, the phase change material includes Si doped x Sb y Te z SiC (silicon carbide) in.

[0007] In some embodiments, the bulk stoichiometry of the matrix of the phase change material includes a C (carbon) atomic concentration in a range of about 10% to about 16%.

[0008] In some embodiments, the matrix of the phase change material has a thickness in a range from 30 nm to 80 nm.

[0009] In some embodiments, a reset drift coefficient of the integrated circuit at room temperature is no greater than 0.04.

[0010] In some embodiments, a reset drift coefficient of the integrated circuit at an elevated temperature is no greater than 0.04.

[0011] In some embodiments, the conductivity of the integrated circuit at elevated temperatures does not change by more than 10% in one hour.

[0012] In some embodiments, the conductivity of the integrated circuit at elevated temperatures does not change by more than 10% in a day.

[0013] In some embodiments, the matrix of the phase change material is programmable to multiple resistance states, including a full reset state and a full set state, and the change in conductivity of each resistance state does not exceed 10% in one day.

[0014] In some embodiments, the phase change material has a crystallization temperature greater than 200 degrees Celsius.

[0015] In some embodiments, the matrix of the phase change material is configured to be applied with a set pulse having a duration not exceeding 200 ns to change the phase change material from an amorphous phase to a crystalline phase.

[0016] In some embodiments, the integrated circuit is used as a memory device having a mushroom-type structure.

[0017] In some embodiments, a phase change memory device includes a plurality of memory cells. At least one of the memory cells includes the above-mentioned integrated circuit. The phase change memory device is used to execute an inference mode of an analog artificial intelligence (AI) model, and wherein in the inference mode, a plurality of memory elements of the plurality of memory cells are programmed to have a plurality of impedance states corresponding to a corresponding plurality of weights of the plurality of memory cells, and the plurality of impedance states correspond to a plurality of non-overlapping ranges of a plurality of impedance values.

[0018] Another aspect of the present disclosure is characterized by an integrated circuit, comprising: a first electrode; a second electrode; and a matrix of a phase change material coupled between the first electrode and the second electrode. The phase change material comprises Si doped with SiC. x Sb y Te z , wherein x, y and z represent the atomic ratios of the compositions Si, Sb and Te, respectively.

[0019] In some embodiments, the bulk stoichiometry of the matrix of the phase change material includes: a Si atomic concentration in a range from about 7% to about 12%, a Sb atomic concentration in a range from about 27% to about 42%, a Te atomic concentration in a range from about 40% to about 60%, and a C atomic concentration in a range from about 10% to about 16%.

[0020] In some embodiments, the reset drift coefficient of the integrated circuit at elevated temperatures is no greater than 0.04.

[0021] In some embodiments, the matrix of phase change material is programmable to multiple impedance states, including a fully reset state and a fully set state, and the conductivity of each impedance state does not change by more than 10% in a day.

[0022] In some embodiments, a phase change memory device includes a plurality of memory cells, wherein at least one of the plurality of memory cells includes the above-mentioned integrated circuit. The phase change memory device is used to execute an inference mode of a simulated artificial intelligence model, and in the inference mode, a plurality of memory elements of the plurality of memory cells are programmed to have a plurality of impedance states corresponding to a corresponding plurality of weights of the plurality of memory cells, the impedance states corresponding to a plurality of non-overlapping ranges of a plurality of impedance values.

[0023] Another aspect of the present disclosure is a phase change memory device, comprising: a plurality of memory cells. Each memory cell comprises a memory element, comprising: a first electrode and a second electrode, and a phase change material matrix coupled between the first electrode and the second electrode, wherein the phase change material comprises Si x Sb y Te z , where x, y and z represent atomic ratios of the compositions Si, Sb and Te, respectively, and where the bulk stoichiometry of the matrix of the phase change material includes a Si atomic concentration in a range from about 7% to about 12%, a Sb atomic concentration in a range from about 27% to about 42%, and a Te atomic concentration in a range from about 40% to about 60%; and a control circuit is coupled to the plurality of memory cells and is used to control one or more operations on the plurality of memory cells.

[0024] In some embodiments, the phase change material includes Si doped xSb y Te z The SiC in the phase change material, and the bulk stoichiometry of the matrix of the phase change material includes: a C atomic concentration is in the range of about 10% to about 16%.

[0025] In some embodiments, a phase change memory device is used to execute an inference mode of a simulated artificial intelligence model, and wherein in the inference mode, multiple memory elements of multiple memory cells are programmed to have multiple impedance states corresponding to corresponding multiple weights of the multiple memory cells, and the impedance states correspond to multiple non-overlapping ranges of multiple impedance values.

[0026] In order to better understand the above and other aspects of the present invention, the following embodiments are specifically cited and described in detail with reference to the accompanying drawings. Other features, aspects and advantages will become apparent from the description, drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram is shown illustrating an example operation of a memory device including a phase change material (PCM).

[0028] Figure 2 Schematic diagrams of example phase change materials with corresponding compositions (Si (silicon), Sb (antimony) and Te (tellurium)) and reset drift coefficients (eg, at room temperature) are shown.

[0029] Figure 3 to Figure 4 Schematic diagram showing example performance characteristics of a PCM cell made from an example SiSbTe PCM (Material A).

[0030] Figures 5 and 6 Schematic diagram showing example performance characteristics of a PCM cell made from another example SiSbTe PCM (Material B).

[0031] Figure 7 Graph showing the drift performance characteristics (at 65 degrees Celsius) of a PCM cell made from material A programmed to a series of impedance states for one hour.

[0032] Figure 8 Graph showing the drift performance characteristics (at 65 degrees Celsius) of a PCM cell made from material B programmed to a series of impedance states for one hour.

[0033] Fig. 9 Graph showing the drift performance characteristics (at 65 degrees Celsius) of a PCM cell made from material A programmed to a series of impedance states over a day.

[0034] Fig. 10A Schematic diagrams of exemplary phase change materials having corresponding compositions (Si, Sb, Te, and C (carbon)) at various atomic concentrations are shown.

[0035] Fig. 10B Draw Fig. 10A Schematic diagram of the resistivity of material A, material C and material D as a function of temperature.

[0036] Fig.11 Schematic diagram showing example performance characteristics of a PCM cell made from example SiSbTe (Material C) with low SiC (Silicon Carbide) doping.

[0037] Fig.12 Schematic diagram showing example performance characteristics of a PCM cell made from example SiSbTe with high SiC (silicon carbide) doping (material D).

[0038] Fig.13 Schematic diagram showing the drift performance characteristics (at 65 degrees Celsius) of a PCM cell made from material C programmed into a range of impedance states.

[0039] Fig.14 Schematic diagram showing the drift performance characteristics (at 65 degrees Celsius) of a PCM cell made from material D programmed into a range of impedance states.

[0040] Fig.15 Schematic diagram showing the drift performance characteristics (at 65 degrees Celsius) of a PCM cell made from material C programmed to a series of impedance states over a day.

[0041] Fig.16A A cross-sectional view of an example memory device fabricated from a PCM material having a mushroom-type structure is shown.

[0042] Fig. 16B A cross-sectional view of an exemplary memory device fabricated from PCM material having an "active in via" type structure is shown.

[0043] Fig. 16C A cross-sectional view of an exemplary memory device fabricated from a PCM material having a pore-type structure is shown.

[0044] Fig.16D A cross-sectional view of an example memory structure including multiple memory elements fabricated from a PCM material having a cross-point structure is depicted.

[0045] Fig.17A A schematic diagram of an integrated circuit including an array of phase change memory cells is shown.

[0046] Fig. 17B Drawn on Fig.17A A schematic diagram of an example of the operation of a portion of a phase change memory cell in a phase change memory array.

[0047] Fig.18A and Fig.18B A schematic diagram of an artificial neural network (ANN) example and an expanded diagram of a neuron N6 of the ANN are respectively shown.

[0048] Fig.19 A schematic diagram of an example memory for performing a multiply-accumulate calculation (MAC) is shown.

[0049] Fig. 20A A schematic diagram of an example system for performing a training mode is shown.

[0050] Fig. 20B A schematic diagram of an example system for executing an inference mode is shown.

[0051] The same reference numbers and names in the various drawings represent the same elements. It should also be understood that the various exemplary embodiments shown in the drawings are merely illustrative representations and are not necessarily drawn to scale.

[0052]

Explanation of symbols

[0053] 100: Example

[0054] 102,104,106: Pulse

[0055] 200: Data Table

[0056] 302,304,402,404,406,408,502,504,602,604,606,608,1102, 1104,1112,1114,1116,1118,1202,1204,1212,1214,1216,1218: curve

[0058] 1000, 1010, 1020: Trajectory

[0059] 1002,1012,1022: Status

[0060] 1600,1630,1650,1670a,1780a,1782a,1784a,1786a,1911,1921,1931,1941: memory components

[0061] 1602,1632,1652,1672: memory matrix

[0062] 1604,1642,1664: Active area

[0063] 1606,1634,1654,1674: First electrode

[0064] 1608: Dielectric layer

[0065] 1610, 1636, 1656, 1676: Second electrode

[0066] 1612: Narrow Edge

[0067] 1638, 1658: Upper surface

[0068] 1640,1660: lower surface

[0069] 1644,1662: Width

[0070] 1670: Memory Structure

[0071] 1678: Switching Layer

[0072] 1700: Integrated Circuits

[0073] 1705: Phase Change Memory Array

[0074] 1710: Word line decoder and driver

[0075] 1711: Word line decoder

[0076] 1715, 1794, 1796, 2005, WL2: word line

[0077] 1720: Bit line decoder

[0078] 1725,1790,1792,2003,BL2: bit line

[0079] 1730: Block data input structure

[0080] 1735, 1760: Bus

[0081] 1740: Data input line

[0082] 1745: Data output line

[0083] 1750: Controller

[0084] 1755: Bias configuration supply voltage and current source

[0085] 1765: Other circuits

[0086] 1775: Block Sense Amplifier

[0087] 1780,1782,1784,1786,1910, 1920,1930,1940,2020i j ,2070i j : Memory unit

[0088] 1780b,1782b,1784b,1786b: Access device

[0089] 1785: Source Line Termination Circuit

[0090] 1788: Source line

[0091] 1798: Current Path

[0092] 1800: ANN

[0093] 1900, 2010, 2060: Memory

[0094] 2000,2050: System

[0095] 2002: DAC

[0096] 2004: Sampling and Preservation Unit

[0097] 2006: ADC

[0098] 2022 ij ,2072 ij :resistance

[0099] G1,G2,G3,G4,G i ,G ij : Conductivity

[0100] I, I1, I2, I3, I4, Ii: current

[0101] L0, L1, L2: Layer

[0102] N0,N1,N2,N3,N4,N5,N6,N7,N8: Neurons

[0103] V1, V2, V3, V4, Vn: voltage

[0104] w i ,w ij : Weight

[0105] x i :Signal DETAILED DESCRIPTION

[0106] Phase change materials (PCM) can be used to form memory elements, such as FIG. 16A to FIG. 16D As described in more detail in . The memory element may include a PCM layer and first and second electrodes electrically contacting the PCM layer. In operation, a voltage is applied to the first and second electrodes to cause a current to pass through the PCM layer. This current allows for read / sense and write operations for the memory cell.

[0107] The PCM layer includes an active region in which a large phase change between a crystalline state and an amorphous state occurs during set and reset operations. Figure 1 An example 100 of the operation of a memory element including a matrix of PCM is depicted. The operation is performed by applying an electronic pulse (e.g., a voltage pulse) which changes the temperature of the PCM layer. During a reset operation, a fast (or short) (e.g., about 50 ns) high temperature pulse 102 may be used to cause the PCM in the active region, which is in a low impedance crystallized state (set state), to transition to a high impedance amorphous state (or reset state). The high point of the high temperature pulse 102 is above the melting temperature of the PCM. The fast high temperature pulse 102 may melt or decompose the crystallized structure, after which the phase change material cools rapidly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous phase. During a set operation, a long (e.g., 100 ns to 10 s) medium temperature pulse 104 is used to cause the PCM in the active region, which is in a high impedance amorphous state (or reset state), to transition to a low impedance crystallized state (or set state). The high point of the medium temperature pulse 104 is below the melting temperature of the PCM, but above the crystallization temperature of the PCM. The read pulse 106 does not generate a lot of heat / temperature in the PCM layer, wherein the high point of the temperature of the read pulse 106 is below the crystallization temperature of the PCM. This differential impedance state corresponds to the storage of data in the memory cell.

[0108] In phase change memory, data is stored by causing transitions between amorphous and crystalline states in the active region of the phase change material. The difference between the highest impedance R1 in the high impedance amorphous reset state and the lowest impedance R2 in the low impedance crystalline set state defines a read margin for distinguishing cells in the amorphous reset state from cells in the crystalline set state. Similarly, as in Fig. 20B As discussed in more detail in , the difference between the highest impedance R1 and the lowest impedance R2 enables the memory element to be programmed into multiple impedance states, which may correspond to non-overlapping ranges of impedance values. The multiple impedance states may be used as corresponding weights for inference in an analog artificial intelligence (AI) system.

[0109] Hardware acceleration for deep learning using analog non-volatile memory (NVM) requires large arrays with high device yield, high accuracy multiply-accumulate (MAC) operations, and a routing framework for implementing arbitrary deep neural networks (DNNs). Analog memory-based DNN accelerators use a variety of memories, and phase-change memory is one of the best candidates. In NVM-based accelerators, weights are implemented in the conductivity values ​​G of analog impedance elements, and excitations are implemented in the form of voltage or time-encoding [V(t)]. However, the drift nature of PCM materials (or changes in conductivity over time) is a significant challenge to maintaining accuracy in DNN applications. This drift nature is the overlap of impedance levels in time with an exponential power-law due to the impedance drift of the amorphous phase over time.

[0110] In some examples, conventional undoped Ge2Sb2Te5 (GST) (germanium antimony telluride) based materials show high drift coefficients (e.g., 0.08 to 0.1). As the content of Ge (germanium) increases, the drift performance decreases with higher drift coefficients. With SiO2 (silicon dioxide) or SiC (silicon carbide) doped into GST based PCM materials, there is no significant improvement in drift coefficient.

[0111] Various embodiments of the present disclosure provide techniques for managing phase change materials based on SiSbTe (SST) (silicon antimony tellurium) with or without SiC doping, which show lower drift coefficients compared to traditional GST-based materials and can be suitable for analog AI applications, such as analog accelerators. By replacing Ge with Si, SiSbTe-based PCM materials show improved drift performance compared to GST-based materials. SiSbTe PCM materials with specific Si:Sb:Te ratios can have good drift performance (e.g., not greater than 0.04), and the drift coefficient can be further reduced by additional SiC doping (e.g., not greater than 0.03). For reference purposes, in the present disclosure, SiSbTe materials without and with additional SiC or any other dopant doping are referred to as SST-based PCM materials or SST family materials.

[0112] Sb-Te dual alloys can be important phase change materials. Si compositions (or elements) can not only improve data retention and thermal stability, but also maintain good electrical performance. However, too much Si content may reduce the reversible phase change ability and other device parameters of Sb-Te, because the Si in the SST-based PCM material remains amorphous and does not participate in the phase change process. Appropriate SiC doping can improve the drift performance of SST-based PCM materials and increase the crystallization temperature. However, too much SiC doping may reduce the drift performance.

[0113] In addition to low drift coefficients, SST-based PCM materials may also have high crystallization temperatures (e.g., greater than 200 degrees Celsius) to prevent undesired transitions from an amorphous reset state to a crystallized set state at elevated operating temperatures for better data retention. SST-based PCM materials may also have low reset currents (e.g., about 1 mA, compared to undoped GST-225 which requires greater than 1.3 mA under the same measurement conditions) to transition from a crystallized set state to an amorphous reset state. SST-based PCM materials may also have fast set speeds (e.g., about 200 ns) to improve device performance. SST-based PCM materials may have a large impedance range (about 104 to 107 ohms) and may be programmed to multiple impedance states that may correspond to non-overlapping ranges of impedance values ​​and may be normalized as different weights for analog AI applications. For example, a fully reset state is referenced as weight "0", while a fully set state is referenced as weight "1", and any other intermideate states (e.g., partially set and partially reset) correspond to weights ranging from 0 to 1.

[0114] In some embodiments, the bulk stoichiometry of the SST-based PCM material includes: Si atomic concentration ranging from about 7% to about 12%, Sb atomic concentration ranging from about 27% to about 42%, Te atomic concentration ranging from about 40% to about 60%, and / or C atomic concentration ranging from about 10% to about 16%. In addition to the ranges described herein, the techniques implemented herein may enable the development of any other suitable composition of atomic concentrations for the composition Si, Sb, Te and C, such as for various suitable applications including data storage applications and / or analog AI applications. In addition to SiC dopants, other suitable dopants (e.g., SiO2) may also be used in the SST family to improve drift performance, storage performance, read / write performance, or any other suitable performance.

[0115] The SST-based PCM materials as implemented herein may be applied to any device or system including elements that may be written, read and / or erased, and may have properties (e.g., conductivity / resistance) that vary in a range. This technology may be applied to 2-dimensional (2D) memory devices or 3-dimensional (3D) memory devices. This technology may be applied to a variety of memory types, such as single-level cell (SLC) devices, multi-level cell (MLC) devices such as 2-level cell devices, triple-level cell (TLC) devices, quad-level cell (QLC) devices, or penta-level cell (PLC) devices. The technology may be applied to various types of memory systems, such as storage class memory (SCM), persistent memory, embedded phase change memory (PCM), 3D crosspoint memory technology, phase change random access memory (PCRAM), or any other storage system based on various types of memory devices, such as static random access memory (SRAM), dynamic random access memory (DRAM), resistive random access memory (ReRAM), magnetic random access memory (MRAM), or others. Additionally or alternatively, the technology may be applied to systems based on, for example, SCM or PCM, such as universal flash storage (UFS), peripheral component interconnect express (PCIe) storage, embedded multimedia cards (eMMC) storage, storage in dual in-line memory modules (DIMM), or others. The technology can be equally applied to magnetic disks, optical disks or others.This technology can be applied to any suitable application, such as applications using AI mechanisms such as ANN for deep learning. These applications may include games, natural language processing, expert systems, vision systems, speech recognition, handwriting recognition, intelligent robots, data centers, cloud computing services, automotive applications, and others.

[0116] A PCM cell may refer to a basic device comprising a matrix of PCM material coupled between two electrodes. A PCM cell may be used as a memory element, for example in FIG. 16A to FIG. 16D As described in more detail in . The properties of the PCM material (including the drift coefficient) can be determined by measuring the corresponding PCM cells. In the crystallized set state, the measured resistivity or conductivity of the PCM cell is relatively stable over a long period of working cycles. In the amorphous reset state, the resistivity (conductivity) continues to increase (decrease) and stabilizes over time. The reset drift coefficient can be used to indicate the stability of the resistivity or conductivity of the PCM material. The reset drift coefficient is based on the properties of the PCM material and also on the temperature. The reset drift coefficient can be higher at elevated temperature (e.g., 65 degrees Celsius) than when it is at room temperature (e.g., 25 degrees Celsius).

[0117] In the present disclosure, the impedance drift of a PCM cell may be determined by measuring the impedance of the PCM cell over time in an impedance state (e.g., a reset state, a set state, or an intermediate state), plotting this data in a graph of the logarithm of resistance versus the logarithm of time, and then calculating the slope of the plotted data. Slope is sometimes referred to in mathematics as gradient, which is a number that measures the slope and direction of a line or line segment connecting two points. Slope may vary substantially with height and horizontal distance, and is referred to as "rise over run." Slope v may be mathematically represented as:

[0118] V = (y2-y1) / (x2-x1),

[0119] In the above equations, y2-y1 = Δy or the vertical change in the graph, while x2-x1 = Δx or the horizontal change in the graph. In the present disclosure, Δy is the change in the logarithm of impedance, and Δx is the change in the logarithm of time.

[0120] Figure 2 A data table 200 of example phase change materials with corresponding compositions (Si, Sb, and Te) and reset drift coefficients (e.g., at room temperature) is shown. For comparison, the properties of the Ge2Sb2Te5 PCM material (atomic percent concentration of composition and) are also listed in Figure 2 middle.

[0121] like Figure 2As shown, by removing the Ge composition, the Sb2Te3 material has a drift coefficient (e.g., 0.06) lower than the Ge2Sb2Te5 material (e.g., 0.08 to 0.10). With additional Si doping (e.g., material A and material B), the reset drift coefficient can be even lower. For example, material A includes Si, Sb, and Te in an atomic percentage concentration of 7:41.9:51.1, and has a reset drift coefficient of about 0.04, for example, Figure 5 In comparison, material B includes Si, Sb and Te in atomic percentage concentrations of 7.6:32.9:59.5 and has a reset drift coefficient of about 0.002, for example Figure 6 More detailed description in .

[0122] Figure 3 to Figure 4 Example performance characteristics of a PCM cell made from an example SiSbTe PCM (Material A) are depicted. Figure 3 RI curves 302 and 304 are shown for the reset state and the set state of material A. Impedance (R) is measured when a reset current (I) is applied to the PCM cell. The reset current may correspond to a reset voltage. Figure 3 As shown in the reset current of about 650 μA, the reset state and the set state of material A begin to have a large impedance difference (e.g., from about 2×10 4 Ohms to about 10 7 Ohms). The reset current of material A (e.g., about 650 μA) is lower than the reset current of Ge2Sb2Te5 (e.g., about 1.3 to 1.5 mA), for example, using a test device of the same size under the same test conditions.

[0123] Figure 4 U curve 402, curve 404, curve 406 and curve 408 showing the relationship between the impedance of the PCM cell and the applied set pulse (voltage value and pulse width) during the set operation are shown. The pulse width represents the set speed. U curve 402 shows the impedance change when the set pulse is 50ns pulse width at different voltages, U curve 404 shows the impedance change when the set pulse is 200ns pulse width at different voltages, U curve 406 shows the impedance change when the set pulse is 1μs pulse width at different voltages and U curve 408 shows the impedance change when two sequential reset / set pulses (e.g., reset pulse (e.g., 6V / 50ns to reset) followed by set pulse (e.g., 2V / 1μs)) are 1μs pulse width at different voltages. It shows that the set operation of material A requires a set pulse with a pulse width greater than 200ns, e.g., 1μs.

[0124] Figures 5 and 6 Example performance characteristics of a PCM cell made from an example SiSbTe PCM (Material B) are depicted. Figure 5RI curves 502 and 504 are shown for the reset state and the set state of material B. Impedance (R) is measured when a reset current (I) is applied to the PCM cell. Figure 5 It is shown that at a reset current of about 1.1 mA, the reset state and the set state of material B begin to have a large impedance difference (e.g., from about 10 4 Ohms to about 10 6 Ohms). The reset current of material B (e.g., about 1.1 mA) is lower than the reset current of Ge2Sb2Te5 (about 1.3 to 1.5 mA). Compared to material B, material A has a larger impedance difference and a lower reset current, representing better performance.

[0125] Figure 6 U curve 602, curve 604, curve 606 and curve 608 showing the relationship between the impedance of the PCM cell and the applied setting pulse (voltage value and pulse width) during the setting operation are shown. U curve 602 shows the impedance change when the setting pulse is 50ns pulse width at different voltages, U curve 604 shows the impedance change when the setting pulse is 200ns pulse width at different voltages, U curve 606 shows the impedance change when the setting pulse is 1μs pulse width at different voltages, and U curve 608 shows the impedance change when two sequential setting pulses are 1μs pulse width at different voltages. It shows that the setting operation of material B requires a setting pulse with a pulse width of about 200ns. Compared with material A, material B has a faster setting speed.

[0126] Next, to test the drift characteristics of the PCM material, the impedance of the PCM cell is respectively determined based on the change of the PCM material over time at an elevated temperature (e.g., 65 degrees Celsius). At the same time, the PCM cell having the PCM material is programmed to multiple impedance states (corresponding to multiple impedance values) between a fully reset state (having the highest impedance value) and a fully set state (having the lowest impedance value). Intermediate impedance states between the fully reset state and the fully set state may be partially reset (or amorphized) and partially set (or crystallized). As discussed herein, multiple impedance states may correspond to multiple conductivities, which may be used as a series of weights in analog AI applications.

[0127] Figure 7 Drift performance characteristics (at 65 degrees Celsius) of a PCM cell made from material A programmed to a range of resistance states over a period of one hour are shown. A range of resistance states can be obtained by programming material A at different voltages. Figure 7 The diagram (a) shows the impedance change over time for a series of impedance states. Figure 7 Graph (b) shows the conductivity change over time for a series of impedance states. Conductivity (G) is the inverse of impedance (R), for example, G=1 / R. Figure 7Graph (c) of shows the change (%) of G over time for a series of impedance states. It shows that the respective conductivity of a series of impedance states of material A varies in the range from about -15% to -40% z.

[0128] Figure 8 Drift performance characteristics (at 65 degrees Celsius) of a PCM cell made from material B programmed to a range of resistance states over a period of one hour are shown. A range of resistance states can be obtained by programming material B at different voltages. Figure 8 The diagram (a) shows the impedance change over time for a series of impedance states. Figure 8 Graph (b) shows the conductivity change over time for a series of impedance states. Figure 8 Graph (c) of FIG. 1 shows a series of impedance states with time G changes (%). It shows that the individual conductivity changes of a series of impedance states of material B are less than 10%, which is more stable than material A.

[0129] Fig. 9 The drift performance characteristics of a PCM cell made from material B programmed to a range of impedance states over a one-day period (at 65 degrees Celsius) are shown. A range of impedance states can be obtained by programming material B at different voltages. Fig. 9 The diagram (a) shows the impedance change over time for a series of impedance states. Fig. 9 Graph (b) shows the conductivity change over time for a series of impedance states. Fig. 9 Figure (c) shows a series of impedance states G changes over time (%). It shows that the conductivity of a series of impedance states of material B increases with temperature rise of about 10 4 s (about 2.8 hours) is stable, and the corresponding conductivity G changes by about 10% during this period. The conductivity change becomes larger after this time.

[0130] As shown above, material A has a larger impedance difference and a lower reset current than material B, and has a lower drift coefficient than Ge2Sb2Te5 material. To further improve the drift coefficient of material A, SiSbTe PCM material can be doped with SiC. SiC-doped SiSbTe can be obtained by using SiSbTe PCM material and SiC material as co-sputter targets. For example, Fig. 10A The material C (or material D) shown in FIG. 4 can be formed by using the material A as the first plating target and a SiC material with a low SiC density as the second plating target.

[0131] Fig. 10AAn example phase change material having various atomic concentrations at various corresponding compositions (Si, Sb, Te and C) is shown. It is shown that compared to material A (Si:Sb:Te=7:41.9:51.1), at low SiC doping, material C has a higher Si atomic concentration (7.4%), a lower Sb atomic concentration (27.3%), a slightly lower Te atomic concentration (49.8%), and an additional C atomic concentration (15.5%). Compared to material C, at high SiC doping, material D has a higher Si atomic concentration (9.2%), a higher Sb atomic concentration (34.3%), a lower Te atomic concentration (42.1%), and a slightly lower C atomic concentration (14.5%). Therefore, with more SiC doping, the Si atomic concentration can be increased, the Sb atomic concentration can be increased, the Te atomic concentration can be reduced, and the C atomic concentration can be reduced.

[0132] Fig. 10B Draw Fig. 10A The resistivity of material A, material C and material D as a function of temperature. Fig. 10B The resistivity versus temperature curves for material A (trace 1000 ), material C (trace 1010 ), and material D (trace 1020 ) are shown and can be used to determine the crystallization temperature Tx for the different materials.

[0133] As in Fig. 10B As shown in , the resistivity of materials C and D begins to decrease significantly at a temperature of about 240 degrees Celsius. This means that the crystallization temperature of materials C and D is about 240 degrees Celsius. The resistivity of material A begins to decrease significantly at about 225 degrees Celsius, which means that the crystallization temperature of material A is about 225 degrees Celsius. Materials C and D have higher crystallization temperatures than material A, thereby achieving the desired performance characteristics and improving data retention at elevated temperatures. This means that additional SiC doping into material A (or SiSbTe PCM material) can slightly increase the crystallization temperature and thus achieve better data retention.

[0134] As in Fig. 10B As shown in FIG. 1 , the resistivity of material A in the crystallized setting state 1002 is less than 0.01 Ω-cm. The resistivity of material C in the crystallized setting state 1012 at a lower temperature is greater than 0.01 Ω-cm (about 0.02 Ω-cm), and becomes smaller (e.g., to 0.01 Ω-cm) as the temperature increases. The resistivity of material D in the crystallized setting state 1022 is less than 0.01 Ω-cm over the entire temperature range, and becomes larger as the temperature increases.

[0135] Fig.11 Example performance characteristics of a PCM cell made from example SiSbTe (Material C) with low SiC (Silicon Carbide) doping are depicted. Fig.11Graph (a) of FIG. 1 shows RI curves 1102 and 1104 for the reset state and the set state of material C. Impedance (R) is measured when a reset current (I) is applied to the PCM cell. The reset current may correspond to a reset voltage. Fig.11 Figure (a) shows that at a reset current of about 1.1 mA, the reset state and the set state of material C begin to have a large impedance difference (e.g., from about 4×10 4 Ohm to about 2×10 6 Ohms). The reset current of material C (e.g., about 1.1 mA) is lower than the reset current of Ge2Sb2Te5 (about 1.3 to 1.5 mA).

[0136] Fig.11 Figure (b) shows U curves 1112, 1114, 1116 and 1118 showing the relationship between the impedance of the PCM cell and the applied setting pulse (voltage value and pulse width) during the setting operation. The pulse width represents the setting speed. U curve 1112 shows the impedance change when the setting pulse is 50ns pulse width at different voltages, U curve 1114 shows the impedance change when the setting pulse is 200ns pulse width at different voltages, U curve 1116 shows the impedance change when the setting pulse is 1μs pulse width at different voltages, and U curve 1118 shows the impedance change when two sequential setting pulses are 1μs pulse width at different voltages. It shows that the setting operation of material C requires a setting pulse with a pulse width of about 200ns.

[0137] Fig.12 Example performance characteristics of a PCM cell made from example SiSbTe (Material D) with high SiC (Silicon Carbide) doping are shown. Fig.12 Graph (a) of FIG. 1 shows RI curve 1202 and curve 1204 for the reset state and the set state of material D. Impedance (R) is measured when a reset current (I) is applied to the PCM cell. Fig.12 Figure (a) shows that at a reset current of about 1.0 mA, the reset state and the set state of material D begin to have a large impedance difference (e.g., from about 6×10 4 Ohm to about 3×10 6 Ohms). The reset current of material D (e.g., about 1 mA) is lower than the reset current of Ge2Sb2Te5 (about 1.3 to 1.5 mA). Compared to material C, material D has a larger impedance difference and a slightly lower reset current, representing better performance.

[0138] Fig.12Graph (b) of FIG. 1 shows U curves 1212, 1214, 1216 and 1218 showing the relationship between the impedance of the PCM cell and the applied set pulse (voltage value and pulse width) during the set operation. U curve 1212 shows the impedance change when the set pulse is 50ns pulse width at different voltages, U curve 1214 shows the impedance change when the set pulse is 200ns pulse width at different voltages, U curve 1216 shows the impedance change when the set pulse is 1μs pulse width at different voltages, and U curve 1218 shows the impedance change when two sequential set pulses are 1μs pulse width at different voltages. It shows that the set operation of material D requires a set pulse with a pulse width of about 200ns, similar to material C. Compared with material A, both material C and material D have faster set speed, smaller impedance range and higher reset current.

[0139] Next, to test the drift characteristics of the SiC-doped SiSbTe PCM material, the impedance of the PCM cell is determined based on the change of the PCM material at an elevated temperature (e.g., 65 degrees Celsius) over time (e.g., 2.8 hours or one day). At the same time, the PCM cell with the PCM material is programmed to multiple impedance states (corresponding to multiple impedance values) between a fully reset state (with the highest impedance value) and a fully set state (with the lowest impedance value).

[0140] Fig.13 The drift performance characteristics (at 65 degrees Celsius) of a PCM cell made from material C programmed to a range of impedance states are shown, for example, in the set state (about 4×10 4 Ohms) and reset state (e.g. 2×10 6 A range of impedance states can be obtained by programming material C with different voltages. As noted above, the drift coefficient of the impedance state can be obtained by plotting the measurement points over time. Fig.13 Figure (a) shows a series of impedance states at 10 4 seconds (or 2.8 hours) of impedance change, from which the drift coefficient can be calculated separately. Fig.13 Graph (b) of FIG. 1 shows the drift coefficient from the set state to the reset state of material C. It shows that for material C, the total drift coefficient is less than + / - 0.02, which is lower than the total drift coefficient of material A (e.g., about 0.04), also at room temperature. Fig.13 Figure (c) shows the distribution of drift coefficients in each state (including the set state, reset state and intermediate state). The reset drift coefficient of material C is about 0.02, which is lower than the reset drift coefficient of material A (e.g., about 0.04), and the same is true at room temperature.

[0141] Fig.14The drift performance characteristics (at 65 degrees Celsius) of a PCM cell made from material D programmed to a range of impedance states are shown, for example, in the set state (about 4×10 4 Ohms) and reset state (e.g. 2×10 6 A range of impedance states can be obtained by programming material D with different voltages. As noted above, the drift coefficient of the impedance state can be obtained by plotting the measurement points over time. Fig.14 Figure (a) shows a series of impedance states at 10 4 seconds (or 2.8 hours) of impedance change, from which the drift coefficient can be calculated separately. Fig.14 Graph (b) shows the drift coefficient from the set state to the reset state of material D. It shows that for material D, the total drift coefficient is less than + / - 0.03, which is lower than the total drift coefficient of material A (e.g., about 0.04), also at room temperature. Fig.14 Figure (c) shows the distribution of drift coefficients in various states (including set state, reset state and intermediate state). The reset drift coefficient of material D is about 0.03, which is lower than the reset drift coefficient of material A (e.g., about 0.04), also at room temperature. Compared with material D, material C shows a lower reset drift coefficient. The results show that SiC doping can improve drift performance. With higher SiC doping, the drift performance may decrease slightly.

[0142] Fig.15 The drift performance characteristics of a PCM cell made from material C programmed to a range of impedance states over a one-day period (at 65 degrees Celsius) are shown. A range of impedance states can be obtained by programming material C at different voltages. Fig.15 Graph (a) shows the conductivity change over time for a series of impedance states. Fig.15 Figure (b) shows the G change (%) of a series of impedance states over time. It shows that the conductivity of a series of impedance states of material C is stable after one day of temperature increase, and the corresponding G change of a series of impedance states in one day is about 10%, showing better performance than material B (such as Fig. 9 Drift performance).

[0143] Note that material A, material B, material C, and material D described in the present disclosure are only examples of SST-based PCM materials or SST family materials. Other applicable compositions with different atomic percentage concentrations of Si, Sb, Te, and C may also be used to improve drift performance and / or other performance (e.g., high crystallization temperature, low reset current, fast reset speed, fast set speed, and / or large impedance range). The total atomic percentage concentration of the different compositions is 100%.

[0144] For example, the SST-based PCM material may include Si having an atomic percent concentration in a first range between a minimum concentration and a maximum concentration. The minimum concentration of the first range may be about 1%, 2%, 3%, 4%, 5%, 6%, 7%, or 8%, and the maximum concentration of the first range may be 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, or 20%. In one example, the first range is from about 7% to 12%. The SST-based PCM material may include Sb having an atomic percent concentration in a second range. The minimum concentration of the second range may be about 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, or 30%, and the maximum concentration of the second range may be 31%, 32%, 33%, 34%, 35%, 36%, 37%, 38%, 39%, 40%, 41%, 42%, 43%, 44%, or 45%. In one example, the second range is from about 27% to 42%. The SST-based PCM material may include Te with an atomic percentage concentration in a third range. The minimum concentration of the third range may be about 35%, 36%, 37%, 38%, 39%, 40%, 41%, 42%, 43%, 44% or 45%, and the maximum concentration of the third range may be 50%, 51%, 52%, 53%, 54%, 55%, 56%, 57%, 58%, 59%, 60%, 61%, 62%, 63%, 64% or 65%. In one example, the second third range is from about 40% to 60%. The SST-based PCM material may include C with an atomic percentage concentration in a fourth range. The minimum concentration of the fourth range may be about 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14% or 15%, and the maximum concentration of the fourth range may be 15%, 16%, 17%, 18%, 19% or 20%. In one example, the fourth range is from about 10% to 42%.

[0145] The PCM materials described herein (eg, SST-based PCM materials with good drift performance) can be used to develop memory devices, such as FIG. 16A to FIG. 16D The memory element can be used to form a phase change memory device with good drift performance, for example in FIG. 17A to FIG. 17B Phase change memory devices with good drift performance can be used in analog AI systems, such as FIG. 18A to FIG. 20B More detailed description in .

[0146] Fig.16AA cross-sectional view of an example memory device 1600 made from a PCM material having a mushroom-type structure is shown. The PCM material may be an SST-based PCM material, such as Material A, Material B, Material C, Material D, or any other SST-based PCM material as described herein.

[0147] In some embodiments, for example Fig.16A As shown in FIG. 1 , the memory element 1600 includes a memory substrate 1602 of a PCM material as a memory material. The memory element 1600 includes an active region 1604. The memory element 1600 includes a first electrode 1606 extending through a dielectric layer 1608 to contact a bottom surface of the memory substrate 1602. A second electrode 1610 is formed on the memory substrate 1602 to generate a current between the first electrode 1606 and the second electrode 1610 through the memory substrate 1602. The first electrode 1606 and the second electrode 1610 may include, for example, TiN (titanium nitride) or TaN (tantalum nitride). Alternatively, the first electrode 1606 and the second electrode 1610 may each be W (tungsten), WN (tungsten nitride), TiAlN (titanium aluminum nitride) or TaAlN (tantalum aluminum nitride), or include, for example, one or more elements selected from the group consisting of one or more of the following elements: doped Si, Si, C, Ge, Cr (chromium), Ti (titanium), W, Mo (molybdenum), Al (aluminum), Ta, Cu (copper), Pt (platinum), Ir (iridium), La (lanthanum), Ni (tweezers), N (nitrogen), O (oxygen), Ru (ruthenium) or a combination thereof. The dielectric layer 1608 may include silicon nitride, silicon oxynitride, silicon oxide and other suitable dielectric materials.

[0148] The memory device 1600 includes a first electrode 1606 having a relatively narrow side 1612 (or outer diameter). The narrow side 1612 of the first electrode 1606 causes the area of ​​contact between the first electrode 1606 and the memory substrate 1602 to be smaller than the area of ​​contact between the memory substrate 1602 and the second electrode 1610. Therefore, current is concentrated in the portion of the memory substrate 1602 adjacent to the first electrode 1606, resulting in the active region 1604 contacting or adjacent to the first electrode 1606, as shown in the figure. The memory substrate 1602 also includes an inactive region outside the active region 1604, which is inactive in the sense that it does not undergo a phase transition during operation. Although the inactive region outside the active region 1604 does not undergo a phase transition during device operation, the bulk stoichiometry of the entire memory substrate 1602 including the active region 1604 and the inactive region includes PCM material.

[0149] Fig. 16BA cross-sectional view of an example memory element 1630 made from a PCM material having an "active-in-via" type structure is shown. The PCM material can be an SST-based PCM material, such as Material A, Material B, Material C, Material D, or any other SST-based PCM material as described herein.

[0150] In some embodiments, for example Fig. 16B As shown in FIG. 1 , the memory element 1630 includes a memory matrix 1632 of PCM material passing through the memory matrix 1632 in an alternating electrode current path. The memory matrix 1632 is pillar-shaped and contacts a first electrode 1634 and a second electrode 1636 at an upper surface 1638 and a lower surface 1640, respectively. The memory matrix 1632 has a width 1644 that is substantially the same as the width of the first electrode 1634 and the second electrode 1636 to define a multi-layer pillar surrounded by a dielectric layer (not shown). As used herein, the term "substantially" means to accommodate manufacturing tolerances. In operation, as current passes through the memory matrix 1632 between the first electrode 1634 and the second electrode 1636, the active region 1642 heats faster than other areas within the memory element. This results in most phase transitions occurring within the active region during device operation.

[0151] Fig. 16C A cross-sectional view of an example memory element 1650 made from a PCM material having a pore-type structure is depicted. The PCM material may be an SST-based PCM material, such as Material A, Material B, Material C, Material D, or any other SST-based PCM material as described herein.

[0152] The memory element 1650 includes a memory base 1652 of PCM material passing through the memory base 1652 in an alternating electrode current path. The memory base 1652, surrounded by a dielectric layer (not shown), contacts a first electrode 1654 and a second electrode 1656 at an upper surface 1658 and a lower surface 1660, respectively. The memory base 1652 has a varying width 1662, which is generally smaller than the width of the first electrode 1654 and the second electrode 1656. In operation, as current passes through the memory base 1652 between the first electrode 1654 and the second electrode 1656, the active region 1664 heats faster than the rest of the memory element. Therefore, most phase transitions occur in the volume of the memory base 1652 within the active region during device operation.

[0153] Fig.16DA cross-sectional view of an example memory structure 1670 including a plurality of memory elements 1670a made from a PCM material having a cross-point structure is depicted. The PCM material may be an SST-based PCM material, such as Material A, Material B, Material C, Material D, or any other SST-based PCM material as described herein.

[0154] Each memory element 1670a includes a memory matrix 1672 of PCM material, a first electrode 1674, and a second electrode 1676. A switching layer 1678 may be positioned between the first electrode 1674 and the second electrode 1676. Fig.16D As shown in, in the cross-point structure, the first electrode 1674 can be shared by multiple memory elements 1670a along a first direction (e.g., direction Y), the second electrode 1676 can be shared by multiple memory elements 1670a along a second direction (e.g., direction X), and multiple memory elements 1670a can be stacked along a third direction (e.g., direction Z).

[0155] It will be understood that the PCM materials described herein may be used in a variety of memory device structures and are not limited to the memory device structure described herein.

[0156] Memory elements (e.g. Fig.16A The memory element 1600, Fig. 16B The memory element 1630, Fig. 16C The memory element 1650 or Fig.16D The memory structure 1670) can be used to form a phase change memory device, for example FIG. 17A to FIG. 17B More detailed description in .

[0157] Fig.17AA schematic diagram of an integrated circuit 1700 including an array of phase change memory cells is shown. The integrated circuit 1700 may be a phase change memory device. The phase change memory 1700 includes a phase change memory array 1705 of phase change memory cells that may be operated as described herein. A word line decoder and driver 1710 having read, set, reset, set verify, reset verify, and high current repair modes is coupled to and electrically communicates with a plurality of word lines 1715 arranged along rows in the phase change memory array 1705. A (column) bit line decoder 1720 is electrically communicated with a plurality of bit lines 1725 arranged along rows in the phase change memory array 1705 for reading data from or writing data to the phase change memory cells in the phase change memory array 1705. Addresses are supplied to the word line decoder and driver 1710 and the bit line decoder 1720 on a bus 1760. Sense circuits (sense amplifiers) and block data-in structures 1730 are coupled to bit line decoders 1720 via data buses 1735. Data is provided to block data-in structures 1730 via data-in lines 1740 from input / output terminals on integrated circuit 1700 or from other data sources internal or external to integrated circuit 1700. Other circuits 1765 may be included on integrated circuit 1700, such as general purpose processors or special purpose application circuits, or a combination of modules that provide system-on-a-chip functions supported by phase change memory array 1705. Data is provided from block data-in structures 1730 to input / output terminals on integrated circuit 1700 or to other data destinations internal or external to integrated circuit 1700 via data-out lines 1745.

[0158] Integrated circuit 1700 includes controller 1750 for read, set, reset, set verify, reset verify, and high current repair modes. Implementation in this example, controller 1750 uses a bias arrangement state machine to control the application of bias arrangement supply voltage and current source 1755, in the application of bias arrangement including read, set, reset, set verify, reset verify, and high current repair modes. Controller 1750 is coupled to the sense amplifier in block 1775 for controlling bias arrangement supply voltage and current source 1755 in response to output signals from block data input structure 1730. Controller 1750 may be implemented using special-purpose logic circuitry as is known in the art. In alternative embodiments, controller 1750 includes a general purpose processor that may be implemented on the same integrated circuit to execute a computer program to control the operation of integrated circuit 1700.

[0159] Fig. 17B Drawn on Fig.17A An example of the operation of a portion of a phase change memory cell in the phase change memory array 1705. Fig. 17B As shown in FIG. , each memory cell includes a memory element (eg Fig.16A The memory element 1600, Fig. 16B The memory element 1630, Fig. 16C The memory element 1650 or Fig.16D The memory structure 1670 of the present invention may include a memory cell 1670 of the present invention, or any PCM cell as described herein) and an access device (such as a transistor, a diode, or a selector switch). The memory element may be used as a resistor element. The memory cell may have a 1S1R structure including a selector and a resistor element.

[0160] As in Fig. 17B As shown in FIG. 1 , four memory cells 1780, 1782, 1784, and 1786 have phase change memory elements 1780a, 1782a, 1784a, and 1786a, respectively, and access devices 1780b, 1782b, 1784b, and 1786b, respectively. The memory cells can be programmed to a plurality of impedance states including a high impedance state (e.g., a reset state) and a low impedance state (e.g., a set state), corresponding to a non-overlapping range of impedance values ​​for the phase change memory elements.

[0161] In some embodiments, the sources of each access transistor of memory cell 1780, memory cell 1782, memory cell 1784, and memory cell 1786 are commonly connected to source line 1788, which terminates in source line termination circuit 1785. In other embodiments, the sources of the access devices are not electrically connected, but are independently controllable. Source line termination circuit 1785 may be, for example, a ground terminal. Alternatively, in some embodiments, source line termination circuit 1785 may include bias circuitry such as a voltage source and a current source and encoding circuitry for applying a bias configuration to source line 1788 instead of ground.

[0162] A plurality of word lines including word lines 1794 and word lines 1796 extend in parallel along a first direction. Word lines 1794 and word lines 1796 are in electrical communication with word line decoder 1711. Gates of access transistors of memory cells 1780 and 1784 are connected to word line 1794. Gates of access transistors of memory cells 1782 and 1786 are connected to word line 1796. A plurality of word lines including bit lines 1790 and bit lines 1792 extend in parallel along a second direction. Bit lines 1790 and bit lines 1792 are in electrical communication with bit line decoder 1720. Phase change memory elements 1780a and 1782a couple bit lines 1790 to corresponding drains of access transistors of memory cells 1780 and 1782. Phase change memory element 1784a and phase change memory element 1786a couple bit line 1792 to corresponding drains of access transistors of memory cell 1784 and memory cell 1786 .

[0163] It will be understood that the phase change memory array 1705 is not limited to Fig. 17B The array configuration shown in FIG. 1 is a schematic diagram of an array configuration. Other array configurations may also be used. Additionally, instead of MOS transistors, bipolar transistors or diodes may be used as access devices in some embodiments.

[0164] In operation, each of memory cell 1780, memory cell 1782, memory cell 1784, and memory cell 1786 stores a data value based on the impedance of its corresponding phase change memory element 1780a, phase change memory element 1782a, phase change memory element 1784a, and phase change memory element 1786a. The data value can be determined, for example, by comparing the current on the bit line used to select the memory cell with its reference current. In memory cells that can be programmed to three or more impedance states, multiple reference currents can be established so that different ranges of bit line currents correspond to each of the three or more impedance states.

[0165] Reading or writing to a selected memory cell of the phase change memory array 1705 can be accomplished by applying appropriate voltages to the corresponding word line and coupling the corresponding bit line to a bias voltage, causing current to flow through the selected memory cell including through the corresponding memory element. For example, a current path 1798 through the selected memory cell 1782 is established sufficiently by applying a bias voltage to the bit line 1790, the word line 1796, and the source line 1788 to turn on the access transistor of the memory cell 1782, and induce current in the flow path 1798, from the bit line 1790 to the source line 1788, or vice versa.

[0166] In a read (or sense) operation of memory cell 1782, a bias voltage is applied across the selected memory cell to induce a current through the memory element. The current does not cause the memory element to undergo a change in impedance state. The magnitude of the current through the memory element depends on the impedance of the memory element, and thus the data value stored in memory cell 1782. Thus, the induced current is used to read the memory cell, as the magnitude of this current depends on which impedance state of the memory element corresponds to the stored or absent data value.

[0167] Fig.18A and Fig.18B An example of an artificial neural network (ANN: 1800) and an expanded diagram of a neuron N6 of the ANN 1800 are shown respectively. Fig.18A As shown in , ANN 1800 is a collection of connected units or nodes, such as neuron N0, neuron N1, neuron N2, neuron N3, neuron N4, neuron N5, neuron N6, neuron N7 and neuron N8, all of which are called artificial neurons. Multiple artificial neurons are organized in multiple layers. For example, layer L0 includes neuron N0, neuron N1 and neuron N2; layer L1 includes neuron N3, neuron N4, neuron N5 and neuron N6; and layer L2 includes neuron N7 and neuron N8.

[0168] In some embodiments, multiple different layers of an ANN perform different types of transformations on their inputs. One of the multiple different layers is the first or input layer of the ANN, such as layer L0, while another layer is the last or output layer of the ANN, such as layer L2. The ANN includes one or more internal layers, such as layer L1, between the input layer and the output layer. After one or more round trips to the internal layers, the signal moves from the input layer to the output layer.

[0169] In some embodiments, at each connection point between artificial neurons, such as a connection point from neuron N2 to neuron N6, or a connection point from neuron N6 to neuron N8, a signal can be transmitted from one to another. The artificial neuron that receives the signal can process the signal, and then the signal artificial neuron is connected to the signal. In some embodiments, the signals at the connection points between multiple artificial neurons are real numbers, and the output of each artificial neuron is calculated as a nonlinear function of the sum of its inputs. Each connection point can have a weight that is adjusted as the learning process progresses. The weight increases or decreases the strength of the signal at the connection point.

[0170] In some embodiments, a combination of input data (e.g., from various samples) is presented to the ANN, such as at an input layer such as layer L0. A series of operations are performed at each subsequent layer such as layer L1. Fig.18A In the fully connected network shown in , the output operation from each node is presented to all nodes in the subsequent layer. The final layer of a trained ANN, such as layer L2, can be associated with determining a classification that matches the input data, for example from a fixed combination of multiple labeled candidates, which can be regarded as "supervised learning".

[0171] Fig.18B An expanded diagram of the operation performed on artificial neuron N6, which is represented as an example of an artificial neuron in an ANN. Input signals x0, x1, and x2 from other artificial neurons of the ANN 1800, such as from artificial neuron N0, neuron N1, and neuron N2, are transmitted to artificial neuron N6. Each input signal is weighted by the weight associated with the corresponding connection point, and the weighted signal is received and processed by the artificial neuron. For example, the connection point from artificial neuron N0 to artificial neuron N6 has a weight w0, and the weighted signal x0 is transmitted from neuron N0 to neuron N6 through the connection point, resulting in the value of the signal received and processed by neuron N6 being w0 x0. Similarly, multiple connection points from artificial neuron N1 and neuron N2 to artificial neuron N6 have weights w1 and w2, respectively, resulting in the values ​​of multiple signals received and processed by neuron N6 from neuron N1 and neuron N2 being w1 x1 and w2 x2, respectively.

[0172] The artificial neuron processes weighted input signals internally, such as by changing its internal state (deemed as activation) in accordance with the input, and generates an output signal in accordance with the input and activation. For example, artificial neuron N6 generates an output signal that is a result of an output function f, which is applied to a weighted combination of multiple input signals received by artificial neuron N6. In this manner, the artificial neurons of ANN 1800 form a graph with weights directed that connects multiple outputs of several neurons to multiple inputs of other neurons. In some embodiments, multiple weights, activation functions, output functions, or any combination of these parameters of the artificial neuron can be modified by a learning process, such as deep learning.

[0173] In some embodiments, the operation is a multiply-accumulate (MAC) calculation, which may be an action in an AI operation. Fig.18B As shown in FIG. , each data value x of multiple input signals i by its associated weight w i The products are then summed to get ∑ i w i x i , and finally the bias value b can be added to obtain the calculated value z=∑ i w i x i + b. Then, the operation value z is calculated by starting the function f to obtain the output value a=f(∑ i w i x i + b). The output value a can be provided as a node output (or output signal) to the next layer as input.

[0174] For example, the AI ​​model of ANN 1800 can be operated in training mode and reasoning mode. For the AI ​​model to provide answers to questions, multiple connection points between answers and questions can be strengthened by repeatedly performing network training. In training mode, initially, a combination of test data with correct labels known as training materials is given to the AI ​​model. Then, the reasoning of the AI ​​model generated by the combination of test data is monitored, and the AI ​​model can respond true or false. The goal of the learning method is to detect patterns, and what the AI ​​model does in this case is to search and classify data based on data similarity. The AI ​​training model can be similar to training in multimedia data processing. Mathematically, in training mode, multiple weights in the AI ​​model are adjusted to maximize output. In reasoning mode, the AI ​​model is placed in practice based on what is learned in training. The AI ​​model can generate a reasoning model with training and fixed weights to classify, solve, and / or answer questions.

[0175] Fig.19An example memory 1900 for performing multiply-accumulate (MAC) is shown. The memory 1900 may be a phase change memory device as described in the present disclosure, for example, FIG. 17A to FIG. 17B Integrated circuit 1700 in. Memory 1900 Phase change memory array (such as in FIG. 17A to FIG. 17B The phase change memory array 1705 in FIG. 1 includes a plurality of memory cells 1910, 1920, 1930, and 1940 (as shown in FIG. 1 ). Fig. 17B 1780, memory cell 1782, memory cell 1784, or memory cell 1786). The memory cell may include a memory element, such as Fig.16A The memory element 1600, Fig. 16B The memory element 1630, Fig. 16C The memory element 1650 or Fig.16D Memory structure 1670, Fig. 17B Memory element 1780a, memory element 1782a, memory element 1784a, or memory element 1786a, or any PCM cell as described herein. Memory cell 1910, memory cell 1920, memory cell 1930, and memory cell 1940 include, for example, memory element 1911, memory element 1921, memory element 1931, and memory element 1941, respectively, as corresponding resistors corresponding to corresponding conductivity G1, conductivity G2, conductivity G3, and conductivity G4.

[0176] When voltage V1, voltage V2, voltage V3 and voltage V4 are respectively input to bit line BL2, a plurality of corresponding read currents I1, current I2, current I3 and current I4 flow into word line WL2. Read current I1 is equal to the product of voltage V1 and conductivity G1; read current I2 is equal to the product of voltage V2 and conductivity G2; read current I3 is equal to the product of voltage V3 and conductivity G3; read current I4 is equal to the product of voltage V4 and conductivity G4. The total current I is equal to the sum of the products of voltage V1, voltage V2, voltage V3 and voltage V4 and conductivity G1, conductivity G2, conductivity G3 and conductivity G4. If voltage V1, voltage V2, voltage V3 and voltage V4 are represented as input signal x i And conductivity G1, conductivity G2, conductivity G3 and conductivity G4 are expressed as weight w i , then the total current I is expressed as the input signal x i and weight w i The sum of the products is as follows:

[0177]

[0178] Through Fig.19 In the memory 1900, the MAC in the AI ​​operation can be implemented.

[0179] Fig. 20A An example system 2000 for performing a training mode is shown. The system 2000 includes a memory 2010 including, for example, a plurality of memory cells 2020 arranged in a matrix. ij The system 2000 may further include a plurality of digital-to-analog converters (DAC 2002), each coupled to a corresponding bit line 2003 (eg, Fig.19 Each DAC 2002 is used to convert an input digital signal, such as a voltage Fig.19 The voltages V1, V2, V3 and V4 are converted into analog voltage signals. The system 2000 may also include a plurality of sampling and holding units 2004 (S&H units), each of which is coupled to a corresponding word line 2005 (eg Fig.19 The analog-to-digital converter (ADC 2006) is coupled to the plurality of sampling and storage units 2004. Each sampling and storage unit 2004 may include one or more logic units and / or circuits for sampling and storing the summed current analog signal (e.g., Fig.19 ), and ADC 2006 can be used to sum the summed current analog signals from each word line 2005 and convert the final summed result from an analog signal to a digital signal for further processing.

[0180] Each memory unit 2020 ij May have, for example, an adjustable resistor 2022 ij . Each adjustable resistor is 2022 ij With conductivity G ij These conductivity G ij Can be used to represent the weight w ij ,For example Fig.18B The weight w shown in i When the memory 2010 executes the training mode, the weight w ij needs to be continuously updated so that the adjustable resistor 2022 ij The memory 2010 can be smoothly used to execute the training mode.

[0181] Fig. 20B An example system 2050 for executing the inference mode is shown. System 2050 is similar to system 2000, including DAC 2002, sample and hold unit 2004, and ADC 2006. Fig. 20AIn the system 2000, the system 2050 includes a memory 2060, which is different from the memory 2010. The memory 2060 includes, for example, a plurality of memory cells 2070 arranged in a matrix. ij Each memory unit 2070 ij May have, for example, a fixed resistor 2072 ij , unlike 2022 with adjustable resistor ij Memory Unit 2020 ij . Each fixed resistor 2072 ij With fixed conductivity G ij These conductivity G ij Can be used to represent fixed weights w ij In the process of executing the inference mode, the weight w ij has been set and will not be changed arbitrarily, for example according to Fig. 20A The trained G ij , so that the fixed resistor 2072 ij The memory 2060 can be smoothly used to execute the reasoning mode. Therefore, it is desirable to have non-volatility and good data retention for AI reasoning to keep the weights fixed at low power consumption. The memory 2060 can be implemented by a phase change memory as described in the present disclosure, for example, FIG. 17B to FIG. 17B Integrated circuit 1700 in. Memory unit 2070 ij It can be implemented by a memory unit as described in the present disclosure, for example Fig. 17B Memory cell 1780, memory cell 1782, memory cell 1784, or memory cell 1786 in the embodiment of the present invention. Fixed resistor 2072 ij It can be implemented by the memory element as described in the present disclosure, for example Fig.16A The memory element 1600, Fig. 16B The memory element 1630, Fig. 16C The memory element 1650 or Fig.16D Memory structure 1670, Fig. 17B 1780a, memory element 1782a, memory element 1784a, or memory element 1786a, or any PCM cell described herein.

[0182] The present disclosure and other examples may be implemented as one or more computer program products, for example, one or more modules of computer program instructions encoded on a computer-readable medium are executed by a data processing device or control the operation of the data processing device. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, or one or more combinations thereof. The term "data processing device" includes all devices, equipment and machines for processing data, including, for example, a programmable processor, a computer or multiple processors or computers. In addition to hardware, this device may include program code that establishes the execution environment of the computer program in question, such as program code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof.

[0183] The system may include all devices, equipment and machines for processing data, including, for example, a programmable processor, a computer or multiple processors or computers. In addition to hardware, the system may include program code that establishes the execution environment of the computer program in question, for example, program code constituting processor firmware, protocol stack, database management system, operating system or one or more combinations thereof.

[0184] A computer program (also referred to as a program, software, software application, instruction code, or program code) may be written in any form of programming language, including compiled or interpreted languages, and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored as part of a file that stores other programs or data (e.g., one or more instruction codes stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, subroutines, or portions of program code). A computer program may be configured to execute on one computer or on multiple computers. The multiple computers may be located at one location or distributed across multiple locations and interconnected by a communications network.

[0185] The procedures and logic flows described herein may be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The procedures and logic flows may also be performed by special purpose logic circuitry, and the apparatus may also be implemented by special purpose logic circuitry, for example, a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0186] Processors suitable for executing computer programs include, for example, both general-purpose microprocessors and special-purpose microprocessors, and any one or more processors of any type of digital computer. Generally speaking, the processor will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer may also include or be operably coupled to one or more mass storage devices for storing data to receive data from the one or more mass storage devices, or to transmit data to the one or more mass storage devices, or both. Examples of the one or more mass storage devices are magnetic disks, magneto-optical disks, or optical disks. However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data may include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks. The processor and memory may be supplemented by or incorporated into dedicated logic circuits.

[0187] Although many details may be described herein, these details should not be interpreted as limitations on the claimed or claimable scope of the present invention, but rather as descriptions of features for specific embodiments. Certain features described herein in separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination. Furthermore, although several features may be described above as acting in certain combinations and even initially claimed as such, one or more features from the claimed combination may be excluded from the combination in some cases, and the claimed combination may be for sub-combinations or variations of sub-combinations. Similarly, although several operations are depicted in a particular order in the drawings, it should not be understood that these operations must be performed in the particular order shown or in a sequential order, or that all described operations must be performed to achieve the desired result.

[0188] Only a few examples and implementations are described. Variations, modifications, and enhancements based on the examples and implementations and other implementations may be accomplished based on what is disclosed.

[0189] In summary, although the present invention has been disclosed above with preferred embodiments and exemplary details, it is to be understood that these examples are intended to illustrate rather than to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached claims.

Claims

1. An integrated circuit, comprising: a first electrode; a second electrode; as well as A body of a phase change material is coupled between the first electrode and the second electrode. Wherein, the phase change material comprises Si x Sb y Te z , where x, y and z represent the atomic ratio of the composition Si (silicon), Sb (antimony) and Te (tellurium), respectively, and Wherein, the bulk stoichiometry of the matrix of the phase change material includes a Si atomic concentration in a range from about 7% to about 12%.

2. The integrated circuit of claim 1 , wherein the bulk stoichiometry of the matrix of the phase change material comprises: a Sb atomic concentration in a range from about 27% to about 42%, and A Te atomic concentration is in a range from about 40% to about 60%.

3. The integrated circuit according to claim 1, wherein the phase change material comprises Si doped x Sb y Te z SiC (silicon carbide) in.

4. The integrated circuit of claim 3, wherein the bulk stoichiometry of the matrix of the phase change material comprises: A C (carbon) atom concentration is in a range of about 10% to about 16%. 5 . The integrated circuit of claim 1 , being used as a memory device having a mushroom-like structure.

6. A phase change memory device comprising a plurality of memory cells, wherein at least one of the memory cells comprises the integrated circuit according to claim 1, and The phase change memory device is used to execute an inference mode of an analog artificial intelligence (AI) model, and in the inference mode, multiple memory elements of the memory cells are programmed to have multiple impedance states corresponding to corresponding multiple weights of the memory cells, and the impedance states correspond to multiple non-overlapping ranges of multiple impedance values.

7. An integrated circuit comprising: a first electrode; a second electrode; as well as A matrix of a phase change material is coupled between the first electrode and the second electrode, The phase change material comprises SiC doped Si x Sb y Te z , wherein x, y and z represent the atomic ratios of Si, Sb and Te in the composition, respectively, Wherein, the bulk stoichiometry of the matrix of the phase change material comprises: A Si atomic concentration is in a range from about 7% to about 12%, A Sb atomic concentration is in a range from about 27% to about 42%, A Te atomic concentration is in a range from about 40% to about 60%, and A C atom concentration is in a range of about 10% to about 16%. 8 . The integrated circuit of claim 7 , wherein a reset drift coefficient of the integrated circuit at a rising temperature is no greater than 0.

04.

9. An integrated circuit as claimed in claim 7, wherein the matrix of the phase change material is programmable to a plurality of impedance states, the impedance states comprising a fully reset state and a fully set state, and The change in conductivity of each of these impedance states does not exceed 10% in one day.

10. A phase change memory device comprising a plurality of memory cells, wherein at least one of the memory cells comprises the integrated circuit according to claim 7, The phase change memory device is used to execute an inference mode of a simulated artificial intelligence model, and In the inference mode, a plurality of memory elements of the memory cells are programmed to have a plurality of impedance states corresponding to a corresponding plurality of weights of the memory cells, the impedance states corresponding to a plurality of non-overlapping ranges of impedance values.

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