MIM capacitor structure and preparation method thereof

Abstract

The invention provides an MIM capacitor structure and a preparation method thereof, in the preparation method, a groove is firstly formed in a first insulating layer, then lamination of a second metal layer, a second insulating layer, a third metal layer, a third insulating layer, an Nth metal layer, an Nth insulating layer and an (N + 1) th metal layer is carried out in the groove, N is an integer greater than or equal to 4, and N is an integer greater than or equal to 4. The method comprises the following steps of: depositing a top dielectric layer on an (N + 1) th metal layer at the top end of a groove, forming a first conductive plug to an Nth conductive plug, and finally realizing parallel connection of multiple paths of MIM capacitors at the bottom of the groove and in the groove through a patterned metal layer at the top, thereby forming a groove type MIM capacitor structure with at least two paths connected in parallel. The MIM capacitor structure prepared by the invention is not only a groove type capacitor structure, but also a parallel capacitor structure, so that the capacitance density in a unit area can be effectively improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a MIM capacitor structure and a method for preparing the same. Background Art

[0002] MIM (Metal-Insulator-Metal) capacitors are also called plate capacitors. The MIM capacitor value is accurate and does not change with bias voltage. Generally, in semiconductor devices, the MIM capacitor structure is composed of a lower metal layer, an insulating dielectric layer, and an upper metal layer.

[0003] Although MIM capacitors have accurate capacitance values, their capacitance per unit area is small, about one-third of the MOM (Metal-Oxide-Metal) capacitance value. Currently, semiconductor devices usually use a single-layer MIM capacitor structure, but it is difficult to increase the capacitance density of a single-layer MIM capacitor structure by reducing the thickness of the dielectric layer. Summary of the invention

[0004] The present application provides a MIM capacitor structure and a preparation method thereof, which can solve the problem of low capacitance density of the MIM capacitor structure in current semiconductor devices.

[0005] On the one hand, an embodiment of the present application provides a method for preparing a MIM capacitor structure, comprising: Providing a semiconductor structure, wherein the top layer of the semiconductor structure is a first metal layer; forming a first insulating layer, wherein the first insulating layer covers the first metal layer; Etching the first insulating layer to the surface of the first metal layer to form a groove; forming a second metal layer, wherein the second metal layer covers the sidewalls and bottom wall of the trench and the first insulating layer; forming a second insulating layer, wherein the second insulating layer covers the second metal layer; forming a third metal layer, wherein the third metal layer covers the second insulating layer; forming a third insulating layer, wherein the third insulating layer covers the third metal layer; forming an Nth metal layer, the Nth metal layer covering the third insulating layer, wherein N is an integer greater than or equal to 4; forming an Nth insulating layer, wherein the Nth insulating layer covers the Nth metal layer; forming an N+1th metal layer, wherein the N+1th metal layer covers the Nth insulating layer and fills a remaining space of the trench; Grinding and removing the second metal layer to the N+1th metal layer and the second insulating layer to the Nth insulating layer beyond the surface of the first insulating layer; forming a top dielectric layer, wherein the top dielectric layer covers the second metal layer to the N+1th metal layer, and the first insulating layer to the Nth insulating layer; forming a first conductive plug, a second conductive plug to an Nth conductive plug, wherein the first conductive plug penetrates the top dielectric layer and the first insulating layer and is connected to the first metal layer, the second conductive plug penetrates the top dielectric layer and is connected to the third metal layer, and the Nth conductive plug penetrates the top dielectric layer and is connected to the N+1th metal layer; A patterned metal layer is formed, wherein the patterned metal layer covers the first conductive plug, the second conductive plug to the Nth conductive plug respectively, so as to form at least two parallel MIM capacitor structures.

[0006] Optionally, in the method for preparing the MIM capacitor structure, the material of the first metal layer and the material of the second metal layer are both copper.

[0007] Optionally, in the method for preparing the MIM capacitor structure, the material of the third metal layer, the material of the Nth metal layer, and the material of the N+1th metal layer are all titanium nitride.

[0008] Optionally, in the method for preparing the MIM capacitor structure, the material of the patterned metal layer is aluminum.

[0009] Optionally, in the method for preparing the MIM capacitor structure, the material of the first insulating layer is silicon dioxide.

[0010] Optionally, in the method for preparing the MIM capacitor structure, the material of the second insulating layer, the material of the third insulating layer and the material of the Nth insulating layer are all silicon nitride.

[0011] Optionally, in the method for preparing the MIM capacitor structure, the thickness of the second insulating layer is 300 angstroms to 700 angstroms; the thickness of the third insulating layer is 300 angstroms to 700 angstroms; and the thickness of the Nth insulating layer is 300 angstroms to 700 angstroms.

[0012] Optionally, in the preparation method of the MIM capacitor structure, the top dielectric layer includes: a stacked SiON layer and an undoped silicon glass layer, the SiON layer covers the second metal layer to the N+1th metal layer, and the first insulating layer to the Nth insulating layer, and the undoped silicon glass layer covers the SiON layer.

[0013] Optionally, in the method for preparing the MIM capacitor structure, a chemical mechanical polishing process is used to polish and remove the second metal layer to the N+1th metal layer and the second insulating layer to the Nth insulating layer that extend beyond the surface of the first insulating layer.

[0014] On the other hand, the embodiment of the present application further provides a MIM capacitor structure, including: A semiconductor structure, wherein the top layer of the semiconductor structure is a first metal layer; a first insulating layer, wherein the first insulating layer covers the first metal layer; a groove, wherein the groove is located in the first insulating layer and exposes the first metal layer at the bottom; a second metal layer, wherein the second metal layer covers the sidewalls and the bottom wall of the trench; a second insulating layer, wherein the second insulating layer covers the second metal layer; a third metal layer, the third metal layer covering the second insulating layer; a third insulating layer, wherein the third insulating layer covers the third metal layer; An Nth metal layer, the Nth metal layer covering the third insulating layer, wherein N is an integer greater than or equal to 4; an Nth insulating layer, the Nth insulating layer covering the Nth metal layer; an N+1th metal layer, the N+1th metal layer covering the Nth insulating layer and filling a remaining space of the trench; A top dielectric layer, the top dielectric layer covering the second metal layer to the N+1th metal layer, and the first insulating layer to the Nth insulating layer; a first conductive plug, a second conductive plug to an Nth conductive plug, wherein the first conductive plug penetrates the top dielectric layer and the first insulating layer and is connected to the first metal layer, the second conductive plug penetrates the top dielectric layer and is connected to the third metal layer, and the Nth conductive plug penetrates the top dielectric layer and is connected to the N+1th metal layer; A patterned metal layer, wherein the patterned metal layer covers the first conductive plug, the second conductive plug to the Nth conductive plug respectively, so as to form at least two parallel MIM capacitor structures.

[0015] The technical solution of this application has at least the following advantages: In the preparation method of the MIM capacitor structure provided in the present application, a groove is first formed in the first insulating layer, and then a second metal layer, a second insulating layer, a third metal layer, a third insulating layer, an Nth metal layer, an Nth insulating layer and an N+1th metal layer are stacked in the groove, wherein N is an integer greater than or equal to 4, and then a top dielectric layer is deposited on the N+1th metal layer at the top of the groove, and then first to Nth conductive plugs are formed, and finally, the parallel connection of multiple MIM capacitors at the bottom of the groove and in the groove is realized through the patterned metal layer of the top layer, thereby forming a trench-type MIM capacitor structure with at least two parallel paths. Compared with the traditional flat plate capacitor, the MIM capacitor structure prepared in the present application is not only a trench-type capacitor structure, but also a parallel capacitor structure, which can effectively improve the capacitance density per unit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 is a flow chart of a method for preparing a MIM capacitor structure according to an embodiment of the present invention; Figure 2-Figure 9 It is a schematic diagram of the semiconductor structure in each process step of preparing the MIM capacitor structure according to an embodiment of the present invention; The reference numerals are described as follows: 10-semiconductor structure, 21-first metal layer, 22-second metal layer, 23-third metal layer, 24-fourth metal layer, 25-fifth metal layer, 31-first insulating layer, 32-second insulating layer, 33-third insulating layer, 34-fourth insulating layer, 40-groove, 50-top dielectric layer, 61-first conductive plug, 62-second conductive plug, 63-third conductive plug, 64-fourth conductive plug, 70-patterned metal layer. DETAILED DESCRIPTION

[0018] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0020] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0021] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0022] The present application embodiment provides a method for preparing a MIM capacitor structure, referring to Figure 1 , Figure 1 : is a flow chart of a method for preparing a MIM capacitor structure according to an embodiment of the present invention, wherein the method for preparing a MIM capacitor structure comprises: First, perform step S1: refer to Figure 2 , Figure 2 1 is a schematic diagram of a semiconductor structure after trenches are formed according to an embodiment of the present application. A semiconductor structure 10 is provided, and a top layer of the semiconductor structure 10 is a first metal layer 21 .

[0023] In this embodiment, the first metal layer 21 is made of copper.

[0024] Then, execute step S2: continue to refer to Figure 2 , forming a first insulating layer 31 , wherein the first insulating layer 31 covers the first metal layer 21 .

[0025] In this embodiment, the first insulating layer 31 is made of silicon dioxide.

[0026] Next, execute step S3: continue to refer to Figure 2 , etching the first insulating layer 31 to the surface of the first metal layer 21 to form a groove 40.

[0027] Further, step S4 is performed: refer to Figure 3 , Figure 3 It is a schematic diagram of the semiconductor structure after the second metal layer is formed in an embodiment of the present application, wherein the second metal layer 22 is formed, and the second metal layer 22 covers the sidewalls and bottom wall of the trench 40 and the first insulating layer 31 .

[0028] In this embodiment, the second metal layer 22 is made of copper.

[0029] Next, execute step S5: refer to Figure 4 , Figure 4 It is a schematic diagram of the semiconductor structure after the fourth insulating layer is formed in an embodiment of the present application, wherein a second insulating layer 32 is formed, and the second insulating layer 32 covers the second metal layer 22 .

[0030] In this embodiment, the second insulating layer 32 is made of silicon nitride.

[0031] Preferably, the second insulating layer 32 has a thickness of 300 angstroms to 700 angstroms.

[0032] Further, execute step S6: continue to refer to Figure 4 , forming a third metal layer 23 , wherein the third metal layer 23 covers the second insulating layer 32 .

[0033] In this embodiment, the third metal layer 23 is made of titanium nitride.

[0034] Next, execute step S7: continue to refer to Figure 4 , forming a third insulating layer 33 , wherein the third insulating layer 33 covers the third metal layer 23 .

[0035] In this embodiment, the third insulating layer 33 is made of silicon nitride.

[0036] Preferably, the thickness of the third insulating layer 33 is 300 angstroms to 700 angstroms.

[0037] Further, execute step S8: continue to refer to Figure 4 , forming an Nth metal layer, wherein the Nth metal layer covers the third insulating layer, wherein N is an integer greater than or equal to 4.

[0038] In this embodiment, taking N as 4 as an example, a fourth metal layer 24 is formed, and the fourth metal layer 24 covers the third insulating layer 33 .

[0039] In this embodiment, the fourth metal layer 24 is made of titanium nitride.

[0040] Next, execute step S9: continue to refer to Figure 4, forming a fourth insulating layer 34 , wherein the fourth insulating layer 34 covers the fourth metal layer 24 .

[0041] In this embodiment, the fourth insulating layer 34 is made of silicon nitride.

[0042] Preferably, the fourth insulating layer 34 has a thickness of 300 angstroms to 700 angstroms.

[0043] Further, step S10 is performed: refer to Figure 5 , Figure 5 It is a schematic diagram of the semiconductor structure after the fifth metal layer is formed according to an embodiment of the present application, wherein the fifth metal layer 25 is formed, and the fifth metal layer 25 covers the fourth insulating layer 34 and fills the remaining space of the trench 40 .

[0044] In this embodiment, the fifth metal layer 25 is made of titanium nitride.

[0045] Next, execute step S11: refer to Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the second metal layer to the fifth metal layer and the second insulating layer to the fourth insulating layer are polished and removed beyond the surface of the first insulating layer in an embodiment of the present application, and the second metal layer 22 to the fifth metal layer 25 and the second insulating layer 32 to the fourth insulating layer 34 are polished and removed beyond the surface of the first insulating layer 31.

[0046] Preferably, a chemical mechanical polishing process is used to polish and remove the second metal layer 22 to the fifth metal layer 25 and the second insulating layer 32 to the fourth insulating layer 34 that extend beyond the surface of the first insulating layer 31 .

[0047] Further, step S12 is performed: refer to Figure 7 , Figure 7 It is a schematic diagram of the semiconductor structure after forming a top dielectric layer according to an embodiment of the present application, wherein a top dielectric layer 50 is formed, and the top dielectric layer 50 covers the second metal layer 22 to the fifth metal layer 25 , and the second insulating layer 32 to the fourth insulating layer 34 .

[0048] Preferably, the top dielectric layer 50 comprises: a stacked SiON layer and an undoped silicon glass layer (USG film layer), the SiON layer covers the second metal layer to the N+1th metal layer, and the first insulating layer to the Nth insulating layer, and the undoped silicon glass layer covers the SiON layer.

[0049] Next, execute step S13: refer to Figure 8 , Figure 8It is a schematic diagram of the semiconductor structure after the first conductive plug, the second conductive plug to the fourth conductive plug are formed according to an embodiment of the present application, forming a first conductive plug 61, a second conductive plug 62, a third conductive plug 63 and a fourth conductive plug 64, the first conductive plug 61 penetrates the top dielectric layer 50 and the first insulating layer 31 and is connected to the first metal layer 21, the second conductive plug 62 penetrates the top dielectric layer 50 and is connected to the third metal layer 23, the third conductive plug 63 penetrates the top dielectric layer 50 and is connected to the fourth metal layer 24, and the fourth conductive plug 64 penetrates the top dielectric layer 50 and is connected to the fifth metal layer 25.

[0050] Finally, execute step S14: refer to Fig. 9 , Fig. 9 It is a schematic diagram of the semiconductor structure after a patterned metal layer is formed in an embodiment of the present application, forming a patterned metal layer 70, wherein the patterned metal layer 70 covers the first conductive plug 61, the second conductive plug 62, the third conductive plug 63 and the fourth conductive plug 64, respectively, and the first conductive plug 61, the second conductive plug 62, the third conductive plug 63 and the fourth conductive plug 64 are not connected to each other after the patterned metal layer 70 is respectively connected.

[0051] This embodiment takes N=4 as an example, so the first metal layer 21 / the second metal layer 22, the second insulating layer 32 and the third metal layer 23 constitute a MIM capacitor; the fourth metal layer 24, the fourth insulating layer 34 and the fifth metal layer 25 constitute a MIM capacitor.

[0052] The two MIM capacitors are connected in parallel through the patterned metal layer 70 , thereby forming a two-way parallel MIM capacitor structure.

[0053] In other embodiments, when N is 6, three MIM capacitors can be obtained, namely: the first metal layer 21 / the second metal layer 22, the second insulating layer 32 and the third metal layer 23 constitute a MIM capacitor; the fourth metal layer 24, the fourth insulating layer 34 and the fifth metal layer 25 constitute a MIM capacitor; the sixth metal layer, the sixth insulating layer and the seventh metal layer constitute a MIM capacitor. Through the patterned metal layer 70, the above three MIM capacitors can be connected in parallel to form a three-way parallel trench-type MIM capacitor structure. In summary, in the MIM capacitor structure provided in the present application, N is greater than or equal to 4 and is a multiple of 2, and a patterned metal layer 70 and the first to Nth conductive plugs are used to form an N / 2-way parallel trench-type MIM capacitor structure.

[0054] In the present application, the actual value of N is selected according to the actual capacitance density requirements, so as to design the lateral opening size of the groove 40 so as to deposit a second metal layer, a second insulating layer, a third metal layer, a third insulating layer, ..., an Nth metal layer, an Nth insulating layer and an N+1th metal layer in the groove 40.

[0055] In this embodiment, the material of the patterned metal layer 70 is aluminum.

[0056] In the present application, a groove is first formed in the first insulating layer, and then a second metal layer, a second insulating layer, a third metal layer, a third insulating layer, an Nth metal layer, an Nth insulating layer and an N+1th metal layer are stacked in the groove, wherein N is an integer greater than or equal to 4, and then a top dielectric layer is deposited on the N+1th metal layer at the top of the groove, and then the first to Nth conductive plugs are formed, and finally, the parallel connection of multiple MIM capacitors at the bottom of the groove and in the groove is realized through the patterned metal layer of the top layer, thereby forming a trench-type MIM capacitor structure with at least two parallel paths. Compared with traditional flat-plate capacitors, the MIM capacitor structure prepared in the present application is not only a trench-type capacitor structure, but also a parallel capacitor structure, which can effectively improve the capacitance density per unit area.

[0057] Based on the same inventive concept, the present application embodiment also provides a MIM capacitor structure, referring to Fig. 9 , the MIM capacitor structure comprises: A semiconductor structure 10, wherein the top layer of the semiconductor structure 10 is a first metal layer 21; A first insulating layer 31, wherein the first insulating layer 31 covers the first metal layer 21; a groove 40, wherein the groove 40 is located in the first insulating layer 31 and exposes the first metal layer 21 at the bottom; A second metal layer 22, wherein the second metal layer 22 covers the sidewalls and the bottom wall of the groove 40; A second insulating layer 32, wherein the second insulating layer 32 covers the second metal layer 22; A third metal layer 23, wherein the third metal layer 23 covers the second insulating layer 32; A third insulating layer 33, wherein the third insulating layer 33 covers the third metal layer 23; a fourth metal layer 24, wherein the fourth metal layer 24 covers the third insulating layer 33; a fourth insulating layer 34 , wherein the fourth insulating layer 34 covers the fourth metal layer 24 ; a fifth metal layer 25 , wherein the fifth metal layer 25 covers the fourth insulating layer 34 and fills a remaining space of the trench 40 ; A top dielectric layer 50, wherein the top dielectric layer 50 covers the second metal layer 22 to the fifth metal layer 25, and the first insulating layer 31 to the fourth insulating layer 34; A first conductive plug 61, a second conductive plug 62 to a fourth conductive plug 64, wherein the first conductive plug 61 penetrates the top dielectric layer 50 and the first insulating layer 31 and is connected to the first metal layer 21, the second conductive plug 62 penetrates the top dielectric layer 50 and is connected to the third metal layer 23, the third conductive plug 63 penetrates the top dielectric layer 50 and is connected to the fourth metal layer 24, and the fourth conductive plug 64 penetrates the top dielectric layer 50 and is connected to the fifth metal layer 25; The patterned metal layer 70 covers the first conductive plug 61 , the second conductive plug 62 to the fourth conductive plug 64 respectively to form a two-way parallel MIM capacitor structure.

[0058] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing a MIM capacitor structure, characterized in that: include: Providing a semiconductor structure, wherein the top layer of the semiconductor structure is a first metal layer; forming a first insulating layer, wherein the first insulating layer covers the first metal layer; Etching the first insulating layer to a surface of the first metal layer to form a groove; forming a second metal layer, wherein the second metal layer covers the sidewalls and bottom wall of the trench and the first insulating layer; forming a second insulating layer, wherein the second insulating layer covers the second metal layer; forming a third metal layer, wherein the third metal layer covers the second insulating layer; forming a third insulating layer, wherein the third insulating layer covers the third metal layer; forming an Nth metal layer, wherein the Nth metal layer covers the third insulating layer, wherein N is an integer greater than or equal to 4; forming an Nth insulating layer, wherein the Nth insulating layer covers the Nth metal layer; forming an N+1th metal layer, wherein the N+1th metal layer covers the Nth insulating layer and fills a remaining space of the trench; Grinding and removing the second metal layer to the N+1th metal layer and the second insulating layer to the Nth insulating layer beyond the surface of the first insulating layer; Forming a top dielectric layer, wherein the top dielectric layer covers the second metal layer to the N+1th metal layer, and the first insulating layer to the Nth insulating layer; forming a first conductive plug, a second conductive plug to an Nth conductive plug, wherein the first conductive plug penetrates the top dielectric layer and the first insulating layer and is connected to the first metal layer, the second conductive plug penetrates the top dielectric layer and is connected to the third metal layer, and the Nth conductive plug penetrates the top dielectric layer and is connected to the N+1th metal layer; A patterned metal layer is formed, wherein the patterned metal layer covers the first conductive plug, the second conductive plug to the Nth conductive plug respectively, so as to form at least two parallel MIM capacitor structures.

2. The method for preparing the MIM capacitor structure according to claim 1, characterized in that: The material of the first metal layer and the material of the second metal layer are both copper.

3. The method for preparing the MIM capacitor structure according to claim 1, characterized in that: The material of the third metal layer, the material of the Nth metal layer and the material of the N+1th metal layer are all titanium nitride.

4. The method for preparing the MIM capacitor structure according to claim 1, characterized in that: The material of the patterned metal layer is aluminum.

5. The method for preparing the MIM capacitor structure according to claim 1, characterized in that: The material of the first insulating layer is silicon dioxide.

6. The method for preparing the MIM capacitor structure according to claim 1, characterized in that: The material of the second insulating layer, the material of the third insulating layer and the material of the Nth insulating layer are all silicon nitride.

7. The method for preparing the MIM capacitor structure according to claim 1, characterized in that: The thickness of the second insulating layer is 300 angstroms to 700 angstroms; the thickness of the third insulating layer is 300 angstroms to 700 angstroms; and the thickness of the Nth insulating layer is 300 angstroms to 700 angstroms.

8. The method for preparing the MIM capacitor structure according to claim 1, characterized in that: The top dielectric layer includes: a stacked SiON layer and an undoped silicon glass layer, the SiON layer covers the second metal layer to the N+1th metal layer and the first insulating layer to the Nth insulating layer, and the undoped silicon glass layer covers the SiON layer.

9. The method for preparing a MIM capacitor structure according to claim 1, characterized in that: A chemical mechanical polishing process is used to polish and remove the second metal layer to the N+1th metal layer and the second insulating layer to the Nth insulating layer that exceed the surface of the first insulating layer.

10. A MIM capacitor structure, characterized in that: include: A semiconductor structure, wherein the top layer of the semiconductor structure is a first metal layer; a first insulating layer, wherein the first insulating layer covers the first metal layer; a groove, wherein the groove is located in the first insulating layer and exposes the first metal layer at the bottom; a second metal layer, wherein the second metal layer covers the sidewalls and the bottom wall of the trench; a second insulating layer, wherein the second insulating layer covers the second metal layer; a third metal layer, the third metal layer covering the second insulating layer; a third insulating layer, wherein the third insulating layer covers the third metal layer; An Nth metal layer, the Nth metal layer covering the third insulating layer, wherein N is an integer greater than or equal to 4; an Nth insulating layer, the Nth insulating layer covering the Nth metal layer; an N+1th metal layer, the N+1th metal layer covering the Nth insulating layer and filling a remaining space of the trench; A top dielectric layer, the top dielectric layer covering the second metal layer to the N+1th metal layer, and the first insulating layer to the Nth insulating layer; a first conductive plug, a second conductive plug to an Nth conductive plug, wherein the first conductive plug penetrates the top dielectric layer and the first insulating layer and is connected to the first metal layer, the second conductive plug penetrates the top dielectric layer and is connected to the third metal layer, and the Nth conductive plug penetrates the top dielectric layer and is connected to the N+1th metal layer; A patterned metal layer, wherein the patterned metal layer covers the first conductive plug, the second conductive plug to the Nth conductive plug respectively, so as to form at least two parallel MIM capacitor structures.

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