FRED semiconductor device and preparation method thereof

Abstract

The invention discloses an FRED semiconductor device and a preparation method, and relates to the technical field of semiconductors. After Pt ions are sputtered, metal evaporation is carried out, a plurality of crucibles including a 1 # Ti crucible, a 2 # Ni crucible and a 4 # Al crucible are adopted in the metal evaporation process, evaporation of 2KA Ti at the position of the 1 # crucible, evaporation of 25KA Al at the position of the 4 # crucible, evaporation of 1.15 KA Ti at the position of the 1 # crucible and evaporation of 8KA Ni at the position of the 2 # crucible are sequentially carried out, and a TiAlTiNi metal structure is obtained; a metal layer in the prior art is changed from an Ag surface to an Ni surface, so that the phenomena of PI glue falling and layering after Ni / Ag high-temperature curing can be effectively solved, the appearance yield is improved, the failure cost is reduced, and the glue falling probability is reduced from 60% to 0; meanwhile, the price of the metal Ag is higher than that of the metal Ni, so that the purpose of reducing the production cost can be achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a FRED semiconductor device and a preparation method thereof. Background Art

[0002] In the production process of FRED products, according to production requirements, the back-end metal layer lithography only has one metal layer of TiNiAg or TiNiAl. In order to improve product performance and give it better product advantages, PI lithography process is added on the surface of the metal layer to act as a passivation layer to improve the product's voltage resistance. The PI glue used in the PI lithography process has inherent defects due to its own composition, as follows: At present, there are two kinds of metal surfaces for FRED products in the industry, namely Al surface and Ag surface. PI glue has good adhesion to Al surface, and usually PI glue will not fall off. However, it has very poor adhesion to Ag surface, and PI glue is prone to fall off, resulting in unqualified appearance yield, scrap treatment, and increased failure cost.

[0003] When the photoresist falls off, the normal measure is to increase the adhesion of HMDS enhancement glue to the wafer surface. However, for PI photoresist, HMDS will destroy the bonding between PI and Si, resulting in electrical properties and packaging reliability not meeting the expected results.

[0004] After the PI glue operation is completed, high-temperature curing and baking are required at a temperature of 350°C. The expansion coefficients of metal Ag and Ni are different. After high temperature, under the action of oxygen, Ag and Ni surface stratification will occur, which will cause the material to break and become unusable. When the Ag surface is not suitable for the PI process and the Al surface cannot meet market demand, how to effectively solve the problem of PI glue falling off and Ni / Ag stratification after high-temperature curing, and improve the appearance yield is a technical problem that needs to be solved urgently in this case. Summary of the invention

[0005] In view of the above problems, the present invention provides a FRED semiconductor device and a preparation method which effectively solves the phenomenon of PI debonding and Ni / Ag delamination after high temperature curing.

[0006] A method for preparing a FRED semiconductor device comprises the following steps: Step 1, growing an oxide layer on the surface of the epitaxial layer, and injecting a drive-in into the oxide layer to obtain an N junction; Step 2, preparing a P-type voltage divider ring on the oxide layer; Step 3, injecting B element between a pair of P-type voltage divider rings in the middle of the top surface of the oxide layer, and obtaining the first P junction after the injection is advanced; Step 4: TEOS, PSG and USG deposition processes are sequentially performed on the oxide layer; and a third photolithography is performed to implant B element to form a second P junction; The fifth step is to sputter Pt ions to obtain the N-region, improve the surface conductivity and reduce the resistance; then perform metal evaporation. The metal evaporation process includes: There are three crucible positions on the machine end, namely 1# Ti crucible, 2# Ni crucible and 4# Al crucible; The machine sequentially evaporates Ti at the 1# crucible position, Al at the 4# crucible position, Ti at the 1# crucible position, and Ni at the 2# crucible position to obtain a TiAlTiNi metal structure; The sixth step is to perform metal layer photolithography and alloying using an alloying machine to enhance the metal's anti-oxidation properties; The seventh step is to perform PI layer photolithography to obtain a passivation layer.

[0007] Specifically, in the seventh step of the PI layer photolithography process, the thickness of the photoresist is ≥3um after high-temperature curing.

[0008] Specifically, in the fifth step, 2KA of Ti is evaporated from crucible #1 for the first time, and 1.15KA of Ti is evaporated for the second time.

[0009] Specifically, in the fifth step, 25KA of Al is evaporated at the 4# crucible position.

[0010] Specifically, in the fifth step, 8KA of Ni is evaporated at the 2# crucible position.

[0011] A FRED semiconductor device comprises an epitaxial layer and an oxide layer connected sequentially from bottom to top; The oxide layer is provided with: An N junction extending downward from a top surface of the oxide layer; A Pt region extending downward from the top surface of the oxide layer; The first P junction is provided with a plurality of P junctions, each extending downward from the oxide layer and the top surface of the Pt region; A second P junction extends downward from the top surface of the Pt region, and its two sides are respectively connected to the first P junction in the middle; The silicon dioxide layer is provided with a plurality of layers which are spaced apart on the top surface of the oxide layer; A PSG region, wrapped on the plurality of silicon dioxide layers, with a bottom surface connected to the first P junction and the second P junction respectively; There are several TiAlTiNi metal layers, which are respectively arranged at the sides of the PSG area; the bottom surfaces of the TiAlTiNi metal layers at the sides are respectively connected to the N junctions, and the bottom surfaces of the TiAlTiNi metal layers in the middle are respectively connected to the second P junctions.

[0012] Specifically, a distance is provided between the N junction and the bottom surface of the oxide layer.

[0013] Specifically, the PI layer is disposed on the top surface of the PSG region and is connected to the TiAlTiNi metal layer.

[0014] After sputtering Pt ions, the present invention performs metal evaporation, and the metal evaporation process includes multiple crucibles, namely, a 1# Ti crucible, a 2# Ni crucible and a 4# Al crucible, wherein 2KA of Ti is evaporated at the 1# crucible, 25KA of Al is evaporated at the 4# crucible, 1.15KA of Ti is evaporated at the 1# crucible, and finally 8KA of Ni is evaporated at the 2# crucible to obtain a TiAlTiNi metal structure; the metal layer of the prior art is changed from an Ag surface to a Ni surface, which can effectively solve the problems of PI debonding and Ni / Ag delamination after high-temperature curing, improve the appearance yield, reduce the failure cost, and reduce the probability of debonding from 60% to 0; at the same time, since the price of metal Ag is higher than that of metal Ni, the purpose of reducing production costs can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of the structure of the oxide layer; Figure 2 It is a schematic diagram of preparing N junction structure; Figure 3 is a schematic diagram of preparing the first P junction structure; Figure 4 is a schematic diagram of preparing the second P junction structure; Figure 5 It is a schematic diagram of the structure of the PSG region; Figure 6 It is a schematic diagram of the structure of preparing TiAlTiNi metal layer; Figure 7 It is a schematic diagram of the structure of the prepared PI layer; In the figure, 100 is the epitaxial layer, 200 is the oxide layer, 300 is the N junction, 400 is the Pt region, 510 is the first P junction, 520 is the second P junction, 600 is the silicon dioxide layer, 700 is the PSG region, 800 is the TiAlTiNi metal layer, and 900 is the PI layer. DETAILED DESCRIPTION

[0016] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0017] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0018] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0019] Reference below Figure 1-7 describe the invention; A method for preparing a FRED semiconductor device comprises the following steps: Step 1, such as Figure 1 As shown, an oxide layer is grown on the surface of the epitaxial layer, and the active area pattern is obtained on the oxide layer by photolithography. After wet etching and degumming, P element is implanted, and an N junction is obtained after the implantation is advanced ( Figure 2 Medium + ); Step 2, such as Figure 3 As shown, secondary photolithography is performed to obtain a voltage divider ring pattern, and then wet etching is performed to remove the resist, and a plurality of P-type voltage divider rings ( Figure 3 The rectangular box with the meaning P); Step 3, injecting B element, and then advancing it to obtain a plurality of first P junctions set at intervals ( Figure 4 The orange grid line area in the middle); Step 4: Figure 5 As shown, TEOS (film thickness 2K, Figure 5 The orange area SiO2 in the figure), PSG (phosphorus-doped silicate glass, film thickness 3K) and USG (undoped silicate glass, film thickness 3K) deposition processes (obtained Figure 5 The blue area PSG in the figure); on this basis, the third photolithography is performed to obtain the hole layer pattern and dry etching is performed (the blue area in the figure); then the B element is injected with glue to form the second P junction ( Figure 4The middle section of the cross-hatched area) works together with the P region in step three to replace silicon atoms to form positively charged holes, thereby forming current.

[0020] Step 5: Figure 6 As shown, after photolithography and stripping of the hole layer, Pt ions are sputtered, that is, Figure 6 The N (epi) region is obtained to obtain the N-region, thereby improving the surface conductivity, reducing resistance, and thus improving the working efficiency and stability of the device. Then metal evaporation is performed. The metal evaporation process includes: There are 4 crucible positions on the machine end, namely 1# Ti crucible, 2# Ni crucible, 3# Ag crucible and 4# Al crucible; The machine sequentially evaporates 2KA of Ti at the 1# crucible position, 25KA of Al at the 4# crucible position, 1.15KA of Ti at the 1# crucible position, and finally 8KA of Ni at the 2# crucible position to obtain a TiAlTiNi metal structure. Due to the different metal structures, the 3# crucible was not used, and the 3# crucible was prepared for the preparation of Ag-containing metal structures.

[0021] The sixth step is to perform metal layer photolithography. After metal corrosion, the metal in the photoresist protection area is retained, and organic debonding is performed. After debonding, alloying is performed using an alloying machine. The alloying step plays a role in surface treatment and enhances the metal's anti-oxidation properties. The seventh step is to perform PI layer photolithography, coat PI glue on the surface of the material, and perform PI layer photolithography to obtain a passivation layer.

[0022] The thickness of the PI layer photoresist must meet the requirement of ≥3um after high-temperature curing to reflect the role of PI photoresist as a passivation layer. The main functions of PI photoresist as a passivation layer include protecting the chip surface, preventing corrosion and oxidation, improving the reliability and stability of the chip, and extending the service life of the chip. PI photoresist has excellent thermal stability, mechanical properties, chemical resistance and electrical insulation properties, which enable it to play an important role in the chip manufacturing process. PI photoresist is a high-performance engineering plastic with the following characteristics: Thermal stability: High temperature resistance up to 400℃ and above, long-term use temperature range is -200~300℃ Mechanical properties: High strength and rigidity, suitable for use in various harsh environments.

[0023] ‌Chemical Resistance‌: Excellent resistance to a wide range of chemicals.

[0024] ‌Electrical insulation performance‌: At 103 Hz, the dielectric constant is 4.0 and the dielectric loss is only 0.004-0.007‌ ( Figure 7 middle PI region).

[0025] The FRED semiconductor device comprises an epitaxial layer 100 and an oxide layer 200 connected sequentially from bottom to top; The oxide layer 200 is provided with: An N junction 300 extends downward from the top surface of the oxide layer 200 and is spaced apart from the bottom surface of the oxide layer 200; A Pt region 400 extends downward from the top surface of the oxide layer 200 and overlaps with the bottom surface of the oxide layer 200; The first P junction 510 is provided with a plurality of junctions, each extending downward from the top surface of the oxide layer 200 and the Pt region 400, and each having a spacing with the top surface of the oxide layer 200 and the Pt region 400; The second P junction 520 extends downward from the top surface of the Pt region 400, and the two sides are respectively connected to the first P junction 510 in the middle; A silicon dioxide layer 600 is provided, with a plurality of layers, which are spaced apart and arranged on the top surface of the oxide layer 200; A PSG region 700, wrapped on the plurality of silicon dioxide layers 600, with the bottom surface connected to the first P junction 510 and the second P junction 520 respectively; In semiconductor manufacturing, first forming a stable silicon dioxide layer can ensure basic planarization and insulation performance. Subsequently, by adding phosphorus to form PSG, the interlayer insulation and hole filling effects can be further optimized, thereby improving the performance and reliability of the chip.

[0026] There are several TiAlTiNi metal layers 800, which are respectively arranged on the sides of the PSG area 800; the bottom surfaces of the side TiAlTiNi metal layers 700 are respectively connected to the N junctions 300, and the bottom surfaces of the middle TiAlTiNi metal layers 800 are respectively connected to the second P junctions 520.

[0027] The PI layer 900 is disposed on the top surface of the PSG region 700 and connected to the TiAlTiNi metal layer 800 .

[0028] The TiAlTiNi metal layer in this case has the following functions: 1. Electrical and thermal conductivity: The metal layer is mainly used as electrodes, conductors, impedance matching and other components, which can improve the speed and reliability of the circuit and reduce power consumption.

[0029] 2. Protecting devices: The metal layer can act as a protective layer to prevent damage to the device caused by the environment or process conditions. For example, the metal layer can prevent the device from oxidation, corrosion, mechanical damage, etc.

[0030] According to the experimental results, changing the metal structure and changing the metal layer from Ag surface to Ni surface can effectively solve the problems of PI debonding and Ni / Ag delamination after high-temperature curing, improve the appearance yield, reduce the failure cost, and reduce the probability of debonding from 60% to 0; at the same time, since metal Ag is more expensive than metal Ni, the purpose of reducing production costs can be achieved.

[0031] Regarding the contents disclosed in this case, there are a few points that need to be explained: (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design; (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments; The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for preparing a FRED semiconductor device, characterized in that: The following steps are involved: Step 1, growing an oxide layer on the surface of the epitaxial layer, and injecting a drive-in into the oxide layer to obtain an N junction; Step 2, preparing a P-type voltage divider ring on the oxide layer; Step 3, injecting B element between a pair of P-type voltage divider rings in the middle of the top surface of the oxide layer, and obtaining the first P junction after the injection is advanced; Step 4: TEOS, PSG and USG deposition processes are sequentially performed on the oxide layer; and a third photolithography is performed to implant B element to form a second P junction; The fifth step is to sputter Pt ions to obtain the N-region, improve the surface conductivity and reduce the resistance; Then metal evaporation is carried out. The metal evaporation process includes: There are three crucible positions on the machine end, namely 1# Ti crucible, 2# Ni crucible and 4# Al crucible; The machine sequentially evaporates Ti at the 1# crucible position, Al at the 4# crucible position, Ti at the 1# crucible position, and Ni at the 2# crucible position to obtain a TiAlTiNi metal structure; The sixth step is to perform metal layer photolithography and alloying using an alloying machine to enhance the metal's anti-oxidation properties; The seventh step is to perform PI layer photolithography to obtain a passivation layer.

2. The method for preparing a FRED semiconductor device according to claim 1, characterized in that: In the seventh step, in the PI layer photolithography process, the thickness of the photoresist is ≥3um after high-temperature curing.

3. The method for preparing a FRED semiconductor device according to claim 1, characterized in that: In the fifth step, 2KA of Ti was evaporated from crucible #1 for the first time, and 1.15KA of Ti was evaporated for the second time.

4. The method for preparing a FRED semiconductor device according to claim 1, characterized in that: In the fifth step, 25KA of Al is evaporated at the 4# crucible position.

5. The method for preparing a FRED semiconductor device according to claim 1, characterized in that: In the fifth step, 8KA of Ni is evaporated at the 2# crucible position.

6. A FRED semiconductor device, prepared by the method for preparing a FRED semiconductor device according to claim 1, characterized in that: It comprises an epitaxial layer (100) and an oxide layer (200) which are connected sequentially from bottom to top; The oxide layer (200) is provided with: An N junction (300) extending downward from the top surface of the oxide layer (200); A Pt region (400) extending downward from the top surface of the oxide layer (200); A first P junction (510) is provided, and extends downward from the top surface of the oxide layer (200) and the Pt region (400) respectively; A second P junction (520) extends downward from the top surface of the Pt region (400), with two sides respectively connected to the first P junction (510) in the middle; The silicon dioxide layer (600) is provided with a plurality of silicon dioxide layers, which are arranged at intervals on the top surface of the oxide layer (200); A PSG region (700) is wrapped on the plurality of silicon dioxide layers (600), and the bottom surface is respectively connected to the first P junction (510) and the second P junction (520); The TiAlTiNi metal layer (800) is provided with a plurality of layers, which are respectively arranged on the side of the PSG region (800); the bottom surfaces of the TiAlTiNi metal layers (700) on the side are respectively connected to the N junction (300), and the bottom surfaces of the TiAlTiNi metal layers (800) in the middle are respectively connected to the second P junction (520).

7. A FRED semiconductor device according to claim 6, characterized in that: A distance is provided between the N junction (300) and the bottom surface of the oxide layer (200).

8. A FRED semiconductor device according to claim 6, characterized in that: The PI layer (900) is disposed on the top surface of the PSG region (700) and is connected to the TiAlTiNi metal layer (800).

Images