Ultra-large current gain high-voltage NPN tube and preparation method thereof

Abstract

The invention belongs to the technical field of NPN tube preparation, and relates to an ultra-large current gain high-voltage NPN tube and a preparation method thereof. According to the invention, boron impurity high-energy ions are injected into an N-epitaxial layer to form a P-type injection region; injecting phosphorus or arsenic impurity high-energy ions into the N-epitaxial layer, and forming an N-injection region in the P-type injection region; performing oxidation diffusion on the N-epitaxial layer to enable the P-type injection region to form a P-type base region and enable the N-injection region to form an N-emitter region; sequentially carrying out phosphorus impurity pre-doping and oxidation diffusion on the N-emitter region and the N-epitaxial layer to form two N + emitter regions; a base region metal electrode, an emitter region metal electrode and a collector region metal electrode are respectively deposited on the surface of the N-epitaxial layer, the base region metal electrode is connected with the P-type base region, the emitter region metal electrode is connected with an N + emitter region in the N-emitter region, and the collector region metal electrode is connected with an N + emitter region in the N-epitaxial layer. According to the invention, on the basis of improving the current gain, the NPN tube can be ensured to obtain relatively high withstand voltage.

Description

Technical Field

[0001] The invention belongs to the technical field of NPN tube preparation, and relates to an ultra-large current gain high-voltage NPN tube and a preparation method thereof. Background Art

[0002] When amplifying signals in a circuit, ultra-large current gain transistors can significantly increase the amplitude of the signal, thereby achieving effective signal amplification. This amplification effect is widely used in communications, audio amplification, and instrumentation. In communication systems, they can enhance signal strength and ensure long-distance and stable transmission of information; in the field of audio amplification, they can improve the clarity and loudness of the sound, bringing users a better auditory experience; and in instrumentation, they ensure the accuracy and sensitivity of the measurement results.

[0003] For NPN transistors, the current gain is affected by many factors, including the doping concentration of the emitter region, the doping concentration of the base region, and the width of the base region. These factors are closely related to the manufacturing process of analog circuits and directly determine the performance of the transistor. During the preparation process, the doping concentration and base width need to be precisely controlled to ensure that the transistor has an ideal current gain and stability.

[0004] However, in the field of analog integrated circuits, especially those circuits that need to withstand high voltages, the preparation process of NPN tubes faces some challenges. Due to the limitations of furnace tube control accuracy and process volatility, as well as the mutual constraints between the current gain and withstand voltage performance of NPN tubes, it is difficult to achieve a higher current gain while ensuring that the withstand voltage meets the circuit requirements. At present, in order to meet the high withstand voltage requirements of more than 40V, the current gain of general NPN tubes is usually only a few dozen to one or two hundred, which is difficult to meet the miniaturization of electronic equipment, and to a certain extent limits the miniaturization and low power consumption of electronic equipment.

[0005] In summary, the current gain is insufficient for analog integrated circuits that require high voltage use. Summary of the invention

[0006] The purpose of the present invention is to provide a super-large current gain high-voltage NPN tube and a preparation method thereof to solve the technical problem of insufficient current gain in analog integrated circuits requiring high voltage use. The present invention greatly improves the current gain of the NPN tube on the basis of ensuring the high withstand voltage of the NPN tube.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions: In a first aspect, the present invention provides a method for preparing a super-large current gain high-voltage NPN tube, comprising the following steps: High-energy boron impurity ions are injected into the N-epitaxial layer to form a P-type injection region; Implanting phosphorus or arsenic impurity high energy ions into the N-epitaxial layer to form an N-implantation region in the P-type implantation region; Oxidation diffusion is performed on the N-epitaxial layer to form a P-type base region in the P-type injection region and an N-injection region into an N-emitter region; Pre-doping and oxidizing and diffusing phosphorus impurities are performed on the N-emitter region and the N-epitaxial layer respectively to form two N+emitter regions; A base metal electrode, an emitter metal electrode and a collector metal electrode are deposited on the surface of the N-epitaxial layer respectively. The base metal electrode is connected to the P-type base region, the emitter metal electrode is connected to the N+ emitter region inside the N-emitter region, and the collector metal electrode is connected to the N+ emitter region inside the N-epitaxial layer.

[0008] Furthermore, the step of injecting high-energy boron impurity ions into the N-epitaxial layer to form a P-type implantation region is as follows: Thermally growing a first silicon dioxide layer on the N-epitaxial layer, wherein the thickness of the first silicon dioxide layer is less than or equal to 200 nm; Coating a photoresist on the surface of the first silicon dioxide layer to form a first photoresist layer, and photolithographically forming a P-type base region injection window on the first photoresist layer; Boron impurity high-energy ions are injected into the N-epitaxial layer through the P-type base region injection window to form a P-type injection region on the N-epitaxial layer.

[0009] Furthermore, the step of injecting phosphorus or arsenic impurity high energy ions into the N-epitaxial layer to form an N-implantation region in the P-type implantation region is as follows: Removing the first photoresist layer on the surface of the first silicon dioxide layer and re-coating the photoresist to form a second photoresist layer, and photolithographically forming an N-emitter region injection window on the second photoresist layer; Phosphorus or arsenic impurity high energy ions are implanted into the N-epitaxial layer through the first silicon dioxide layer using the N-emitter region implantation window to form an N-implantation region in the P-type implantation region.

[0010] Furthermore, the N-epitaxial layer is injected with phosphorus or arsenic impurity high-energy ions, with an injection energy of 240keV and an injection dose of 2E14cm -2 ~4E14cm -2 .

[0011] Furthermore, the N-epitaxial layer is oxidized and diffused to form a P-type base region in the P-type injection region and an N-emitter region in the N-injection region, as follows: The N-epitaxial layer including the P-type injection region and the N-injection region is subjected to oxidation diffusion at 1150°C for 40 minutes. After the oxidation diffusion is completed, it is subjected to nitrogen push-bonding at 1150°C for 60 minutes, and a second silicon dioxide layer is grown on the surface of the N-epitaxial layer. The thickness of the second silicon dioxide layer is 550nm~650nm, so that the P-type injection region forms a P-type base region, and the N-injection region forms an N-emitter region.

[0012] Furthermore, phosphorus impurity pre-doping and oxidation diffusion are sequentially performed on the N-emitter region and the N-epitaxial layer to form two N+ emitter regions, as follows: coating a photoresist on the surface of the second silicon dioxide layer to form a third photoresist layer; The third photoresist layer is etched by photolithography and the second silicon dioxide layer is etched by wet method to form two N+ emitter region doping windows, wherein a port of one N+ emitter region doping window contacts the surface of the N- emitter region, and a port of the other N+ emitter region doping window contacts the surface of the N- epitaxial layer; Phosphorus impurity pre-doping and phosphorus impurity re-diffusion are performed in the N- emitter region and the N-epitaxial layer in sequence through the N+ emitter region doping window to form two N+ emitter regions. The ambient temperature for the phosphorus impurity pre-doping is 930°C, and the ambient temperature for the phosphorus impurity re-diffusion is 950°C.

[0013] Further, the base metal electrode, emitter metal electrode and collector metal electrode are deposited on the surface of the N-epitaxial layer, the base metal electrode is connected to the P-type base region, the emitter metal electrode is connected to the N+ emitter region inside the N-emitter region, and the collector metal electrode is connected to the N+ emitter region in the N-epitaxial layer, as follows: Cleaning the surface of the N-epitaxial layer; A third silicon dioxide layer with a thickness of 19 nm to 21 nm is grown on the surface of the N-epitaxial layer, an insulating dielectric layer is deposited on the third silicon dioxide layer, and a photoresist is coated on the insulating dielectric layer to form a fourth photoresist layer, wherein the material of the insulating dielectric layer is USG, and the thickness of the insulating dielectric layer is 450 nm to 550 nm; Photolithography of a fourth photoresist layer, forming a contact hole window of the base region, a contact hole window of the emitter region, and a contact hole window of the collector region on the fourth photoresist layer; Wet-etch the insulating dielectric layer and the third silicon dioxide layer between the contact hole window of the base region, the contact hole window of the emitter region, the contact hole window of the collector region and the N-epitaxial layer to form the contact hole of the base region, the contact hole of the emitter region and the contact hole of the collector region, wherein the contact hole of the base region is connected to the P-type base region, the contact hole of the emitter region is connected to the N+ emitter region inside the N-emitter region, and the contact hole of the collector region is connected to the N+ emitter region inside the N-epitaxial layer; Depositing metal in the contact hole of the base region to form a base region metal electrode; Depositing metal in the contact hole of the emitter region to form a metal electrode of the emitter region; Metal is deposited in the contact hole of the collector region to form a metal electrode of the collector region.

[0014] Furthermore, a third silicon dioxide layer with a thickness of 19 nm to 21 nm is grown on the surface of the N-epitaxial layer, specifically as follows: A third silicon dioxide layer with a thickness of 19 nm to 21 nm is grown on the surface of the N-epitaxial layer in an environment of 850° C.

[0015] Furthermore, the resistivity of the N-epitaxial layer is 4.0 Ω.cm to 4.4 Ω.cm, and the thickness of the N-epitaxial layer is 11.5 μm to 13.5 μm.

[0016] In a second aspect, the present invention provides an ultra-large current gain high-voltage NPN transistor, comprising an N-epitaxial layer, a third silicon dioxide layer and an insulating dielectric layer are arranged on the N-epitaxial layer, the third silicon dioxide layer is located between the N-epitaxial layer and the insulating dielectric layer, and a base metal electrode, an emitter metal electrode and a collector metal electrode are embedded in the third silicon dioxide layer and the insulating dielectric layer; The N-epitaxial layer is provided with a P-type base region, an N-emitter region and two N+emitter regions, the N-emitter region is located inside the P-type base region, one N+emitter region is located in the N-epitaxial layer, and the other N+emitter region is located in the N-emitter region; The base metal electrode is connected to the P-type base region, the emitter metal electrode is connected to the N+ emitter region inside the N- emitter region, and the collector metal electrode is connected to the N+ emitter region in the N- epitaxial layer.

[0017] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention forms a P-type injection region by injecting boron impurity high-energy ions into an N-epitaxial layer; injecting phosphorus or arsenic impurity high-energy ions into the N-epitaxial layer to form an N-injection region in the P-type injection region, which is a key step in forming a high-voltage ultra-large current gain NPN tube; performing oxidation diffusion on the N-epitaxial layer to form a P-type base region in the P-type injection region and an N-emitter region in the N-injection region; performing phosphorus impurity pre-doping and oxidation diffusion on the N-emitter region and the N-epitaxial layer in sequence to form two N+ emitter regions; depositing a base region metal electrode, an emitter region metal electrode and a collector region metal electrode on the surface of the N-epitaxial layer, respectively, the base region metal electrode is connected to the P-type base region, the emitter region metal electrode is connected to the N+ emitter region inside the N-emitter region, and the collector region metal electrode is connected to the N+ emitter region in the N-epitaxial layer. The present invention solves the contradiction between emitter doping and injection efficiency by adding an N-region emitter injection when performing P-type base injection. The NPN tube prepared by the new process method can achieve a common emitter current gain of more than 1000 and a CE junction withstand voltage of 100V. On the basis of improving the current gain, the high withstand voltage of the NPN tube is also guaranteed.

[0018] 2. The third silicon dioxide layer grown at low temperature in the present invention avoids the redistribution of impurities in the P-type base region, N+ emitter region and N- emitter region caused by high-temperature thermal processes.

[0019] 3. The N-epitaxial layer of the present invention helps to withstand high voltage and is a key part of the device's withstand voltage performance. The third silicon dioxide layer is located between the N-epitaxial layer and the insulating dielectric layer, which plays an isolation and protection role, helps to prevent current leakage and breakdown, thereby improving the reliability and stability of the device. The insulating dielectric layer enhances the insulation performance of the device and ensures electrical isolation between different electrodes. The third silicon dioxide layer and the insulating dielectric layer are embedded with base metal electrodes, emitter metal electrodes and collector metal electrodes, providing the necessary current path and external connection points for the device. The N-epitaxial layer is provided with a P-type base region, an N-emitter region and two N+ emitter regions, the N-emitter region is located inside the P-type base region, one N+ emitter region is located in the N-epitaxial layer, and the other N+ emitter region is located in the N-emitter region; the base metal electrode is connected to the P-type base region, the emitter metal electrode is connected to the N+ emitter region inside the N-emitter region, and the collector metal electrode is connected to the N+ emitter region in the N-epitaxial layer. The P-type base region, the N- emitter region and the N+ emitter region together constitute the amplification region of the device. The N- emitter region is the main region for emitting electrons. The high doping concentration of the N+ emitter region helps to reduce contact resistance and improve current injection efficiency, thereby further enhancing the current gain performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The impurity doping distribution diagram of the base region and emitter region of the NPN tube prepared by the existing process and the present invention, wherein: Figure 1 a is the impurity doping distribution of the base region and emitter region of the NPN tube prepared by the existing process; Figure 1 b is the impurity doping distribution of the base region and emitter region of the NPN tube prepared by the present invention; Figure 2 The Ic-Vc curve diagram of the output characteristics of the NPN tube prepared by the present invention and the existing process, wherein: Figure 2 a is the Ic-Vc curve of the output characteristics of the NPN tube prepared by the existing process; Figure 2 b is the Ic-Vc curve diagram of the output characteristics of the NPN tube prepared by the present invention; Figure 3 This is a cross-sectional view of a high-energy ion implantation barrier oxide layer of ≤200nm grown on the surface of an N-type epitaxial layer of the present invention; Figure 4 The cross-sectional view of the present invention is to form the NPN tube base window by photolithography and complete the P-type boron impurity implantation; Figure 5 The cross-sectional view of the present invention is to form the N-emitter region window of the NPN tube by photolithography and complete the N-type phosphorus impurity implantation; Figure 6 It is a cross-sectional view of the P-type base region 6 and the N-type emitter region 7 of the NPN tube formed after oxidation diffusion of the present invention; Figure 7 The cross-sectional view of the doping window of the N+ emitter region is formed by photolithography and etching of the oxide layer in the present invention; Figure 8 This is a cross-sectional view of the N+ emitter region 8 of the NPN tube formed by phosphorus pre-deposition and oxidation diffusion in the N+ emitter region of the present invention; Fig. 9 This is a cross-sectional view of the present invention in which the front oxide layer is washed away and a silicon dioxide layer of ≤20nm is thermally grown on the surface of the N-type epitaxial layer; Fig.10 A schematic diagram of depositing an insulating dielectric layer of a certain thickness and photolithographically etching contact holes according to the present invention; Fig.11 A schematic diagram of the contact holes for etching the insulating dielectric layer and forming the emitter region, base region and collector region of the NPN tube according to the present invention; Fig.12 A schematic diagram of depositing metal and photolithography to form each electrode of the NPN tube according to the present invention; Fig.13 The figure is a flow chart of the method of the present invention.

[0021] Among them: 1. N-epitaxial layer; 2. first silicon dioxide layer; 3. first photoresist layer; 4. P-type injection region; 5. N-injection region; 6. P-type base region; 7. N-emitter region; 8. N+ emitter region; 9. insulating dielectric layer; 10. base region metal electrode; 11. emitter region metal electrode; 12. collector region metal electrode; 13. P-type base region injection window; 14. N-emitter region injection window; 15. N+ emitter region doping window; 16. base region contact hole window; 17. emitter region contact hole window; 18. collector region contact hole window; 19. base region contact hole; 20. emitter region contact hole; 21. collector region contact hole; 22. second silicon dioxide layer; 23. third silicon dioxide layer; 24. second photoresist layer; 25. third photoresist layer; 26. fourth photoresist layer. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "first", "second", etc. in the specification of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] The present invention is further described in detail below in conjunction with the accompanying drawings: See also Fig.13 The present invention discloses a method for preparing a super-large current gain high-voltage NPN tube, comprising the following steps: S1, high-energy boron impurity ions are injected into the N-epitaxial layer 1 to form a P-type injection region 4; S2, implanting phosphorus or arsenic impurity high energy ions into the N-epitaxial layer 1 to form an N-implantation region 5 in the P-type implantation region 4; S3, oxidizing and diffusing the N-epitaxial layer 1, so that the P-type implantation region 4 forms a P-type base region 6, and the N-implantation region 5 forms an N-emitter region 7; S4, respectively performing phosphorus impurity pre-doping and oxidation diffusion on the N-emitter region 7 and the N-epitaxial layer 1 to form two N+ emitter regions 8; S5. A base metal electrode 10, an emitter metal electrode 11 and a collector metal electrode 12 are deposited on the surface of the N-epitaxial layer 1 respectively. The base metal electrode 10 is connected to the P-type base region 6. The emitter metal electrode 11 is connected to the N+ emitter region 8 inside the N-emitter region 7. The collector metal electrode 12 is connected to the N+ emitter region 8 inside the N-epitaxial layer 1.

[0025] The present invention solves the contradiction between emitter doping and injection efficiency by adding an N-region emitter injection when performing P-type base injection. The NPN tube prepared by the new process method can achieve a common emitter current gain of more than 1000 and a CE junction withstand voltage of 100V. On the basis of improving the current gain, it is also ensured that the NPN tube can obtain a higher withstand voltage.

[0026] Embodiment 1: See also Fig.13 This embodiment discloses a method for preparing a super-large current gain high-voltage NPN tube, comprising the following steps: S1, boron impurity high energy ions are injected into the N-epitaxial layer 1 to form a P-type injection region 4, as follows: Thermally growing a first silicon dioxide layer 2 on the N-epitaxial layer 1, wherein the thickness of the first silicon dioxide layer 2 is less than or equal to 200 nm; A photoresist is coated on the surface of the first silicon dioxide layer 2 to form a first photoresist layer 3, and a P-type base region injection window 13 is formed on the first photoresist layer 3 by photolithography; Boron impurity high energy ions are implanted into the N-epitaxial layer 1 through the P-type base region implantation window 13 to form a P-type implantation region 4 on the N-epitaxial layer 1 .

[0027] Preferably, the resistivity of the N-epitaxial layer 1 is 4.0Ω.cm, and the thickness of the N-epitaxial layer 1 is 11.5μm.

[0028] S2, implanting phosphorus or arsenic impurity high energy ions into the N-epitaxial layer 1 to form an N-implantation region 5 in the P-type implantation region 4, as follows: The first photoresist layer 3 on the surface of the first silicon dioxide layer 2 is removed and re-coated with photoresist to form a second photoresist layer 24, and an N-emitter region injection window 14 is formed on the second photoresist layer 24 by photolithography; Phosphorus or arsenic impurity high energy ions are implanted into the N-epitaxial layer 1 through the first silicon dioxide layer 2 using the N-emitter region implantation window 14 , thereby forming an N-implantation region 5 in the P-type implantation region 4 .

[0029] Preferably, the phosphorus or arsenic impurity high energy ions are injected into the N-epitaxial layer 1, the injection energy is 240keV, and the injection dose is 2E14cm -2 .

[0030] S3, oxidizing and diffusing the N-epitaxial layer 1, so that the P-type implantation region 4 forms a P-type base region 6, and the N-implantation region 5 forms an N-emitter region 7, as follows: The N-epitaxial layer 1 including the P-type injection region 4 and the N-injection region 5 is subjected to oxidation diffusion at 1150°C for 40 minutes. After the oxidation diffusion, it is subjected to nitrogen push-on at 1150°C for 60 minutes, and a second silicon dioxide layer 22 is grown on the surface of the N-epitaxial layer 1. The thickness of the second silicon dioxide layer 22 is 550nm, so that the P-type injection region 4 forms a P-type base region 6, and the N-injection region 5 forms an N-emitter region 7.

[0031] S4, respectively, performing phosphorus impurity pre-doping and oxidation diffusion on the N-emitter region 7 and the N-epitaxial layer 1 to form two N+ emitter regions 8, as follows: Coating photoresist on the surface of the second silicon dioxide layer 22 to form a third photoresist layer 25; The third photoresist layer 25 is etched by photolithography and the second silicon dioxide layer 22 is etched by wet method to form two N+ emitter region doping windows 15, wherein the port of one N+ emitter region doping window 15 contacts the surface of the N- emitter region 7, and the port of the other N+ emitter region doping window 15 contacts the surface of the N- epitaxial layer 1. That is, the N+ emitter region doping window 15 is a through hole opened on the third photoresist layer 25 and the second silicon dioxide layer 22, wherein the port of one through hole contacts the surface of the N- emitter region 7, and the port of the other through hole contacts the surface of the N- epitaxial layer 1.

[0032] Phosphorus impurity pre-doping and phosphorus impurity re-diffusion are performed in the N- emitter region 7 and the N-epitaxial layer 1 in sequence through the N+ emitter region doping window 15 to form two N+ emitter regions 8. The ambient temperature for the phosphorus impurity pre-doping is 930°C, and the ambient temperature for the phosphorus impurity re-diffusion is 950°C.

[0033] S5, a base metal electrode 10, an emitter metal electrode 11 and a collector metal electrode 12 are deposited on the surface of the N-epitaxial layer 1, the base metal electrode 10 is connected to the P-type base region 6, the emitter metal electrode 11 is connected to the N+ emitter region 8 inside the N-emitter region 7, and the collector metal electrode 12 is connected to the N+ emitter region 8 in the N-epitaxial layer 1, as follows: Cleaning the surface of the N-epitaxial layer 1; A 19 nm thick third silicon dioxide layer 23 is grown on the surface of the N-epitaxial layer 1, an insulating dielectric layer 9 is deposited on the third silicon dioxide layer 23, and a photoresist is coated on the insulating dielectric layer 9 to form a fourth photoresist layer 26, wherein the insulating dielectric layer 9 is made of USG and has a thickness of 450 nm; Photolithography of a fourth photoresist layer 26, forming a contact hole window 16 of the base region, a contact hole window 17 of the emitter region, and a contact hole window 18 of the collector region on the fourth photoresist layer 26; Wet-etch the insulating dielectric layer 9 and the third silicon dioxide layer 23 between the contact hole window 16 of the base region, the contact hole window 17 of the emitter region, the contact hole window 18 of the collector region and the N-epitaxial layer 1 to form a contact hole 19 of the base region, a contact hole 20 of the emitter region and a contact hole 21 of the collector region, wherein the contact hole 19 of the base region is connected to the P-type base region 6, the contact hole 20 of the emitter region is connected to the N+ emitter region 8 inside the N-emitter region 7, and the contact hole 21 of the collector region is connected to the N+ emitter region 8 inside the N-epitaxial layer 1; Depositing metal in the contact hole 19 of the base region to form a base region metal electrode 10; Depositing metal in the contact hole 20 of the emitter region to form the emitter region metal electrode 11; Metal is deposited in the contact hole 21 of the collector region to form a collector region metal electrode 12.

[0034] Preferably, a 19 nm thick third silicon dioxide layer 23 is grown on the surface of the N-epitaxial layer 1, specifically as follows: A third silicon dioxide layer 23 with a thickness of 19 nm is grown on the surface of the N-epitaxial layer 1 in an environment of 850° C.

[0035] Embodiment 2: Based on the first embodiment, the difference between this embodiment and the first embodiment is that: The resistivity of the N-epitaxial layer 1 is 4.2Ω.cm, and the thickness of the N-epitaxial layer 1 is 12.5μm; Phosphorus or arsenic impurity high energy ions are injected into the N-epitaxial layer 1, with an injection dose of 3E14cm -2 ; The thickness of the second silicon dioxide layer 22 is 600 nm; The thickness of the third silicon dioxide layer 23 is 20 nm; The thickness of the insulating dielectric layer 9 is 500 nm.

[0036] Embodiment three: Based on the first embodiment, the difference between this embodiment and the first embodiment is that: The resistivity of the N-epitaxial layer 1 is 4.4Ω.cm, and the thickness of the N-epitaxial layer 1 is 13.5μm; Phosphorus or arsenic impurity high energy ions are injected into the N-epitaxial layer 1, with an injection dose of 4E14cm -2 ; The thickness of the second silicon dioxide layer 22 is 650 nm; The thickness of the third silicon dioxide layer 23 is 21 nm; The thickness of the insulating dielectric layer 9 is 550 nm.

[0037] Embodiment 4: This embodiment discloses a method for preparing a super-large current gain high-voltage NPN tube. In order to eliminate the high-temperature process of the furnace tube and the constraints of the NPN tube's withstand voltage requirements on the current gain, the present invention creatively proposes a process design and preparation method for a super-large current gain high-voltage NPN tube. The doping distribution of the NPN tube emitter region is changed by multiple doping diffusion processes in the emitter region, and the doping concentration of the emitter region close to the base region is reduced to form an N-emitter region. On the one hand, the injection efficiency of the emitter region is improved, so that the gain of the NPN tube can reach more than 1000. On the other hand, since the emitter junction is a PN-junction, the withstand voltage is also relatively high, which can reach 100V. At the same time, the new process is compatible with conventional analog circuit processes, does not add any thermal processes, and has no obvious effect on the performance of other devices in the original process.

[0038] In view of the factors that affect the gain and withstand voltage of the NPN tube, in the existing NPN tube preparation process, after the base region is injected, the N-type element injection doping process is added once or twice to form a low-doping concentration N-emitter region on the side of the emitter region close to the base region, thereby improving the current gain of the NPN tube.

[0039] The steps of this embodiment are as follows: Step 1, growing a first silicon dioxide layer 2 with a thickness not exceeding 200 nm on the surface of the N-epitaxial layer 1, as a shielding oxide layer for high energy ion implantation, such as Figure 3 As shown; Step 2, a photoresist is coated on the surface of the first silicon dioxide layer 2 to form a first photoresist layer 3, a P-type base region injection window 13 is formed on the first photoresist layer 3 by photolithography, and a boron impurity high-energy ion selective injection is performed to form a P-type injection region 4 in the N-epitaxial layer, as shown in FIG. Figure 4 As shown; Step 3, remove the first photoresist layer 3, re-coat the surface of the first silicon dioxide layer 2 with photoresist to form a second photoresist layer 24, photolithography the second photoresist layer 24 to form an N-emitter injection window 14, and selectively inject high-energy ions of phosphorus or arsenic impurities to form an N-injection region 5 in the N-epitaxial layer 1, as shown in FIG. Figure 5 As shown; Preferably, phosphorus or arsenic impurity high energy ions are selectively implanted into the N-epitaxial layer 1. The energy selected for the implantation region of the N-epitaxial layer 1 needs to be adjusted according to the junction depth of the P-type base region 6 to ensure that after impurity compensation, an N-emitter region 7 is formed on the side of the N+ emitter region close to the base region. Figure 1 shown.

[0040] Preferably, the phosphorus or arsenic impurity high energy ion selective implantation, the dose selected for the N-implantation region 5 and the implantation dose of the P-type base region 6 are in the same order of magnitude, and the implantation dose needs to be adjusted and determined multiple times according to the preparation results, such as Figure 1 shown.

[0041] Step 4, remove the second photoresist layer 24, oxidize and diffuse the N-epitaxial layer 1 including the P-type implantation region 4 and the N-implantation region 5 to form a P-type base region 6 and an N-emitter region 7, and simultaneously grow and thicken the first silicon dioxide layer 2 to form a second silicon dioxide layer 22, as shown in FIG. Figure 6 As shown; Step 5: Coat a photoresist on the surface of the second silicon dioxide layer 22 to form a third photoresist layer 25, and use photolithography to etch the third photoresist layer 25 and wet etching to remove the second silicon dioxide layer 22 to form an N+ emitter region doping window 15, such as Figure 7 As shown; Step 6, remove the third photoresist layer 25, pre-dope with phosphorus impurities, and then perform oxidation diffusion to form two N+ emitter regions 8, such as Figure 8 As shown; Preferably, the N+ emitter region 8 is formed by phosphorus impurity pre-diffusion and oxidation diffusion. It is necessary to optimize the square resistance of the phosphorus impurity pre-diffusion and the temperature of the oxidation diffusion to ensure the stability and repeatability of the manufacturing process.

[0042] Step 7, using HF solution to completely remove the second silicon dioxide layer 22 remaining on the surface of the previous process, and re-grow a third silicon dioxide layer 23 with a thickness of 10nm~20nm on the surface of the N-epitaxial layer 1 at low temperature, such as Fig. 9 As shown; Preferably, the second silicon dioxide layer 22 remaining on the surface from the previous process is completely removed, so as to avoid the oxide layer medium containing charges and various defects left by ion implantation from the previous process affecting the lateral current flowing along the surface of the NPN tube.

[0043] Preferably, the low-temperature grown third silicon dioxide layer 23 has a temperature of 800°C to 850°C, and a thickness of the third silicon dioxide layer 23 of 19nm to 21nm. The low-temperature grown third silicon dioxide layer 23 avoids impurity redistribution in the P-type base region, N+ emitter region and N- emitter region caused by high-temperature thermal processes.

[0044] Step 8, depositing a certain thickness of insulating dielectric layer 9, coating the insulating dielectric layer 9 with photoresist to form a fourth photoresist layer 26, and photolithographically forming a contact hole window 16 of the base region of the NPN tube, a contact hole window 17 of the emitter region, and a contact hole window 18 of the collector region on the fourth photoresist layer 26, as shown in FIG. Fig.10 As shown; Step 9, wet etching is used to remove the insulating dielectric layer 9 and the third silicon dioxide layer 23 corresponding to the contact hole window 16 of the base region, the contact hole window 17 of the emitter region, and the contact hole window 18 of the collector region, so as to form the contact hole 19 of the base region, the contact hole 20 of the emitter region, and the contact hole 21 of the collector region of the NPN tube. Fig.11 shown.

[0045] Step 10, depositing metal, photolithography and etching to form the base metal electrode 10, the emitter metal electrode 11 and the collector metal electrode 12 of the NPN tube, such as Fig.12 shown.

[0046] See also Figure 1 and Figure 2 , Figure 1 a is the impurity doping distribution of the base region and emitter region of the NPN tube prepared by the existing process; Figure 1 b is the impurity doping distribution of the base region and emitter region of the NPN tube prepared by the present invention; Figure 2 a is the Ic-Vc curve of the output characteristics of the NPN tube prepared by the existing process; Figure 2 b is the output characteristic Ic-Vc curve diagram of the NPN tube prepared by the present invention; the present invention solves the contradiction between emitter doping and injection efficiency by adding an N-region emitter injection when performing P-type base injection, and on the basis of improving current gain, it also ensures that the NPN tube can obtain a higher withstand voltage.

[0047] The common emitter current gain of the NPN tube prepared by the new process can reach more than 1000, and the CE junction withstand voltage can reach 100 V. If the circuit operating voltage is reduced, the required withstand voltage of the NPN tube is reduced, and the current gain of the NPN tube prepared by the new process can even be greater than 10,000.

[0048] Embodiment five: This embodiment discloses a method for preparing a super-large current gain high-voltage NPN tube, combining Figure 2~Figure 11 , further describing the invention: S1, using P type <111> , a silicon substrate with a square resistance of 10Ω.cm~20Ω.cm; S2, using an epitaxial furnace to grow an N-epitaxial layer 1, the thickness of the N-epitaxial layer 1 is 11.5μm~13.5μm, the resistivity of the N-epitaxial layer 1 is 4.0Ω.cm~4.4Ω.cm, and a first silicon dioxide layer 2 is thermally grown on the N-epitaxial layer 1, see Figure 3 , the thickness of the first silicon dioxide layer 2 is 200 nm; S3, photolithography and etching to form a P-type base region injection window 13, and P-type boron impurity high-energy ion implantation is performed, with an injection energy of 80keV and an injection dose of 3E14cm -2 ~6E14cm -2 , forming a P-type implantation region 4, and then removing the photoresist, see Figure 4 ; S4, photolithography and etching to form a low-doping concentration N-emitter injection window 14, and perform phosphorus impurity high-energy ion implantation, with an implantation energy of 240keV and an implantation dose of 2E14cm -2 ~4E14cm -2 , forming an N-implantation region 5, see Figure 5 , and then removing the photoresist; S5, after 40 minutes of oxidation diffusion at 1150°C, and 60 minutes of nitrogen push-in at 1150°C, a second silicon dioxide layer 22 of a certain thickness is grown on the surface of the N-epitaxial layer 1, the thickness of the second silicon dioxide layer 22 is 550-650nm, and a P-type base region 6 and a low-doping concentration N-emitter region 7 are formed, see Figure 6 ; S6, photolithography is performed to form a high doping concentration N+ emitter region doping window 15, and wet etching is performed to completely remove the second silicon dioxide layer 22 at the N+ emitter region doping window 15, and the photoresist is removed, and then phosphorus pre-doping at 930°C and phosphorus impurity re-diffusion at 950°C are performed to form an N+ emitter region 8 and a high doping concentration lead-out region as a collector region, see Figure 8 ; S7, using HF acid solution with a volume ratio of 3:1 to clean for 15 minutes, completely stripping off the second silicon dioxide layer 22 remaining in the previous process on the surface of the epitaxial layer. Using a low-temperature oxidation furnace tube, 850°C to re-grow a third silicon dioxide layer 23 with a thickness of 190nm~210nm, see Fig. 9 ; S8, LPCVD deposits an insulating dielectric layer 9, made of USG with a thickness of 450nm~550nm, wherein LPCVD is low pressure chemical vapor deposition, and USG is undoped silicon glass or undoped silicon dioxide. Photolithography and wet etching are used to form the contact hole 19 of the base region of the NPN tube, the contact hole 20 of the emitter region, and the contact hole 21 of the collector region, such as Fig.11 As shown; S9, PVD deposits a metal aluminum silicon copper (AlSiCu) dielectric with a thickness of 2μm, where PVD is chemical vapor deposition, Al is aluminum, Si is silicon, and CU is copper. Photolithography is performed to form the base metal electrode 10, the emitter metal electrode 11, and the collector metal electrode 12 of the NPN tube, and then annealing is performed at 450°C for 30 minutes to form an ohmic contact between the metal and silicon.

[0049] The current gain three-temperature test results of the NPN tube prepared in this embodiment and the NPN tube prepared by the prior art are shown in Table 1, wherein the emitter region of the NPN tube is a circle with a diameter of 12 μm.

[0050] Table 1. Current gain three-temperature test results of NPN tube:

[0051] Based on the above method, the present invention also discloses a super-large current gain high-voltage NPN tube, see Fig.12 , including an N-epitaxial layer 1, which helps to withstand high voltage and is a key part of the device's withstand voltage performance. A third silicon dioxide layer 23 and an insulating dielectric layer 9 are arranged on the N-epitaxial layer 1. The third silicon dioxide layer 23 is located between the N-epitaxial layer 1 and the insulating dielectric layer 9, which plays a role of isolation and protection, helps to prevent current leakage and breakdown, thereby improving the reliability and stability of the device. The insulating dielectric layer 9 further enhances the insulation performance of the device and ensures electrical isolation between different electrodes. The third silicon dioxide layer 23 and the insulating dielectric layer 9 are embedded with a base metal electrode 10, an emitter metal electrode 11 and a collector metal electrode 12, providing the device with necessary current paths and external connection points.

[0052] The N-epitaxial layer 1 is provided with a P-type base region 6, an N-emitter region 7 and two N+ emitter regions 8, the N-emitter region 7 is located inside the P-type base region 6, one N+ emitter region 8 is located in the N-epitaxial layer 1, and the other N+ emitter region 8 is located in the N-emitter region 7; the P-type base region 6, the N-emitter region and the N+ emitter region together constitute the amplification region of the device, the N-emitter region 7 is the main region for emitting electrons, and the high doping concentration of the N+ emitter region helps to reduce the contact resistance and improve the current injection efficiency, thereby further enhancing the current gain performance of the device.

[0053] The base metal electrode 10 is connected to the P-type base region 6 , the emitter metal electrode 11 is connected to the N+ emitter region 8 inside the N− emitter region 7 , and the collector metal electrode 12 is connected to the N+ emitter region 8 inside the N− epitaxial layer 1 .

[0054] The above contents are only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A method for preparing a super-large current gain high-voltage NPN tube, characterized in that: The following steps are involved: High-energy boron impurity ions are injected into the N-epitaxial layer (1) to form a P-type injection region (4); Implanting phosphorus or arsenic impurity high energy ions into the N-epitaxial layer (1) to form an N-implantation region (5) in the P-type implantation region (4); Performing oxidation diffusion on the N-epitaxial layer (1) so that the P-type implantation region (4) forms a P-type base region (6) and the N-implantation region (5) forms an N-emitter region (7); Pre-doping and oxidative diffusion of phosphorus impurities are performed on the N-emitter region (7) and the N-epitaxial layer (1) respectively, to form two N+ emitter regions (8); A base metal electrode (10), an emitter metal electrode (11) and a collector metal electrode (12) are deposited on the surface of the N-epitaxial layer (1), respectively; the base metal electrode (10) is connected to the P-type base region (6), the emitter metal electrode (11) is connected to the N+ emitter region (8) inside the N-emitter region (7), and the collector metal electrode (12) is connected to the N+ emitter region (8) inside the N-epitaxial layer (1).

2. The method for preparing a super-large current gain high-voltage NPN tube according to claim 1, characterized in that: The step of injecting high-energy boron impurity ions into the N-epitaxial layer (1) to form the P-type implantation region (4) is as follows: Thermally growing a first silicon dioxide layer (2) on the N-epitaxial layer (1), wherein the thickness of the first silicon dioxide layer (2) is less than or equal to 200 nm; Coating a photoresist on the surface of the first silicon dioxide layer (2) to form a first photoresist layer (3), and photolithographically forming a P-type base region injection window (13) on the first photoresist layer (3); Boron impurity high-energy ions are injected into the N-epitaxial layer (1) through a P-type base region injection window (13), thereby forming a P-type injection region (4) on the N-epitaxial layer (1).

3. The method for preparing a super-large current gain high-voltage NPN tube according to claim 2, characterized in that: The step of injecting phosphorus or arsenic impurity high energy ions into the N-epitaxial layer (1) to form an N-implantation region (5) in the P-type implantation region (4) is as follows: Removing the first photoresist layer (3) on the surface of the first silicon dioxide layer (2) and re-coating the photoresist to form a second photoresist layer (24), and photolithographically forming an N-emitter region injection window (14) on the second photoresist layer (24); Phosphorus or arsenic impurity high-energy ions are injected into the N-epitaxial layer (1) through the first silicon dioxide layer (2) using the N-emitter region injection window (14), thereby forming an N-injection region (5) in the P-type injection region (4).

4. The method for preparing a super-large current gain high-voltage NPN tube according to claim 3, characterized in that: The method comprises injecting phosphorus or arsenic impurity high energy ions into the N-epitaxial layer (1), with the injection energy being 240 keV and the injection dose being 2E14 cm -2 ~4E14cm -2 .

5. The method for preparing a super-large current gain high-voltage NPN tube according to claim 1, characterized in that: The N-epitaxial layer (1) is subjected to oxidation diffusion so that the P-type injection region (4) forms a P-type base region (6) and the N-injection region (5) forms an N-emitter region (7), specifically as follows: The N-epitaxial layer (1) comprising a P-type injection region (4) and an N-injection region (5) is subjected to oxidation diffusion at 1150°C for 40 minutes. After the oxidation diffusion is completed, the layer is subjected to nitrogen push bonding at 1150°C for 60 minutes. A second silicon dioxide layer (22) is grown on the surface of the N-epitaxial layer (1). The thickness of the second silicon dioxide layer (22) is 550nm-650nm. The P-type injection region (4) forms a P-type base region (6), and the N-injection region (5) forms an N-emitter region (7).

6. The method for preparing a super-large current gain high-voltage NPN tube according to claim 4, characterized in that: The phosphorus impurity pre-doping and oxidation diffusion are sequentially performed on the N-emitter region (7) and the N-epitaxial layer (1) to form two N+ emitter regions (8), specifically as follows: Coating a photoresist on the surface of the second silicon dioxide layer (22) to form a third photoresist layer (25); The third photoresist layer (25) is etched by photolithography and the second silicon dioxide layer (22) is etched by wet etching to form two N+ emitter region doping windows (15), wherein a port of one N+ emitter region doping window (15) contacts the surface of the N- emitter region (7), and a port of the other N+ emitter region doping window (15) contacts the surface of the N- epitaxial layer (1); Phosphorus impurity pre-doping and phosphorus impurity re-diffusion are performed in sequence in the N-emitter region (7) and the N-epitaxial layer (1) through an N+ emitter region doping window (15) to form two N+ emitter regions (8), wherein the ambient temperature for the phosphorus impurity pre-doping is 930° C., and the ambient temperature for the phosphorus impurity re-diffusion is 950° C.

7. The method for preparing a super-large current gain high-voltage NPN tube according to claim 1, characterized in that: The base metal electrode (10), the emitter metal electrode (11) and the collector metal electrode (12) are deposited on the surface of the N-epitaxial layer (1), respectively, the base metal electrode (10) is connected to the P-type base region (6), the emitter metal electrode (11) is connected to the N+ emitter region (8) inside the N-emitter region (7), and the collector metal electrode (12) is connected to the N+ emitter region (8) inside the N-epitaxial layer (1), as follows: Cleaning the surface of the N-epitaxial layer (1); A third silicon dioxide layer (23) having a thickness of 19 nm to 21 nm is grown on the surface of the N-epitaxial layer (1), an insulating dielectric layer (9) is deposited on the third silicon dioxide layer (23), and a photoresist is coated on the insulating dielectric layer (9) to form a fourth photoresist layer (26), wherein the material of the insulating dielectric layer (9) is USG, and the thickness of the insulating dielectric layer (9) is 450 nm to 550 nm; Photolithography of a fourth photoresist layer (26), forming a contact hole window (16) of the base region, a contact hole window (17) of the emitter region, and a contact hole window (18) of the collector region on the fourth photoresist layer (26); Wet etching the insulating dielectric layer (9) and the third silicon dioxide layer (23) between the contact hole window (16) of the base region, the contact hole window (17) of the emitter region, the contact hole window (18) of the collector region and the N-epitaxial layer (1) to form a contact hole (19) of the base region, a contact hole (20) of the emitter region and a contact hole (21) of the collector region, wherein the contact hole (19) of the base region is connected to the P-type base region (6), the contact hole (20) of the emitter region is connected to the N+ emitter region (8) inside the N-emitter region (7), and the contact hole (21) of the collector region is connected to the N+ emitter region (8) inside the N-epitaxial layer (1); Depositing metal in the contact hole (19) of the base region to form a base region metal electrode (10); Depositing metal in the contact hole (20) of the emitter region to form an emitter region metal electrode (11); Metal is deposited in the contact hole (21) of the collector region to form a collector region metal electrode (12).

8. The method for preparing a super-large current gain high-voltage NPN tube according to claim 7, characterized in that: The step of growing a third silicon dioxide layer (23) with a thickness of 19 nm to 21 nm on the surface of the N-epitaxial layer (1) is as follows: A third silicon dioxide layer (23) with a thickness of 19 nm to 21 nm is grown on the surface of the N-epitaxial layer (1) in an environment of 850° C.

9. The method for preparing a super-large current gain high-voltage NPN tube according to claim 1, characterized in that: The resistivity of the N-epitaxial layer (1) is 4.0 Ω.cm to 4.4 Ω.cm, and the thickness of the N-epitaxial layer (1) is 11.5 μm to 13.5 μm.

10. An ultra-large current gain high-voltage NPN tube prepared by the method for preparing an ultra-large current gain high-voltage NPN tube according to any one of claims 1 to 9, characterized in that: The invention comprises an N-epitaxial layer (1), a third silicon dioxide layer (23) and an insulating dielectric layer (9) are arranged on the N-epitaxial layer (1), the third silicon dioxide layer (23) is located between the N-epitaxial layer (1) and the insulating dielectric layer (9), and a base region metal electrode (10), an emitter region metal electrode (11) and a collector region metal electrode (12) are embedded in the third silicon dioxide layer (23) and the insulating dielectric layer (9); The N-epitaxial layer (1) is provided with a P-type base region (6), an N-emitter region (7) and two N+ emitter regions (8), the N-emitter region (7) is located inside the P-type base region (6), one N+ emitter region (8) is located inside the N-epitaxial layer (1), and the other N+ emitter region (8) is located inside the N-emitter region (7); The base region metal electrode (10) is connected to the P-type base region (6), the emitter region metal electrode (11) is connected to the N+ emitter region (8) inside the N- emitter region (7), and the collector region metal electrode (12) is connected to the N+ emitter region (8) inside the N- epitaxial layer (1).

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