Insulated gate bipolar transistor and preparation method thereof

Abstract

The invention discloses an insulated gate bipolar transistor and a preparation method thereof in the technical field of semiconductor devices. The transistor comprises a substrate which comprises a P + silicon substrate, an N + epitaxial layer and an N-epitaxial layer from bottom to top; the active region is sequentially provided with a P well, a gate insulating layer, a polycrystalline silicon gate, an insulating leveling layer and an emitter electrode from bottom to top, and an N well is arranged in the P well; a field limiting ring, a polycrystalline silicon field plate, an insulating leveling layer and a metal field plate are sequentially arranged in the terminal area from bottom to top; the cut-off region is sequentially provided with a cut-off ring, a polycrystalline silicon field plate and an insulating leveling layer from bottom to top; wherein the N-epitaxial layer is provided with oxidation masking layers, and the oxidation masking layers are arranged between the adjacent field limiting rings and between the field limiting rings and the cut-off rings. The insulated gate bipolar transistor is of a soft punch-through type and is high in noise interference resistance and low in power consumption, back injection and annealing are not needed, the production process is simplified, the cost is reduced, and the device reliability is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an insulated gate bipolar transistor and a preparation method thereof. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is a fully controlled power semiconductor device that combines the gate electrode voltage control characteristics of metal oxide semiconductor field effect transistor (MOSFET) and the low on-resistance characteristics of bipolar junction transistor (BJT). It is a core component in the field of power control and electric energy conversion. It can adjust the voltage, current, frequency, phase, etc. in the circuit according to signal instructions. It is called the "CPU of the power electronics industry" and the "heart of the industrial Internet". In recent years, with the rapid development of industries such as new energy vehicles, clean energy power generation and low-altitude economy, IGBT application scenarios have become more and more extensive, and the performance requirements for IGBT are also gradually increasing.

[0003] There are two main technical solutions for manufacturing IGBTs: one is to manufacture punch-through IGBTs through epitaxial process; the other is to manufacture non-punch-through and field-stop IGBTs through backside injection and thermal annealing. Punch-through IGBTs are difficult to precisely control in the epitaxial growth process because the epitaxial thickness and doping concentration are difficult to control. At the same time, during the wafer tape-out process, the epitaxial wafer will be affected by high-temperature operations such as thermal oxidation and annealing, causing overdiffusion. The carrier injection efficiency is difficult to control, and the dynamic characteristics of the device are poor. Non-punch-through and field-stop IGBTs are usually hard-breakdown due to the limited backside injection depth, and have weak anti-electromagnetic interference, noise suppression and reliability. At the same time, backside annealing will affect the front MOS structure, posing certain reliability risks.

[0004] Therefore, there is an urgent need to launch a high-performance, high-reliability insulated gate bipolar transistor device into the market. Summary of the invention

[0005] The present application solves the current problems of poor electrical characteristics and weak reliability of insulated gate bipolar transistors by providing an insulated gate bipolar transistor and a preparation method thereof, thereby improving the performance and reliability of the insulated gate bipolar transistor.

[0006] The present application provides an insulated gate bipolar transistor, comprising: The substrate includes a P+ silicon substrate, an N+ epitaxial layer, and an N- epitaxial layer from bottom to top; wherein the P+ silicon substrate is a collector region, the N+ epitaxial layer is a buffer region, and the N- epitaxial layer is a drift region; An active region, a terminal region and a cut-off region are provided on the N-epitaxial layer; The active area is provided with a P well, a gate insulating layer, a polysilicon gate, an insulating leveling layer and an emitter electrode in sequence from bottom to top, an N well is provided in the P well, and the P well is connected to the emitter electrode through a contact hole in the insulating leveling layer; The terminal region is provided with a P-implanted field limiting ring, a polysilicon field plate, the insulating leveling layer and a metal field plate in sequence from bottom to top, the P-implanted field limiting ring is connected to the polysilicon field plate, and the polysilicon field plate is connected to the metal field plate through a contact hole in the insulating leveling layer; The cut-off region is provided with an N-injection cut-off ring, the polysilicon field plate and the insulating leveling layer in sequence from bottom to top, and the N-injection field limiting ring is connected to the polysilicon field plate; Among them, an oxidation masking layer is arranged on the N-epitaxial layer, and the oxidation masking layer is arranged between adjacent P injection field limiting rings and between the P injection field limiting ring and the N injection cut-off ring. The polysilicon field plate and the insulating leveling layer are located above the oxidation masking layer.

[0007] The beneficial effects of the above embodiments are: the insulated gate bipolar transistor is a soft punch-through type, wherein the N+ epitaxial layer can buffer the built-in electric field, reduce the thickness of the depletion region, i.e., the drift region of the N- epitaxial layer, reduce the forward conduction voltage, reduce power consumption, and delay the expansion speed of the depletion layer boundary, so that the turn-off transient electrical characteristics are very soft; when the polysilicon gate receives an electrical signal, the P well will form an inversion layer as a conductive channel, the N well provides electrons, the insulating leveling layer is used to cover the front structure to isolate water vapor, and the oxidation masking layer and the polysilicon field plate are used to optimize the electric field line distribution in the device and reduce the surface collision ionization rate. After structural optimization, the insulated gate bipolar transistor has strong anti-noise interference ability, low power consumption, no need for back injection and annealing, simplifies the production process and reduces costs, and avoids the influence of back annealing on front impurities, thereby improving device reliability.

[0008] Based on the above embodiments, the present application can be further improved as follows: In one of the embodiments of the present application, a collector electrode is disposed on the back side of the substrate.

[0009] In one embodiment of the present application, the doping element of the N+ epitaxial layer is arsenic. Arsenic has a larger relative atomic mass and a smaller diffusion coefficient, which is beneficial to avoid over-diffusion of impurities.

[0010] In one embodiment of the present application, the doping concentration of the N-epitaxial layer is 1e 12 -1e 15 cm -3 The thickness is 30 μm-260 μm; the doping concentration of the N+ epitaxial layer is 1e 14 ~9e 17 cm-3 The thickness is 3μm~20μm; the doping concentration of the P+ silicon substrate is 1e 16 ~9e 19 cm -3 The thickness is within the range of 0.5μm~5μm.

[0011] In one embodiment of the present application, in the P+ silicon substrate, the boron ion doping concentration is 1-3 orders of magnitude higher than the arsenic ion or phosphorus ion doping concentration; in the N+ epitaxial layer, the arsenic ion doping concentration is higher than the boron ion or phosphorus ion doping concentration, and under the same depth conditions, the arsenic ion doping concentration is 1-3 orders of magnitude higher than the boron ion, and under the same doping concentration conditions, the arsenic ion doping depth is 2-5μm deeper than the boron ion; in the N- epitaxial layer, the phosphorus ion doping concentration is 1-3 orders of magnitude higher than the boron ion or arsenic ion doping concentration. The above-mentioned overall thermal budget control enables the soft punch-through insulated gate bipolar transistor to adjust the collector carrier injection efficiency in the forward conduction mode, reduce the forward conduction voltage, and further reduce power consumption; at the same time, it slows down the expansion speed of the depletion layer boundary, effectively suppressing high dv / dt, di / dt electromagnetic interference noise.

[0012] In one embodiment of the present application, the width of the field limiting ring is 5-20 μm, and the doping concentration is 1e 13 ~1e 16 cm -3 The junction depth after annealing is 5~15μm; the width of the cut-off ring is 20~60μm, and the doping concentration is 1e 14 ~1e 19 cm -3 , the junction depth after annealing is 5~15μm.

[0013] In one embodiment of the present application, the implantation dose of the P well is 1e 13 -5e 14 cm -3 The junction depth is 3-6 μm; the N-well injection dose is 5e 14 -9e 15 cm -3 The knot pushing depth is 0.1-1.5μm.

[0014] The present application also provides a method for preparing the above-mentioned insulated gate bipolar transistor, comprising the following steps: S1: Selecting the N- / N+ / P+ triple-doped substrate, wherein the substrate comprises, from bottom to top, a P+ silicon substrate, an N+ epitaxial layer, and an N- epitaxial layer; S2: Form an oxide mask layer with a thickness of 10000~25000Å on the top of the N-epitaxial layer through a thermal oxidation process, and open windows through a photolithography and etching process to form an injection region of an active region, a field limiting ring, and a cutoff ring, retain the oxide mask layer between the field limiting rings, and form a field limiting ring and a cutoff ring through an injection and annealing process; S3: growing a gate insulating layer with a thickness of about 500-1500 Å on the N-epitaxial layer and the oxidation mask layer by dry oxygen oxidation, depositing a polysilicon layer with a thickness of 5000-15000 Å as a gate, and opening the P-well injection region by a photolithography and etching process to simultaneously form a polysilicon gate and a polysilicon field plate pattern; wherein the gate insulating layer is grown twice to cover the polysilicon gate; S4: forming a P well and an N well in the P well injection region by an injection and annealing process; S5: depositing 10000-20000Å BPSG as an insulating leveling layer and reflowing, opening contact holes by photolithography and etching process, depositing 3-5μm thick Al as an emitter electrode and a metal field plate on the insulating leveling layer by vacuum evaporation, the metal field plate is connected to the polysilicon field plate through the contact hole, and the emitter metal electrode is connected to the P well through the contact hole; S6: Grind the P+ silicon substrate, perform back thinning, retain 0.5-5 μm thick substrate as collector area, and vacuum evaporate 1-3 μm Al as collector electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0016] Figure 1 This is a schematic diagram of the structure of an insulated gate bipolar transistor in an embodiment of the present application; Figure 2 A schematic diagram of a method for preparing an insulated gate bipolar transistor in an embodiment of the present application Figure 1 ; Figure 3 A schematic diagram of a method for preparing an insulated gate bipolar transistor in an embodiment of the present application Figure 2 ; Figure 4 A schematic diagram of a method for preparing an insulated gate bipolar transistor in an embodiment of the present application Figure 3 ; Figure 5 A schematic diagram of a method for preparing an insulated gate bipolar transistor in an embodiment of the present application Figure 4; Figure 6 A schematic diagram of a method for preparing an insulated gate bipolar transistor in an embodiment of the present application Figure 5 ; Figure 7 Schematic diagram of comparison of impurity diffusion depths in the drift region, buffer region and collector region in the substrate in the embodiment of the present application.

[0017] Among them, 11. N- epitaxial layer, 12. N+ epitaxial layer, 13. P+ silicon substrate, 21. oxidation mask layer, 22. field limiting ring, 23. cut-off ring, 31. polysilicon gate, 32. gate insulation layer, 33. polysilicon field plate, 41. P well, 42. N well, 51. insulating leveling layer, 52. emitter electrode, 53. metal field plate, 61. collector electrode. DETAILED DESCRIPTION

[0018] The present invention is further explained below in conjunction with specific implementation methods. It should be understood that these implementation methods are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

[0019] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0020] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "above", "back", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. It should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0021] In the description of the present invention, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in the present invention and the features of different embodiments or examples without contradiction.

[0022] The embodiments of the present application provide an insulated gate bipolar transistor and a method for preparing the same, thereby solving the problems of poor electrical characteristics and low reliability of the current insulated gate bipolar transistor and improving the performance and reliability of the insulated gate bipolar transistor.

[0023] The technical solution in the embodiment of the present application is to solve the above problems, and the overall idea is as follows: Example: like Figure 1 As shown, an insulated gate bipolar transistor comprises: The substrate includes a P+ silicon substrate 13, an N+ epitaxial layer 12, and an N- epitaxial layer 11 from bottom to top; wherein the P+ silicon substrate 13 is a collector region, the N+ epitaxial layer 12 is a buffer region, and the N- epitaxial layer 11 is a drift region; a collector electrode 61 is arranged on the back of the substrate.

[0024] An active region, a terminal region and a cut-off region are arranged on the N-epitaxial layer 11; The active area is provided with a P well 41, a gate insulating layer 32, a polysilicon gate 31, an insulating leveling layer 51 and an emitter electrode 52 in order from bottom to top. An N well 42 is provided in the P well 41, and the P well 41 is connected to the emitter electrode 52 through a contact hole in the insulating leveling layer 51; The terminal region is provided with a P-implanted field limiting ring 22, a polysilicon field plate 33, an insulating leveling layer 51 and a metal field plate 53 in sequence from bottom to top. The P-implanted field limiting ring 22 is connected to the polysilicon field plate 33, and the polysilicon field plate 33 is connected to the metal field plate 53 through a contact hole in the insulating leveling layer 51. The cut-off region is provided with an N-implantation cut-off ring 23, a polysilicon field plate 33 and an insulating leveling layer 51 in sequence from bottom to top, and the N-implantation field limiting ring 22 is connected to the polysilicon field plate 33; Among them, an oxidation masking layer 21 is arranged on the N-epitaxial layer 11, and the oxidation masking layer 21 is arranged between adjacent P injection field limiting rings 22, and between the P injection field limiting ring 22 and the N injection cut-off ring 23. The polysilicon field plate 33 and the insulating leveling layer 51 are located above the oxidation masking layer 21.

[0025] Furthermore, in the substrate, the doping concentration of the N-epitaxial layer 11 is 1e 12 -1e 15 cm -3The thickness is 30μm-260μm; the doping concentration of N+ epitaxial layer 12 is 1e 14 ~9e 17 cm -3 The thickness is 3μm~20μm; the doping concentration of P+ silicon substrate 13 is 1e 16 ~9e 19 cm -3 Within the range, the original P+ silicon substrate thickness is generally 50μm~150μm, and the thickness of the P+ silicon substrate after thinning is generally 0.5~5μm.

[0026] The resistivity and thickness of the N-epitaxial layer 11 (drift region) of the N- / N+ / P+ triple-layer doped epitaxial wafer depend on the IGBT operating voltage; when the operating voltage is 600V, the resistivity of the N-epitaxial layer 11 (drift region) is in the range of 18Ω.cm~32Ω.cm, and the thickness is in the range of 30μm~100μm; when the operating voltage is 1200V, the resistivity of the N-epitaxial layer 11 (drift region) is in the range of 35Ω.cm~100Ω.cm, and the thickness is in the range of 100μm~200μm; when the operating voltage is 1700V, the resistivity of the N-epitaxial layer 11 (drift region) is in the range of 80Ω.cm~160Ω.cm, and the thickness is in the range of 160μm~260μm.

[0027] like Figure 1-6 As shown, the method for preparing the insulated gate bipolar transistor comprises the following steps: S1: Figure 2 As shown, a N- / N+ / P+ three-layer doped substrate is selected, and the substrate includes a P+ silicon substrate 13, an N+ epitaxial layer 12, and an N- epitaxial layer 11 from bottom to top; S2: Figure 3 As shown, an oxide mask layer 21 with a thickness of 10000-25000Å is formed on the top of the N-epitaxial layer 11 by a thermal oxidation process, and a window is opened by a photolithography process to form an injection region of an active region, a field limiting ring 22 and a stop ring 23, and the oxide mask layer 21 between the field limiting rings 22 is retained. The field limiting rings 22 and the stop rings 23 are formed by an injection and annealing process. The width of the field limiting ring 22 is 5-20μm, and the doping concentration is 1e 13 ~1e 16 cm -3 After annealing, the junction depth is 5~15μm, the width of the cut-off ring 23 is 20~60μm, and the doping concentration is 1e 14 ~1e 19 cm -3 , the junction depth after annealing is 5~15μm; S3: Figure 4As shown, a gate insulating layer 32 with a thickness of about 500-1500 Å is grown on the N-epitaxial layer 11 and the oxidation mask layer 21 by dry oxygen oxidation, a 5000-15000 Å polysilicon layer is deposited as a gate, and a P-well implantation region is opened by a photolithography and etching process to simultaneously form a polysilicon gate 31 and a polysilicon field plate 33 pattern; wherein the gate insulating layer 32 is grown twice, thereby covering the polysilicon gate 31; S4: Figure 5 As shown, a P well 41 and an N well 42 are formed in the P well injection region by an injection and annealing process, and the injection dose of the P well 41 is 1e 13 -5e 14 cm -3 , the junction depth is 3-6μm, and the N well 42 injection dose is 5e 14 -9e 15 cm -3 , the pushing depth is 0.1-1.5μm; S5: Figure 6 As shown, 10000-20000Å BPSG is deposited as an insulating leveling layer 51 and reflowed, a contact hole is opened by a photolithography and etching process, and 3-5μm thick Al is deposited on the insulating leveling layer 51 by vacuum evaporation as an emitter electrode 52 and a metal field plate 53, the metal field plate 53 is connected to the polysilicon field plate 33 through the contact hole, and the emitter metal electrode is connected to the P well 41 through the contact hole; S6: Figure 1 As shown, the P+ silicon substrate 13 is ground and thinned on the back side, leaving a 0.5-5 μm thick substrate as the collector region, and 1-3 μm Al is vacuum evaporated as the collector electrode 61.

[0028] Furthermore, the high temperature operations such as oxidation, annealing and reflow in steps S2 / 3 / 4 / 5 require an overall thermal budget to control the impurity diffusion depth of the drift region, buffer region and collector region in the N- / N+ / P+ three-layer epitaxial wafer, such as Figure 7 As shown: the impurity diffusion depths of the drift region, buffer region and collector region in the N- / N+ / P+ three-layer epitaxial wafer after overall thermal budget meet the following conditions: in the collector region of the P+ silicon substrate, the boron ion doping concentration is 1-3 orders of magnitude higher than the arsenic ion or phosphorus ion doping concentration; in the N+ epitaxial layer buffer region, the arsenic ion doping concentration is higher than the boron ion or phosphorus ion doping concentration, and under the same depth conditions, the arsenic ion doping concentration is 1-3 orders of magnitude higher than the boron ion, and under the same doping concentration conditions, the arsenic ion doping depth is 2-5μm deeper than the boron ion; in the drift region of the N- epitaxial layer, the phosphorus ion doping concentration is 1-3 orders of magnitude higher than the boron ion doping concentration.

[0029] The technical solutions in the above embodiments of the present application have at least the following technical effects or advantages: 1. Compared with the traditional manufacturing process of punch-through insulated gate bipolar transistor, the present invention reduces the thickness of N+ buffer layer and P+ collector region through thermal budget and back thinning methods, controls the impurity diffusion depth, thereby adjusting the back carrier injection efficiency and conductivity modulation effect, and optimizing the dynamic electrical characteristics of the device; the N+ buffer layer is doped with arsenic, which has a larger relative atomic mass and a smaller diffusion coefficient, which is beneficial to avoid excessive diffusion of impurities; epitaxial wafers that meet the design parameters are purchased through industrial chain cooperation to avoid the cost pressure of epitaxial equipment.

[0030] 2. Compared with non-punch-through and field-stop insulated gate bipolar transistors, the present invention does not require backside injection and annealing, which simplifies the production process and reduces costs. At the same time, it avoids the influence of backside annealing on front side impurities and improves device reliability.

[0031] 3. The N+ buffer of the soft punch-through insulated gate bipolar transistor of the present invention can buffer the built-in electric field, reduce the thickness of the depletion region, i.e., the drift region of the N-epitaxial layer, and in the forward conduction mode, adjust the carrier injection efficiency of the collector, reduce the forward conduction voltage, and greatly reduce power consumption; at the same time, it delays the expansion speed of the depletion layer boundary, so that the turn-off transient electrical characteristics are very soft, which has advantages in suppressing higher dv / dt, di / dt electromagnetic interference noise.

[0032] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. An insulated gate bipolar transistor, characterized in that: include: A substrate, including from bottom to top a P+ silicon substrate, an N+ epitaxial layer, and an N- epitaxial layer; An active region, a terminal region and a cut-off region are provided on the N-epitaxial layer; The active area is provided with a P well, a gate insulating layer, a polysilicon gate, an insulating leveling layer and an emitter electrode in sequence from bottom to top, an N well is provided in the P well, and the P well is connected to the emitter electrode through a contact hole in the insulating leveling layer; The terminal region is provided with a field limiting ring, a polysilicon field plate, the insulating leveling layer and a metal field plate in sequence from bottom to top, the field limiting ring is connected to the polysilicon field plate, and the polysilicon field plate is connected to the metal field plate through a contact hole in the insulating leveling layer; The cut-off region is provided with a cut-off ring, the polysilicon field plate and the insulating leveling layer in sequence from bottom to top, and the field limiting ring is connected to the polysilicon field plate; Wherein, an oxidation masking layer is arranged on the N-epitaxial layer, and the oxidation masking layer is arranged between adjacent field limiting rings and between the field limiting ring and the cut-off ring.

2. The insulated gate bipolar transistor according to claim 1, wherein: A collector electrode is arranged on the back side of the substrate.

3. The insulated gate bipolar transistor according to claim 1, wherein: The doping element of the N+ epitaxial layer is arsenic.

4. The insulated gate bipolar transistor according to claim 1, wherein: The doping concentration of the N-epitaxial layer is 1e 12 -1e 15 cm -3 The thickness is 30 μm-260 μm; the doping concentration of the N+ epitaxial layer is 1e 14 ~9e 17 cm -3 The thickness is 3μm~20μm; the doping concentration of the P+ silicon substrate is 1e 16 ~9e 19 cm -3 The thickness is in the range of 0.5 μm-5 μm.

5. The insulated gate bipolar transistor according to claim 4, characterized in that: In the P+ silicon substrate, the boron ion doping concentration is 1-3 orders of magnitude higher than the arsenic ion or phosphorus ion doping concentration; in the N+ epitaxial layer, the arsenic ion doping concentration is higher than the boron ion or phosphorus ion doping concentration, and under the same depth conditions, the arsenic ion doping concentration is 1-3 orders of magnitude higher than that of the boron ion, and under the same doping concentration conditions, the arsenic ion doping depth is 2-5μm deeper than that of the boron ion; in the N- epitaxial layer, the phosphorus ion doping concentration is 1-3 orders of magnitude higher than that of the boron ion doping concentration.

6. The insulated gate bipolar transistor according to claim 1, wherein: The width of the field limiting ring is 5-20 μm, and the doping concentration is 1e 13 ~1e 16 cm -3 The junction depth after annealing is 5~15μm; the width of the cut-off ring is 20~60μm, and the doping concentration is 1e 14 ~1e 19 cm -3 , the junction depth after annealing is 5~15μm.

7. The insulated gate bipolar transistor according to claim 1, wherein: The implantation dose of the P well is 1e 13 -5e 14 cm -3 The junction depth is 3-6 μm; the N-well injection dose is 5e 14 -9e 15 cm -3 The knot pushing depth is 0.1-1.5μm.

8. A method for preparing an insulated gate bipolar transistor according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1: Selecting the substrate, wherein the substrate includes the P+ silicon substrate, the N+ epitaxial layer, and the N- epitaxial layer; S2: forming an oxidation mask layer on the top of the N-epitaxial layer by a thermal oxidation process, and opening a window by a photolithography and etching process to form the implantation region of the active region, the field limiting ring and the cut-off ring, retaining the oxidation mask layer between the field limiting rings, and forming the field limiting ring and the cut-off ring by an implantation and annealing process; S3: growing a gate insulating layer on the N-epitaxial layer and the oxidation mask layer by dry oxygen oxidation, depositing a polysilicon layer as a gate, and opening a P-well implantation region by a photolithography and etching process to simultaneously form the polysilicon gate and polysilicon field plate; S4: forming the P well and the N well in the P well injection region by an injection and annealing process; S5: depositing BPSG as the insulating leveling layer and reflowing, opening contact holes by photolithography and etching, depositing metal as the emitter electrode and metal field plate on the insulating leveling layer by vacuum evaporation, the metal field plate is connected to the polysilicon field plate through the contact hole, and the emitter metal electrode is connected to the P well through the contact hole; S6: Grind the P+ silicon substrate, perform backside thinning, and vacuum evaporate metal as a collector electrode.

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