LDMOS device and preparation method thereof

Abstract

The invention provides a preparation method of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device, which comprises the following steps of: while thinning an isolation material layer in a high-voltage MOS (Metal Oxide Semiconductor) device region, etching a part of thickness of the isolation material layer in the high-voltage MOS device region to form a bulge structure covering a junction position of a shallow trench isolation structure and an active region edge (the isolation material layer), namely, forming a shallow trench isolation structure on the high-voltage MOS device region; a protruding structure (isolation material layer) with a certain thickness is reserved at the junction position of the shallow trench isolation structure and the edge of the active region, so that the thickness of a gate oxide layer in the edge region of the active region is larger than that of a gate oxide layer in the middle region of the active region, and the purpose of improving the threshold voltage at the channel corner of the high-voltage device is achieved. The difference value between the threshold voltage at the middle position of the channel and the threshold voltage at the corner position of the channel of the high-voltage device is reduced (compensated / compensated), the double-peak phenomenon of an ID-VG curve of the high-voltage device is avoided, and meanwhile the drift condition of parasitic parameters of the device is also avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an LDMOS device and a method for preparing the same. Background Art

[0002] Due to the metal gate process used at the 28nm node and below, especially for display driver chips, MOS devices with an operating voltage of tens of volts need to be integrated at the same time. On the one hand, the high-voltage devices currently use the STI (Shallow Trench Isolation) structure instead of the LOCOS (Local Oxidation of Silicon) structure; on the other hand, the gate oxide layer of the high-voltage device adopts a process of first etching and then deposition. The etching process causes the boron ions in the P-type silicon substrate to segregate into the STI due to the high solid solubility of STI for boron ions (B), and the deposition process causes sharp corners in the corners of the active area edge area close to the STI during the gate oxide layer growth process due to process limitations.

[0003] The above two factors cause the threshold voltage VT at the channel corner to be smaller than the threshold voltage VT in the middle area of ​​the channel, resulting in a double peak phenomenon in the ID-VG curve (drain-source current-gate-source voltage characteristic curve), which is more obvious especially after substrate bias occurs.

[0004] In order to solve this double peak phenomenon, based on the cause, the traditional solution is to choose to supplement the channel corner area with boron ions, but this involves the IMP ion implantation process, which often causes the device parasitic parameters to drift. Summary of the invention

[0005] The present application provides an LDMOS device and a method for preparing the same, which can solve at least one of the following problems: a large difference between a threshold voltage at a middle position of a channel of a high-voltage device and a threshold voltage at a channel corner position, resulting in a double peak phenomenon in an ID-VG curve, and a drift in device parasitic parameters.

[0006] On the one hand, an embodiment of the present application provides a method for preparing an LDMOS device, comprising:

[0007] A substrate is provided, the substrate at least comprising: a medium voltage MOS device region and a high voltage MOS device region, a plurality of trenches are formed in the substrate of the medium voltage MOS device region and in the substrate of the high voltage MOS device region;

[0008] forming an isolation material layer, wherein the isolation material layer fills the trenches of the medium voltage MOS device region and the trenches of the high voltage MOS device region to form a plurality of shallow trench isolation structures, and the isolation material layer also covers the active areas between the trenches;

[0009] coating a first photoresist layer on the isolation material layer;

[0010] By using a specific photomask, defining an opening pattern of a high-voltage MOS device region on the first photoresist layer to obtain a patterned first photoresist layer;

[0011] Using the patterned first photoresist layer as a mask, etching a portion of the thickness of the isolation material layer and a portion of the thickness of the shallow trench isolation structure in the medium voltage MOS device area and the high voltage MOS device area, wherein in the high voltage MOS device area, an opening is formed in the isolation material layer, and the portion of the thickness of the isolation material layer that is not etched on the side of the opening constitutes a convex structure, the convex structure covers the junction position between the shallow trench isolation structure and the isolation material layer, and the isolation material layer between the convex structure and the shallow trench isolation structure together constitutes a gate oxide layer of the high voltage MOS device area;

[0012] removing the patterned first photoresist layer;

[0013] A gate material layer is formed, wherein the gate material layer covers the shallow trench isolation structure, the protruding structure and the isolation material layer in the high voltage MOS device region, and covers the shallow trench isolation structure and the isolation material layer in the medium voltage MOS device region.

[0014] Optionally, in the method for preparing the LDMOS device, in the high-voltage MOS device region, the thickness of the protruding structure is 10% to 20% of the thickness of the final remaining isolation material layer between the shallow trench isolation structures.

[0015] Optionally, in the preparation method of the LDMOS device, after forming the isolation material layer and before coating the first photoresist layer on the isolation material layer, the thickness of the isolation material layer between the shallow trench isolation structures in the medium voltage MOS device area is less than the thickness of the isolation material layer between the shallow trench isolation structures in the high voltage MOS device area.

[0016] Optionally, in the method for preparing the LDMOS device, the isolation material layer is made of silicon dioxide.

[0017] Optionally, in the method for preparing the LDMOS device, after forming the gate material layer, the method for preparing the LDMOS device further includes:

[0018] coating a second photoresist layer on the gate material layer;

[0019] Defining a gate pattern of a high voltage MOS device region and a gate pattern of a medium voltage MOS device region on the second photoresist layer to obtain a patterned second photoresist layer;

[0020] Using the patterned second photoresist layer as a mask, etching the gate material layers of the medium voltage MOS device region and the high voltage MOS device region to obtain a gate of the high voltage MOS device region and a gate of the medium voltage MOS device region, wherein the gate of the high voltage MOS device region covers the gate oxide layer;

[0021] The patterned second photoresist layer is removed.

[0022] On the other hand, an embodiment of the present application further provides an LDMOS device, including:

[0023] A substrate, the substrate at least comprising: a medium voltage MOS device region and a high voltage MOS device region, a plurality of trenches being formed in the substrate of the medium voltage MOS device region and in the substrate of the high voltage MOS device region;

[0024] An isolation material layer, wherein the isolation material layer fills the trenches of the medium voltage MOS device region and the trenches of the high voltage MOS device region to form a plurality of shallow trench isolation structures, and the isolation material layer also covers the active areas between the trenches;

[0025] A raised structure, wherein the raised structure covers a junction between the shallow trench isolation structure and the isolation material layer in the high-voltage MOS device region, and the isolation material layer between the raised structure and the shallow trench isolation structure together constitutes a gate oxide layer in the high-voltage MOS device region;

[0026] A gate material layer, wherein the gate material layer covers the shallow trench isolation structure, the protruding structure and the isolation material layer in the high voltage MOS device region, and covers the shallow trench isolation structure and the isolation material layer in the medium voltage MOS device region.

[0027] Optionally, in the LDMOS device, in the high-voltage MOS device region, the thickness of the protruding structure is 10% to 20% of the thickness of the isolation material layer finally remaining between the shallow trench isolation structures.

[0028] The technical solution of this application has at least the following advantages:

[0029] The present application provides a method for preparing an LDMOS device, by etching a partial thickness of the isolation material layer in the high-voltage MOS device area while thinning the isolation material layer in the high-voltage MOS device area to form a convex structure covering the junction position of the shallow trench isolation structure and the edge of the active area (isolation material layer), that is, retaining a certain thickness of the convex structure (isolation material layer) at the junction position of the shallow trench isolation structure and the edge of the active area, so that the thickness of the gate oxide layer in the edge area of ​​the active area is greater than the thickness of the gate oxide layer in the middle area of ​​the active area, so as to achieve the purpose of increasing the threshold voltage at the corner of the channel of the high-voltage device, reduce (make up / compensate) the difference between the threshold voltage at the middle position of the channel of the high-voltage device and the threshold voltage at the corner position of the channel, avoid the double peak phenomenon of the ID-VG curve of the high-voltage device, and also avoid the drift of the device parasitic parameters, without affecting other devices. The parasitic parameters of the device are not affected. In addition, the present application only needs to be modified by the mask to realize the process adjustment of preparing the convex structure, and the cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 is a flow chart of a method for preparing an LDMOS device according to an embodiment of the present invention;

[0032] Figure 2-Figure 9 It is a schematic diagram of the semiconductor structure in each process step of preparing an LDMOS device according to an embodiment of the present invention;

[0033] The reference numerals are described as follows:

[0034] 10-substrate, 21-groove, 22-opening, 31-shallow trench isolation structure, 32-isolation material layer of medium voltage MOS device area, 33-isolation material layer of high voltage MOS device area, 34-convex structure, 30-gate oxide layer of high voltage MOS device area, 40-first photoresist layer, 41-patterned first photoresist layer, 50-gate material layer, 51-gate of medium voltage MOS device area, 52-gate of high voltage MOS device area. DETAILED DESCRIPTION

[0035] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0037] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0038] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0039] STI (Shallow Trench Isolation) is used instead of LOCOS (Local Oxidation of Silicon) technology below 0.25 micron node. The introduction of STI will lead to the double peak problem of ID-VG curve of high voltage MOS device. Specifically, the threshold voltage at the channel corner (channel edge) is lower than the threshold voltage at the channel center. Therefore, how to reduce the threshold voltage difference between the channel center and the channel corner (channel edge) is the key to improve the double peak of ID-VG curve. T The formula is as follows:

[0040]

[0041] Among them, V T is the threshold voltage, is the work function difference between metal and semiconductor; T OX is the gate oxide electrical thickness; ε OX is the dielectric constant of the gate oxide; Q OX is the surface charge density of the gate oxide; q is the electron charge; ε s is the dielectric constant of the substrate; N AD is the doping concentration, is the substrate Fermi potential;

[0042] From the above formula, we can know that increasing the threshold voltage V T This can usually be done by increasing the doping concentration N AD and gate oxide electrical thickness T OX to achieve.

[0043] Based on the above problems, the present invention will improve the gate oxide electrical thickness T at the edge of the channel. OX To increase the threshold voltage V at the edge of the channel T , thereby reducing the threshold voltage difference between the channel center position and the channel corner (channel edge) position, the present application embodiment provides a method for preparing an LDMOS device, referring to Figure 1 , Figure 1 1 is a flow chart of a method for preparing an LDMOS device according to an embodiment of the present invention, wherein the method for preparing an LDMOS device comprises:

[0044] First, perform step S1: refer to Figure 2 , Figure 2 It is a schematic diagram of a semiconductor structure after the grooves are formed in an embodiment of the present application, and a substrate 10 is provided, wherein the substrate 10 at least includes: a medium-voltage MOS device area and a high-voltage MOS device area, and a plurality of grooves 21 are formed in the substrate 10 of the medium-voltage MOS device area and in the substrate 10 of the high-voltage MOS device area.

[0045] Then, execute step S2: refer to Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the isolation material layer is formed in an embodiment of the present application, wherein the isolation material layer is formed, and the isolation material layer fills the trenches of the medium-voltage MOS device area and the trenches of the high-voltage MOS device area to form a plurality of shallow trench isolation structures 31, and the isolation material layer also covers the active areas between the trenches to form an isolation material layer 32 of the medium-voltage MOS device area and an isolation material layer 33 of the high-voltage MOS device area.

[0046] In this embodiment, the isolation material layer is made of silicon dioxide.

[0047] In this embodiment, taking the example of preparing NMOS devices in both the medium voltage MOS device area and the high voltage MOS device area, a P-type well region is formed in the substrate between the shallow trench isolation structures 31 of the medium voltage MOS device area, and a P-type well region is also formed in the substrate between the shallow trench isolation structures 31 of the high voltage MOS device area.

[0048] Furthermore, after forming the isolation material layer (step S2) and before coating the first photoresist layer on the isolation material layer (step S3), the thickness of the isolation material layer 32 between the shallow trench isolation structures of the medium voltage MOS device area is less than the thickness of the isolation material layer 33 between the shallow trench isolation structures of the high voltage MOS device area.

[0049] Next, execute step S3: refer to Figure 4 , Figure 4 It is a schematic diagram of the semiconductor structure after the first photoresist layer is coated on the isolation material layer of an embodiment of the present application, and the first photoresist layer 40 is coated on the isolation material layer 32 of the medium voltage MOS device area, the isolation material layer 33 of the high voltage MOS device area and the shallow trench isolation structure 31.

[0050] Further, step S4 is performed: refer to Figure 5 , Figure 5 It is a schematic diagram of the semiconductor structure after forming a patterned first photoresist layer according to an embodiment of the present application. Through a specific mask, an opening pattern of the high-voltage MOS device area is defined on the first photoresist layer 40 to obtain a patterned first photoresist layer 41.

[0051] Next, execute step S5: refer to Figure 6 , Figure 6 It is a schematic diagram of the semiconductor structure after the protruding structure is formed in an embodiment of the present application, wherein the patterned first photoresist layer 41 is used as a mask to etch a portion of the thickness of the isolation material layer 32 in the medium voltage MOS device area and a portion of the thickness of the isolation material layer 33 in the high voltage MOS device area, and a portion of the thickness of the shallow trench isolation structure 31, wherein in the high voltage MOS device area, an opening 22 is formed in the isolation material layer, and the portions of the thickness of the isolation material layer 33 that are not etched on both sides of the opening 22 constitute a protruding structure 34, and the protruding structure 34 covers the boundary between the shallow trench isolation structure 31 and the isolation material layer 33 in the active area, and the protruding structure 34 and the isolation material layer 33 between the shallow trench isolation structure 31 together constitute the gate oxide layer 30 of the high voltage MOS device area.

[0052] In the high-voltage MOS device region, the thickness of the protruding structure 34 is 10% to 20% of the thickness of the isolation material layer 33 of the high-voltage MOS device region finally remaining between the shallow trench isolation structures 31 .

[0053] Further, step S6 is performed: refer to Figure 7 , Figure 7 It is a schematic diagram of the semiconductor structure after the first patterned photoresist layer is removed according to an embodiment of the present application, wherein the first patterned photoresist layer 41 is removed.

[0054] Finally, execute step S7: reference Figure 8 , Figure 8 It is a schematic diagram of the semiconductor structure after the gate material layer is formed in an embodiment of the present application, wherein a gate material layer 50 is formed, wherein the gate material layer 50 covers the shallow trench isolation structure 31, the protruding structure 34 and the isolation material layer 33 in the high-voltage MOS device area, and covers the shallow trench isolation structure 31 and the isolation material layer 32 in the medium-voltage MOS device area.

[0055] In the present application, while thinning the isolation material layer in the high-voltage MOS device area, a partial thickness of the isolation material layer is etched in the high-voltage MOS device area to form a convex structure covering the junction position of the shallow trench isolation structure and the edge of the active area (isolation material layer), that is, a convex structure (isolation material layer) of a certain thickness is retained at the junction position of the shallow trench isolation structure and the edge of the active area, so that the thickness of the gate oxide layer in the edge area of ​​the active area is greater than the thickness of the gate oxide layer in the middle area of ​​the active area, so as to achieve the purpose of improving the threshold voltage at the channel corner of the high-voltage device, reduce / make up / compensate for the difference between the threshold voltage at the middle position of the channel of the high-voltage device and the threshold voltage at the channel corner position, avoid the double peak phenomenon of the ID-VG curve of the high-voltage device, and also avoid the drift of the device parasitic parameters, without affecting other devices. The parasitic parameters of the device are not affected. In addition, the present application only needs to be modified by the mask to realize the process adjustment of preparing the convex structure, and the cost is low.

[0056] For further reference, Fig. 9 , Fig. 9 is a schematic diagram of a semiconductor structure after forming a gate of a high voltage MOS device region and a gate of a medium voltage MOS device region according to an embodiment of the present application. After forming a gate material layer 50, the method for preparing the LDMOS device may further include:

[0057] Step S8.1: coating a second photoresist layer (not shown) on the gate material layer 50;

[0058] Step S8.2: defining a gate pattern of a high voltage MOS device region and a gate pattern of a medium voltage MOS device region on the second photoresist layer to obtain a patterned second photoresist layer;

[0059] Step S8.3: using the patterned second photoresist layer as a mask, etching the gate material layer 50 of the medium voltage MOS device region and the high voltage MOS device region to obtain a gate 52 of the high voltage MOS device region and a gate 51 of the medium voltage MOS device region, wherein the gate 52 of the high voltage MOS device region covers the gate oxide layer 30; that is, the gate 52 of the high voltage MOS device region covers the protruding structure 34 and the isolation material layer 33 of the high voltage MOS device region;

[0060] Step S8.4: removing the patterned second photoresist layer.

[0061] Based on the same inventive concept, the present application embodiment also provides an LDMOS device, referring to Figure 7 , the LDMOS device comprises:

[0062] A substrate 10, the substrate at least comprising: a medium voltage MOS device region and a high voltage MOS device region, a plurality of trenches 21 are formed in the substrate 10 of the medium voltage MOS device region and in the substrate 10 of the high voltage MOS device region;

[0063] An isolation material layer, wherein the isolation material layer fills the trenches 21 of the medium voltage MOS device region and the trenches 21 of the high voltage MOS device region to form a plurality of shallow trench isolation structures 31, and the isolation material layer also covers the active area between the trenches 21, wherein the isolation material layer between the shallow trench isolation structures 31 of the medium voltage MOS device region is the isolation material layer 32 of the medium voltage MOS device region; and the isolation material layer between the shallow trench isolation structures 31 of the high voltage MOS device region is the isolation material layer 33 of the high voltage MOS device region;

[0064] A protruding structure 34, wherein the protruding structure 34 covers the boundary between the shallow trench isolation structure 31 and the isolation material layer 33 in the high-voltage MOS device region, and the protruding structure 34 and the isolation material layer 33 between the shallow trench isolation structure together constitute a gate oxide layer 30 in the high-voltage MOS device region;

[0065] A gate material layer 50, wherein the gate material layer 50 covers the shallow trench isolation structure 31, the protruding structure 34 and the isolation material layer 33 of the high voltage MOS device area, and covers the shallow trench isolation structure 34 and the isolation material layer 32 of the medium voltage MOS device area.

[0066] Preferably, in the high-voltage MOS device region, the thickness of the protruding structure 34 is 10% to 20% of the thickness of the isolation material layer 33 of the high-voltage MOS device region finally remaining between the shallow trench isolation structures 31 .

[0067] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing an LDMOS device, characterized in that: include: A substrate is provided, the substrate at least comprising: a medium voltage MOS device region and a high voltage MOS device region, a plurality of trenches are formed in the substrate of the medium voltage MOS device region and in the substrate of the high voltage MOS device region; forming an isolation material layer, wherein the isolation material layer fills the trenches of the medium voltage MOS device region and the trenches of the high voltage MOS device region to form a plurality of shallow trench isolation structures, and the isolation material layer also covers the active areas between the trenches; coating a first photoresist layer on the isolation material layer; By using a specific photomask, defining an opening pattern of a high-voltage MOS device region on the first photoresist layer to obtain a patterned first photoresist layer; Using the patterned first photoresist layer as a mask, etching a portion of the thickness of the isolation material layer and a portion of the thickness of the shallow trench isolation structure in the medium voltage MOS device area and the high voltage MOS device area, wherein in the high voltage MOS device area, an opening is formed in the isolation material layer, and the portion of the thickness of the isolation material layer that is not etched on the side of the opening constitutes a convex structure, the convex structure covers the junction position between the shallow trench isolation structure and the isolation material layer, and the isolation material layer between the convex structure and the shallow trench isolation structure together constitutes a gate oxide layer of the high voltage MOS device area; removing the patterned first photoresist layer; A gate material layer is formed, wherein the gate material layer covers the shallow trench isolation structure, the protruding structure and the isolation material layer in the high voltage MOS device region, and covers the shallow trench isolation structure and the isolation material layer in the medium voltage MOS device region.

2. The method for preparing an LDMOS device according to claim 1, characterized in that: In the high-voltage MOS device region, the thickness of the protruding structure is 10% to 20% of the thickness of the isolation material layer finally remaining between the shallow trench isolation structures.

3. The method for preparing an LDMOS device according to claim 1, characterized in that: After forming the isolation material layer and before coating the first photoresist layer on the isolation material layer, the thickness of the isolation material layer between the shallow trench isolation structures in the medium voltage MOS device area is less than the thickness of the isolation material layer between the shallow trench isolation structures in the high voltage MOS device area.

4. The method for preparing an LDMOS device according to claim 1, characterized in that: The material of the isolation material layer is silicon dioxide.

5. The method for preparing an LDMOS device according to claim 1, characterized in that: After forming the gate material layer, the method for preparing the LDMOS device further includes: coating a second photoresist layer on the gate material layer; Defining a gate pattern of a high voltage MOS device region and a gate pattern of a medium voltage MOS device region on the second photoresist layer to obtain a patterned second photoresist layer; Using the patterned second photoresist layer as a mask, etching the gate material layers of the medium voltage MOS device region and the high voltage MOS device region to obtain a gate of the high voltage MOS device region and a gate of the medium voltage MOS device region, wherein the gate of the high voltage MOS device region covers the gate oxide layer; The patterned second photoresist layer is removed.

6. An LDMOS device, characterized in that: include: A substrate, the substrate at least comprising: a medium voltage MOS device region and a high voltage MOS device region, a plurality of trenches being formed in the substrate of the medium voltage MOS device region and in the substrate of the high voltage MOS device region; An isolation material layer, wherein the isolation material layer fills the trenches of the medium voltage MOS device region and the trenches of the high voltage MOS device region to form a plurality of shallow trench isolation structures, and the isolation material layer also covers the active areas between the trenches; A raised structure, wherein the raised structure covers a junction between the shallow trench isolation structure and the isolation material layer in the high-voltage MOS device region, and the isolation material layer between the raised structure and the shallow trench isolation structure together constitutes a gate oxide layer in the high-voltage MOS device region; A gate material layer, wherein the gate material layer covers the shallow trench isolation structure, the protruding structure and the isolation material layer in the high voltage MOS device region, and covers the shallow trench isolation structure and the isolation material layer in the medium voltage MOS device region.

7. The LDMOS device according to claim 6, characterized in that: In the high-voltage MOS device region, the thickness of the protruding structure is 10% to 20% of the thickness of the isolation material layer finally remaining between the shallow trench isolation structures.

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