Semiconductor device structure, forming method and radio frequency switch

Abstract

The application relates to a semiconductor device structure, a forming method and a radio frequency switch, the semiconductor device structure comprising a substrate, a gate structure located on the substrate, a first doped region, a second doped region, a third doped region and a fourth doped region located in the substrate, the first doped region and the second doped region each comprising at least two sub-doped regions distributed side by side, and the doping concentration of the sub-doped region close to the gate structure in the first doped region and / or the second doped region is smaller than the doping concentration of the sub-doped region far from the gate structure. In the embodiment of the application, while keeping the resistance value of the on-state resistance of the switch device unchanged or smaller, the doping concentration of the sub-doped regions close to the channel, such as the first sub-doped region and the third sub-doped region, is lower, and it is difficult to form a band-to-band tunneling current with the well region or the formed band-to-band tunneling current is lower, so that the requirement of high breakdown voltage can be met.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device structure, a method of forming it, and a radio frequency switch. Background Technology

[0002] Radio frequency (RF) switches are analog devices widely used in the radio frequency (RF) field. Their purpose is to switch RF signals, typically used in RF front-end modules, with applications including mobile phones, WiFi, and Bluetooth. Common uses include antenna switches, band switches, and tuners. Because they function as switches for RF signals, which usually have a certain power, RF switches must meet specific breakdown voltage requirements.

[0003] As a type of switch, an RF switch has two operating states: on and off. In the on state, an RF switch can be equivalent to a low-resistance metal line. In this state, the requirement is to have the lowest possible on-resistance to minimize signal loss during RF transmission. In the off state, an RF switch can be equivalent to a capacitor. In this state, the requirements are to have the lowest possible off-state capacitance to minimize RF signal leakage, while also meeting a certain breakdown voltage (BV) to prevent the device from breaking down and failing to maintain the off state under high-power RF signals. Based on these requirements, RF switches are typically manufactured using 2.5V NMOS transistors. The performance requirements for RF switches include high breakdown voltage, low on-resistance, low off-state capacitance, and a small footprint to achieve the same performance.

[0004] However, in actual fabrication, once the device architecture is determined, one possible method to improve the device's breakdown voltage (BV) is through lightly doped drain (LDD) technology and adjustment of ion implantation (IMP). In this case, a high breakdown voltage and low on-resistance are a trade-off. While adjusting the implantation amount through LDD to increase the breakdown voltage, it also increases the on-resistance. Therefore, how to improve the device's BV without increasing the on-resistance is one of the key factors in enhancing the competitiveness of switching devices and remains a problem to be solved. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a semiconductor device structure, a method for forming the device, and a radio frequency switch.

[0006] In a first aspect, embodiments of this application disclose a semiconductor device structure, comprising: a substrate; a gate structure located on the substrate; a first doped region, a second doped region, a third doped region, and a fourth doped region located within the substrate; the first doped region, the second doped region, the third doped region, and the fourth doped region all having the same conductivity type; the first doped region and the third doped region are connected and located on a first side of the gate structure; the first doped region is closer to the gate structure than the third doped region; the doping concentration of the first doped region is less than the doping concentration of the third doped region; the second doped region and the fourth doped region are connected and located on a second side of the gate structure; the second doped region is closer to the gate structure than the fourth doped region; the doping concentration of the second doped region is less than the doping concentration of the fourth doped region; both the first doped region and the second doped region include at least two sub-doped regions arranged side by side; in the first doped region and / or the second doped region, the doping concentration of the sub-doped region closer to the gate structure is less than the doping concentration of the sub-doped region farther from the gate structure.

[0007] In a second aspect, embodiments of this application disclose a method for forming a semiconductor device structure. The method includes: providing a substrate; the substrate including a region for forming a gate structure; forming a first doped region and a second doped region within the substrate; the first doped region being located on a first side of the region for forming the gate structure; the second doped region being located on a second side of the region for forming the gate structure; wherein the first doped region and the second doped region each include at least two sub-doped regions arranged side by side; in the first doped region and / or the second doped region, the doping concentration of the sub-doped region closer to the region for forming the gate structure is less than the doping concentration of the sub-doped region farther from the region for forming the gate structure; forming a third doped region and a fourth doped region within the substrate; the third doped region being located on the first side of the region for forming the gate structure; the fourth doped region being located on the second side of the region for forming the gate structure; the first doped region and the third doped region being connected; the first doped region being closer to the region for forming the gate structure than the third doped region; the doping concentration of the first doped region being less than the doping concentration of the third doped region; the second doped region and the fourth doped region being connected; the second doped region being closer to the region for forming the gate structure than the fourth doped region; the doping concentration of the second doped region being less than the doping concentration of the fourth doped region.

[0008] Thirdly, embodiments of this application disclose a radio frequency switch, which includes the semiconductor device structure described above.

[0009] Fourthly, embodiments of this application disclose an electronic device, which includes the semiconductor device structure described above.

[0010] The technical solution provided in this application has the following technical effects:

[0011] A substrate, a gate structure on the substrate, and a first doped region, a second doped region, a third doped region, and a fourth doped region within the substrate. The first, second, third, and fourth doped regions have the same conductivity type. The first and third doped regions are connected and located on the first side of the gate structure. The first doped region is closer to the gate structure than the third doped region, and its doping concentration is lower than that of the third doped region. The second and fourth doped regions are connected and located on the second side of the gate structure. The second doped region is closer to the gate structure than the fourth doped region, and its doping concentration is lower than that of the fourth doped region. Both the first and second doped regions include at least two sub-doped regions arranged side by side. In the first and / or second doped regions, the doping concentration of the sub-doped region closer to the gate structure is lower than that of the sub-doped region farther from the gate structure. In this embodiment, while keeping the on-state resistance of the switching device constant or decreasing, the sub-doped regions adjacent to the channel, such as the first and third sub-doped regions, have low doping concentrations and are difficult to form band tunneling current with the well region, or the formed band tunneling current is low. Therefore, the requirement for high breakdown voltage can be achieved. Attached Figure Description

[0012] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 1 ;

[0014] Figure 2 This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 2 ;

[0015] Figure 3 This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 3 ;

[0016] Figure 4 This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 4 ;

[0017] Figure 5 This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 5 ;

[0018] Figure 6This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 6 ;

[0019] Figure 7 This is a schematic diagram of a method for forming a semiconductor device structure provided in an embodiment of this application. Figure 1 ;

[0020] Figure 8 This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 7 ;

[0021] Figure 9 This is a schematic diagram of a method for forming a semiconductor device structure provided in an embodiment of this application. Figure 2 ;

[0022] Figures 10-15 This is a schematic diagram of the formation process of a semiconductor device structure provided in an embodiment of this application;

[0023] Figure 16 This is a schematic diagram of a method for forming a semiconductor device structure provided in an embodiment of this application. Figure 3 ;

[0024] Figures 17-19 This is a schematic diagram of the formation process of another semiconductor device structure provided in the embodiments of this application;

[0025] Figures 20-22 This is a schematic diagram of the formation process of the LDD region in a semiconductor device structure provided in an embodiment of this application;

[0026] Figures 23-25 This is a schematic diagram of the formation process of the LDD region in another semiconductor device structure provided in this application embodiment. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0028] It should be noted that the term "an embodiment" or "embodiment" in the specification of the embodiments of this application refers to a specific feature, structure, or characteristic that can be included in at least one implementation of this application. It should be understood that in the specification, claims, and accompanying drawings of the embodiments of this application, the terms "upper," "lower," "top," "bottom," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, in the description of this embodiment, unless otherwise stated, "a plurality of" means two or more. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, or product that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0029] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0030] To make the objectives, technical solutions, and advantages disclosed in the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of this application and are not intended to limit the embodiments of this application.

[0031] In this embodiment of the application, the threshold voltage V t This refers to the gate voltage when a conductive channel is formed between the source and drain of a MOSFET. Subthreshold current refers to the gate voltage V0 of the MOSFET. G Below the threshold voltage V t This refers to the minute leakage current between the source and drain when the device is in a subthreshold state.

[0032] In this embodiment, under the ideal current-voltage characteristics of a MOSFET, when the gate voltage V G Less than the threshold voltage V t The leakage current is 0. However, in practice, when the gate voltage V... G Less than the threshold voltage V t When a MOSFET is in a weak inversion state (different from the strong inversion state when it is turned on), this region is called the subthreshold region. When a MOSFET is operating in the subthreshold region, although there are charge carriers in the conductive channel, the concentration is low, so the leakage current is very small, but it is not actually zero. This leakage current is called the subthreshold current.

[0033] In one alternative embodiment, the RF switch is fabricated using a 2.5V NMOS device. However, to ensure a sufficiently low on-state resistance, the gate length is often below 0.16µm, far lower than the minimum gate length typically used for 2.5V devices. This results in a very high off-state current Ioff when both the gate voltage Vg and substrate voltage Vb are 0V, making it impossible to achieve the desired off-state function for the RF signal. Furthermore, because the RF voltage swing couples to the device's gate, the gate voltage is higher than 0V during actual operation, leading to even greater leakage current. Therefore, in practical applications, the gate voltage Vg and substrate voltage Vb corresponding to the off-state switch are typically biased at -2.5V DC to reduce the off-state current Ioff. However, when the gate DC bias is set to -2.5V, the switch is in an accumulation state. When using LDD technology, if the LDD implantation concentration is too high, significant gate-induced drain leakage (GIDL) current will be generated between the P-type accumulation layer of the channel and the high-concentration N-doped layer of the LDD due to band-to-band tunneling. This will result in a lower breakdown voltage BV, which does not meet the requirements of high breakdown voltage and low on-resistance for RF switches.

[0034] Based on this Figure 1 This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 1 ,like Figure 1 As shown, the semiconductor device structure includes:

[0035] The substrate 10 includes a gate structure 11 located on the substrate 10 and a first doped region 12, a second doped region 13, a third doped region 14, and a fourth doped region 15 located within the substrate 10. The first doped region 12, the second doped region 13, the third doped region 14, and the fourth doped region 15 all have the same conductivity type.

[0036] The first doped region 12 and the third doped region 14 are connected and located on the first side of the gate structure 11. The first doped region 12 is closer to the gate structure 11 than the third doped region 14. The doping concentration of the first doped region 12 is less than that of the third doped region 14. The second doped region 13 and the fourth doped region 15 are connected and located on the second side of the gate structure 11. The second doped region 13 is closer to the gate structure 11 than the fourth doped region 15. The doping concentration of the second doped region 13 is less than that of the fourth doped region 15.

[0037] The first doped region 12 and the second doped region 13 each include at least two sub-doped regions arranged side by side. In the first doped region 12 and / or the second doped region 13, the doping concentration of the sub-doped region closer to the gate structure 11 is less than the doping concentration of the sub-doped region farther away from the gate structure 11.

[0038] like Figure 1 As shown, the first doped region 12 may include two sub-doped regions, such as a first sub-doped region 121 near the gate structure 11 and a second sub-doped region 122 away from the gate structure 11, wherein the doping concentration of the first sub-doped region 121 is less than the doping concentration of the second sub-doped region 122. The second doped region 13 may include two sub-doped regions, such as a third sub-doped region 131 near the gate structure 11 and a fourth doped region 132 away from the gate structure 11, wherein the doping concentration of the third sub-doped region 131 is less than the doping concentration of the fourth sub-doped region 132.

[0039] In this embodiment of the application, the substrate 10 can be an SOI (Silicon-On-Insulator) substrate.

[0040] Since the RF switch fabricated using the semiconductor device structure involved in this application embodiment employs a MOS device, such as an NMOS device or a PMOS device, in some possible embodiments, such as an NMOS device, the conductivity type of the well region of substrate 10 is different from that of the third doped region 14 (fourth doped region 15, first doped region 12, and second doped region 13). The dopant injected into the well region of substrate 10 is a P-type impurity, while the dopant injected into the first doped region 12, second doped region 13, third doped region 14, and fourth doped region 15 in the well region is an N-type impurity. Alternatively, in a PMOS device, the conductivity type of the well region of substrate 10 is different from that of the third doped region 14 (fourth doped region 15, first doped region 12, and second doped region 13). The dopant injected into the well region of substrate 10 is an N-type impurity, while the dopant injected into the first doped region 12, second doped region 13, third doped region 14, and fourth doped region 15 in the well region is a P-type impurity. The following explanation will be based on NMOS devices. For examples of PMOS devices, please refer to the NMOS device documentation, which will not be repeated here.

[0041] Optionally, the gate structure 11 includes a gate oxide layer and a polysilicon gate, wherein the gate oxide layer is located between the substrate 10 and the polysilicon gate. The third doped region 14 and the fourth doped region 15 can form the source and drain, respectively, and the first doped region 12 and the second doped region 13 can be considered as LDD regions.

[0042] The above Figure 1 This refers to the structure of a semiconductor device in its non-operating state. Figure 2 This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 2 , which is the structure of a semiconductor device in its working state, such as Figure 2 As shown, in Figure 1 The schematic diagram also includes a channel 16 shown in the substrate 10 below the gate structure 11. In other words, the first doped region 12 and the third doped region 14 are connected, and the first doped region 12 and the third doped region 14 are located on the first side of the channel 16, with the first doped region 12 being closer to the channel 16 than the third doped region 14. The second doped region 13 and the fourth doped region 15 are connected, and the second doped region 13 and the fourth doped region 15 are located on the second side of the channel 16, with the second doped region 13 being closer to the channel 16 than the fourth doped region 15.

[0043] As can be seen from the above structure, the two sub-doped regions included in the first doped region 12 or the second doped region 13 can be regarded as a resistor formed by two sub-resistors connected in series. The doping concentration of the sub-doped region closer to the channel 16 is lower than that of the sub-doped region farther from the channel 16. In this case, the resistance formed by the two sub-resistors connected in series can be the same as or even lower than the resistance formed by the LDD region with the same doping concentration, thereby keeping the on-state resistance of the switching device unchanged or decreasing. At the same time, since the doping concentration of the sub-doped regions adjacent to the channel 16, such as the first sub-doped region 121 and the third sub-doped region 131, is low, it is difficult to form a band tunneling current with the well region, or the formed band tunneling current is low. Therefore, the requirement of high breakdown voltage can be achieved.

[0044] In this embodiment of the application, the first doped region 12 includes at least two sub-doped regions with the same area size, and the second doped region 13 includes at least two sub-doped regions with the same area size.

[0045] In one alternative embodiment, the region size refers to the distance, or length, of the sub-doped region in a first direction. This first direction is parallel to the substrate and is the direction in which the gate extends towards the doped region. Figure 3 This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 3 ,like Figure 3 As shown, the length L2 of the first sub-doped region 121 and the length L1 of the second sub-doped region 122 included in the first doped region 12 are the same. Similarly, the lengths of the third sub-doped region 131 and the fourth sub-doped region 132 included in the second doped region 13 are the same.

[0046] In another alternative embodiment, the region size refers to the distance of the sub-doped region in a second direction, also known as the thickness, where the second direction is perpendicular to the substrate, and the first direction is perpendicular to the second direction. Figure 3 As shown, the thickness of the first sub-doped region 121 and the second sub-doped region 122 included in the first doped region 12 are the same. Similarly, the thickness of the third sub-doped region 131 and the fourth sub-doped region 132 included in the second doped region 13 are the same.

[0047] In this embodiment, the first doped region 12 includes at least two sub-doped regions, some of which are of different sizes. Similarly, the second doped region 13 includes at least two sub-doped regions, some of which are of different sizes.

[0048] In an alternative embodiment, the region size refers to the distance in a first direction of the sub-doped region, also known as the length. Figure 4 This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 4 ,like Figure 4As shown, in the at least two sub-doped regions included in the first doped region 12, the region size of the sub-doped region with lower doping concentration is larger than the region size of the sub-doped region with higher doping concentration; that is, the length of the first sub-doped region 121 is greater than the length of the second sub-doped region 122. Similarly, in the at least two sub-doped regions included in the second doped region 13, the region size of the sub-doped region with lower doping concentration is larger than the region size of the sub-doped region with higher doping concentration; that is, the length of the third sub-doped region 131 is greater than the length of the fourth sub-doped region 132.

[0049] Alternatively, in the at least two sub-doped regions included in the first doped region 12, the region size of the sub-doped region with lower doping concentration is smaller than the region size of the sub-doped region with higher doping concentration, that is, the length of the first sub-doped region 121 is smaller than the length of the second sub-doped region 122. Similarly, in the at least two sub-doped regions included in the second doped region 13, the region size of the sub-doped region with lower doping concentration is smaller than the region size of the sub-doped region with higher doping concentration, that is, the length of the third sub-doped region 131 is smaller than the length of the fourth sub-doped region 132.

[0050] Alternatively, in the at least two sub-doped regions included in the first doped region 12, the region size of the sub-doped region with lower doping concentration is larger than the region size of the sub-doped region with higher doping concentration, that is, the length of the first sub-doped region 121 is greater than the length of the second sub-doped region 122. In the at least two sub-doped regions included in the second doped region 13, the region size of the sub-doped region with lower doping concentration is smaller than the region size of the sub-doped region with higher doping concentration, that is, the length of the third sub-doped region 131 is less than the length of the fourth sub-doped region 132.

[0051] In another alternative embodiment, the region size refers to the distance in the second direction of the sub-doped region, also known as the thickness. Among the at least two sub-doped regions included in the first doped region 12, the region size of the sub-doped region with the lower doping concentration is larger than the region size of the sub-doped region with the higher doping concentration; that is, the thickness of the first sub-doped region 121 is greater than the thickness of the second sub-doped region 122. Similarly, among the at least two sub-doped regions included in the second doped region 13, the region size of the sub-doped region with the lower doping concentration is larger than the region size of the sub-doped region with the higher doping concentration; that is, the thickness of the third sub-doped region 131 is greater than the thickness of the fourth sub-doped region 132.

[0052] Alternatively, in the at least two sub-doped regions included in the first doped region 12, the area size of the sub-doped region with lower doping concentration is smaller than the area size of the sub-doped region with higher doping concentration, that is, the thickness of the first sub-doped region 121 is smaller than the thickness of the second sub-doped region 122. Similarly, in the at least two sub-doped regions included in the second doped region 13, the area size of the sub-doped region with lower doping concentration is smaller than the area size of the sub-doped region with higher doping concentration, that is, the thickness of the third sub-doped region 131 is smaller than the thickness of the fourth sub-doped region 132.

[0053] Alternatively, in the at least two sub-doped regions included in the first doped region 12, the region size of the sub-doped region with lower doping concentration is larger than the region size of the sub-doped region with higher doping concentration, that is, the thickness of the first sub-doped region 121 is greater than the thickness of the second sub-doped region 122. In the at least two sub-doped regions included in the second doped region 13, the region size of the sub-doped region with lower doping concentration is smaller than the region size of the sub-doped region with higher doping concentration, that is, the thickness of the third sub-doped region 131 is less than the thickness of the fourth sub-doped region 132.

[0054] In this embodiment, to prepare the first doped region 12 and the second doped region 13, during ion implantation, efforts are made to avoid implanting the first doped region 12 and the second doped region 13 below the gate structure 11 in the substrate 10. The semiconductor device structure also includes two first barriers located on the substrate 10. Similarly, to prepare the third doped region 14 and the fourth doped region 15, during ion implantation, efforts are made to avoid implanting the third doped region 14 and the fourth doped region 15 into the first doped region 12 and the second doped region 13. The semiconductor device structure also includes two second barriers located on the substrate 10.

[0055] Figure 5 This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 5 ,like Figure 5 As shown, it includes a first retaining wall 17 and a second retaining wall 18.

[0056] Optional, such as Figure 5 As shown, two first barriers are located on the first side and the second side of the gate structure 11, respectively, and the two first barriers are in contact with the side surfaces of the first side and the second side of the gate structure 11, respectively. Optionally, the side surface of the first side of one of the two first barriers 171 is in contact with the side surface of the first side of the gate structure 11, and the side surface of the first side of the other of the two first barriers 172 is in contact with the side surface of the second side of the gate structure 11.

[0057] like Figure 5 As shown, two second barrier walls are located on opposite sides of the gate structure 11 and are respectively in contact with the side of the first barrier wall. Each first barrier wall is located between each second barrier wall and the gate structure 11; that is, each first barrier wall is located between the second barrier wall it is in contact with and the gate structure. The two second barrier walls respectively shield the first doped region 12 and the second doped region 13. Optionally, the side of the second side of one of the first barrier walls 171 is in contact with one of the second barrier walls 181, and the side of the second side of the other first barrier wall 172 is in contact with the other second barrier wall 182.

[0058] Optionally, the first doped region 12 and the second doped region 13 can both be formed before the gate structure 11 is formed. Optionally, the first doped region 12 and the second doped region 13 can both be formed after the gate structure 11 and the two first barriers, and before the two second barriers are formed.

[0059] In the embodiments of this application, the first doped region 12 and / or the second doped region 13 may include at least two sub-doped regions in various ways.

[0060] In some possible embodiments, each of the at least two sub-doped regions included in the first doped region 12 and / or the second doped region 13 is formed by a single round of doping. Taking the first doped region 12 as an example, the first sub-doped region 121 can be formed first, followed by the second sub-doped region 122, thus obtaining the first doped region 12. Alternatively, the second sub-doped region 122 can be formed first, followed by the first sub-doped region 121, thus obtaining the first doped region 12.

[0061] In other possible embodiments, each of the at least two sub-doped regions included in the first doped region 12 and / or the second doped region 13 is formed by one or more rounds of doping. Taking the first doped region 12 as an example, each sub-doped region is formed by one or more rounds of doping, wherein the number of doping rounds of the sub-doped region with lower doping concentration is less than the number of doping rounds of the sub-doped region with higher doping concentration.

[0062] In this embodiment, since the fabrication process of the semiconductor device structure is self-aligned, the area of ​​the first overlapping region corresponding to the first doped region 12 and the gate structure 11 is less than or equal to a preset value, and the area of ​​the second overlapping region corresponding to the second doped region 13 and the gate structure 11 is less than or equal to a preset value. Optionally, the preset value can be zero. That is, ions in the first doped region 12 and the second doped region 13 will not be implanted into the substrate 10 below the gate.

[0063] The above embodiment is described with two sub-doped regions contained in the first doped region 12 and the second doped region 13. In practical applications, in order to meet the requirements of high breakdown voltage and low on-resistance of the switching device, the number of sub-doped regions contained in the first doped region 12 and the second doped region 13 can be three or more.

[0064] Figure 6 This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 6 ,like Figure 6As shown, the first doped region 12 includes three sub-doped regions, wherein the doping concentration of the first sub-doped region 121 is less than the doping concentration of the second sub-doped region 122, and the doping concentration of the second sub-doped region 122 is less than the doping concentration of the fifth sub-doped region 123. The second doped region 13 includes three sub-doped regions, wherein the doping concentration of the third sub-doped region 131 is less than the doping concentration of the fourth sub-doped region 132, and the doping concentration of the fourth sub-doped region 132 is less than the doping concentration of the sixth sub-doped region 133.

[0065] Optionally, in some alternative embodiments, the number of sub-doped regions in the first doped region 12 and the second doped region 13 is asymmetric, for example, the first doped region 12 contains two sub-doped regions and the second doped region 13 contains three sub-doped regions.

[0066] Figure 7 This is a schematic diagram of a method for forming a semiconductor device structure according to an exemplary embodiment. Figure 1 It should be noted that this specification provides the operational steps of the methods described in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operational steps may be included. The order of steps listed in the embodiments is merely one possible execution order among many steps and does not represent the only execution order. In actual system or product execution, the methods shown in the embodiments or drawings can be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment). Specifically, as shown in the embodiments or drawings... Figure 7 As shown, this flowchart includes at least the following steps S701-S705:

[0067] In step S701, a substrate is provided; the substrate includes a region on which a gate structure is formed.

[0068] Optionally, the substrate includes a well region, on which a region forming a gate structure is included.

[0069] Figure 8 This is a schematic diagram of a semiconductor device structure provided in an embodiment of this application. Figure 7 ,like Figure 8 As shown, the substrate 10 includes a support substrate 101, a buried oxide layer 102 on the support substrate 101, a well region 103, and shallow trench isolation 19 located on both sides of the well region.

[0070] In step S703, a first doped region and a second doped region are formed in the substrate; the first doped region is located on the first side of the region where the gate structure is formed; the second doped region is located on the second side of the region where the gate structure is formed; wherein, both the first doped region and the second doped region include at least two sub-doped regions distributed side by side; in the first doped region and / or the second doped region, the doping concentration of the sub-doped region closer to the region where the gate structure is formed is less than the doping concentration of the sub-doped region farther away from the region where the gate structure is formed.

[0071] In step S705, a third doped region and a fourth doped region are formed in the substrate; the third doped region is located on the first side of the region where the gate structure is formed; the fourth doped region is located on the second side of the region where the gate structure is formed; the first doped region and the third doped region are connected; the first doped region is closer to the region where the gate structure is formed than the third doped region; the doping concentration of the first doped region is less than the doping concentration of the third doped region; the second doped region and the fourth doped region are connected; the second doped region is closer to the region where the gate structure is formed than the fourth doped region; the doping concentration of the second doped region is less than the doping concentration of the fourth doped region.

[0072] In this embodiment, a first doped region and a second doped region are first formed in the well region within the substrate, and then a third doped region and a fourth doped region are formed in the well region within the substrate.

[0073] In this embodiment of the application, the gate structure can be formed before or after the formation of the first doped region and the second doped region.

[0074] First embodiment: The gate structure can be formed before the first doped region and the second doped region are formed.

[0075] Figure 9 This is a schematic diagram of a method for forming a semiconductor device structure according to an exemplary embodiment. Figure 2 , specifically Figure 9 As shown, it includes:

[0076] In step S901, a substrate is provided; the substrate includes a region on which a gate structure is formed.

[0077] Figure 10 This is a schematic diagram illustrating the formation process of a semiconductor device structure according to an exemplary embodiment. The schematic diagram mainly includes a substrate 10, which includes a supporting substrate 101, a buried oxide layer 102 on the supporting substrate 101, a well region 103, and shallow trench isolation 19 located on both sides of the well region 103. Optionally, this is a schematic diagram illustrating the formation process of the semiconductor device structure. Figure 1 For the schematic diagram of the structure formation, please refer to the fabrication process of NMOS or PMOS, which will not be repeated here.

[0078] In step S903, a gate structure is formed on the substrate, and the gate structure is located in the region where the gate structure is formed.

[0079] exist Figure 10 A gate structure 11 can be formed on the substrate 10 shown. Figure 11This is a schematic diagram illustrating the formation process of a semiconductor device structure according to an exemplary embodiment. The gate structure 11 includes a gate oxide layer and a polysilicon gate, wherein the gate oxide layer is located between the substrate 10 and the polysilicon gate. Optionally, the gate oxide layer can be formed first, followed by the formation of the polysilicon gate on the gate oxide layer. Subsequently, two first barriers 17 are formed on both sides of the gate structure 11. The two first barriers 17 are used to prevent ions from being implanted under the gate structure 11 in the substrate 10 during the formation of the first doped region 12 and the second doped region 13.

[0080] exist Figure 11 Based on the structure shown, photoresist can be formed to prepare for ion implantation of the first doped region 12 and the second doped region 13. Figure 12 This is a schematic diagram illustrating the formation process of a semiconductor device structure according to an exemplary embodiment, such as... Figure 12 As shown, photoresist is formed above the third doped region 14 and the fourth doped region 15 to prevent ion implantation into other regions during the first doped region 12 and the second doped region 13.

[0081] In step S905, a first doped region and a second doped region are formed in the substrate; the first doped region is located on the first side of the gate structure; the second doped region is located on the second side of the gate structure; wherein, both the first doped region and the second doped region include at least two sub-doped regions distributed side by side; in the first doped region and / or the second doped region, the doping concentration of the sub-doped region closer to the gate structure is less than the doping concentration of the sub-doped region farther from the gate structure.

[0082] Figure 13 This is a schematic diagram illustrating the formation process of a semiconductor device structure according to an exemplary embodiment. Figure 12 Based on the structure shown, a first doped region 12 and a second doped region 13 can be formed in the substrate 10 by light ion implantation.

[0083] In step S907, a third doped region and a fourth doped region are formed in the substrate; the third doped region is located on the first side of the gate structure; the fourth doped region is located on the second side of the gate structure; the first doped region and the third doped region are connected; the first doped region is closer to the gate structure than the third doped region; the doping concentration of the first doped region is less than the doping concentration of the third doped region; the second doped region and the fourth doped region are connected; the second doped region is closer to the gate structure than the fourth doped region; the doping concentration of the second doped region is less than the doping concentration of the fourth doped region.

[0084] Figure 14 This is a schematic diagram illustrating the formation process of a semiconductor device structure according to an exemplary embodiment. Figure 13Based on the structure shown, two second barriers 18 can be formed to prevent ions from being implanted into the first doped region 12 and the second doped region 13 in the substrate 10 during the formation of the third doped region 14 and the fourth doped region 15 by ion implantation.

[0085] Figure 15 This is a schematic diagram illustrating the formation process of a semiconductor device structure according to an exemplary embodiment. Figure 14 Based on the structure shown, the photoresist on the substrate 10 can be removed, and a third doped region 14 and a fourth doped region 15 can be formed in the substrate 10 by ion reimplantation. The third doped region 14 and the fourth doped region 15 can form the source and drain, respectively, and the first doped region 12 and the second doped region 13 can be considered as LDD regions.

[0086] Second embodiment: The gate structure can be formed after the formation of the first doped region and the second doped region, but before the formation of the third doped region and the fourth doped region.

[0087] Figure 16 This is a schematic diagram of a method for forming a semiconductor device structure according to an exemplary embodiment. Figure 3 , specifically Figure 16 As shown, it includes:

[0088] In step S1601, a substrate is provided; the substrate includes a region on which a gate structure is formed.

[0089] like Figure 10 As shown in the schematic diagram, the structure mainly includes a substrate 10, which includes a supporting substrate 101, a buried oxide layer 102 on the supporting substrate 101, a well region 103, and shallow trench isolation 19 located on both sides of the well region. Optionally, a schematic diagram of the semiconductor device structure formation process is also provided. Figure 1 For the schematic diagram of the structure formation, please refer to the fabrication process of NMOS or PMOS, which will not be repeated here.

[0090] In step S1603, a first doped region and a second doped region are formed in the substrate; the first doped region is located on the first side of the region where the gate structure is formed; the second doped region is located on the second side of the region where the gate structure is formed; wherein, both the first doped region and the second doped region include at least two sub-doped regions distributed side by side; in the first doped region and / or the second doped region, the doping concentration of the sub-doped region closer to the region where the gate structure is formed is less than the doping concentration of the sub-doped region farther from the region where the gate structure is formed.

[0091] exist Figure 10 Based on the structure shown, photoresist can be formed. Figure 17This is a schematic diagram of the formation process of another semiconductor device structure according to an exemplary embodiment. Photoresist is formed in the region where the gate structure 11 is formed, above the third doped region 14 and above the fourth doped region 15, so that when ions are implanted into the first doped region 12 and the second doped region 13, implantation into other regions is prevented.

[0092] Figure 18 This is a schematic diagram illustrating the formation process of another semiconductor device structure according to an exemplary embodiment. Figure 17 Based on the structure shown, such as Figure 18 As shown, a first doped region 12 and a second doped region 13 can be formed in the substrate 10 by ion light implantation.

[0093] In step S1605, a gate structure is formed on the substrate, and the gate structure is located in the region where the gate structure is formed.

[0094] Figure 19 This is a schematic diagram illustrating the formation process of another semiconductor device structure according to an exemplary embodiment. Figure 18 Based on the structure shown, such as Figure 19 As shown, the photoresist in the region forming the gate structure 11 is removed, a gate oxide layer is formed first, and then a polysilicon gate is formed on the gate oxide layer. Subsequently, two first barriers 17 are formed on both sides of the gate structure 11. The two first barriers 17 are used to prevent ions from being implanted under the gate structure 11 in the substrate 10 during the formation of the first doped region 12 and the second doped region 13 by ion implantation.

[0095] In step S1607, a third doped region and a fourth doped region are formed in the substrate; the third doped region is located on the first side of the region where the gate structure is formed; the fourth doped region is located on the second side of the region where the gate structure is formed; the first doped region and the third doped region are connected; the first doped region is closer to the region where the gate structure is formed than the third doped region; the doping concentration of the first doped region is less than the doping concentration of the third doped region; the second doped region and the fourth doped region are connected; the second doped region is closer to the region where the gate structure is formed than the fourth doped region; the doping concentration of the second doped region is less than the doping concentration of the fourth doped region.

[0096] exist Figure 19 Based on the structure shown, it is possible to... Figure 14 As shown, two second barriers 18 can be formed to prevent ions from being implanted into the first doped region 12 and the second doped region 13 in the substrate 10 during the formation of the third doped region 14 and the fourth doped region 15. Subsequently, it can be done as follows... Figure 15As shown, the photoresist on the substrate 10 is removed, and a third doped region 14 and a fourth doped region 15 are formed in the substrate 10 by ion reimplantation. The third doped region 14 and the fourth doped region 15 can form the source and drain, respectively, and the first doped region 12 and the second doped region 13 can be considered as LDD regions.

[0097] The following describes step S905 in the two formation processes described above. Figure 12 Afterwards) or step S1603 Figure 17 The following describes the formation method of the first doped region 12 and the second doped region 13, assuming that the first doped region 12 and the second doped region 13 include two symmetrical sub-doped regions. Figure 17 Let's take an example to illustrate. Similarly, we can see that the first doped region 12 and the second doped region 13 consist of two symmetrical sub-doped regions combined. Figure 12 The specific implementation examples are not described here.

[0098] In the first embodiment, each sub-doped region in the first doped region 12 and the second doped region 13 is formed by one round of doping.

[0099] Optionally, if both the first doped region 12 and the second doped region 13 include two sub-doped regions, ions of a first concentration are implanted into the first preset region and the second preset region to form a first sub-doped region 121 in the first doped region 12 and a third sub-doped region 131 in the second doped region 13.

[0100] Figure 20 This is a schematic diagram illustrating the formation process of an LDD region in a semiconductor device structure according to an exemplary embodiment. Figure 17 Based on this, firstly, photoresist can be formed above the third preset region and the fourth preset region, and then ions of the first concentration can be implanted into the first preset region and the second preset region to form the first sub-doped region 121 in the first doped region 12 and the third sub-doped region 131 in the second doped region 13.

[0101] Figure 21 This is a schematic diagram illustrating the formation process of an LDD region in a semiconductor device structure according to an exemplary embodiment. Figure 20 Based on this, photoresist can be formed above the first sub-doped region 121 within the first doped region 12 and the third sub-doped region 131 within the second doped region 13, and the photoresist above the third preset region and the fourth preset region can be removed.

[0102] Figure 22 This is a schematic diagram illustrating the formation process of an LDD region in a semiconductor device structure according to an exemplary embodiment. Figure 21Based on this, ions of a second concentration can be implanted into the third and fourth preset regions to form a second sub-doped region 122 within the first doped region 12 and a fourth sub-doped region 132 within the second doped region 13, wherein the first concentration is less than the second concentration. Since the combination of the first and third preset regions corresponds to the first doped region 12, and the combination of the second and fourth preset regions corresponds to the second doped region 13, the first doped region 12 and the second doped region 13 can be obtained.

[0103] In the second embodiment, each sub-doped region in the first doped region 12 and the second doped region 13 is formed by one round of doping or multiple rounds of doping.

[0104] Figure 23 This is a schematic diagram illustrating the formation process of the LDD region in another semiconductor device structure according to an exemplary embodiment. Optionally, in Figure 17 Based on this, when both the first doped region 12 and the second doped region 13 include two sub-doped regions, such as Figure 23 As shown, ions of a first concentration are implanted into the first region corresponding to the first doped region 12 and the second region corresponding to the second doped region 13.

[0105] Figure 24 This is a schematic diagram illustrating the formation process of the LDD region in another semiconductor device structure according to an exemplary embodiment. Figure 24 Based on this, photoresist is formed on the non-third region in the first region and the non-fourth region in the second region.

[0106] Figure 25 This is a schematic diagram illustrating the formation process of the LDD region in another semiconductor device structure according to an exemplary embodiment. Figure 25 Based on this, ions of a second concentration are implanted into the third region contained in the first region and the fourth region contained in the second region to form the first sub-doped region 121 and the second sub-doped region 122 included in the first doped region 12, and the third sub-doped region 131 and the fourth sub-doped region 132 included in the second doped region 13.

[0107] Wherein, the first sub-doped region 121 in the first doped region 12 is the non-third region after ion implantation in the first region, the second sub-doped region 122 in the first doped region 12 is the third region after ion implantation in the first region, the third sub-doped region 131 in the second doped region 13 is the non-fourth region after ion implantation in the second region, and the fourth sub-doped region 132 in the second doped region 13 is the fourth region after ion implantation in the second region.

[0108] In this embodiment, the process of forming a semiconductor device structure (including materials, temperature, thickness, etc.) can refer to the process of forming a CMOS transistor (NMOS transistor or PMOS transistor) in the prior art, and will not be described again here.

[0109] It should be noted that the methods and structural embodiments provided above belong to the same concept, and their specific implementation process can be found in the structural embodiments, which will not be repeated here.

[0110] Accordingly, this application also provides a radio frequency switch, which includes the semiconductor device structure described above.

[0111] Accordingly, embodiments of this application also provide an electronic device that includes the semiconductor device structure described above.

[0112] The electronic device described in the embodiments of this application can be any electronic product or device such as a smartphone, desktop computer, tablet computer, laptop computer, digital assistant, augmented reality (AR) / virtual reality (VR) device, smart voice interaction device, smart home appliance, smart wearable device, vehicle terminal device, etc., or any intermediate product including the above-mentioned storage device.

[0113] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0114] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0115] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0116] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device structure, characterized in that, The semiconductor device structure is used for a radio frequency switch, and the semiconductor device structure includes: Substrate; Gate structure located on the substrate; The substrate contains a first doped region, a second doped region, a third doped region, and a fourth doped region; the first doped region, the second doped region, the third doped region, and the fourth doped region all have the same conductivity type, and the third doped region and the fourth doped region form the source and the drain, respectively; The first doped region and the third doped region are connected and located on the first side of the gate structure; the first doped region is closer to the gate structure than the third doped region; the doping concentration of the first doped region is less than the doping concentration of the third doped region. The second doped region and the fourth doped region are connected and located on the second side of the gate structure; The second doped region is closer to the gate structure than the fourth doped region; the doping concentration of the second doped region is less than that of the fourth doped region. Both the first doped region and the second doped region are lightly doped drain regions, and each includes at least two sub-doped regions arranged side by side. The at least two sub-doped regions arranged side by side are equivalent to two sub-resistors connected in series to maintain or reduce the resistance values ​​of the first doped region and the second doped region respectively. The doping concentration of the sub-doped region closer to the gate structure in the first doped region and the second doped region is less than the doping concentration of the sub-doped region farther from the gate structure, so as to reduce the band tunneling current between the first doped region and the second doped region and the well region of the substrate when the RF switch is in the off state with negative voltage bias, thereby increasing the breakdown voltage.

2. The semiconductor device structure according to claim 1, characterized in that, The first doped region includes at least two sub-doped regions with the same area size; The second doped region includes at least two sub-doped regions with the same area size.

3. The semiconductor device structure according to claim 1, characterized in that, In the first doped region, which includes at least two sub-doped regions, the region size of the sub-doped region with lower doping concentration is larger than the region size of the sub-doped region with higher doping concentration. In the second doped region, which includes at least two sub-doped regions, the region size of the sub-doped region with lower doping concentration is larger than that of the sub-doped region with higher doping concentration.

4. The semiconductor device structure according to any one of claims 1-3, characterized in that, It also includes two first barriers located on the substrate; The two first barriers are located on the first and second sides of the gate structure, respectively, and are in contact with the side surfaces of the first and second sides of the gate structure, respectively.

5. The semiconductor device structure according to claim 4, characterized in that, It also includes two second barrier walls located on the substrate, which respectively shield the first doped region and the second doped region; The two second baffles are located on both sides of the gate structure and are respectively in contact with the side of the first baffle. Each first baffle is located between each second baffle and the gate structure.

6. The semiconductor device structure according to any one of claims 1-3, characterized in that, The area of ​​the first overlapping region corresponding to the first doped region and the gate structure is less than or equal to a preset value; The area of ​​the second overlapping region corresponding to the second doped region and the gate structure is less than or equal to the preset value.

7. A method for forming a semiconductor device structure, characterized in that, The semiconductor device structure is used for a radio frequency switch, and the method includes: A substrate is provided; the substrate includes a region on which a gate structure is formed; A first doped region and a second doped region are formed within the substrate; the first doped region is located on a first side of the region where the gate structure is formed; the second doped region is located on a second side of the region where the gate structure is formed; wherein, both the first doped region and the second doped region are lightly doped drain regions, and each includes at least two sub-doped regions arranged side by side, the at least two sub-doped regions being equivalent to two sub-resistors connected in series, to maintain or reduce the resistance values ​​corresponding to the first doped region and the second doped region respectively; among the first doped region and the second doped region, the doping concentration of the sub-doped region closer to the region where the gate structure is formed is less than the doping concentration of the sub-doped region farther from the region where the gate structure is formed, so as to reduce the band tunneling current between the first doped region and the second doped region and the well region of the substrate respectively when the RF switch is in the off state with negative voltage bias, thereby increasing the breakdown voltage; A third doped region and a fourth doped region are formed within the substrate; the third doped region is located on a first side of the region where the gate structure is formed; the fourth doped region is located on a second side of the region where the gate structure is formed; the third doped region and the fourth doped region form the source and drain, respectively; the first doped region and the third doped region are connected; the first doped region is closer to the region where the gate structure is formed than the third doped region; the doping concentration of the first doped region is less than the doping concentration of the third doped region; the second doped region and the fourth doped region are connected; the second doped region is closer to the region where the gate structure is formed than the fourth doped region; the doping concentration of the second doped region is less than the doping concentration of the fourth doped region.

8. The method for forming a semiconductor device structure according to claim 7, characterized in that, The formation of the first doped region and the second doped region within the substrate includes: When both the first doped region and the second doped region include a first sub-doped region and a second sub-doped region, ions of a first concentration are implanted into the first preset region and the second preset region to form a first sub-doped region within the first doped region and a third sub-doped region within the second doped region. Ions of a second concentration are implanted into a third and a fourth predetermined region to form a second sub-doped region within the first doped region and a fourth sub-doped region within the second doped region; the first concentration is less than the second concentration. The first preset region and the third preset region together correspond to the first doped region; the second preset region and the fourth preset region together correspond to the second doped region.

9. The method for forming a semiconductor device structure according to claim 7, characterized in that, The formation of the first doped region and the second doped region within the substrate includes: When both the first doped region and the second doped region include a first sub-doped region and a second sub-doped region, ions of a first concentration are implanted into the first region corresponding to the first doped region and the second region corresponding to the second doped region. By implanting ions of a second concentration into the third region contained in the first region and the fourth region contained in the second region, a first sub-doped region and a second sub-doped region are formed in the first doped region and the second doped region. The first sub-doped region in the first doped region is the non-third region after ion implantation in the first region; the second sub-doped region in the first doped region is the third region after ion implantation in the first region. The third sub-doped region in the second doped region is the non-fourth region after ion implantation in the second region; the fourth sub-doped region in the second doped region is the fourth region after ion implantation in the second region.

10. The method for forming a semiconductor device structure according to claim 7, characterized in that, Before forming the first doped region and the second doped region in the substrate, the method further includes: A gate structure is formed on the substrate; the gate structure is located in the region where the gate structure is formed. Wherein, the first doped region is located on the first side of the gate structure; the second doped region is located on the second side of the gate structure; in the first doped region and the second doped region, the doping concentration of the sub-doped region closer to the gate structure is less than the doping concentration of the sub-doped region farther from the gate structure; The third doped region is located on the first side of the gate structure; the fourth doped region is located on the second side of the gate structure; the first doped region is closer to the gate structure than the third doped region; the second doped region is closer to the gate structure than the fourth doped region.

11. The method for forming a semiconductor device structure according to claim 7, characterized in that, After the formation of the first and second doped regions in the substrate, and before the formation of the third and fourth doped regions in the substrate, the method further includes: A gate structure is formed on the substrate; the gate structure is located in the region where the gate structure is formed. The third doped region is located on the first side of the gate structure; the fourth doped region is located on the second side of the gate structure; the first doped region is closer to the gate structure than the third doped region; and the second doped region is closer to the gate structure than the fourth doped region.

12. The method for forming a semiconductor device structure according to claim 10 or 11, characterized in that, The gate structure includes a gate oxide layer and a polysilicon gate; after forming the gate structure on the substrate, it further includes: On the substrate, two first barriers are formed on both sides of the gate structure.

13. The method for forming a semiconductor device structure according to claim 12, characterized in that, Before forming the third and fourth doped regions within the substrate, the method further includes: On the substrate, two second barriers are formed on the outer sides of the two first barriers; the two second barriers are used to shield the first doped region and the second doped region, respectively.

14. A radio frequency switch, characterized in that, The radio frequency switch includes the semiconductor device structure as described in any one of claims 1 to 6.

15. An electronic device, characterized in that, The electronic device includes the semiconductor device structure as described in any one of claims 1 to 6.

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