Semiconductor device

Abstract

The semiconductor device may include first, second, and third source / drain patterns, a semiconductor pattern between the first and third source / drain patterns, a gate dielectric layer in contact with the semiconductor pattern, a gate electrode in contact with the gate dielectric layer, a blocking semiconductor pattern between the first and second source / drain patterns, and a gate electrode between the first and second source / drain patterns. A blocking dielectric layer in contact with the blocking semiconductor pattern; and a blocking electrode in contact with the blocking dielectric layer. The blocking dielectric layer may include a first layer in contact with the first source / drain pattern and the second source / drain pattern, a second layer in contact with the blocking electrode, and a third layer between the first layer and the second layer. The dielectric material of the third layer may be different from the dielectric materials of the first and second layers.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0147917 filed on October 31, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including an active pattern. Background Art

[0003] Semiconductor devices may include integrated circuits having metal oxide semiconductor field effect transistors (MOSFETs). As the size and design rules of semiconductor devices are gradually reduced, the size of MOSFETs is also reduced. The reduced size of MOSFETs may deteriorate the operating characteristics of semiconductor devices. Therefore, various studies have been conducted to manufacture semiconductor devices with excellent performance while overcoming the limitations caused by the integration of semiconductor devices. Summary of the invention

[0004] Some embodiments of the inventive concept provide a semiconductor device having increased reliability and improved electrical performance and a method of manufacturing the same.

[0005] According to an embodiment of the present invention, a semiconductor device may include a first source / drain pattern; a second source / drain pattern and a third source / drain pattern adjacent to the first source / drain pattern; a plurality of semiconductor patterns between the first source / drain pattern and the third source / drain pattern; a gate dielectric layer in contact with the plurality of semiconductor patterns; a gate electrode in contact with the gate dielectric layer; a plurality of blocking semiconductor patterns between the first source / drain pattern and the second source / drain pattern; a blocking dielectric layer in contact with the plurality of blocking semiconductor patterns; and a blocking electrode in contact with the blocking dielectric layer. The blocking dielectric layer may include a first layer in contact with the first source / drain pattern and the second source / drain pattern, a second layer in contact with the blocking electrode, and a third layer between the first layer and the second layer. The dielectric material in the third layer may be different from the dielectric material of the first layer and the dielectric material of the second layer.

[0006] According to an embodiment of the present inventive concept, a semiconductor device may include a first source / drain pattern; a second source / drain pattern and a third source / drain pattern adjacent to the first source / drain pattern; a plurality of semiconductor patterns between the first source / drain pattern and the third source / drain pattern; a gate dielectric layer in contact with the plurality of semiconductor patterns; a gate electrode in contact with the gate dielectric layer; a plurality of blocking semiconductor patterns between the first source / drain pattern and the second source / drain pattern; a blocking dielectric layer in contact with the plurality of blocking semiconductor patterns; and a first blocking electrode in contact with the blocking dielectric layer. The dielectric material of the blocking dielectric layer may be different from the dielectric material of the gate dielectric layer.

[0007] According to an embodiment of the present invention, a semiconductor device may include a first source / drain pattern; a second source / drain pattern and a third source / drain pattern adjacent to the first source / drain pattern; a plurality of semiconductor patterns located between the first source / drain pattern and the third source / drain pattern; a gate dielectric layer in contact with the plurality of semiconductor patterns; a gate electrode in contact with the gate dielectric layer; a gate contact electrically connected to the gate electrode; a plurality of blocking semiconductor patterns located between the first source / drain pattern and the second source / drain pattern; a blocking dielectric layer in contact with the blocking semiconductor pattern; a blocking electrode in contact with the blocking dielectric layer; a blocking electrode contact electrically connected to the blocking electrode; a plurality of gate spacers in contact with the blocking dielectric layer; a gate capping pattern in contact with a top surface of the blocking electrode and the blocking dielectric layer; and an active contact electrically connected to a corresponding one of the first source / drain pattern, the second source / drain pattern, and the third source / drain pattern. The blocking dielectric layer may include a first layer, a second layer, and a third layer, and the first layer may be in contact with the first source / drain pattern, the second source / drain pattern, and the plurality of blocking semiconductor patterns. The second layer may be in contact with the blocking electrode. The third layer may be located between the first layer and the second layer, and the first layer and the second layer may include oxide. The third layer may include nitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 and Figure 2 A conceptual diagram illustrating a logic cell of a semiconductor device according to some embodiments.

[0009] Figure 3A A plan view of a semiconductor device according to some embodiments is shown.

[0010] Figure 3B Shown along Figure 3A A cross-sectional view taken along line AA′.

[0011] Figure 3C Shown along Figure 3A A cross-sectional view taken along line BB′.

[0012] Figure 3D Shows Figure 3B An enlarged view of part E1.

[0013] Figure 3E Shows Figure 3C An enlarged view of portion E2.

[0014] Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 Shows FIG. 3A to FIG. 3E A cross-sectional view of a method for manufacturing a semiconductor device is shown.

[0015] Fig. 9 A cross-sectional view of a semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0016] Figure 1 and Figure 2 A conceptual diagram illustrating a logic cell of a semiconductor device according to some embodiments.

[0017] refer to Figure 1 , a single height cell SHC may be provided. For example, a first power line M1_R1 and a second power line M1_R2 may be provided on the substrate 100. The first power line M1_R1 may be a path for providing a source voltage (VSS). For example, the first power line M1_R1 may be a path for providing a ground voltage. The second power line M1_R2 may be a path for providing a drain voltage (VDD). For example, the second power line M1_R2 may be a path for providing a power supply voltage.

[0018] The single height cell SHC may be defined between the first power line M1_R1 and the second power line M1_R2. The single height cell SHC may include a first active region AR1 and a second active region AR2. One of the first active region AR1 and the second active region AR2 may be a PMOSFET region, and the other of the first active region AR1 and the second active region AR2 may be an NMOSFET region. The single height cell SHC may have a complementary metal oxide semiconductor (CMOS) structure disposed between the first power line M1_R1 and the second power line M1_R2.

[0019] Each of the first active region AR1 and the second active region AR2 may have a first width WI1 along the first direction D1. The first height HE1 may be defined as a length of the single height cell SHC in the first direction D1. The first height HE1 may be the same or substantially the same as a distance (eg, a spacing) between the first power line M1_R1 and the second power line M1_R2.

[0020] The single height cell SHC may constitute a logic unit. In this specification, a logic unit may refer to a logic device that performs a specific function, such as AND, OR, XOR, XNOR, and inverter. A logic unit may include transistors for constituting a logic device and wiring lines for connecting the transistors to each other.

[0021] refer to Figure 2, a double height cell DHC may be provided. For example, a first power line M1_R1, a second power line M1_R2, and a third power line M1_R3 may be provided on the substrate 100. The first power line M1_R1 may be provided between the second power line M1_R2 and the third power line M1_R3. The third power line M1_R3 may be a path for providing a source voltage (VSS).

[0022] The double height cell DHC may be defined between the second power line M1_R2 and the third power line M1_R3 The double height cell DHC may include two first active regions AR1 and two second active regions AR2.

[0023] One of the two second active regions AR2 may be adjacent to the second power line M1_R2. The other of the two second active regions AR2 may be adjacent to the third power line M1_R3. The two first active regions AR1 may be adjacent to the first power line M1_R1. When viewed in a plan view, the first power line M1_R1 may be disposed between the two first active regions AR1.

[0024] The second height HE2 may be defined to indicate the length of the double height unit DHC in the first direction D1. The second height HE2 may be Figure 1 The two first active regions ARI of the double-height cell DHC may be commonly connected to serve as one active region.

[0025] Figure 2 The double height cell DHC shown can be defined as a multi-height cell. In some embodiments, the multi-height cell can include a triple height cell, whose cell height is approximately three times that of a single height cell SHC.

[0026] Figure 3A A plan view of a semiconductor device according to some embodiments is shown. Figure 3B Shown along Figure 3A A cross-sectional view taken along line AA′. Figure 3C Shown along Figure 3A A cross-sectional view taken along line BB′. Figure 3D Shows Figure 3B An enlarged view of part E1. Figure 3E Shows Figure 3C An enlarged view of portion E2.

[0027] Reference Figure 3A , Figure 3B and Figure 3C, the semiconductor device may include a substrate 100. The substrate 100 may be a semiconductor substrate, a dielectric substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate may include, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium phosphate (GaP), or gallium arsenide (GaAs). The substrate 100 may have a plate shape extending along a plane elongated in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other.

[0028] The substrate 100 may include a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be portions of the substrate 100 that protrude along a third direction D3. The third direction D3 may intersect the first direction D1 and the second direction D2. For example, the third direction D3 may be a vertical direction perpendicular to the first direction D1 and the second direction D2.

[0029] The device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may have the first active pattern AP1 and the second active pattern AP2 disposed therein. The device isolation layer ST may include a dielectric material. For example, the device isolation layer ST may include oxide.

[0030] A source / drain pattern SD may be provided. The source / drain pattern SD may overlap the first active pattern AP1 or the second active pattern AP2 in the third direction D3. The source / drain pattern SD overlapping the first active pattern AP1 in the third direction D3 may be arranged on the first active pattern AP1 in the second direction D2.

[0031] The source / drain pattern SD may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. The source / drain pattern SD may include a semiconductor material. The source / drain pattern SD may include one of silicon (Si), silicon-germanium (SiGe), and germanium (Ge). In some embodiments, the source / drain pattern SD overlapping the first active pattern AP1 in the third direction D3 may include p-type impurities to have a p-conductivity type.

[0032] A channel structure CH1 may be provided. The channel structure CH1 may be disposed between the source / drain patterns SD. The channel structure CH1 may overlap the first active pattern AP1 or the second active pattern AP2 in the third direction D3.

[0033] The channel structure CH1 may each include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 that overlap each other in the third direction D3. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in the third direction D3. In some embodiments, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include silicon (Si). For example, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include crystalline silicon. In some embodiments, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include silicon-germanium (SiGe).

[0034] A gate electrode GE extending in the first direction D1 may be provided. The gate electrode GE may overlap one or more of the first active pattern AP1 and the second active pattern AP2 in the third direction D3. The gate electrode GE may overlap the channel structure CH1 in the third direction D3. The gate electrode GE and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may constitute a three-dimensional field effect transistor (e.g., MBCFET or GAAFET).

[0035] A gate dielectric layer GI may be provided. The gate dielectric layer GI may separate the gate electrode GE from the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 and the source / drain pattern SD. The gate dielectric layer GI may contact the top surface, the bottom surface, and the sidewall of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate dielectric layer GI may contact the source / drain pattern SD. The gate dielectric layer GI may include a dielectric material. For example, the gate dielectric layer GI may include an oxide.

[0036] The gate electrode GE may include a first electrode layer GL1 in contact with the gate dielectric layer GI and a second electrode layer GL2 in contact with the first electrode layer GL1. The first electrode layer GL1 may be disposed between the gate dielectric layer GI and the second electrode layer GL2. The first electrode layer GL1 may separate the second electrode layer GL2 from the gate dielectric layer GI.

[0037] The first electrode layer GL1 and the second electrode layer GL2 may include conductive materials different from each other. For example, the first electrode layer GL1 may include at least one selected from TiN, TiO, AlN, AlO, TiAlN, and TiAlO, and the second electrode layer GL2 may include at least one selected from Ti and Al.

[0038] A first blocking channel structure 140 and a second blocking channel structure 150 may be provided. Each of the first blocking channel structure 140 and the second blocking channel structure 150 may be disposed between the source / drain patterns SD. Each of the first blocking channel structure 140 and the second blocking channel structure 150 may be disposed between the gate electrodes GE. Each of the first blocking channel structure 140 and the second blocking channel structure 150 may be disposed between the channel structures CH1. The first blocking channel structure 140 may overlap the first active pattern AP1 in the third direction D3. The second blocking channel structure 150 may overlap the second active pattern AP2 in the third direction D3.

[0039] The first blocking channel structure 140 may include a first blocking semiconductor pattern 141, a second blocking semiconductor pattern 142, and a third blocking semiconductor pattern 143 overlapping each other in the third direction D3. The first blocking semiconductor pattern 141, the second blocking semiconductor pattern 142, and the third blocking semiconductor pattern 143 may be spaced apart from each other in the third direction D3. The first blocking semiconductor pattern 141, the second blocking semiconductor pattern 142, and the third blocking semiconductor pattern 143 may include the same material as the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0040] The second blocking channel structure 150 may include a fourth blocking semiconductor pattern 151, a fifth blocking semiconductor pattern 152, and a sixth blocking semiconductor pattern 153 overlapping each other in the third direction D3. The fourth blocking semiconductor pattern 151, the fifth blocking semiconductor pattern 152, and the sixth blocking semiconductor pattern 153 may be spaced apart from each other in the third direction D3. The fourth blocking semiconductor pattern 151, the fifth blocking semiconductor pattern 152, and the sixth blocking semiconductor pattern 153 may include the same material as the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0041] A first blocking electrode 131 and a second blocking electrode 134 extending in the first direction D1 may be provided. The first blocking electrode 131 and the second blocking electrode 134 may be arranged in the first direction D1. The first blocking electrode 131 may overlap the first active pattern AP1 in the third direction D3. The first blocking electrode 131 may overlap the first blocking channel structure 140 in the third direction D3. The second blocking electrode 134 may overlap the second active pattern AP2 in the third direction D3. The second blocking electrode 134 may overlap the second blocking channel structure 150 in the third direction D3. The first blocking electrode 131 and the second blocking electrode 134 may include the same conductive material as the second electrode layer GL2 of the gate electrode GE. For example, the first blocking electrode 131 and the second blocking electrode 134 may include at least one selected from Ti and Al.

[0042] The blocking electrode separation layer 160 may be disposed between the first blocking electrode 131 and the second blocking electrode 134. The blocking electrode separation layer 160 may separate the first blocking electrode 131 and the second blocking electrode 134 from each other in the first direction D1. The blocking electrode separation layer 160 may include a dielectric material.

[0043] A first blocking dielectric layer 132 and a second blocking dielectric layer 135 may be provided. The first blocking dielectric layer 132 may separate the first blocking electrode 131 from the first blocking semiconductor pattern 141, the second blocking semiconductor pattern 142, and the third blocking semiconductor pattern 143, and the source / drain pattern SD. The second blocking dielectric layer 135 may separate the second blocking electrode 134 from the fourth blocking semiconductor pattern 151, the fifth blocking semiconductor pattern 152, and the sixth blocking semiconductor pattern 153, and the source / drain pattern SD. The first blocking dielectric layer 132 may contact the top surface, the bottom surface, and the sidewall of each of the first blocking semiconductor pattern 141, the second blocking semiconductor pattern 142, and the third blocking semiconductor pattern 143. The second blocking dielectric layer 135 may contact the top surface, the bottom surface, and the sidewall of each of the fourth blocking semiconductor pattern 151, the fifth blocking semiconductor pattern 152, and the sixth blocking semiconductor pattern 153.

[0044] A gate spacer GS may be provided. A pair of gate spacers GS may be provided on opposite sides of the gate electrode GE, the first blocking electrode 131, or the second blocking electrode 134. The gate spacer GS may extend along the first direction D1. The top surface of the gate spacer GS may be coplanar with the top surface of the first interlayer dielectric layer 110 to be discussed below. The gate spacer GS may include a dielectric material.

[0045] A gate capping pattern GP may be provided. The gate capping pattern GP may be provided on the gate electrode GE, the first blocking electrode 131, or the second blocking electrode 134. The gate capping pattern GP may extend along the first direction D1. The gate capping pattern GP may include a dielectric material having an etching selectivity with respect to the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 to be discussed below. For example, the gate capping pattern GP may include a nitride.

[0046] A first interlayer dielectric layer 110 may be provided to cover the gate spacer GS and the source / drain pattern SD. The first interlayer dielectric layer 110 may have a top surface substantially coplanar with a top surface of the gate capping pattern GP and a top surface of the gate spacer GS. The first interlayer dielectric layer 110 may be provided thereon with a second interlayer dielectric layer 120 covering the gate capping pattern GP. The first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 may include a dielectric material. For example, the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 may include an oxide.

[0047] The active contact AC may be disposed to penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120. The active contact AC may be electrically connected to the source / drain pattern SD. The gate electrode GE, the first blocking electrode 131, or the second blocking electrode 134 may be disposed between the active contacts AC adjacent to each other in the second direction D2. The active contact AC may have a strip shape extending in the first direction D1.

[0048] In some embodiments, the metal-semiconductor compound layer may be interposed between the active contact AC and the source / drain pattern SD. In this case, the active contact AC may be electrically connected to the source / drain pattern SD through the metal-semiconductor compound layer. For example, the metal-semiconductor compound layer may include at least one selected from titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0049] In some embodiments, the active contact AC may include a conductive pattern and a barrier pattern. The barrier pattern may cover the sidewall and bottom surface of the conductive pattern. For example, the conductive pattern may include at least one selected from aluminum, copper, tungsten, molybdenum, and cobalt, and the barrier pattern may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0050] A gate contact GC may be provided. The gate contact GC may penetrate the second interlayer dielectric layer 120 and the gate capping pattern GP. The gate contact GC may contact the gate electrode GE. The gate contact GC may include a conductive material.

[0051] A first blocking electrode contact portion 133 may be provided. The first blocking electrode contact portion 133 may penetrate the second interlayer dielectric layer 120 and the gate capping pattern GP. The first blocking electrode contact portion 133 may contact the first blocking electrode 131. The first blocking electrode contact portion 133 may include a conductive material.

[0052] A second blocking electrode contact portion 136 may be provided. The second blocking electrode contact portion 136 may penetrate the second interlayer dielectric layer 120 and the gate capping pattern GP. The second blocking electrode contact portion 136 may contact the second blocking electrode 134. The second blocking electrode contact portion 136 may include a conductive material.

[0053] Cells (e.g., single-height cells) may be disposed on opposite sides of each of the first blocking electrode 131, the first blocking dielectric layer 132, the first blocking channel structure 140, the second blocking electrode 134, the second blocking dielectric layer 135, and the second blocking channel structure 150. The first blocking electrode 131, the first blocking dielectric layer 132, the first blocking channel structure 140, the second blocking electrode 134, the second blocking dielectric layer 135, and the second blocking channel structure 150 may electrically separate the cells from each other.

[0054] refer to Figure 3D and Figure 3E The source / drain pattern SD overlapping the first active pattern AP1 in the third direction D3 may include a first source / drain pattern SD1, a second source / drain pattern SD2 adjacent to the first source / drain pattern SD1, and a third source / drain pattern SD3 adjacent to the first source / drain pattern SD1. The first source / drain pattern SD1 may be disposed between the second source / drain pattern SD2 and the third source / drain pattern SD3.

[0055] The first blocking electrode 131 and the first blocking dielectric layer 132 may be disposed between the first source / drain pattern SD1 and the second source / drain pattern SD2. The gate electrode GE and the gate dielectric layer GI may be disposed between the first source / drain pattern SD1 and the third source / drain pattern SD3.

[0056] The first blocking electrode 131 may include a first blocking electrode portion 131 a between the first active pattern AP1 and the first blocking semiconductor pattern 141, a second blocking electrode portion 131 b between the first blocking semiconductor pattern 141 and the second blocking semiconductor pattern 142, a third blocking electrode portion 131 c between the second blocking semiconductor pattern 142 and the third blocking semiconductor pattern 143, and a fourth blocking electrode portion 131 d on the first blocking semiconductor pattern 141, the second blocking semiconductor pattern 142, and the third blocking semiconductor pattern 143.

[0057] The first blocking dielectric layer 132 may include a first layer 132a, a second layer 132b, and a third layer 132c. The first layer 132a may contact the first active pattern AP1, the first to third blocking semiconductor patterns 141 to 143, the source / drain pattern SD, and the gate spacer GS. The third layer 132c may contact the first blocking electrode 131. The second layer 132b may be disposed between the first layer 132a and the third layer 132c. The second layer 132b may separate the first layer 132a and the third layer 132c from each other.

[0058] The first blocking dielectric layer 132 may include a dielectric material different from the gate dielectric layer GI. The second layer 132b may include a dielectric material different from the dielectric materials of the first layer 132a and the third layer 132c. For example, the second layer 132b may include a nitride (e.g., SiN), and the first layer 132a and the third layer 132c may include an oxide (e.g., SiO or HfO).

[0059] The first blocking dielectric layer 132 may include a portion disposed between the first active pattern AP1 and the first blocking semiconductor pattern 141, a portion disposed between the first blocking semiconductor pattern 141 and the second blocking semiconductor pattern 142, a portion disposed between the second blocking semiconductor pattern 142 and the third blocking semiconductor pattern 143, and a portion disposed on the first blocking semiconductor pattern 141, the second blocking semiconductor pattern 142, and the third blocking semiconductor pattern 143. Figure 3D When viewed in the illustrated cross section, portions of the first blocking dielectric layer 132 disposed on the first, second, and third blocking semiconductor patterns 141 , 142 , and 143 may have a U-shape.

[0060] Each of the first layer 132a, the second layer 132b, and the third layer 132c may include a portion disposed between the first active pattern AP1 and the first blocking semiconductor pattern 141, a portion disposed between the first blocking semiconductor pattern 141 and the second blocking semiconductor pattern 142, a portion disposed between the second blocking semiconductor pattern 142 and the third blocking semiconductor pattern 143, and a portion disposed on the first blocking semiconductor pattern 141, the second blocking semiconductor pattern 142, and the third blocking semiconductor pattern 143. Figure 3D A portion of each of the first, second, and third layers 132 a , 132 b , and 132 c disposed on the first, second, and third blocking semiconductor patterns 141 , 142 , and 143 may have a U-shape when viewed in the illustrated cross section.

[0061] For example, a width W1 of a fourth blocking electrode portion 131d of the first blocking electrode 131 in the second direction D2 may be smaller than a width W2 of a portion of the gate electrode GE disposed on the semiconductor patterns SP1, SP2, and SP3 in the second direction D2.

[0062] The thickness of the first blocking dielectric layer 132 may be greater than the thickness of the gate dielectric layer GI. For example, a portion of the first blocking dielectric layer 132 in contact with the sidewall of the fourth blocking electrode portion 131d of the first blocking electrode 131 may have a thickness T1 in the second direction D2 greater than a thickness T2 of a portion of the gate dielectric layer GI in contact with the sidewall of a portion of the gate electrode GE on the semiconductor patterns SP1, SP2, and SP3.

[0063] The second layer 132b of the first blocking dielectric layer 132 may include a material in which electrons or holes are captured. When a voltage is applied to the first blocking electrode 131, electrons or holes may be captured in the second layer 132b of the first blocking dielectric layer 132. The holes or electrons captured in the second layer 132b of the first blocking dielectric layer 132 may increase the threshold voltage of the first blocking semiconductor pattern 141, the second blocking semiconductor pattern 142, and the third blocking semiconductor pattern 143, and the first blocking semiconductor pattern 141, the second blocking semiconductor pattern 142, and the third blocking semiconductor pattern 143 may be electrically blocked. Therefore, the first blocking electrode 131, the first blocking dielectric layer 132, and the first blocking semiconductor pattern 141, the second blocking semiconductor pattern 142, and the third blocking semiconductor pattern 143 may be electrically separated from each other unit.

[0064] In some embodiments, the first source / drain pattern SD1, the second source / drain pattern SD2, and the third source / drain pattern SD3 may include p-type impurities, a negative voltage may be applied to the first blocking electrode 131 so that holes are captured in the second layer 132 b of the first blocking dielectric layer 132, and the captured holes may increase the threshold voltage of the first blocking semiconductor pattern 141, the second blocking semiconductor pattern 142, and the third blocking semiconductor pattern 143.

[0065] In some embodiments, the first source / drain pattern SD1, the second source / drain pattern SD2, and the third source / drain pattern SD3 may include p-type impurities, a positive voltage may be applied to the first blocking electrode 131 so that electrons are captured in the second layer 132 b of the first blocking dielectric layer 132, and the captured electrons may increase the threshold voltages of the first blocking semiconductor pattern 141, the second blocking semiconductor pattern 142, and the third blocking semiconductor pattern 143.

[0066] refer to Figure 3A , Figure 3B and Figure 3C, the second blocking electrode 134, the second blocking dielectric layer 135, and the fourth blocking semiconductor pattern 151, the fifth blocking semiconductor pattern 153, and the sixth blocking semiconductor pattern 153 may have similar structures and operations to the first blocking electrode 131, the first blocking dielectric layer 132, and the first blocking semiconductor pattern 141, the second blocking semiconductor pattern 142, and the third blocking semiconductor pattern 143.

[0067] In some embodiments, the first active pattern AP1 may be included in the PMOSFET region, and the second active pattern AP2 may be included in the NMOSFET region. In this case, a negative voltage may be applied to the first blocking electrode 131 to electrically block the first, second, and third blocking semiconductor patterns 141, 142, and 143, and a positive voltage may be applied to the second blocking electrode 134 to electrically block the fourth, fifth, and sixth blocking semiconductor patterns 151, 153, and 153.

[0068] In the semiconductor device according to some embodiments, holes or electrons may be trapped to electrically insulate a cell including the first source / drain pattern SD1 and a cell including the second source / drain pattern SD2 .

[0069] In addition, a process for forming a physical insulation structure that physically insulates a cell including the first source / drain pattern SD1 from a cell including the second source / drain pattern SD2 may be omitted. For example, a deposition material for forming the physical insulation structure may remain on the source / drain pattern SD to limit and / or prevent an increase in difficulty in forming the active contact AC.

[0070] Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 Shows FIG. 3A to FIG. 3E A cross-sectional view of a method for manufacturing a semiconductor device is shown.

[0071] refer to Figure 4 , the first active pattern AP1 and the second active pattern (see Figure 3C AP2) may be formed on the substrate 100. A device isolation layer (see Figure 3C A channel structure CH1, a first blocking channel structure 140, and a second blocking channel structure (see Figure 3C of 150).

[0072] The formation of the channel structure CH1, the first blocking channel structure 140, and the second blocking channel structure 150 may include: forming first and second preliminary layers alternately stacked with each other; forming sacrificial patterns PP, mask patterns MS, and gate spacers GS; and etching the first and second preliminary layers using the mask patterns MS and the gate spacers GS as etching masks.

[0073] The first preliminary layer may include a material having an etch selectivity with respect to the second preliminary layer. For example, the second preliminary layer may include Si, and the first preliminary layer may include SiGe. The sacrificial pattern PP may include, for example, polysilicon. The mask pattern MS may include a dielectric material.

[0074] The second preliminary layer may be etched to form semiconductor patterns SP1, SP2, and SP3 and blocking semiconductor patterns 141, 142, 143, 151, 152, and 153. The first preliminary layer may be etched to form first and second sacrificial semiconductor patterns 171 and 172. The first and second sacrificial semiconductor patterns 171 and 172 may include a material having an etching selectivity with respect to the semiconductor patterns SP1, SP2, and SP3 and the blocking semiconductor patterns 141, 142, 143, 151, 152, and 153.

[0075] A source / drain pattern SD may be formed. The source / drain pattern SD may be formed by a selective epitaxial growth process. The first sacrificial semiconductor pattern 171 may be disposed between the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0076] refer to Figure 5 , a first interlayer dielectric layer 110 may be formed. The mask pattern MS and the sacrificial pattern PP may be removed. The first space 175 may be defined as indicating an empty space formed when the sacrificial pattern PP is removed. The first sacrificial semiconductor pattern 171 and the second sacrificial semiconductor pattern 172 may be removed through the first space 175. The second space 173 may be defined as indicating an empty space formed when the first sacrificial semiconductor pattern 171 is removed. The third space 174 may be defined as indicating an empty space formed when the second sacrificial semiconductor pattern 172 is removed.

[0077] refer to Figure 6 , the filling layer 181 may be formed to fill the second space 173 and the first space 175 overlapping the second space 173 in the third direction D3. The filling layer 181 may include, for example, metal or nitride.

[0078] The gate dielectric layer GI, the gate electrode GE, and the preliminary capping layer 183 may be formed to fill the third space 174 and the first space 175 overlapping the third space 174 in the third direction D3. The preliminary capping layer 183 may include, for example, nitride.

[0079] refer to Figure 7 , the filling layer 181 may be removed. Removal of the filling layer 181 may open the second space 173 and the first space 175 overlapping the second space 173 in the third direction D3.

[0080] refer to Figure 8 , a first blocking electrode 131, a first blocking dielectric layer 132, a second blocking electrode (see Figure 3C 134) and a second blocking dielectric layer (see Figure 3C The blocking electrode separation layer 160 may be formed between the first blocking electrode 131 and the second blocking electrode 134 and between the first blocking dielectric layer 132 and the second blocking dielectric layer 135 (see Figure 3C 160 in the above table).

[0081] The preliminary capping layer 183 may be removed. A gate capping pattern GP may be formed on the gate electrode GE, the first blocking electrode 131, and the second blocking electrode 134.

[0082] refer to Figure 3B and Figure 3C , a second interlayer dielectric layer 120 may be formed. An active contact AC, a gate contact GC, a first blocking electrode contact 133, and a second blocking electrode contact 136 may be formed.

[0083] In some embodiments, in the process of removing the second sacrificial semiconductor pattern 172 and the sacrificial pattern PP, the first sacrificial semiconductor pattern 171 may not be removed, and the sacrificial pattern PP overlapping the first sacrificial semiconductor pattern 171 in the third direction D3 may not be removed. A mask layer may be formed to cover the first sacrificial semiconductor pattern 171 and the sacrificial pattern PP overlapping the first sacrificial semiconductor pattern 171 in the third direction D3, and thus the first sacrificial semiconductor pattern 171 and the sacrificial pattern PP overlapping the first sacrificial semiconductor pattern 171 in the third direction D3 may not be removed. After forming the gate dielectric layer GI and the gate electrode GE, the first sacrificial semiconductor pattern 171 and the sacrificial pattern PP overlapping the first sacrificial semiconductor pattern 171 in the third direction D3 may be removed.

[0084] In some embodiments, instead of forming the initial capping layer 183 , the gate capping pattern GP may be formed on the gate electrode GE. Afterwards, after forming the blocking electrodes 131 and 134 and the blocking dielectric layers 132 and 135 , the gate capping pattern GP may be formed on the blocking electrodes 131 and 134 .

[0085] Fig. 9 1 shows a cross-sectional view of a semiconductor device according to some embodiments. In addition to the above discussion, Fig. 9 The semiconductor device can be similar to FIG. 3A to FIG. 3E semiconductor devices.

[0086] refer to Fig. 9 , the semiconductor device may include a first material layer 232 between the first source / drain pattern SD1 and the second source / drain pattern SD2. The first material layer 232 may include a first portion 232a between the first blocking semiconductor pattern 141 and the first active pattern AP1, a second portion 232b between the first blocking semiconductor pattern 141 and the second blocking semiconductor pattern 142, a third portion 232c between the second blocking semiconductor pattern 142 and the third blocking semiconductor pattern 143, and a fourth portion 232d located on the first blocking semiconductor pattern 141, the second blocking semiconductor pattern 142, and the third blocking semiconductor pattern 143. When the semiconductor device is configured as shown in FIG. Fig. 9 When viewed in the cross section shown, the fourth portion 232d of the first material layer 232 may have a U-shape. The first material layer 232 may be electrically floating. The first material layer 232 may not be provided with a contact portion electrically connected thereto.

[0087] The capping dielectric layer 231 may be disposed on the fourth portion 232d of the first material layer 232. The lower portion of the capping dielectric layer 231 may be disposed within the fourth portion 232d of the first material layer 232. The upper portion of the capping dielectric layer 231 may be located at a higher level than the fourth portion 232d of the first material layer 232. The width of the lower portion of the capping dielectric layer 231 may be smaller than the width of the upper portion of the capping dielectric layer 231. The capping dielectric layer 231 may include a dielectric material. For example, the capping dielectric layer 231 may include a nitride.

[0088] The first material layer 232 may have a different work function from the gate electrode GE. Since the first material layer 232 and the gate electrode GE are different from each other in work function, the first, second, and third blocking semiconductor patterns 141, 142, and 143 may have increased threshold voltages and may be electrically blocked.

[0089] In some embodiments, the first active pattern AP1 may be included in the PMOSFET region, and the first material layer 232 may have a work function smaller than that of the gate electrode GE. In this case, for example, the gate electrode GE may include Ti or Al, and the first material may include at least one selected from Ca, K, Lu, Eu, Gd, La, Mg, As, Ba, Ce, Cs, Hf, Li, Nd, Rb, Tb, Yb, Na, Sr, Tl, Sc, Sm, Th, U, Y, and Zr.

[0090] In some embodiments, the first active pattern AP1 may be included in the NMOSFET region, and the first material layer 232 may have a work function greater than that of the gate electrode GE. In this case, for example, the gate electrode GE may include Ti or Al, and the first material layer 232 may include at least one selected from Au, Be, Co, Cu, Hg, Fe, Ir, Cr, Mo, Ru, Se, Sn, Ni, Pd, Re, Sb, Si, Te, Os, Pt, and Rh.

[0091] In some embodiments, the semiconductor device may include a first active pattern AP1 included in the PMOSFET region and a second active pattern AP2 included in the NMOSFET region. The first material layer 232 on the first active pattern AP1 may have a work function smaller than that of the gate electrode GE. The second material layer may be disposed on the second active pattern AP2. The second material layer may include a material different from the first material layer 232. The second material layer may have a work function greater than that of the gate electrode GE.

[0092] In the semiconductor device according to some embodiments of the inventive concept, cells may be electrically separated by an electrical insulation structure.

[0093] In semiconductor devices according to some embodiments of the inventive concept, a process for forming a structure for physically insulating cells may be omitted, and thus difficulty of subsequent processes may be limited and / or prevented from being increased due to the process for forming the physical insulation structure.

[0094] Although some embodiments of the present invention have been discussed with reference to the accompanying drawings, it should be understood that various changes in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, it should be understood that the above embodiments are only illustrative and not restrictive in all aspects.

Claims

1. A semiconductor device, comprising: a first source / drain pattern; a second source / drain pattern and a third source / drain pattern, adjacent to the first source / drain pattern; a plurality of semiconductor patterns, located between the first source / drain pattern and the third source / drain pattern; a gate dielectric layer, contacting the plurality of semiconductor patterns; a gate electrode, contacting the gate dielectric layer; a plurality of blocking semiconductor patterns, located between the first source / drain pattern and the second source / drain pattern; a blocking dielectric layer in contact with the plurality of blocking semiconductor patterns; as well as a blocking electrode in contact with the blocking dielectric layer, wherein the blocking dielectric layer comprises a first layer in contact with the first source / drain pattern and the second source / drain pattern, a second layer in contact with the blocking electrode, and a third layer located between the first layer and the second layer; and The dielectric material in the third layer is different from the dielectric material in the first layer and the dielectric material in the second layer.

2. The semiconductor device according to claim 1, wherein The first layer and the second layer include oxides, and The third layer includes nitride.

3. The semiconductor device according to claim 1, wherein The thickness of the blocking dielectric layer is greater than the thickness of the gate dielectric layer.

4. The semiconductor device according to claim 1, wherein: The blocking electrode comprises: a first blocking electrode portion over the plurality of blocking semiconductor patterns; and A second blocking electrode portion is provided between the plurality of blocking semiconductor patterns.

5. The semiconductor device according to claim 4, wherein: The first blocking electrode portion has a width smaller than a width of a portion of the gate electrode over the plurality of semiconductor patterns.

6. The semiconductor device according to claim 1, further comprising: The blocking electrode contact portion is in contact with the blocking electrode.

7. The semiconductor device according to claim 1, wherein The gate electrode comprises: a first electrode layer, contacting the gate dielectric layer; and The second electrode layer is in contact with the first electrode layer.

8. The semiconductor device according to claim 7, wherein: The conductive material in the second electrode layer is the same as the conductive material of the blocking electrode.

9. A semiconductor device comprising: a first source / drain pattern; a second source / drain pattern and a third source / drain pattern, adjacent to the first source / drain pattern; a plurality of semiconductor patterns, located between the first source / drain pattern and the third source / drain pattern; a gate dielectric layer, contacting the plurality of semiconductor patterns; a gate electrode, contacting the gate dielectric layer; a plurality of blocking semiconductor patterns, located between the first source / drain pattern and the second source / drain pattern; a blocking dielectric layer in contact with the plurality of blocking semiconductor patterns; as well as a first blocking electrode, contacting the blocking dielectric layer, The dielectric material of the blocking dielectric layer is different from the dielectric material of the gate dielectric layer.

10. The semiconductor device according to claim 9, wherein The blocking dielectric layer comprises: a first layer, contacting the first source / drain pattern and the second source / drain pattern; a second layer in contact with the first blocking electrode; and a third layer, located between the first layer and the second layer, The dielectric material in the third layer is different from the dielectric material in the first layer, the dielectric material in the second layer, and the dielectric material in the gate dielectric layer. 11 . The semiconductor device of claim 9 , wherein the blocking dielectric layer contacts top surfaces of the plurality of blocking semiconductor patterns and bottom surfaces of the plurality of blocking semiconductor patterns.

12. The semiconductor device according to claim 9, further comprising: a plurality of gate spacers overlapping the plurality of blocking semiconductor patterns, The blocking dielectric layer is in contact with the plurality of gate spacers.

13. The semiconductor device according to claim 12, further comprising: a gate capping pattern located between the plurality of gate spacers, Wherein, the gate capping pattern is in contact with the blocking dielectric layer and the first blocking electrode.

14. The semiconductor device according to claim 9, further comprising: a first active pattern overlapping the first blocking electrode; a second active pattern spaced apart from the first active pattern; a second blocking electrode overlapping the second active pattern; as well as The barrier electrode separation layer is located between the first barrier electrode and the second barrier electrode.

15. The semiconductor device according to claim 14, wherein: applying a negative voltage to the first blocking electrode, and A positive voltage is applied to the second blocking electrode.

16. The semiconductor device according to claim 15, wherein: The first source / drain pattern, the second source / drain pattern, and the third source / drain pattern include p-type impurities.

17. The semiconductor device according to claim 9, wherein: A first portion of the blocking dielectric layer is located above the plurality of blocking semiconductor patterns, and A second portion of the blocking dielectric layer is located between the plurality of blocking semiconductor patterns.

18. The semiconductor device according to claim 17, wherein: The first portion of the blocking dielectric layer has a U-shape.

19. A semiconductor device comprising: a first source / drain pattern; a second source / drain pattern and a third source / drain pattern, adjacent to the first source / drain pattern; a plurality of semiconductor patterns, located between the first source / drain pattern and the third source / drain pattern; a gate dielectric layer, contacting the plurality of semiconductor patterns; a gate electrode, contacting the gate dielectric layer; a gate contact portion electrically connected to the gate electrode; a plurality of blocking semiconductor patterns, located between the first source / drain pattern and the second source / drain pattern; a blocking dielectric layer in contact with the plurality of blocking semiconductor patterns; a blocking electrode in contact with the blocking dielectric layer; a blocking electrode contact portion electrically connected to the blocking electrode; a plurality of gate spacers in contact with the blocking dielectric layer; a gate capping pattern in contact with a top surface of the blocking electrode and the blocking dielectric layer; as well as An active contact portion is electrically connected to a corresponding source / drain pattern among the first source / drain pattern, the second source / drain pattern and the third source / drain pattern, wherein: The blocking dielectric layer comprises a first layer, a second layer and a third layer, The first layer contacts the first source / drain pattern, the second source / drain pattern, and the plurality of blocking semiconductor patterns, The second layer is in contact with the blocking electrode, The third layer is located between the first layer and the second layer, The first layer and the second layer include oxides, and The third layer includes nitride.

20. The semiconductor device according to claim 19, wherein The first layer, the second layer, and the third layer are in contact with the gate capping pattern, and The first layer contacts the plurality of gate spacers.

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