Semiconductor structure and methods for forming semiconductor structures

Abstract

A semiconductor structure and its formation method are disclosed. The structure includes: a substrate comprising a device region and a non-device region; the substrate comprising a first substrate, a second substrate, and an insulating layer sequentially stacked between the first substrate and the second substrate; the insulating layer comprising a first insulating portion located in the device region and a second insulating portion located in the non-device region, wherein the first insulating portion and the second insulating portion are made of different materials and the thermal conductivity of the first insulating portion is greater than that of the second insulating portion; and a device structure located in the device region, the device structure being formed on the side of the first substrate facing away from the insulating layer and corresponding vertically to the first insulating portion. The heat dissipation problem of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] In an era of rapid development in the information technology industry, 5G applications are becoming increasingly widespread, and research investment in 6G continues to increase, leading to higher demands on integrated circuits. Continuous improvements in process technology and innovations in device structures have resulted in shrinking device feature sizes, increasing integration density, reducing power consumption, and improving performance. However, with the shrinking feature sizes, the interactions within and between devices via the substrate in bulk silicon technology are becoming increasingly severe, leading to a series of new challenges related to materials, device physics, device structure, and process technology. Devices based on bulk silicon materials exhibit substrate interactions between devices, i.e., latch-up effects, which affect device performance.

[0003] To address the latch-up effect, existing technologies often use silicon-on-insulator (SiI) wafers as substrates. However, using SiI wafers as substrates can easily lead to self-heating, which can also affect device performance. Currently, there are three main methods to improve the self-heating effect: first, increasing the device area; second, increasing the thickness of the top-layer second substrate silicon or decreasing the thickness of the buried silicon dioxide layer; and third, creating bulk contacts to provide heat dissipation pathways. However, the improvement effect of these three methods is limited and not conducive to improving chip performance.

[0004] Therefore, how to solve the self-heating effect of silicon on insulators is a technical problem that needs to be addressed continuously. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, thereby solving the self-heating effect of silicon on insulator.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate, the substrate including a device region and a non-device region, the substrate including a first substrate, a second substrate, and an insulating layer located between the first substrate and the second substrate, the insulating layer including a first insulating portion located in the device region and a second insulating portion located in the non-device region, wherein the first insulating portion and the second insulating portion are made of different materials and the thermal conductivity of the first insulating portion is greater than that of the second insulating portion; and a device structure located in the device region, the device structure being formed on the side of the first substrate facing away from the insulating layer and corresponding vertically to the first insulating portion.

[0007] Optionally, the resistivity of the first insulating part is greater than the resistivity of the second insulating part.

[0008] Optionally, the material of the first insulating portion includes aluminum nitride or silicon nitride; the material of the second insulating portion includes silicon oxide.

[0009] Optionally, the thickness of the first insulating portion is the same as the thickness of the second insulating portion.

[0010] Optionally, the thickness of the second substrate is less than the thickness of the first substrate.

[0011] Optionally, the device structure includes a transistor, a diode, or a triode; the transistor includes: a gate structure located on a first substrate and source / drain doped regions located on both sides of the gate structure within the first substrate.

[0012] Accordingly, the present invention also provides a method for forming the semiconductor structure, comprising:

[0013] Step S1: Forming a substrate, comprising: providing a first substrate; forming an insulating layer on one side of the first substrate, the insulating layer comprising a first insulating portion and a second insulating portion, wherein the material of the first insulating portion is different from that of the second insulating portion and the thermal conductivity of the first insulating portion is greater than that of the second insulating portion; providing a second substrate; bonding the second substrate to the insulating layer; thinning the side of the first substrate opposite to the insulating layer to form the substrate; wherein the substrate comprises a device region and a non-device region, the first insulating portion being located in the device region and the second insulating portion being located in the non-device region;

[0014] Step S2: A device structure is formed in the device region. The device structure is formed on the side of the first substrate facing away from the insulating layer, and the device structure corresponds vertically to the first insulating portion.

[0015] Optionally, forming an insulating layer on a first substrate includes: forming a second insulating material layer on the first substrate; removing the second insulating material layer from the device region and forming a second insulating portion in a non-device region; forming a first insulating material layer covering the device region and the second insulating portion; planarizing the first insulating material layer until the surface of the second insulating portion is exposed, and forming the first insulating portion on the first substrate in the device region.

[0016] Optionally, before forming an insulating layer on the first substrate, the method further includes: forming an alignment mark groove in a non-device area of ​​the first substrate, wherein when the second insulating portion is formed on the first substrate, the alignment mark groove is also filled with the second insulating portion.

[0017] Optionally, the side of the first substrate facing away from the insulating layer is thinned, specifically including: thinning the side of the first substrate facing away from the insulating layer until the second insulating portion within the alignment mark groove is exposed, thereby forming the substrate.

[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0019] In the semiconductor structure of the present invention, the first insulating portion is located in the device region and at the bottom of the device structure. The material of the first insulating portion is different from that of the second insulating portion, and the thermal conductivity of the first insulating portion is greater than that of the second insulating portion. Therefore, the first insulating portion can easily conduct the heat generated by the device structure and conduct it out through the second substrate, thereby fundamentally improving the self-heating effect of the substrate and thus improving the performance of the semiconductor structure.

[0020] Furthermore, the resistivity of the first insulating portion is greater than that of the second insulating portion. Because of its higher resistivity, the first insulating portion maintains the insulation effect between the first and second substrates, preserving the isolation between the device regions and eliminating latch-up effects.

[0021] In the method of forming the technical solution of the present invention, the first insulating portion is formed in the device region and at the bottom of the device structure. The material of the first insulating portion is different from that of the second insulating portion, and the thermal conductivity of the first insulating portion is greater than that of the second insulating portion. Therefore, the first insulating portion can easily conduct the heat generated by the device structure and conduct it out through the second substrate, thereby fundamentally improving the self-heating effect of the substrate and improving the performance of the semiconductor structure. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a semiconductor structure in one embodiment;

[0023] Figures 2 to 8 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0024] As described in the background section, there are still many problems to be solved regarding silicon-on-insulator (SiO2) as a substrate. These will be explained in detail below with reference to the accompanying drawings.

[0025] Figure 1This is a schematic diagram of a semiconductor structure in one embodiment. The substrate of the semiconductor structure is a silicon-on-insulator (SiI) wafer, which has a three-layer structure: a first substrate 100, a second substrate 102, and an insulating layer 101 located between the first substrate 100 and the second substrate 102. The top layer, the second substrate 102, is the area where the device is fabricated. The middle insulating layer 101 is buried silicon dioxide, and the bottom layer, the first substrate 100, is the substrate silicon. Due to the isolation effect of the silicon dioxide insulating layer 101 and the isolation structure 105, there is no substrate interaction between the device areas, i.e., no latch-up effect, which can effectively improve the performance of the device. However, due to the poor thermal conductivity of the buried silicon dioxide, the heat generated during device operation is not easily conducted away, forming a temperature accumulation and leading to a self-heating effect. The self-heating effect causes the temperature of the top layer, the second substrate 102, to rise. As the temperature of the silicon device area of ​​the top layer, the second substrate 102, rises sharply, lattice scattering is enhanced, and the electron carrier mobility decreases. The output characteristic curve of the device shows a negative conductivity effect where the leakage current decreases as the voltage increases when the leakage voltage is large.

[0026] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure and a method for forming the semiconductor structure. By disposing a first insulating portion in the device region and at the bottom of the device structure, the material of the first insulating portion is different from that of the second insulating portion, and the thermal conductivity of the first insulating portion is greater than that of the second insulating portion. Therefore, the first insulating portion can easily conduct the heat generated by the device structure and conduct it away through the second substrate, fundamentally improving the self-heating effect of the substrate and thereby enhancing the performance of the semiconductor structure.

[0027] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0028] Figures 2 to 8 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0029] The method for forming the semiconductor structure includes:

[0030] Step S1: Forming a substrate, comprising: providing a first substrate; forming an insulating layer on one side of the first substrate, the insulating layer comprising a first insulating portion and a second insulating portion, wherein the material of the first insulating portion is different from that of the second insulating portion and the thermal conductivity of the first insulating portion is greater than that of the second insulating portion; providing a second substrate; bonding the second substrate to the insulating layer; thinning the side of the first substrate opposite to the insulating layer to form the substrate; wherein the substrate comprises a device region I and a non-device region II, the first insulating portion being located in the device region I and the second insulating portion being located in the non-device region II.

[0031] Step S2: A device structure is formed in the device region. The device structure is formed on the side of the first substrate facing away from the insulating layer, and the device structure corresponds vertically to the first insulating portion.

[0032] Wherein, device region I is the region that forms the device structure. In a specific embodiment, the device structure includes transistors, diodes, or triodes, etc.; non-device region II is the region that forms other non-devices, such as circuit connections, resistors, capacitors, inductors, etc.

[0033] Please refer to the substrate formation process. Figures 2 to 6 .

[0034] Please refer to Figure 2 Provide a first substrate 200; etch the first substrate 200 of the non-device region II, and form an alignment mark groove 201 within the first substrate 200.

[0035] In this embodiment, the material of the first substrate 200 is silicon.

[0036] In other embodiments, the material of the first substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0037] A method for etching a first substrate 200 of a non-device region II to form an alignment mark groove 201 within the first substrate 200 includes: forming a patterned mask layer (not shown) on the first substrate 200, the patterned mask layer exposing a portion of the surface of the first substrate 200 of the non-device region II; etching the first substrate 200 using the patterned mask layer as a mask to form the alignment mark groove 201 within the first substrate 200.

[0038] The process for etching the first substrate 200 of the non-device region II includes a dry etching process.

[0039] Please refer to Figure 3 A second insulating portion 203 is formed on the first substrate 200.

[0040] The method of forming the second insulating portion 203 includes: forming a second insulating portion material layer (not shown) on a first substrate 200 and within an alignment mark groove 201; removing the second insulating portion material layer of device region I; and forming the second insulating portion 203 on a first substrate 200 in a non-device region II and within an alignment mark groove 201, wherein the second insulating portion 203 has an opening 204 that exposes the surface of the first substrate 200 of device region I.

[0041] The material of the second insulating portion 203 includes an insulating material. Preferably, the material of the second insulating portion 203 includes silicon oxide.

[0042] The process for forming the second insulating part includes chemical vapor deposition or physical vapor deposition.

[0043] Please refer to Figure 4 A first insulating portion 205 is formed on the first substrate 200 of the device region I.

[0044] The method of forming the first insulating portion 205 includes: forming a first insulating material layer (not shown) inside the opening 204 of the device region I and on the second insulating portion 203, the first insulating material layer covering the device region I and the second insulating portion 203; planarizing the first insulating material layer until the surface of the second insulating portion 203 is exposed, and forming the first insulating portion 205 on the first substrate 200 of the device region I.

[0045] In this embodiment, the top surface of the first insulating material layer located within the opening 204 is higher than the depth of the opening 204, so the first insulating portion 205 is formed after the first insulating material layer is planarized.

[0046] The first insulating portion 205 and the second insulating portion 203 constitute an insulating layer between the first substrate 200 and the subsequent second substrate.

[0047] In this embodiment, the material of the first insulating part 205 is different from the material of the second insulating part 203.

[0048] In this embodiment, the thermal conductivity of the first insulating part 205 is greater than that of the second insulating part 203, so the first insulating part 205 has better thermal conductivity and stronger heat conduction ability, and can easily conduct away the heat generated by the device structure formed in the device region I from the first substrate 200, so as to avoid the situation of temperature accumulation and self-heating effect.

[0049] As one embodiment, when the second insulating portion is preferably silicon oxide, the thermal conductivity of the first insulating portion 205 is greater than 1.4 W·m. -1 ·℃ -1 .

[0050] In this embodiment, the resistivity of the first insulating portion 205 is greater than the resistivity of the second insulating portion 203. The higher resistivity of the first insulating portion 205 allows it to maintain the insulation effect between the first substrate 200 and the second substrate 300, preserving the isolation between device region I and the second substrate and eliminating latch-up effects. Preferably, the resistivity of the first insulating portion 205 is greater than 10⁻⁶. 4 Ω·cm, and is greater than the resistivity of the second insulating part.

[0051] In one specific embodiment, the material of the first insulating portion 205 includes aluminum nitride or silicon nitride. The material of the first insulating portion 205 includes aluminum nitride. The materials of the first insulating portion and the second insulating portion are different, and the resistivity and thermal conductivity of the material of the first insulating portion are both greater than those of the material of the second insulating portion. Those skilled in the art can choose the specific materials of the first insulating portion and the second insulating portion according to the actual situation, and no limitation is made here.

[0052] In this embodiment, the thickness of the first insulating portion 205 is the same as the thickness of the second insulating portion 203.

[0053] Preferably, the thickness of the first insulating portion 205 and the thickness of the second insulating portion 203 are both 2000 angstroms, that is, the thickness of the insulating layer is 2000 angstroms. Those skilled in the art can set a suitable thickness for the insulating layer according to actual conditions, and this is not limited here.

[0054] In this embodiment, the insulating layer includes a first insulating portion 205 located in device region I and a second insulating portion 203 located in non-device region II. The insulating layer is composed of two parts. The second insulating portion 203 does not require high thermal conductivity, thus the material cost of the second insulating portion 203 is low. The insulating layer can have good thermal conductivity to device region I while maintaining a low cost.

[0055] In other embodiments, the insulating layer can be formed solely from the material of the first insulating portion, so that both the device region and the non-device region have good thermal conductivity, effectively improving the self-heating effect of the substrate.

[0056] Please refer to Figure 5 A second substrate 300 is provided; the second substrate 300 is bonded to the insulating layer, the insulating layer being located between the first substrate 200 and the second substrate 300.

[0057] In this embodiment, the material of the second substrate 300 is silicon.

[0058] In other embodiments, the material of the second substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0059] Bonding the second substrate 300 to the insulating layer includes: polishing the surface of the insulating layer and the surface of the second substrate 300; after polishing the surface of the insulating layer and the surface of the second substrate 300, bonding the second substrate 300 to the insulating layer; and performing heat treatment on the bonded second substrate 300 and the insulating layer to complete the bonding of the second substrate 300 to the insulating layer.

[0060] In this embodiment, the thickness of the first insulating portion 205 is the same as the thickness of the second insulating portion 203. This allows the insulating layer to provide a surface with high flatness during bonding, facilitating the formation of strong chemical bonds when bonding with the second substrate 300.

[0061] Please refer to Figure 6 After bonding the second substrate 300 to the insulating layer, the side of the first substrate 200 facing away from the insulating layer is thinned until the second insulating portion 203 within the alignment mark groove 201 is exposed, thus forming a substrate. The substrate comprises: a first substrate 200, an insulating layer, and a second substrate 300 stacked sequentially, with the insulating layer located between the first substrate 200 and the second substrate 300.

[0062] It should be noted that the thinned surface of the first substrate 200 is the side facing away from the insulating layer, and the thinned first substrate 200 exposes the surface of the second insulating portion 203 aligned with the bottom of the marking groove 201.

[0063] The process of thinning the first substrate 200 includes chemical mechanical polishing or etching.

[0064] In this embodiment, the thickness of the second substrate 300 is greater than the thickness of the first substrate 200.

[0065] The second substrate 300 has a thickness in the millimeter range. The thickness of the second substrate 300 is relatively thick, serving as a structural support for forming the device structure on the first substrate 200. The first substrate 200 is used to form the device structure. The thickness of the first substrate 200 is relatively thin, ranging from the micrometer range, with the appropriate thickness selected according to the device requirements of the chip, within the range of 0.01 micrometers to 10 micrometers.

[0066] Please refer to Figure 7 An isolation structure 208 is formed within the thinned first substrate 200. The isolation structure penetrates the first substrate 200 and contacts the insulating layer. The isolation structure 208 surrounds the first substrate 200 of the device region I.

[0067] In this embodiment, the first insulating portion 205 extends to the bottom of the isolation structure 208.

[0068] The method for forming the isolation structure 208 includes: forming a patterned mask layer (not shown) on a first substrate 200, the patterned mask layer exposing a portion of the surface of the first substrate 200 surrounding the device region I; etching the first substrate 200 using the patterned mask layer as a mask to expose the surface of an insulating layer, forming an isolation opening in the first substrate 200; and forming the isolation structure 208 within the isolation opening.

[0069] In this embodiment, the material of the isolation structure 208 includes silicon oxide.

[0070] Please refer to Figure 8 Step S2: A device structure is formed in device region I. The device structure is formed on the side of the first substrate 200 facing away from the insulating layer, and the device structure corresponds vertically to the first insulating portion 205.

[0071] The device structure includes transistors, diodes, or triodes.

[0072] In this embodiment, the device structure includes a transistor, which includes a gate structure 206 located on a first substrate 200 and source / drain doped regions 207 located on both sides of the gate structure 206 within the first substrate 200.

[0073] The gate structure 206 includes: a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0074] In one embodiment, the material of the gate dielectric layer includes silicon oxide or a low-k (K less than 3.9) material; the material of the gate layer includes polysilicon.

[0075] In another embodiment, the gate dielectric layer is made of a high dielectric constant material with a dielectric constant greater than 3.9. The gate dielectric layer is a high-K (K greater than 3.9) dielectric material, including hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide; LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitrides, or other suitable materials; the gate layer is made of a metal, including tungsten.

[0076] The first insulating portion 205 is located in device region I and at the bottom of the device structure. The material of the first insulating portion 205 is different from that of the second insulating portion 203, and the thermal conductivity of the first insulating portion 205 is greater than that of the second insulating portion 203. Therefore, the first insulating portion 205 can easily conduct the heat generated by the device structure and conduct it out through the second substrate 300, fundamentally improving the self-heating effect of the substrate and thus improving the performance of the semiconductor structure.

[0077] Accordingly, the present invention also provides a semiconductor structure, please refer to [link / reference needed]. Figure 7 ,include:

[0078] The substrate includes a device region I and a non-device region II. The substrate includes a first substrate 200, a second substrate 300, and an insulating layer located between the first substrate 200 and the second substrate 300, which are stacked sequentially. The insulating layer includes a first insulating portion 205 located in the device region I and a second insulating portion 203 located in the non-device region II. The first insulating portion 205 and the second insulating portion 203 are made of different materials, and the thermal conductivity of the first insulating portion 205 is greater than that of the second insulating portion 203.

[0079] The device structure is located in the device region I. The device structure is formed on the side of the first substrate 200 facing away from the insulating layer and corresponds vertically to the first insulating portion 205.

[0080] In this embodiment, the resistivity of the first insulating portion 205 is greater than the resistivity of the second insulating portion 203.

[0081] In this embodiment, the material of the first insulating portion 205 includes aluminum nitride or silicon nitride; the material of the second insulating portion 203 includes silicon oxide.

[0082] In this embodiment, the thickness of the first insulating portion 205 is the same as the thickness of the second insulating portion 203.

[0083] In this embodiment, the thickness of the second substrate 300 is greater than the thickness of the first substrate 200.

[0084] In this embodiment, the device structure includes a transistor, a diode, or a triode; the transistor includes a gate structure 206 located on a first substrate 200 and source / drain doped regions 207 located on both sides of the gate structure 206 within the first substrate 200.

[0085] The first insulating portion 205 is located in device region I and at the bottom of the device structure. The thermal conductivity of the first insulating portion 205 is greater than that of the second insulating portion 203. Therefore, the first insulating portion 205 can easily conduct the heat generated by the device structure and conduct it out through the second substrate 300, thereby fundamentally improving the self-heating effect of the substrate and thus improving the performance of the semiconductor structure.

[0086] The materials, formation process, working principle, specific implementation method and beneficial effects of the semiconductor structure involved in the embodiments of the present invention can be found in the semiconductor structure formation method of the embodiments of the present invention, and will not be repeated here.

[0087] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate comprising a device region and a non-device region, the substrate comprising a first substrate, a second substrate, and an insulating layer disposed between the first substrate and the second substrate in sequence, the insulating layer comprising a first insulating portion disposed in the device region and a second insulating portion disposed in the non-device region, wherein the first insulating portion and the second insulating portion are made of different materials and the thermal conductivity of the first insulating portion is greater than that of the second insulating portion, the insulating layer is located on the surface of the first substrate and is bonded to the second substrate; the second insulating portion is located on the first substrate in the non-device region and in an alignment mark groove within the first substrate in the non-device region, the second insulating portion located in the alignment mark groove penetrating the first substrate; The device structure is located in the device region and is formed on the side of the first substrate facing away from the insulating layer, and is vertically corresponding to the first insulating portion.

2. The semiconductor structure as described in claim 1, characterized in that, The resistivity of the first insulating part is greater than that of the second insulating part.

3. The semiconductor structure as described in claim 1, characterized in that, The material of the first insulating part includes aluminum nitride or silicon nitride; the material of the second insulating part includes silicon oxide.

4. The semiconductor structure as described in claim 1, characterized in that, The thickness of the first insulating portion is the same as the thickness of the second insulating portion.

5. The semiconductor structure as described in claim 1, characterized in that, The thickness of the second substrate is greater than the thickness of the first substrate.

6. The semiconductor structure as described in claim 1, characterized in that, The device structure includes a transistor, a diode, or a triode; the transistor includes a gate structure located on a first substrate and source / drain doped regions located on both sides of the gate structure within the first substrate.

7. A method for forming a semiconductor structure as described in any one of claims 1 to 6, characterized in that, include: Step S1: Forming a substrate, wherein forming the substrate includes: Provide the first base; An insulating layer is formed on one side of the first substrate. The insulating layer includes a first insulating portion and a second insulating portion, wherein the material of the first insulating portion is different from that of the second insulating portion and the thermal conductivity of the first insulating portion is greater than that of the second insulating portion. Provide a second substrate; The second substrate is bonded to the insulating layer; The first substrate is thinned on the side facing away from the insulating layer to form the substrate, wherein the substrate includes a device region and a non-device region, the first insulating portion is located in the device region, and the second insulating portion is located in the non-device region; Step S2: A device structure is formed in the device region. The device structure is formed on the side of the first substrate facing away from the insulating layer, and the device structure corresponds vertically to the first insulating portion.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, An insulating layer is formed on a first substrate, comprising: A second insulating material layer is formed on the first substrate; the second insulating material layer in the device region is removed, and a second insulating portion is formed in the non-device region; A first insulating material layer is formed, which covers the device region and the second insulating portion; The first insulating layer is planarized until the surface of the second insulating layer is exposed, and the first insulating layer is formed on the first substrate in the device region.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, Before forming an insulating layer on the first substrate, the method further includes: forming an alignment mark groove in a non-device area of ​​the first substrate, wherein when the second insulating portion is formed on the first substrate, the alignment mark groove is also filled with the second insulating portion.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, Thinning the side of the first substrate away from the insulating layer specifically includes: thinning the side of the first substrate away from the insulating layer until the second insulating portion within the alignment mark groove is exposed, thereby forming the substrate.

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