Double-gate radio frequency switch device

Abstract

The invention discloses a double-gate radio frequency switch device, and relates to the technical field of radio frequency switches. The SOI device comprises a substrate layer, a buried oxide layer and a device layer of an SOI wafer, the device layer comprises a source end, a drain end, a body end I, a body end II, a gate end I and a gate end II; the source end and the drain end are distributed on the two sides of the single NMOS switching device; the body end I, the body end II, the gate end I and the gate end II are distributed between the source end and the drain end; the gate end I is distributed at the upper part of the body end I; and the gate end II is distributed on the body end II. According to the scheme of the double-gate NMOS switch device designed based on the SOI process, the layout area of a radio frequency switch chip can be effectively reduced, the radio frequency layout area can be reduced by 30%-35% under the condition of the same design index, the chip cost is effectively reduced, and the competitiveness of the chip is improved. Meanwhile, the conduction impedance of the double-gate NMOS switching device is obviously reduced, and the low-frequency insertion loss performance of the radio frequency switching circuit is effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of radio frequency switches, and in particular relates to a dual-gate radio frequency switch device. Background Art

[0002] With the continuous development of wireless mobile communication technology, RF switches are playing an increasingly important role in multi-band front-end modules and antenna tuners; especially in the multi-scenario application of antenna tuners, the application of small-size antenna tuners has gradually become a new trend in the industry.

[0003] Taking the industry-standard SP4T antenna tuner as an example, the package size has been continuously reduced from 1.5mm*1.5mm to 1.5mm*1.1mm, and then to 1.3mm*0.95mm. The reduction in package size also poses a great challenge to chip design. The process node of the SOI process determines the area limit of the chip layout. If the design level wants to break through this limit, it can only use new solutions in the layout design of the switch device. The dual-gate NMOS switch device solution based on the SOI process design of the present invention can not only effectively reduce the layout area of ​​the RF switch chip, but also reduce the RF layout area by 30% to 35% under the same design indicators, effectively reducing chip costs and improving chip competitiveness; at the same time, the on-resistance of the dual-gate NMOS switch device will also be significantly reduced, effectively improving the low-frequency insertion loss performance of the RF switch circuit. Summary of the invention

[0004] The present invention provides a dual-gate radio frequency switch device. Compared with the single-gate NMOS switch device in the prior art, the gate terminal is changed from one to two, and the body terminal is changed from one to two, so the overall layout area of ​​the dual-gate NMOS switch device will increase by 15% to 20% compared with the layout area of ​​the single-gate NMOS switch device; at the same time, the voltage resistance of the dual-gate NMOS switch device is twice that of the single-gate NMOS switch device, so under the same voltage resistance conditions, the number of dual-gate NMOS switch devices used can be reduced by half, and the overall area will be reduced by 30% to 35%; compared with the single-gate NMOS switch device, the normalized on-resistance of the dual-gate NMOS switch device in actual design will be 5% smaller; in summary, the disadvantage of the traditional single-gate NMOS switch device with a large layout area is solved.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] A dual-gate radio frequency switch device of the present invention comprises a substrate layer, a buried oxide layer and a device layer of an SOI wafer;

[0007] The device layer includes a source terminal, a drain terminal, a body terminal 1, a body terminal 2, a gate terminal 1, and a gate terminal 2;

[0008] The source terminal and the drain terminal are distributed on both sides of a single NMOS switch device;

[0009] The body terminal 1, body terminal 2, gate terminal 1 and gate terminal 2 are distributed between the source terminal and the drain terminal, and the ports of the body terminal 1, body terminal 2, gate terminal 1 and gate terminal 2 correspond to each other one by one;

[0010] The gate terminal 1 is distributed on the upper part of the body terminal 1; the gate terminal 2 is distributed on the upper part of the body terminal 2.

[0011] Furthermore, a spacing is provided between the first gate terminal and the second gate terminal, and the spacing can be adjusted and optimized at the design level according to specific rules of the process.

[0012] Compared with the prior art, the present invention has the following beneficial effects:

[0013] (1) Compared with the plan view of the single-gate NMOS switch device in the prior art, the dual-gate NMOS switch device based on the SOI process of the present invention has two gate terminals instead of one, and two body terminals instead of one. Therefore, the overall layout area of ​​the dual-gate NMOS switch device will increase by 15% to 20% compared with the layout area of ​​the single-gate NMOS switch device.

[0014] (2) The voltage resistance of dual-gate NMOS switch devices is twice that of single-gate NMOS switch devices. Therefore, under the same voltage resistance conditions, the number of dual-gate NMOS switch devices used can be reduced by half, and the overall area can be reduced by 30% to 35%;

[0015] (3) Compared with a single-gate NMOS switch device, the normalized on-resistance of a dual-gate NMOS switch device in an actual design is 5% smaller;

[0016] (4) The on-resistance of the dual-gate NMOS switch device will also be significantly reduced, effectively improving the low-frequency insertion loss performance of the RF switch circuit.

[0017] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0019] Figure 1 It is a cross-sectional schematic diagram of a single-gate NMOS switch device based on SOI process in the prior art;

[0020] Figure 2It is a cross-sectional schematic diagram of a dual-gate NMOS switch device based on SOI process of the present invention;

[0021] Figure 3 It is a planar schematic diagram of a single-gate NMOS switch device based on SOI process in the prior art;

[0022] Figure 4 It is a schematic plan view of a dual-gate NMOS switch device based on SOI process of the present invention;

[0023] Figure 5 It is the equivalent relationship diagram of the withstand voltage performance of double-gate and single-gate NMOS switch devices under the same withstand voltage conditions;

[0024] In the accompanying drawings, the components represented by the reference numerals are listed as follows:

[0025] B-body terminal, B1-body terminal one, B2-body terminal two, G-gate terminal, G1-gate terminal one, G2-gate terminal two, D-drain terminal, S-source terminal. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] In the description of the present invention, it should be understood that the terms "two sides", "middle", "port", "spacing" and the like indicating orientation or positional relationship are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the components or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0028] like Figure 2 , Figure 4 As shown, the cross-sectional schematic diagram of the dual-gate NMOS switch device based on the SOI process of the present invention mainly includes three levels: the substrate layer of the SOI wafer, the buried oxide layer, and the device layer. The device layer mainly includes six parts: the source terminal S, the drain terminal D, the body terminal B1, the body terminal B2, the gate terminal G1, and the gate terminal G2; the source terminal S and the drain terminal D are distributed on both sides of a single NMOS switch device; the body terminal B1, the body terminal B2, the gate terminal G1, and the gate terminal G2 are distributed in the middle of the source terminal S and the drain terminal D, and the ports of the body terminal B1, the body terminal B2, the gate terminal G1, and the gate terminal G2 correspond to each other one by one; the gate terminal G1 is distributed on the upper part of the body terminal B1; the gate terminal G2 is distributed on the upper part of the body terminal B2.

[0029] There is a spacing between the first gate terminal G1 and the second gate terminal G2; this spacing can be adjusted and optimized at the design level according to specific rules of the process.

[0030] Figure 1 Figure 2 They are all profile drawings, showing cross sections, so the hierarchical information is more comprehensive. Figure 3 Figure 4 They are all plan views, showing the top view of the switch device;

[0031] like Figure 1 and Figure 3 As shown, a cross-sectional schematic diagram of a single-gate NMOS switch device based on SOI process in the prior art is not introduced in detail in the present invention; the prior art solution includes a gate terminal G and a body terminal B.

[0032] like Figure 4 As shown, the plan view of the dual-gate NMOS switch device based on SOI process of the present invention and Figure 3 Compared with the planar schematic diagram of the single-gate NMOS switch device of the prior art shown in FIG. 1 , the gate terminal is changed from one to two: G1 and G2, and the body terminal is changed from one to two: B1 and B2. Therefore, the overall layout area of ​​the dual-gate NMOS switch device will increase by 15% to 20% compared with the layout area of ​​the single-gate NMOS switch device; it depends on the actual layout design details. At the same time, the voltage resistance of the dual-gate NMOS switch device is twice that of the single-gate NMOS switch device, so under the same voltage resistance conditions, the number of dual-gate NMOS switch devices used can be reduced by half, and the overall area will be reduced by 30% to 35%. Specifically, Figure 5 Compared with the single-gate NMOS switch device, the normalized on-resistance of the dual-gate NMOS switch device in actual design is 5% smaller; the specific embodiment is shown in the following Table 1:

[0033]

[0034] Table 1: Measured analysis of normalized on-resistance of dual-gate and single-gate NMOS switch devices in actual design solutions

[0035] The dual-gate NMOS switch device solution designed based on the SOI process of the present invention can not only effectively reduce the layout area of ​​the RF switch chip, but also reduce the RF layout area by 30% to 35% under the same design indicators, effectively reduce the chip cost and improve the competitiveness of the chip; at the same time, the on-resistance of the dual-gate NMOS switch device will also be significantly reduced, effectively improving the low-frequency insertion loss performance of the RF switch circuit.

[0036] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A dual-gate radio frequency switch device, characterized in that: Including the substrate layer, buried oxide layer and device layer of the SOI wafer; The device layer includes a source terminal (S), a drain terminal (D), a body terminal 1 (B1), a body terminal 2 (B2), a gate terminal 1 (G1), and a gate terminal 2 (G2); The source terminal (S) and the drain terminal (D) are distributed on both sides of a single NMOS switch device; The body terminal 1 (B1), the body terminal 2 (B2), the gate terminal 1 (G1) and the gate terminal 2 (G2) are distributed between the source terminal (S) and the drain terminal (D), and the ports of the body terminal 1 (B1), the body terminal 2 (B2), the gate terminal 1 (G1) and the gate terminal 2 (G2) correspond to each other one by one; The gate terminal 1 (G1) is distributed on the upper part of the body terminal 1 (B1); the gate terminal 2 (G2) is distributed on the upper part of the body terminal 2 (B2).

2. A dual-gate radio frequency switch device according to claim 1, characterized in that: A gap is provided between the gate terminal 1 (G1) and the gate terminal 2 (G2).

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