High-voltage MOSFET device and preparation method thereof

Abstract

The invention provides a high-voltage MOSFET device and a preparation method thereof, and the method comprises the steps: forming a high-voltage region gate oxide layer which is flush with the top surface of a polycrystalline silicon dummy gate layer in a low-voltage region in a high-voltage region of the device, then carrying out the thinning, removing the polycrystalline silicon dummy gate layer, and forming a low-voltage region metal gate in a formed U-shaped groove, therefore, the problem that in the prior art, the height of a gate structure of a high-voltage device affects the planarization process of a low-voltage region dummy gate structure is solved, then a second interlayer dielectric layer is formed on a low-voltage region metal gate and a high-voltage region gate oxide layer, and then a high-voltage region metal gate is formed on the second interlayer dielectric layer above the corresponding position of the high-voltage region gate oxide layer. The high-voltage region gate oxide layer and the second interlayer dielectric layer form an effective oxide thickness required by the high-voltage region of the high-voltage MOSFET device, and the process flow is simple.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a high-voltage MOSFET device and a preparation method thereof. Background Art

[0002] With the development of semiconductor technology, high dielectric constant (abbreviated as high-K) materials are usually used as gate dielectric layers in the gate structures of semiconductor devices with high process nodes, and metals are used as gate electrodes to form high-K metal gate structures (HKMG, High-K Metal Gate) to avoid the Fermi level pinning effect and boron penetration effect between high-K materials and traditional gate electrode materials, thereby reducing the leakage current of semiconductor devices.

[0003] The gate structure of HKMG is usually realized by a gate replacement process, that is, a dummy gate structure is first formed in the gate structure formation area, and after all the front processes before HKMG are completed, the dummy gate structure is removed, a U-shaped groove is formed in the dummy gate structure removal area, and then HKMG is formed in the U-shaped groove.

[0004] High-voltage MOSFET (HV-MOSFET) requires a very thick effective oxide thickness (EOT) to withstand ultra-high operating voltage, so the gate height of high-voltage MOSFET devices is much higher than that of general components. In HKMG processes below 28nm, chemical mechanical polishing (CMP) is generally used to flatten the pseudo-gate structure and then remove it. At this time, the gate height of the high-voltage device is relatively high, which will affect the CMP load. For this reason, the substrate of the preset depth in the high-voltage area is generally etched and removed first, and then the effective oxide thickness required for the high-voltage device is formed on the substrate to reduce the CMP load when thinning the pseudo-gate structure. The process flow is relatively complicated. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a high-voltage MOSFET device and a preparation method thereof, which are used to solve the problem that the gate structure height of the high-voltage device in the prior art affects the planarization process of the pseudo gate structure in the low-voltage area, and by first etching away the substrate to a preset depth in the high-voltage area, and then forming the effective oxide thickness required for the high-voltage device on the substrate, thereby reducing the CMP load when thinning the pseudo gate structure and the problem that the process flow is relatively complicated.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a high-voltage MOSFET device, the high-voltage MOSFET device comprising: a semiconductor substrate, a high-voltage region gate structure and a low-voltage region gate structure located on the semiconductor substrate; the high-voltage region gate structure comprises, from bottom to top, a high-voltage region gate oxide layer, a second interlayer dielectric layer and a high-voltage region metal gate, the low-voltage region gate structure comprises a U-shaped low-voltage region gate oxide layer, a low-voltage region metal gate filled inside the U-shaped low-voltage region gate oxide layer, and a dummy gate oxide layer located at the lower part of the outer part of the U-shaped low-voltage region gate oxide layer; wherein the top surface of the high-voltage region gate oxide layer is flush with the top surface of the low-voltage region gate structure, a first interlayer dielectric layer is filled between the high-voltage region gate oxide layer and the low-voltage region gate structure, and the second interlayer dielectric layer is also formed on the low-voltage region gate structure;

[0007] It also includes: an etch stop layer; the etch stop layer is formed respectively on the outer side wall of the gate oxide layer in the high voltage area, the outer side wall of the gate structure in the low voltage area, and between the first interlayer dielectric layer and the semiconductor substrate.

[0008] Optionally, the high-voltage MOSFET device further includes sidewalls, which are respectively formed between an outer sidewall of the high-voltage region gate oxide layer and the etch stop layer, and between an outer sidewall of the low-voltage region gate structure and the etch stop layer.

[0009] Optionally, the high-voltage MOSFET device further includes:

[0010] A shallow trench isolation structure formed in the semiconductor substrate, wherein the shallow trench isolation structure isolates the high-voltage region gate structure from the low-voltage region gate structure;

[0011] A third interlayer dielectric layer, formed on the second interlayer dielectric layer and covering the high voltage area metal gate;

[0012] A first lead-out structure that penetrates the third interlayer dielectric layer and contacts the high-voltage area metal gate, and a plurality of second lead-out structures that penetrate the third interlayer dielectric layer, the second interlayer dielectric layer, the first interlayer dielectric layer and the etch stop layer and contact the source and / or drain in the semiconductor substrate.

[0013] The present invention also provides a method for preparing a high-voltage MOSFET device, characterized in that the preparation method comprises:

[0014] S1, providing a semiconductor substrate, wherein the semiconductor substrate comprises a high voltage region and a low voltage region, and a dummy gate oxide layer is formed on the semiconductor substrate;

[0015] S2, forming a polysilicon dummy gate layer covering the dummy gate oxide layer on the semiconductor substrate;

[0016] S3, removing the polysilicon dummy gate layer and the dummy gate oxide layer at a preset position in the high voltage region of the semiconductor substrate to form a trench at the preset position;

[0017] S4, forming a high voltage region gate oxide layer that fills the trench;

[0018] S5, etching the polysilicon pseudo gate layer and the pseudo gate oxide layer by using a photolithography process and in combination with a hard mask layer, retaining the polysilicon pseudo gate layer and the pseudo gate oxide layer at a preset position in the low voltage region; thereby, the high voltage region gate oxide layer and the hard mask layer located in the high voltage region form a high voltage region stacking structure, and the pseudo gate oxide layer, the polysilicon pseudo gate layer and the hard mask layer located in the low voltage region form a low voltage region stacking structure;

[0019] S6, forming an etching stop layer covering the upper surface of the obtained structure;

[0020] S7, forming a first interlayer dielectric layer on the etch stop layer, wherein the upper surface of the first interlayer dielectric layer is not lower than the top surface of the etch stop layer located on the high voltage region stack structure, and then thinning the first interlayer dielectric layer, the etch stop layer and the hard mask layer until the top surface of the high voltage region gate oxide layer and the top surface of the polysilicon pseudo gate layer are exposed;

[0021] S8, removing the polysilicon pseudo gate layer to form a U-shaped groove;

[0022] S9, forming a U-shaped low-voltage region gate oxide layer on the bottom wall and sidewalls of the U-shaped groove, and then forming a low-voltage region metal gate filling the U-shaped groove on the low-voltage region gate oxide layer;

[0023] S10, forming a second interlayer dielectric layer on the obtained structure, and then forming a high-voltage region metal gate on the second interlayer dielectric layer above a corresponding position of the high-voltage region gate oxide layer.

[0024] Optionally, the semiconductor substrate is a silicon substrate, and in step S4, a thermal oxidation process is used to form the high-voltage region gate oxide layer that fills the trench.

[0025] Optionally, in step S5, the method of etching the polysilicon dummy gate layer and the dummy gate oxide layer using a photolithography process in combination with a hard mask layer includes:

[0026] S51, forming a hard mask layer on the polysilicon dummy gate layer and the high voltage region gate oxide layer;

[0027] S52, forming a photoresist layer on the hard mask layer and patterning the photoresist layer, wherein the patterned photoresist layer covers the hard mask layer above the corresponding position of the gate oxide layer in the high voltage region and the hard mask layer at a preset position in the low voltage region;

[0028] S53, based on the patterned photoresist layer, etching and removing the hard mask layer, the polysilicon dummy gate layer and the dummy gate oxide layer that are not covered by the photoresist layer;

[0029] S54, removing the patterned photoresist layer.

[0030] Furthermore, the planar size of the hard mask layer above the corresponding position of the high-voltage region gate oxide layer covered by the patterned photoresist layer in step S52 is smaller than the planar size of the high-voltage region gate oxide layer.

[0031] Optionally, the hard mask layer is a composite stacked structure of a silicon nitride layer and a silicon oxide layer.

[0032] Optionally, in step S7, the upper surface of the first interlayer dielectric layer is not lower than the top surface of the etch stop layer located on the high voltage region stack structure, and then the first interlayer dielectric layer, the etch stop layer and the hard mask layer are thinned until the top surface of the high voltage region gate oxide layer and the top surface of the polysilicon dummy gate layer are exposed. The method includes:

[0033] S71, thinning the first interlayer dielectric layer by a chemical mechanical polishing process until a top surface of the etch stop layer located on the low-voltage region stack structure is exposed;

[0034] S72, removing the etch stop layer and the hard mask layer located above the corresponding position of the polysilicon pseudo gate layer, and the etch stop layer and the hard mask layer located above the corresponding position of the high voltage region gate oxide layer by using a photolithography and etching process;

[0035] S73, backfilling the first interlayer dielectric layer so that the top surface of the first interlayer dielectric layer is not lower than the top surface of the high voltage region gate oxide layer and the top surface of the polysilicon dummy gate layer;

[0036] S74, thinning the first interlayer dielectric layer by using a chemical mechanical polishing process until the top surface of the high voltage region gate oxide layer and the top surface of the polysilicon dummy gate layer are exposed.

[0037] Optionally, the material of the high voltage region metal gate includes titanium nitride.

[0038] Optionally, after step S10, the following steps are also included:

[0039] S11, forming a third interlayer dielectric layer on the second interlayer dielectric layer, and the third interlayer dielectric layer covers the high voltage area metal gate;

[0040] S12, forming a first lead-out structure penetrating the third interlayer dielectric layer and contacting the high-voltage area metal gate, and a plurality of second lead-out structures penetrating the third interlayer dielectric layer, the second interlayer dielectric layer, the first interlayer dielectric layer and the etch stop layer and contacting the source and / or drain in the semiconductor substrate.

[0041] Optionally, in step S10, while the high-voltage region metal gate is formed on the second interlayer dielectric layer above the corresponding position of the high-voltage region gate oxide layer, a metal resistor is formed at a preset position on the second interlayer dielectric layer to form a resistance structure of the high-voltage MOSFET device at the preset position.

[0042] Optionally, in step S6, before forming the etching stop layer covering the upper surface of the obtained structure, the step further includes forming sidewalls on the outer sidewalls of the high-pressure region stack structure and the outer sidewalls of the low-pressure region stack structure.

[0043] As described above, the high-voltage MOSFET device and its preparation method of the present invention first form a high-voltage region gate oxide layer flush with the top surface of the polysilicon pseudo gate layer in the low-voltage region in the high-voltage region of the device, then thin and remove the polysilicon pseudo gate layer, and form a low-voltage region metal gate in the formed U-shaped groove, thereby solving the problem of the gate structure height of the high-voltage device affecting the planarization process of the low-voltage region pseudo gate structure in the prior art, and then form a second interlayer dielectric layer on the low-voltage region metal gate and the high-voltage region gate oxide layer, and then form a high-voltage region metal gate on the second interlayer dielectric layer above the corresponding position of the high-voltage region gate oxide layer. The high-voltage region gate oxide layer and the second interlayer dielectric layer constitute an effective oxide thickness that meets the requirements of the high-voltage region of the high-voltage MOSFET device, and the process flow is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 Shown is a schematic cross-sectional structure diagram of a high-voltage MOSFET device of the present invention.

[0045] Figure 2 Shown is a schematic flow chart of a method for preparing a high-voltage MOSFET device of the present invention.

[0046] Figures 3 to 14 It shows a schematic diagram of the cross-sectional structure presented in each step of preparing a high-voltage MOSFET device according to the present invention.

[0047] Component number description

[0048] 10 Semiconductor substrate

[0049] 11 Pseudo-gate oxide layer

[0050] 12 Shallow Trench Isolation Structure

[0051] 13 Polysilicon dummy gate layer

[0052] 14 High voltage region gate oxide layer

[0053] 15 Sidewall

[0054] 16 Etch stop layer

[0055] 17 First interlayer dielectric layer

[0056] 18 Low voltage region gate oxide layer

[0057] 19 Low voltage area metal grid

[0058] 20 First hard mask layer

[0059] 21 Groove

[0060] 22 Silicon nitride layer

[0061] 23 Silicon oxide layer

[0062] 24 Photoresist layer

[0063] 25 U-shaped groove

[0064] 26 Second hard mask layer

[0065] 30 Second interlayer dielectric layer

[0066] 31 High voltage area metal grid

[0067] 32 third hard mask layer

[0068] 33 Third interlayer dielectric layer

[0069] 34 First lead structure

[0070] 35 Second lead structure

[0071] 36 The third lead structure

[0072] 37 Resistor Structure

[0073] 38 Low voltage area gate structure

[0074] 39 Metal resistor

[0075] Steps S1 to S10 DETAILED DESCRIPTION

[0076] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0077] See also Figures 1 to 14 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0078] This embodiment provides a high voltage MOSFET device, such as Figure 1 As shown, the high-voltage MOSFET device includes: a semiconductor substrate 10, a high-voltage region gate structure and a low-voltage region gate structure 38 located on the semiconductor substrate 10; the high-voltage region gate structure includes a high-voltage region gate oxide layer 14, a second interlayer dielectric layer 30 and a high-voltage region metal gate 31 from bottom to top, and the low-voltage region gate structure 38 includes a U-shaped low-voltage region gate oxide layer 18, a low-voltage region metal gate 19 filled in the U-shaped low-voltage region gate oxide layer 18, and a dummy gate oxide layer 11 located at the lower part of the U-shaped low-voltage region gate oxide layer 18; wherein the top surface of the high-voltage region gate oxide layer 14 is flush with the top surface of the low-voltage region gate structure 38, a first interlayer dielectric layer 17 is filled between the high-voltage region gate oxide layer 14 and the low-voltage region gate structure 38, and the second interlayer dielectric layer 30 is also formed on the low-voltage region gate structure 38;

[0079] It also includes: an etch stop layer 16; the etch stop layer 16 is formed on the outer sidewall of the high voltage region gate oxide layer 14, the outer sidewall of the low voltage region gate structure 38, and between the first interlayer dielectric layer 17 and the semiconductor substrate 10.

[0080] The high-voltage MOSFET device of this embodiment has an effective oxide thickness that meets the high voltage requirement of the high-voltage MOSFET device through the high-voltage region gate oxide layer and the second interlayer dielectric layer, and the process flow is simple.

[0081] As an example, the semiconductor substrate 10 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon carbide (SiC) substrate or other suitable semiconductor substrates known in the art, and the semiconductor substrate 10 may be pre-fabricated with a P-well and / or N-well and other required structural units.

[0082] As an example, Figure 1 As shown, the high-voltage MOSFET device further includes a sidewall 15, and the sidewall 15 is formed between the outer sidewall of the gate oxide layer 14 in the high-voltage region and the etch stop layer 16, and between the outer sidewall of the gate structure 38 in the low-voltage region and the etch stop layer 16. The sidewall 15 is used to protect the structure sandwiched between the sidewalls 15 in the low-voltage region and the gate oxide layer 14 in the high-voltage region from being damaged during the subsequent use of the device. The sidewall 15 can be a single layer or a composite film layer structure, including but not limited to one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0083] As an example, the thickness of the second interlayer dielectric layer 30 and the material of the second interlayer dielectric layer 30 can be adjusted according to the actual high voltage requirements, and no excessive limitation is made here, as long as the second interlayer dielectric layer 30 and the high voltage region gate oxide layer 14 can form an effective oxide thickness that meets the high voltage requirements of the device.

[0084] As an example, Figure 1 As shown, the high voltage MOSFET device also includes:

[0085] A shallow trench isolation structure 12 formed in the semiconductor substrate 10, wherein the shallow trench isolation structure 12 isolates the high-voltage region gate structure from the low-voltage region gate structure 38;

[0086] A third interlayer dielectric layer 33 is formed on the second interlayer dielectric layer 30 and covers the high voltage region metal gate 31;

[0087] A first lead-out structure 34 penetrates the third interlayer dielectric layer 33 and contacts the high-voltage area metal gate 31, and a plurality of second lead-out structures 35 penetrate the third interlayer dielectric layer 33, the second interlayer dielectric layer 30, the first interlayer dielectric layer 17 and the etch stop layer 16 and contact the source and / or drain in the semiconductor substrate 10.

[0088] This embodiment also provides a method for preparing a high-voltage MOSFET device, which is used to prepare the above-mentioned high-voltage MOSFET device, but is not limited thereto. Other suitable preparation methods may also be used, such as Figure 2 As shown, the preparation method comprises:

[0089] S1, providing a semiconductor substrate, wherein the semiconductor substrate comprises a high voltage region and a low voltage region, and a dummy gate oxide layer is formed on the semiconductor substrate;

[0090] S2, forming a polysilicon dummy gate layer covering the dummy gate oxide layer on the semiconductor substrate;

[0091] S3, removing the polysilicon dummy gate layer and the dummy gate oxide layer at a preset position in the high voltage region of the semiconductor substrate to form a trench at the preset position;

[0092] S4, forming a high voltage region gate oxide layer that fills the trench;

[0093] S5, etching the polysilicon pseudo gate layer and the pseudo gate oxide layer by using a photolithography process and in combination with a hard mask layer, retaining the polysilicon pseudo gate layer and the pseudo gate oxide layer at a preset position in the low voltage region; thereby, the high voltage region gate oxide layer and the hard mask layer located in the high voltage region form a high voltage region stacking structure, and the pseudo gate oxide layer, the polysilicon pseudo gate layer and the hard mask layer located in the low voltage region form a low voltage region stacking structure;

[0094] S6, forming an etching stop layer covering the upper surface of the obtained structure;

[0095] S7, forming a first interlayer dielectric layer on the etch stop layer, wherein the upper surface of the first interlayer dielectric layer is not lower than the top surface of the etch stop layer located on the high voltage region stack structure, and then thinning the first interlayer dielectric layer, the etch stop layer and the hard mask layer until the top surface of the high voltage region gate oxide layer and the top surface of the polysilicon pseudo gate layer are exposed;

[0096] S8, removing the polysilicon pseudo gate layer to form a U-shaped groove;

[0097] S9, forming a U-shaped low-voltage region gate oxide layer on the bottom wall and sidewalls of the U-shaped groove, and then forming a low-voltage region metal gate filling the U-shaped groove on the low-voltage region gate oxide layer;

[0098] S10, forming a second interlayer dielectric layer on the obtained structure, and then forming a high-voltage region metal gate on the second interlayer dielectric layer above a corresponding position of the high-voltage region gate oxide layer.

[0099] The preparation method of the high-voltage MOSFET device of the present embodiment first forms a high-voltage region gate oxide layer flush with the top surface of the polysilicon pseudo gate layer in the low-voltage region in the high-voltage region of the device, then thins and removes the polysilicon pseudo gate layer, and forms a low-voltage region metal gate in the formed U-shaped groove, thereby solving the problem of the gate structure height of the high-voltage device affecting the planarization process of the low-voltage region pseudo gate structure in the prior art, and then forms a second interlayer dielectric layer on the low-voltage region metal gate and the high-voltage region gate oxide layer, and then forms a high-voltage region metal gate on the second interlayer dielectric layer above the corresponding position of the high-voltage region gate oxide layer. The high-voltage region gate oxide layer and the second interlayer dielectric layer constitute an effective oxide thickness that meets the requirements of the high-voltage region of the high-voltage MOSFET device, and the process flow is simple.

[0100] The method for preparing the high voltage MOSFET device of this embodiment is described in detail below with reference to the specific drawings.

[0101] like Figure 3 As shown, step S1 is first performed to provide a semiconductor substrate 10 . The semiconductor substrate 10 includes a high voltage region and a low voltage region, and a dummy gate oxide layer 11 is formed on the semiconductor substrate 10 .

[0102] As an example, the semiconductor substrate 10 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon carbide (SiC) substrate or other suitable semiconductor substrates known in the art, and a P-well and / or an N-well and other required structural units may be pre-fabricated in the semiconductor substrate 10. In the present embodiment, the semiconductor substrate 10 preferably adopts a common Si substrate, and the semiconductor substrate 10 is pre-fabricated with the shallow trench isolation structure 12, and the shallow trench isolation structure 12 is used to isolate the subsequently formed high-voltage region gate structure from the low-voltage region gate structure.

[0103] like Figure 3 As shown, step S2 is then performed to form a polysilicon dummy gate layer 13 covering the dummy gate oxide layer 11 on the semiconductor substrate 10 .

[0104] It should be noted that the surface of the semiconductor substrate 10 on which the dummy gate oxide layer 11 is formed is the upper surface, and the upper and lower directions of the film layers subsequently formed are defined according to the upper and lower directions of the semiconductor substrate 10 .

[0105] As an example, the polysilicon dummy gate layer 13 may be formed by using processes such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), and no excessive limitation is made here.

[0106] like Figure 4 As shown, step S3 is then performed to remove the polysilicon dummy gate layer 13 and the dummy gate oxide layer 11 at a preset position in the high voltage region of the semiconductor substrate 10 to form a trench 21 at the preset position.

[0107] As an example, Figure 4 As shown, a photolithography process can be used in combination with hard mask layer etching to remove the polysilicon pseudo gate layer 13 and the pseudo gate oxide layer 11 located at a preset position in the high voltage region of the semiconductor substrate 10. In this step, a first hard mask layer 20 is formed on the upper surface of the polysilicon pseudo gate layer 13. After the subsequent step S4, a step of removing the first hard mask layer 20 is also included.

[0108] like Figure 5 As shown, step S4 is then performed to form a high voltage region gate oxide layer 14 that fills the trench 21 .

[0109] The formed high-voltage region gate oxide layer 14 is flush with the top surface of the polysilicon pseudo gate layer 13. As an example, the high-voltage region gate oxide layer 14 is a high-K dielectric layer, and the high-K dielectric layer refers to a dielectric having a dielectric constant greater than the dielectric constant of traditional silicon dioxide. In this embodiment, the semiconductor substrate 10 preferably adopts a common Si substrate. As a preferred example, a thermal oxidation process can be used to form the high-voltage region gate oxide layer 14 that fills the trench 21. While silicon oxide is formed in the trench 21, the Si substrate with a preset depth on the bottom wall of the trench 21 and the polysilicon pseudo gate layer 13 with a preset width on the side wall of the trench 21 are both oxidized to form silicon oxide. The silicon oxide in the trench 21 and the silicon oxide that penetrates into the bottom wall and side wall of the trench 21 together form the high-voltage region gate oxide layer 14 to increase the effective oxide thickness required for the high-voltage device.

[0110] like Figure 6 and Figure 7 As shown, step S5 is then performed, in which the polysilicon pseudo gate layer 13 and the pseudo gate oxide layer 11 are etched using a photolithography process in combination with a hard mask layer, and the polysilicon pseudo gate layer 13 and the pseudo gate oxide layer 11 are retained at a preset position in the low-voltage area; thereby, the high-voltage area gate oxide layer 14 and the second hard mask layer 26 located in the high-voltage area form a high-voltage area stacking structure, and the pseudo gate oxide layer 11, the polysilicon pseudo gate layer 13 and the second hard mask layer 26 located in the low-voltage area form a low-voltage area stacking structure.

[0111] like Figure 6 As shown, the hard mask layer in this step is, for example, the second hard mask layer 26. As a specific example, the method of etching the polysilicon dummy gate layer 13 and the dummy gate oxide layer 11 by using a photolithography process and combining the second hard mask layer 26 includes:

[0112] S51, such as Figure 6 As shown, the second hard mask layer 26 is formed on the polysilicon dummy gate layer 13 and the high voltage region gate oxide layer 14 . The second hard mask layer 26 may be, for example, a composite stacked structure of a silicon nitride layer 22 and a silicon oxide layer 23 .

[0113] S52, such as Figure 6As shown, a photoresist layer 24 is formed on the second hard mask layer 26 and patterned, the patterned photoresist layer 24 covers the second hard mask layer 26 above the corresponding position of the gate oxide layer 14 in the high-voltage area and the second hard mask layer 26 at a preset position in the low-voltage area; as a preferred example, based on the consideration of the subsequent etching process deviation, the planar size of the second hard mask layer 26 above the corresponding position of the gate oxide layer 14 in the high-voltage area covered by the patterned photoresist layer 24 is smaller than the planar size of the gate oxide layer 14 in the high-voltage area, so that the planar size of the second hard mask layer 26 formed after the subsequent etching process is not larger than the planar size of the gate oxide layer 14 in the high-voltage area, thereby avoiding affecting the quality of the film layer subsequently formed on the second hard mask layer 26.

[0114] S53, such as Figure 7 As shown, based on the patterned photoresist layer 24 , the second hard mask layer 26 , the polysilicon dummy gate layer 13 and the dummy gate oxide layer 11 that are not covered by the photoresist layer 24 are etched away.

[0115] S54, removing the patterned photoresist layer 24.

[0116] like Fig. 9 As shown, then proceed to step S6 to form a covering Figure 7 The resulting structure is shown with an etch stop layer 16 on the upper surface.

[0117] As an example, Figure 8 As shown, before forming the etching stop layer 16, the step of forming sidewalls 15 on the outer sidewalls of the high-pressure region stack structure and the outer sidewalls of the low-pressure region stack structure is also included.

[0118] The sidewall spacer 15 is used to protect the structure sandwiched between the sidewall spacers 15 in the low voltage region and the gate oxide layer 14 in the high voltage region from being damaged in the subsequent process. The sidewall spacer 15 can be a single layer or a composite film layer structure, including but not limited to one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0119] like Fig. 9 As shown, step S7 is then performed to form a first interlayer dielectric layer 17 on the etch stop layer 16, wherein the upper surface of the first interlayer dielectric layer 17 is not lower than the top surface of the etch stop layer 16 located on the high voltage region stack structure, and then Fig.10 As shown, the first interlayer dielectric layer 17, the etch stop layer 16 and the second hard mask layer 26 are thinned until the top surface of the high voltage region gate oxide layer 14 and the top surface of the polysilicon dummy gate layer 13 are exposed.

[0120] As a specific example, in step S7, the upper surface of the first interlayer dielectric layer 17 is not lower than the top surface of the etch stop layer 16 located on the high voltage region stack structure, and then the first interlayer dielectric layer 17, the etch stop layer 16 and the second hard mask layer 26 are thinned until the top surface of the high voltage region gate oxide layer 14 and the top surface of the polysilicon dummy gate layer 13 are exposed. The method includes:

[0121] S71 , thinning the first interlayer dielectric layer 17 by a chemical mechanical polishing process until the top surface of the etch stop layer 16 located on the low-voltage region stack structure is exposed.

[0122] S72, using a photolithography process to remove the etch stop layer 16 and the second hard mask layer 26 located above the corresponding position of the polysilicon dummy gate layer 13, and the etch stop layer 16 and the second hard mask layer 26 located above the corresponding position of the high voltage region gate oxide layer 14. In this step, the first interlayer dielectric layer 17 filled between the high voltage region and the low voltage region is exemplarily etched to form a recessed upper surface.

[0123] S73, backfilling the first interlayer dielectric layer 17 so that the top surface of the first interlayer dielectric layer 17 is not lower than the top surface of the high voltage region gate oxide layer 14 and the top surface of the polysilicon dummy gate layer 13;

[0124] S74, using a chemical mechanical polishing process to thin the first interlayer dielectric layer 17 until the top surface of the high voltage region gate oxide layer 14 and the top surface of the polysilicon pseudo gate layer 13 are exposed, and the structure formed is as follows: Fig.10 As shown, the top surface of the high-voltage region gate oxide layer 14 is flush with the top surface of the polysilicon dummy gate layer 13 .

[0125] like Fig.11 As shown, step S8 is then performed to remove the polysilicon dummy gate layer 13 to form a U-shaped groove 25 .

[0126] like Fig.12 As shown, step S9 is then performed to form a U-shaped low-voltage region gate oxide layer 18 on the bottom wall and sidewall of the U-shaped groove 25, and then a low-voltage region metal gate 19 is formed on the low-voltage region gate oxide layer 18 to fill the U-shaped groove 25. The dummy gate oxide layer 11, the low-voltage region gate oxide layer 18 and the low-voltage region metal gate 19 constitute a low-voltage region gate structure 38.

[0127] like Fig.13 As shown, then proceed to step S10, Fig.12 A second interlayer dielectric layer 30 is formed on the resulting structure, and then a high-voltage region metal gate 31 is formed on the second interlayer dielectric layer 30 above a corresponding position of the high-voltage region gate oxide layer 14 .

[0128] As an example, the thickness of the second interlayer dielectric layer 30 and the material of the second interlayer dielectric layer 30 can be adjusted according to the actual high voltage requirement, and no excessive limitation is made here, as long as the second interlayer dielectric layer 30 and the high voltage region gate oxide layer 14 can form an effective oxide thickness that meets the high voltage requirement.

[0129] As an example, the material of the high voltage region metal gate 31 includes but is not limited to titanium nitride.

[0130] As an example, Fig.13 As shown, a third hard mask layer 32 can be formed on the high voltage region metal gate 31, and a photolithography process can be used to form the high voltage region metal gate 31 on the second interlayer dielectric layer 30 above the corresponding position of the high voltage region gate oxide layer 14.

[0131] As an example, Fig.14 As shown, after step S10, the following steps are also included:

[0132] S11, forming a third interlayer dielectric layer 33 on the second interlayer dielectric layer 30, and the third interlayer dielectric layer 33 covers the high voltage area metal gate 31;

[0133] S12, forming a first lead-out structure 34 that penetrates the third interlayer dielectric layer 33 and contacts the high-voltage area metal gate 31, and a plurality of second lead-out structures 35 that penetrate the third interlayer dielectric layer 33, the second interlayer dielectric layer 30, the first interlayer dielectric layer 17 and the etch stop layer 16 and contact the source and / or drain in the semiconductor substrate 10.

[0134] As an example, in step S10, while forming the high voltage region metal gate 31 on the second interlayer dielectric layer 30 above the corresponding position of the high voltage region gate oxide layer 14, a metal resistor 39 is formed at a preset position on the second interlayer dielectric layer 30. Fig.14 As shown, step S12, for example, also includes forming a third lead-out structure 36 at the preset position that penetrates the third interlayer dielectric layer 33 and contacts the metal resistor 39, so as to form a resistor structure 37 of the high-voltage MOSFET device at the preset position. In step S10, for example, a photolithography process is used in combination with etching of the third hard mask layer 32 to form the high-voltage region metal gate 31 and the metal resistor 39, and the first lead-out structure 34 and the third lead-out structure 36 also penetrate the third hard mask layer 32.

[0135] In summary, the high-voltage MOSFET device and its preparation method of the present invention first form a high-voltage region gate oxide layer flush with the top surface of the polysilicon pseudo gate layer in the low-voltage region in the device high-voltage region, then thin and remove the polysilicon pseudo gate layer, and form a low-voltage region metal gate in the formed U-shaped groove, thereby solving the problem that the gate structure height of the high-voltage device in the prior art affects the planarization process of the low-voltage region pseudo gate structure, and then form a second interlayer dielectric layer on the low-voltage region metal gate and the high-voltage region gate oxide layer, and then form a high-voltage region metal gate on the second interlayer dielectric layer above the corresponding position of the high-voltage region gate oxide layer, the high-voltage region gate oxide layer and the second interlayer dielectric layer constitute an effective oxide thickness required to meet the high-voltage region of the high-voltage MOSFET device, and the process flow is simple. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0136] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A high voltage MOSFET device, characterized in that: The high-voltage MOSFET device comprises: a semiconductor substrate, a high-voltage region gate structure and a low-voltage region gate structure located on the semiconductor substrate; the high-voltage region gate structure comprises, from bottom to top, a high-voltage region gate oxide layer, a second interlayer dielectric layer and a high-voltage region metal gate, the low-voltage region gate structure comprises a U-shaped low-voltage region gate oxide layer, a low-voltage region metal gate filled inside the U-shaped low-voltage region gate oxide layer, and a dummy gate oxide layer located at the lower part of the U-shaped low-voltage region gate oxide layer; wherein the top surface of the high-voltage region gate oxide layer is flush with the top surface of the low-voltage region gate structure, a first interlayer dielectric layer is filled between the high-voltage region gate oxide layer and the low-voltage region gate structure, and the second interlayer dielectric layer is also formed on the low-voltage region gate structure; It also includes: an etch stop layer; the etch stop layer is formed respectively on the outer side wall of the gate oxide layer in the high voltage area, the outer side wall of the gate structure in the low voltage area, and between the first interlayer dielectric layer and the semiconductor substrate.

2. The high voltage MOSFET device according to claim 1, characterized in that: The high-voltage MOSFET device further includes sidewalls, which are respectively formed between an outer sidewall of the gate oxide layer in the high-voltage region and the etch stop layer, and between an outer sidewall of the gate structure in the low-voltage region and the etch stop layer.

3. The high voltage MOSFET device according to claim 1, characterized in that: The high voltage MOSFET device also includes: A shallow trench isolation structure formed in the semiconductor substrate, wherein the shallow trench isolation structure isolates the high-voltage region gate structure from the low-voltage region gate structure; A third interlayer dielectric layer is formed on the second interlayer dielectric layer and covers the high voltage area metal gate; A first lead-out structure that penetrates the third interlayer dielectric layer and contacts the high-voltage area metal gate, and a plurality of second lead-out structures that penetrate the third interlayer dielectric layer, the second interlayer dielectric layer, the first interlayer dielectric layer and the etch stop layer and contact the source and / or drain in the semiconductor substrate.

4. A method for preparing a high voltage MOSFET device, characterized in that: The preparation method comprises: S1, providing a semiconductor substrate, wherein the semiconductor substrate comprises a high voltage region and a low voltage region, and a dummy gate oxide layer is formed on the semiconductor substrate; S2, forming a polysilicon dummy gate layer covering the dummy gate oxide layer on the semiconductor substrate; S3, removing the polysilicon dummy gate layer and the dummy gate oxide layer at a preset position in the high voltage region of the semiconductor substrate to form a trench at the preset position; S4, forming a high voltage region gate oxide layer that fills the trench; S5, etching the polysilicon pseudo gate layer and the pseudo gate oxide layer by using a photolithography process and in combination with a hard mask layer, retaining the polysilicon pseudo gate layer and the pseudo gate oxide layer at a preset position in the low voltage region; thereby, the high voltage region gate oxide layer and the hard mask layer located in the high voltage region form a high voltage region stacking structure, and the pseudo gate oxide layer, the polysilicon pseudo gate layer and the hard mask layer located in the low voltage region form a low voltage region stacking structure; S6, forming an etching stop layer covering the upper surface of the obtained structure; S7, forming a first interlayer dielectric layer on the etch stop layer, wherein the upper surface of the first interlayer dielectric layer is not lower than the top surface of the etch stop layer located on the high voltage region stack structure, and then thinning the first interlayer dielectric layer, the etch stop layer and the hard mask layer until the top surface of the high voltage region gate oxide layer and the top surface of the polysilicon pseudo gate layer are exposed; S8, removing the polysilicon pseudo gate layer to form a U-shaped groove; S9, forming a U-shaped low-voltage region gate oxide layer on the bottom wall and sidewalls of the U-shaped groove, and then forming a low-voltage region metal gate filling the U-shaped groove on the low-voltage region gate oxide layer; S10, forming a second interlayer dielectric layer on the obtained structure, and then forming a high-voltage region metal gate on the second interlayer dielectric layer above a corresponding position of the high-voltage region gate oxide layer.

5. The method for preparing a high voltage MOSFET device according to claim 4, characterized in that: The semiconductor substrate is a silicon substrate. In step S4, a thermal oxidation process is used to form the high-voltage region gate oxide layer that fills the trench.

6. The method for preparing a high voltage MOSFET device according to claim 4, characterized in that: In step S5, the method of etching the polysilicon dummy gate layer and the dummy gate oxide layer by using a photolithography process in combination with a hard mask layer includes: S51, forming a hard mask layer on the polysilicon dummy gate layer and the high voltage region gate oxide layer; S52, forming a photoresist layer on the hard mask layer and patterning the photoresist layer, wherein the patterned photoresist layer covers the hard mask layer above the corresponding position of the gate oxide layer in the high voltage region and the hard mask layer at a preset position in the low voltage region; S53, based on the patterned photoresist layer, etching and removing the hard mask layer, the polysilicon dummy gate layer and the dummy gate oxide layer that are not covered by the photoresist layer; S54, removing the patterned photoresist layer.

7. The method for preparing a high voltage MOSFET device according to claim 6, characterized in that: The planar size of the hard mask layer above the corresponding position of the high-voltage region gate oxide layer covered by the patterned photoresist layer in step S52 is smaller than the planar size of the high-voltage region gate oxide layer.

8. The method for preparing a high voltage MOSFET device according to claim 4, characterized in that: The hard mask layer is a composite laminated structure of a silicon nitride layer and a silicon oxide layer.

9. The method for preparing a high voltage MOSFET device according to claim 4, characterized in that: In step S7, the upper surface of the first interlayer dielectric layer is not lower than the top surface of the etch stop layer located on the high voltage region stack structure, and then the first interlayer dielectric layer, the etch stop layer and the hard mask layer are thinned until the top surface of the high voltage region gate oxide layer and the top surface of the polysilicon pseudo gate layer are exposed. The method includes: S71, thinning the first interlayer dielectric layer by a chemical mechanical polishing process until a top surface of the etch stop layer located on the low-voltage region stack structure is exposed; S72, removing the etch stop layer and the hard mask layer located above the corresponding position of the polysilicon pseudo gate layer, and the etch stop layer and the hard mask layer located above the corresponding position of the high voltage region gate oxide layer by using a photolithography and etching process; S73, backfilling the first interlayer dielectric layer so that the top surface of the first interlayer dielectric layer is not lower than the top surface of the high voltage region gate oxide layer and the top surface of the polysilicon dummy gate layer; S74, thinning the first interlayer dielectric layer by using a chemical mechanical polishing process until the top surface of the high voltage region gate oxide layer and the top surface of the polysilicon dummy gate layer are exposed.

10. The method for preparing a high voltage MOSFET device according to claim 4, characterized in that: The material of the high voltage area metal gate includes titanium nitride.

11. The method for preparing a high voltage MOSFET device according to claim 4, characterized in that: After step S10, the following steps are also included: S11, forming a third interlayer dielectric layer on the second interlayer dielectric layer, and the third interlayer dielectric layer covers the high voltage area metal gate; S12, forming a first lead-out structure penetrating the third interlayer dielectric layer and contacting the high-voltage area metal gate, and a plurality of second lead-out structures penetrating the third interlayer dielectric layer, the second interlayer dielectric layer, the first interlayer dielectric layer and the etch stop layer and contacting the source and / or drain in the semiconductor substrate.

12. The method for preparing a high voltage MOSFET device according to claim 4, characterized in that: In step S10, while forming the high voltage region metal gate on the second interlayer dielectric layer above the corresponding position of the high voltage region gate oxide layer, a metal resistor is formed at a preset position on the second interlayer dielectric layer to form a resistance structure of the high voltage MOSFET device at the preset position.

13. The method for preparing a high voltage MOSFET device according to claim 4, characterized in that: In step S6, before forming the etching stop layer covering the upper surface of the obtained structure, the step further includes forming sidewalls on the outer sidewalls of the high-pressure region stack structure and the outer sidewalls of the low-pressure region stack structure.

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