Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The occupying layers protrude out of the substrate, extend in the first direction and are arranged in parallel in the second direction, and the first direction is perpendicular to the second direction; the working fin part is located on the placeholder layer; the gate structures are located on the substrate, the gate structures stretch across the working fin parts and cover part of the tops and part of the side walls of the working fin parts, and the gate structures extend in the second direction and are arranged in parallel in the first direction; and the partition structures extend along the second direction and penetrate through the working fin parts between the adjacent gate structures. The performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving towards higher component density and higher integration. Transistors, as one of the basic semiconductor devices, are currently being widely used. Therefore, with the increase in density and integration of semiconductor devices, the gate size of transistors is getting shorter and shorter, and the control ability of traditional planar transistors over channel current becomes weaker, resulting in short channel effects, causing leakage current to increase, and ultimately affecting the electrical performance of semiconductor devices.

[0003] In order to better adapt to the reduction of feature size, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (FinFETs). In the current semiconductor process, the gate cut technology is usually used to cut the strip gate. The cut gate corresponds to different transistors, which can improve the integration of transistors. At the same time, the single diffusion break (SDB) structure is used to cut the strip working fins to electrically isolate the active area structure on both sides of the SDB, which can reduce the polysilicon contact distance (CPP). Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a placeholder layer protruding from the substrate, the placeholder layer extending along a first direction and arranged in parallel along a second direction, the first direction being perpendicular to the second direction; a working fin located on the placeholder layer; a gate structure located on the substrate, the gate structure spanning the working fin and covering a portion of the top and a portion of the side wall of the working fin, the gate structure extending along the second direction and arranged in parallel along the first direction; a partition structure, the partition structure extending along the second direction and passing through the working fins between adjacent gate structures.

[0006] Optionally, the material of the placeholder layer includes insulating material.

[0007] Optionally, the material of the placeholder layer includes silicon oxide.

[0008] Optionally, the partition structure penetrates the working fin and extends longitudinally into the placeholder layer.

[0009] Optionally, the semiconductor structure further includes: an isolation layer located on the substrate, the isolation layer covering the sidewalls of the placeholder layer; and a gate structure located on the isolation layer.

[0010] Optionally, the top surface of the isolation layer is flush with the top surface of the placeholder layer, or the top surface of the isolation layer is higher than the top surface of the placeholder layer.

[0011] Optionally, along the first direction, the width of the partition structure is equal to the width of the gate structure.

[0012] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a placeholder layer protruding from the substrate, the placeholder layer extending along a first direction and arranged in parallel along a second direction, the first direction being perpendicular to the second direction; forming a working fin on the placeholder layer; forming a gate structure spanning the working fin on the substrate, the gate structure covering a portion of the top and a portion of the side wall of the working fin, the gate structure extending along the second direction and arranged in parallel along the first direction; forming a partition structure that runs through the working fins between adjacent gate structures, the partition structure extending along the second direction.

[0013] Optionally, the step of forming a placeholder layer protruding from the substrate includes: forming a plurality of sacrificial layers separated on the substrate; and forming a placeholder layer on the substrate between adjacent sacrificial layers.

[0014] Optionally, in the step of forming a placeholder layer on the substrate between adjacent sacrificial layers, a top surface of the placeholder layer is lower than a top surface of the sacrificial layer.

[0015] Optionally, the step of forming a placeholder layer on the substrate between adjacent sacrificial layers includes: forming a placeholder material layer covering the sacrificial layers and filling the space between adjacent sacrificial layers; removing the placeholder material layer higher than the sacrificial layers; after removing the placeholder material layer higher than the sacrificial layers, removing a portion of the placeholder material layer at a height, and retaining the remaining placeholder material layer as the placeholder layer.

[0016] Optionally, in the step of forming working fins on the placeholder layer: forming working fins in the space above the placeholder layer between adjacent sacrificial layers; after forming the working fins in the space above the placeholder layer between adjacent sacrificial layers, further comprising: removing the sacrificial layer.

[0017] Optionally, the step of forming working fins on the placeholder layers between adjacent sacrificial layers includes: forming a working fin material layer covering the sacrificial layers and filling the space above the placeholder layers between adjacent sacrificial layers; removing the working fin material layer above the sacrificial layers, and retaining the remaining working fin material layer as the working fin.

[0018] Optionally, an epitaxial growth process is used to form a working fin material layer that covers the sacrificial layer and fills the space above the placeholder layer between adjacent sacrificial layers.

[0019] Optionally, in the step of forming a plurality of sacrificial layers separated on the substrate, the material of the sacrificial layers includes silicon germanium.

[0020] Optionally, an isotropic etching process is used to remove the sacrificial layer.

[0021] Optionally, before forming a gate structure spanning the working fin on the substrate, the formation method further includes: forming an isolation layer covering the sidewalls of the placeholder layer on the substrate; in the step of forming the gate structure spanning the working fin on the substrate, forming the gate structure on the isolation layer.

[0022] Optionally, in the step of forming an isolation layer covering the sidewalls of the placeholder layer on the substrate, a top surface of the isolation layer is flush with a top surface of the placeholder layer, or a top surface of the isolation layer is higher than a top surface of the placeholder layer.

[0023] Optionally, the step of forming a partition structure that passes through the working fins between adjacent gate structures includes: removing the gate structure at the position to be isolated and the working fins covered by the gate structure to form a partition opening that passes through the working fins; and forming a partition structure in the partition opening.

[0024] Optionally, in the step of forming a partition opening penetrating the working fin, the partition opening penetrates the working fin and extends longitudinally into the placeholder layer.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0026] In the semiconductor structure provided by the embodiment of the present invention, the placeholder layer protrudes from the substrate, the working fin is located on the placeholder layer, and the partition structure extends along the second direction and penetrates the working fin between adjacent gate structures; in the embodiment of the present invention, there is a placeholder layer between the working fin and the substrate. Compared with the solution in which the working fin and the substrate are provided with a bottom fin extending from the working fin, in order to achieve complete electrical isolation of the working fin, the partition structure needs to completely penetrate the working fin and the bottom fin. The placeholder layer of the embodiment of the present invention occupies the position of the bottom fin, and the partition structure only needs to penetrate the working fin to achieve electrical isolation of the working fin, reducing the penetration depth of the partition structure, and correspondingly reducing the etching depth of the partition opening forming the partition structure, which is beneficial to reducing the stress loss when etching to form the partition opening, and further beneficial to improving the performance of the semiconductor structure. Moreover, in the embodiment of the present invention, the bottom fin that is not working is occupied by the placeholder layer, and the working fin is isolated from the substrate by the placeholder layer, so while ensuring the working effect of the working fin, the working fin is isolated from the substrate, which is beneficial to reducing leakage, and thus beneficial to improving the performance of the semiconductor structure.

[0027] In the formation method provided by the embodiment of the present invention, a placeholder layer protruding from the substrate is formed, a working fin is formed on the placeholder layer, and a partition structure that penetrates the working fin between adjacent gate structures is formed; in the embodiment of the present invention, there is a placeholder layer between the working fin and the substrate. Compared with the solution in which the working fin and the substrate are provided with a bottom fin extending from the working fin, in order to achieve complete electrical isolation of the working fin, the partition structure needs to completely penetrate the working fin and the bottom fin. The placeholder layer of the embodiment of the present invention occupies the position of the bottom fin, and the partition structure only needs to penetrate the working fin to achieve electrical isolation of the working fin, reducing the penetration depth of the partition structure, and correspondingly reducing the etching depth of the partition opening forming the partition structure, which is beneficial to reducing the stress loss when etching to form the partition opening, and further beneficial to improving the performance of the semiconductor structure. Moreover, in the embodiment of the present invention, the bottom fin that is not working is occupied by the placeholder layer, and the working fin is isolated from the substrate by the placeholder layer, so while ensuring the working effect of the working fin, the working fin is isolated from the substrate, which is beneficial to reducing leakage, and thus beneficial to improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 4 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0029] Figures 5 to 8 is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention;

[0030] Figures 9 to 33 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0031] The performance of the current semiconductor structure needs to be improved. The reasons why the performance needs to be improved are analyzed in combination with a method for forming a semiconductor structure.

[0032] Figures 1 to 4 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0033] Combined with reference Figure 1 and Figure 2 , Figure 2 for Figure 1 A cross-sectional view along the AA direction is provided, and a substrate 10 is provided, on which a protruding fin 14 is formed, the fin 14 extends along a first direction and is arranged in parallel along a second direction, and a gate structure 20 is formed on the substrate 10 to cross the fin 14, the gate structure 20 covers a portion of the top and a portion of the side wall of the fin 14, and the gate structure 20 extends along the second direction and is arranged in parallel along the first direction, and the first direction is perpendicular to the second direction.

[0034] Combined with reference Figure 3 and Figure 4 , Figure 4 for Figure 3 In the cross-sectional view along the AA direction, the gate structure 20 at the partitioned position and the fin 14 covered by the gate structure 20 are removed to form a partition opening 30 extending along the first direction and penetrating the fin 14 .

[0035] In order to achieve complete electrical isolation of the fin 14, the fin 14 needs to be completely penetrated. The fin 14 usually includes a working fin for work and a fin not used for work. Therefore, the height of the fin 14 is relatively large, and the etching depth of the corresponding isolation opening 30 is relatively large, which easily leads to a large stress loss caused by the formation of the isolation opening 30, thereby affecting the performance of the semiconductor structure.

[0036] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a placeholder layer protruding from the substrate, the placeholder layer extending along a first direction and arranged in parallel along a second direction, the first direction being perpendicular to the second direction; a working fin located on the placeholder layer; a gate structure located on the substrate, the gate structure spanning the working fin and covering a portion of the top and a portion of the side wall of the working fin, the gate structure extending along the second direction and arranged in parallel along the first direction; a partition structure, the partition structure extending along the second direction and passing through the working fins between adjacent gate structures.

[0037] In the embodiment of the present invention, a placeholder layer is provided between the working fin and the substrate. Compared with the solution in which the bottom fin extending from the working fin is provided between the working fin and the substrate, the partition structure needs to completely penetrate the working fin and the bottom fin in order to achieve complete electrical isolation of the working fin. The placeholder layer in the embodiment of the present invention occupies the position of the bottom fin, and the partition structure only needs to penetrate the working fin to achieve electrical isolation of the working fin, thereby reducing the penetration depth of the partition structure and correspondingly reducing the etching depth of the partition opening forming the partition structure, which is beneficial to reducing the stress loss when etching to form the partition opening, and further beneficial to improving the performance of the semiconductor structure. Moreover, in the embodiment of the present invention, the bottom fin that is not working is occupied by the placeholder layer, and the working fin is isolated from the substrate by the placeholder layer. While ensuring the working effect of the working fin, the working fin is isolated from the substrate, which is beneficial to reducing leakage and thus beneficial to improving the performance of the semiconductor structure.

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 5 to 8 It is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention.

[0040] Combined with reference Figures 5 to 8 , Figure 5 is a top view, Figure 6 for Figure 5 Cross-sectional view along AA direction, Figure 7 for Figure 5 Cross-sectional view along BB direction, Figure 8 for Figure 5 In the cross-sectional view along the CC direction, the semiconductor structure includes: a substrate 100; a placeholder layer 110, which is protruding from the substrate 100, and the placeholder layer 110 is arranged along a first direction (eg Figure 5 ) and along a second direction (as shown in the X direction Figure 5 The first direction is perpendicular to the second direction; the working fin 140 is located on the placeholder layer 110; the gate structure 200 is located on the substrate 100, the gate structure 200 spans the working fin 140 and covers part of the top and part of the sidewall of the working fin 140, the gate structure 200 extends along the second direction and is arranged in parallel along the first direction; the partition structure 310 extends along the second direction and passes through the working fin 140 between adjacent gate structures 200.

[0041] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure, wherein the semiconductor structure includes a fin field effect transistor (FinFET).

[0042] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0043] The placeholder layer 110 is used to occupy the space between the bottom of the working fin 140 and the substrate 100 to reduce the penetration depth of the partition structure 310 . The placeholder layer 110 is also used to isolate the working fin 140 from the substrate 100 .

[0044] Specifically, in the present embodiment, a placeholder layer 110 is provided between the working fin 140 and the substrate 100. Compared with the solution in which the working fin and the substrate are provided with a bottom fin extending from the working fin, the partition structure needs to completely penetrate the working fin and the bottom fin in order to achieve complete electrical isolation of the working fin. The placeholder layer 110 of the present embodiment occupies the position of the bottom fin, and the partition structure 310 only needs to penetrate the working fin 140 to achieve electrical isolation of the working fin 140, thereby reducing the penetration depth of the partition structure 310 and correspondingly reducing the etching depth of the partition opening formed by the partition structure 310, which is beneficial to reducing the stress loss when etching to form the partition opening, and further beneficial to improving the performance of the semiconductor structure. Moreover, in the present embodiment, the bottom fin that is not in operation is occupied by the placeholder layer 110, and the working fin 140 is isolated from the substrate 100 by the placeholder layer 110. While ensuring the working effect of the working fin 140, the working fin 140 is isolated from the substrate 100, which is beneficial to reducing leakage and further beneficial to improving the performance of the semiconductor structure.

[0045] In this embodiment, the material of the placeholder layer 110 includes insulating material.

[0046] The placeholder layer 110 is made of insulating material, so that when the partition structure 310 passes through the active fin 140 without passing through the placeholder layer 110 , electrical isolation of the active fin 140 can be achieved.

[0047] In this embodiment, the material of the placeholder layer 110 includes silicon oxide.

[0048] Silicon oxide is an insulating material and is also a readily available material in the semiconductor field. Using silicon oxide as the placeholder layer 110 is beneficial for reducing the impact of introducing other elements on the semiconductor structure.

[0049] The working fin 140 is used to provide a channel of the fin field effect transistor.

[0050] In this embodiment, the material of the working fin 140 includes silicon, germanium, silicon germanium or III-V semiconductor materials. As an example, in this embodiment, the material of the working fin 140 is silicon.

[0051] The gate structure 200 is used to control the opening and closing of the channel of the transistor. In this embodiment, the gate structure 200 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0052] The gate dielectric layer is used to isolate the gate structure 200 from the working fin. The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Among them, the high-k dielectric material refers to a dielectric material whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. It should be noted that the gate dielectric layer may also include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the working fin. Specifically, the material of the gate oxide layer may be silicon oxide.

[0053] In this embodiment, the material of the gate electrode layer is one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0054] In this embodiment, the gate structure 200 is a metal gate structure. Therefore, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical properties of the metal gate structure.

[0055] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

[0056] The partition structure 310 is a single diffusion break (SDB) structure, which is used to electrically isolate devices on both sides of the SDB structure, and is beneficial to reducing the polysilicon contact poly pitch (CPP).

[0057] In this embodiment, the material of the partition structure 310 includes silicon nitride, silicon carbide or silicon carbonitride. Silicon nitride, silicon carbide or silicon carbonitride has greater hardness, better density and better insulation, so that the isolation performance of the working fin partition structure 310 is guaranteed.

[0058] In this embodiment, the partition structure penetrates the working fin 140 and extends longitudinally into the placeholder layer 110 .

[0059] The partition structure penetrates the working fin 140 and extends longitudinally into the placeholder layer 110. That is, when forming the partition opening of the partition structure 310, etching penetrates the working fin 140 and over-etches into the placeholder layer 110, which is beneficial to ensure complete penetration of the working fin 140, thereby further ensuring complete electrical isolation of the working fin 140 by the partition structure 310.

[0060] In this embodiment, before forming the partition structure 310, a gate structure 200 is first formed at the position to be isolated to occupy the position, and then the gate structure 200 at the position to be isolated is removed to form a partition opening, and then a partition structure 310 is formed in the partition opening. Therefore, in this embodiment, along the first direction, the width of the partition structure 310 is equal to the width of the gate structure 200.

[0061] In this embodiment, the semiconductor structure further includes an isolation layer 150 located on the substrate 100 , and the isolation layer 150 covers the sidewalls of the placeholder layer 110 .

[0062] The isolation layer 150 is a shallow trench isolation (STI) structure, which is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, a STI structure is usually formed between an NMOS transistor and a PMOS transistor.

[0063] In this embodiment, the material of the isolation layer 150 is an insulating material. As an example, the material of the isolation layer 150 is silicon oxide.

[0064] Accordingly, in this embodiment, the gate structure 200 is located on the isolation layer 150 .

[0065] The isolation layer 150 covers the sidewalls of the placeholder layer 110, exposing the sidewalls of the working fin 140. The gate structure 200 is located on the isolation layer 150, so that the gate structure 200 covers the sidewalls of the working fin 140 without covering the sidewalls of the placeholder layer 110, which is beneficial to ensuring the working performance of the semiconductor structure.

[0066] In this embodiment, the top surface of the isolation layer 150 is flush with the top surface of the placeholder layer 110 , or the top surface of the isolation layer 150 is higher than the top surface of the placeholder layer 110 .

[0067] As an example, in this embodiment, the top surface of the isolation layer 150 is higher than the top surface of the placeholder layer 110 .

[0068] The top surface of the isolation layer 150 is higher than the top surface of the placeholder layer 110, which helps to ensure that the side walls of the placeholder layer 110 are completely covered by the isolation layer 150, and helps to further ensure that the gate structure 200 covers the side walls of the working fin 140 without covering the side walls of the placeholder layer 110, thereby helping to further ensure the working performance of the semiconductor structure.

[0069] In this embodiment, the semiconductor structure further includes a dielectric layer 210 covering the working fin 140 and the sidewall of the gate structure 200 .

[0070] The dielectric layer 210 is used to isolate adjacent devices and is also used to provide a process basis for forming the gate structure 200 .

[0071] The material of the dielectric layer 210 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0072] Figures 9 to 33 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0073] Combined with reference Figures 9 to 11 , Fig. 9 is a top view, Fig.10 for Fig. 9 Cross-sectional view along AA direction, Fig.11 for Fig. 9 A cross-sectional view along the BB direction is provided, showing a substrate 100 .

[0074] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure, wherein the semiconductor structure includes a fin field effect transistor (FinFET).

[0075] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0076] Continue to combine references Figures 9 to 11 , forming a placeholder layer 110 protruding from the substrate 100, the placeholder layer 110 extending in a first direction (eg Fig. 9 ) and along a second direction (as shown in the X direction Fig. 9 The first direction is perpendicular to the second direction.

[0077] Subsequently, a working fin is formed on the placeholder layer 110, and a partition structure formed subsequently penetrates the working fin. The placeholder layer 110 is used to occupy the space between the bottom of the working fin and the substrate 100, which helps to reduce the penetration depth of the partition structure formed subsequently. The placeholder layer 110 is also used to isolate the working fin and the substrate 100.

[0078] Specifically, in the present embodiment, a placeholder layer 110 is provided between the subsequently formed working fin and the substrate 100. Compared with the solution in which the working fin and the substrate are provided with a bottom fin extending from the working fin, the partition structure needs to completely penetrate the working fin and the bottom fin in order to achieve complete electrical isolation of the working fin. The placeholder layer 110 of the present embodiment occupies the position of the bottom fin, and the partition structure 310 only needs to penetrate the working fin to achieve electrical isolation of the working fin, thereby reducing the penetration depth of the partition structure and correspondingly reducing the etching depth of the partition opening formed by the partition structure, which is beneficial to reducing the stress loss when etching to form the partition opening, and further beneficial to improving the performance of the semiconductor structure. Moreover, in the present embodiment, the bottom fin that is not in operation is occupied by the placeholder layer 110, and the working fin is isolated from the substrate 100 by the placeholder layer 110. While ensuring the working effect of the working fin, the working fin is isolated from the substrate 100, which is beneficial to reducing leakage and further beneficial to improving the performance of the semiconductor structure.

[0079] In this embodiment, the material of the placeholder layer 110 includes insulating material.

[0080] The placeholder layer 110 is made of insulating material, so that when the partition structure passes through the active fin without passing through the placeholder layer 110 , electrical isolation of the active fin can be achieved.

[0081] In this embodiment, the material of the placeholder layer 110 includes silicon oxide.

[0082] Silicon oxide is an insulating material and is also a readily available material in the semiconductor field. Using silicon oxide as the placeholder layer 110 is beneficial for reducing the impact of introducing other elements on the semiconductor structure.

[0083] In this embodiment, the step of forming the placeholder layer 110 protruding from the substrate 100 includes: forming a plurality of sacrificial layers 120 separated on the substrate 100 .

[0084] The adjacent sacrificial layers 120 are used to enclose a space for forming the placeholder layer 110 . The sacrificial layers 120 are also used to provide support and a growth basis for the subsequent formation of working fins.

[0085] In this embodiment, in the step of forming a plurality of sacrificial layers 120 separated on the substrate 100 , the material of the sacrificial layers 120 includes silicon germanium.

[0086] The sacrificial layer 120 is formed by using silicon germanium, so that epitaxial growth can be performed based on the sacrificial layer 120 to obtain working fins. Moreover, the sacrificial layer 120 needs to be removed later, so the sacrificial layer 120 is easy to remove by using silicon germanium.

[0087] In this embodiment, a placeholder layer 110 is formed on the substrate 100 between adjacent sacrificial layers 120 .

[0088] The sacrificial layer 120 is first used as a placeholder, and then the placeholder layer 110 is formed on the substrate 100 between adjacent sacrificial layers 120 , so that the size and formation position of the placeholder layer 110 are more accurate.

[0089] In this embodiment, in the step of forming the placeholder layer 110 on the substrate 100 between adjacent sacrificial layers 120 , the top surface of the placeholder layer 110 is lower than the top surface of the sacrificial layer 120 .

[0090] The top surface of the placeholder layer 110 is lower than the top surface of the sacrificial layer 120 , so as to provide a space for subsequently forming a working fin above the placeholder layer 110 between adjacent sacrificial layers 120 .

[0091] In this embodiment, the step of forming the placeholder layer 110 on the substrate 100 between adjacent sacrificial layers 120 includes: forming a placeholder material layer (not shown) covering the sacrificial layers 120 and filling the space between the adjacent sacrificial layers 120 .

[0092] The placeholder material layer is used to form the placeholder layer 110 .

[0093] In this embodiment, the placeholder material layer above the sacrificial layer 120 is removed.

[0094] The placeholder material layer above the sacrificial layer 120 is removed to prepare for etching back the placeholder material layer between adjacent sacrificial layers 120 .

[0095] In this embodiment, after removing the placeholder material layer higher than the sacrificial layer 120 , a portion of the placeholder material layer is removed, and the remaining placeholder material layer is retained as the placeholder layer 110 .

[0096] According to the height requirement of the working fins to be formed subsequently, the placeholder material layer at the corresponding height between the adjacent sacrificial layers 120 is removed, and the remaining placeholder material layer is retained as the placeholder layer 110 .

[0097] Combined with reference Figures 12 to 17 , a working fin 140 is formed on the placeholder layer 110 .

[0098] The working fin 140 is used to provide a channel of the fin field effect transistor.

[0099] Accordingly, in this embodiment, in the step of forming the working fins 140 on the placeholder layer 110 , the working fins 140 are formed in the space above the placeholder layer 110 between adjacent sacrificial layers 120 .

[0100] The working fins 140 are formed in the spaces above the placeholder layers 110 between the adjacent sacrificial layers 120 . Accordingly, the working fins 140 are isolated from the substrate 100 by the placeholder layers 110 .

[0101] In this embodiment, the material of the working fin 140 includes silicon, germanium, silicon germanium or III-V semiconductor materials. As an example, in this embodiment, the material of the working fin 140 is silicon.

[0102] Combined with reference Figure 12 to Figure 14 , Fig.12 is a top view, Fig.13 for Fig.12 Cross-sectional view along AA direction, Fig.14 for Fig.12 In the cross-sectional view along the BB direction, the step of forming the working fins 140 on the placeholder layers 110 between adjacent sacrificial layers 120 includes: forming a working fin material layer 130 covering the sacrificial layers 120 and filling the space above the placeholder layers 110 between adjacent sacrificial layers 120 .

[0103] The working fin material layer 130 is used to form the working fins 140 .

[0104] In this embodiment, an epitaxial growth process is used to form the working fin material layer 130 that covers the sacrificial layer 120 and fills the space above the placeholder layer 110 between adjacent sacrificial layers 120 .

[0105] In this embodiment, the material of the sacrificial layer 120 is silicon germanium, and the material of the working fin material layer 130 is silicon, so that the working fin material layer 130 can be grown on the sacrificial layer 120 using an epitaxial growth process to form the working fin material layer 130 .

[0106] The epitaxial growth process can better control the process parameters, has high process controllability, and is easy to obtain a more precise film thickness size. The epitaxial growth process is also easy to form a film layer with less impurities, so that the quality of the working fin material layer 130 is higher.

[0107] Combined with reference Figures 15 to 17 , Fig.15 is a top view, Fig.16 for Fig.15 Cross-sectional view along AA direction, Fig.17 for Fig.15 In the cross-sectional view along the BB direction, the working fin material layer 130 higher than the sacrificial layer 120 is removed, and the remaining working fin material layer 130 is retained as the working fin 140 .

[0108] The top of the sacrificial layer 120 is used as the etching stop position, the working fin material layer 130 higher than the sacrificial layer 120 is removed, and the remaining working fin material layer 130 is retained as the working fin 140, so that the height size of the working fin 140 is more accurate.

[0109] Combined with reference Figures 18 to 20 , Fig.18 is a top view, Fig.19 for Fig.18Cross-sectional view along AA direction, Fig. 20 for Fig.18 In the cross-sectional view along the BB direction, after forming the working fins 140 in the space above the placeholder layer 110 between adjacent sacrificial layers 120 , the forming method further includes: removing the sacrificial layer 120 .

[0110] The sacrificial layer 120 is removed to expose the sidewalls of the working fins 140 , thereby providing a space for the subsequent formation of a gate structure.

[0111] In this embodiment, an isotropic etching process is used to remove the sacrificial layer 120 .

[0112] Using an isotropic etching process to remove the sacrificial layer 120 is beneficial for completely removing the sacrificial layer 120 . The isotropic etching process is also easy to obtain a larger etching selectivity, thereby reducing damage to the working fins 140 and the placeholder layer 110 during the process of removing the sacrificial layer 120 .

[0113] It should be noted that, in this embodiment, the etching selectivity of the etching process for the sacrificial layer 120 and the working fin 140 should not be too small. If the etching selectivity of the etching process for the sacrificial layer 120 and the working fin 140 is too small, it is easy to cause excessive damage to the working fin 140 during the removal of the sacrificial layer 120, which will subsequently affect the working performance of the working fin 140. For this reason, in this embodiment, the etching selectivity of the etching process for the sacrificial layer 120 and the working fin 140 is greater than or equal to 50.

[0114] It should also be noted that, in this embodiment, the etching selectivity of the etching process for the sacrificial layer 120 and the placeholder layer 110 should not be too small. If the etching selectivity of the etching process for the sacrificial layer 120 and the placeholder layer 110 is too small, it is easy to cause excessive damage to the placeholder layer 110 during the removal of the sacrificial layer 120, affecting the reliability of the semiconductor structure. For this reason, in this embodiment, the etching selectivity of the etching process for the sacrificial layer 120 and the placeholder layer 110 is greater than or equal to 20.

[0115] Combined with reference Figure 21 to Figure 23 , Fig.21 is a top view, Fig. 22 for Fig.21 Cross-sectional view along AA direction, Fig.23 for Fig.21 In the cross-sectional view along the BB direction, before forming the gate structure across the working fin 140 on the substrate 100 , the forming method further includes: forming an isolation layer 150 covering the sidewall of the placeholder layer 110 on the substrate 100 .

[0116] The isolation layer 150 is a shallow trench isolation structure, which is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, a STI structure is usually formed between an NMOS transistor and a PMOS transistor.

[0117] In this embodiment, the material of the isolation layer 150 is an insulating material. As an example, the material of the isolation layer 150 is silicon oxide.

[0118] In this embodiment, in the step of forming the isolation layer 150 on the substrate 100 to cover the sidewalls of the placeholder layer 110 , the top surface of the isolation layer 150 is flush with the top surface of the placeholder layer 110 , or the top surface of the isolation layer 150 is higher than the top surface of the placeholder layer 110 .

[0119] As an example, in this embodiment, the top surface of the isolation layer 150 is higher than the top surface of the placeholder layer 110 .

[0120] The top surface of the isolation layer 150 is higher than the top surface of the placeholder layer 110, which helps to ensure that the sidewalls of the placeholder layer 110 are completely covered by the isolation layer 150, and helps to further ensure that the gate structure 200 covers the sidewalls of the working fin 140 without covering the sidewalls of the placeholder layer 110, thereby helping to further ensure the working performance of the semiconductor structure.

[0121] Combined with reference Figure 24 to Figure 26 , Fig.24 is a top view, Fig.25 for Fig.24 Cross-sectional view along AA direction, Fig.26 for Fig.24 In the cross-sectional view along the BB direction, a gate structure 200 is formed on the substrate 100 across the working fin 140 . The gate structure 200 covers a portion of the top and a portion of the sidewall of the working fin 140 . The gate structure 200 extends along the second direction and is arranged in parallel along the first direction.

[0122] The gate structure 200 is used to control the opening and closing of the channel of the transistor. In this embodiment, the gate structure 200 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0123] The gate dielectric layer is used to isolate the gate structure 200 from the working fin. The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Among them, the high-k dielectric material refers to a dielectric material whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. It should be noted that the gate dielectric layer may also include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the working fin. Specifically, the material of the gate oxide layer may be silicon oxide.

[0124] In this embodiment, the material of the gate electrode layer is one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0125] In this embodiment, the gate structure 200 is a metal gate structure. Therefore, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical properties of the metal gate structure.

[0126] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

[0127] Accordingly, in this embodiment, in the step of forming the gate structure 200 across the working fin 140 on the substrate 100 , the gate structure 200 is formed on the isolation layer 150 .

[0128] The isolation layer 150 covers the sidewalls of the placeholder layer 110, exposing the sidewalls of the working fin 140. The gate structure 200 is located on the isolation layer 150, so that the gate structure 200 covers the sidewalls of the working fin 140 without covering the sidewalls of the placeholder layer 110, which is beneficial to ensuring the working performance of the semiconductor structure.

[0129] In this embodiment, the step of forming a gate structure 200 across the working fin 140 on the substrate 100 includes: forming a dielectric layer 210 covering the working fin 140 on the isolation layer 150; forming the gate structure 200 in the dielectric layer 210, and the dielectric layer 210 covers the sidewalls of the gate structure 200.

[0130] The dielectric layer 210 is used to isolate adjacent devices and is also used to provide a process basis for forming the gate structure 200 .

[0131] The material of the dielectric layer 210 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0132] Combined with reference Figures 27 to 33 , forming a partition structure 310 penetrating the working fins 140 between adjacent gate structures 200 , and the partition structure 310 extends along the second direction.

[0133] The partition structure 310 is a single diffusion break (SDB) structure, which is used to electrically isolate devices on both sides of the SDB structure, and is beneficial to reducing the polysilicon contact poly pitch (CPP).

[0134] In this embodiment, the material of the partition structure 310 includes silicon nitride, silicon carbide or silicon carbonitride. Silicon nitride, silicon carbide or silicon carbonitride has greater hardness, better density and better insulation, so that the isolation performance of the working fin partition structure 310 is guaranteed.

[0135] Combined with reference Figure 27 to Figure 29 , Fig. 27 is a top view, Fig.28 for Fig. 27 Cross-sectional view along AA direction, Fig.29 for Fig. 27 In the cross-sectional view along the BB direction, the step of forming the partition structure 310 penetrating the working fins 140 between adjacent gate structures 200 includes: removing the gate structure 200 at the position to be partitioned and the working fins 140 covered by the gate structure 200 to form a partition opening 300 penetrating the working fins 140 .

[0136] The partition opening 300 is used to provide a space for forming a partition structure 310 .

[0137] In this embodiment, before forming the partition structure 310, a gate structure 200 is first formed at the position to be isolated to occupy the position, and then the gate structure 200 at the position to be isolated is removed to form a partition opening 300, and then a partition structure 310 is formed in the partition opening 300. Therefore, in this embodiment, along the first direction, the width of the partition opening 300 is equal to the width of the gate structure 200.

[0138] In this embodiment, in the step of forming the partition opening 300 penetrating the working fin 140 , the partition opening 300 penetrates the working fin 140 and extends into the placeholder layer 110 in the longitudinal direction.

[0139] The isolation opening 300 penetrates the working fin 140 and extends longitudinally into the placeholder layer 110. That is, when forming the isolation opening 300, etching penetrates the working fin 140 and over-etches into the placeholder layer 110, which is beneficial to ensure complete penetration of the working fin 140, thereby further ensuring complete electrical isolation of the working fin 140 by the partition structure 310.

[0140] Combined with reference Figure 30 to Figure 33 , Fig.30 is a top view, Fig.31 for Fig.30 Cross-sectional view along AA direction, Fig.32 for Fig.30 Cross-sectional view along BB direction, Fig.33 for Fig.30 In the cross-sectional view along the CC direction, a partition structure 310 is formed in the partition opening 300 .

[0141] Correspondingly, in this embodiment, along the first direction, the width of the partition structure 310 is equal to the width of the gate structure 200 .

[0142] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A placeholder layer protrudes from the substrate, the placeholder layer extends along a first direction and is arranged in parallel along a second direction, and the first direction is perpendicular to the second direction; A working fin, located on the placeholder layer; a gate structure, located on the substrate, the gate structure spanning the working fin and covering a portion of the top and a portion of the sidewall of the working fin, the gate structure extending along the second direction and arranged in parallel along the first direction; A partition structure extends along the second direction and penetrates the working fins between adjacent gate structures.

2. The semiconductor structure according to claim 1, wherein: The material of the placeholder layer includes insulating material.

3. The semiconductor structure according to claim 2, wherein: The material of the placeholder layer includes silicon oxide.

4. The semiconductor structure according to claim 1, wherein: The partition structure penetrates through the working fin and extends into the placeholder layer in the longitudinal direction.

5. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: an isolation layer, located on the substrate, the isolation layer covering the sidewall of the placeholder layer; The gate structure is located on the isolation layer.

6. The semiconductor structure according to claim 5, characterized in that The top surface of the isolation layer is flush with the top surface of the placeholder layer, or the top surface of the isolation layer is higher than the top surface of the placeholder layer.

7. The semiconductor structure according to claim 1, wherein: Along the first direction, the width of the partition structure is equal to the width of the gate structure.

8. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a placeholder layer protruding from the substrate, wherein the placeholder layer extends along a first direction and is arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction; forming a working fin on the placeholder layer; forming a gate structure across the working fin on the substrate, the gate structure covering a portion of the top and a portion of the sidewall of the working fin, the gate structure extending along the second direction and arranged in parallel along the first direction; A partition structure is formed that penetrates the working fins between adjacent gate structures, and the partition structure extends along the second direction.

9. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming a placeholder layer protruding from the substrate includes: forming a plurality of sacrificial layers separated on the substrate; The placeholder layer is formed on the substrate between adjacent sacrificial layers.

10. The method for forming a semiconductor structure according to claim 8, wherein: In the step of forming the placeholder layer on the substrate between adjacent sacrificial layers, the top surface of the placeholder layer is lower than the top surface of the sacrificial layer.

11. The method for forming a semiconductor structure according to claim 9 or 10, characterized in that: The step of forming the placeholder layer on the substrate between adjacent sacrificial layers comprises: forming a placeholder material layer covering the sacrificial layers and filling the space between the adjacent sacrificial layers; removing the placeholder material layer higher than the sacrificial layer; After removing the placeholder material layer higher than the sacrificial layer, a portion of the placeholder material layer is removed, and the remaining placeholder material layer is retained as the placeholder layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: In the step of forming the working fin on the placeholder layer: forming the working fin in the space above the placeholder layer between adjacent sacrificial layers; After forming the working fin in the space above the placeholder layer between adjacent sacrificial layers, the method further includes: removing the sacrificial layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The step of forming the working fin on the placeholder layer between adjacent sacrificial layers comprises: forming a working fin material layer covering the sacrificial layer and filling the space above the placeholder layer between adjacent sacrificial layers; The working fin material layer higher than the sacrificial layer is removed, and the remaining working fin material layer is retained as the working fin.

14. The method for forming a semiconductor structure according to claim 13, wherein: An epitaxial growth process is adopted to form a working fin material layer which covers the sacrificial layer and fills the space above the placeholder layer between adjacent sacrificial layers.

15. The method for forming a semiconductor structure according to claim 8 or 14, characterized in that: In the step of forming a plurality of sacrificial layers separated on the substrate, the material of the sacrificial layers includes silicon germanium.

16. The method for forming a semiconductor structure according to claim 12, wherein: The sacrificial layer is removed by an isotropic etching process.

17. The method for forming a semiconductor structure according to claim 8, wherein: Before forming a gate structure across the working fin on the substrate, the forming method further includes: forming an isolation layer covering the sidewall of the placeholder layer on the substrate; In the step of forming a gate structure across the working fin on the substrate, the gate structure is formed on the isolation layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: In the step of forming an isolation layer covering the sidewall of the placeholder layer on the substrate, a top surface of the isolation layer is flush with a top surface of the placeholder layer, or a top surface of the isolation layer is higher than a top surface of the placeholder layer.

19. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming a partition structure that penetrates the working fins between adjacent gate structures comprises: removing the gate structure at the position to be partitioned and the working fins covered by the gate structure to form a partition opening that penetrates the working fins; The partition structure is formed in the partition opening.

20. The method for forming a semiconductor structure according to claim 19, wherein: In the step of forming a partition opening penetrating the working fin, the partition opening penetrates the working fin and extends into the placeholder layer in the longitudinal direction.

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