Semiconductor structure for optimizing MOSFET threshold voltage and improving circuit efficiency and process thereof

Abstract

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a semiconductor structure and process for optimizing MOSFET (metal oxide semiconductor field effect transistor) threshold voltage and improving circuit efficiency, the semiconductor structure comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises a P well layer, an N well layer, a P-layer, an N substrate layer and an N drift layer, doped particles are arranged in the P well layer close to the gate region; n-layers are arranged on the left side and the right side in the single MOS cell and located at the joint of the N substrate layer and the N drift layer, and a plurality of low-level doping bubbles are arranged in the N-layers and distributed in the N-layers in parallel. According to the invention, the doped particles form a more stable charge channel by enhancing the potential difference between the P-layer and the grid electrode, the fluctuation of threshold voltage is reduced, and the introduction of the N-layer optimizes the electric field distribution and reduces the leakage current, thereby improving the circuit efficiency.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a semiconductor structure and process thereof for optimizing MOSFET threshold voltage and improving circuit efficiency. Background Art

[0002] The threshold voltage (Vth) of MOSFET is a key parameter that determines the switching characteristics and power consumption of the device. In traditional MOSFET design, the threshold voltage is mainly controlled by adjusting the channel doping concentration or the gate dielectric thickness. In addition, the traditional ion implantation process easily leads to uneven doping distribution in the channel region, affecting the consistency of the threshold voltage.

[0003] The existing patent discloses a power semiconductor MOS device and its preparation method (publication number CN109728097B), wherein an N-type channel buried layer is provided in the P-type body region, and the gate dielectric layer is divided into a first gate dielectric layer in contact with the P-type body region and the drift region, which can cause electron tunneling effect, a second gate dielectric layer located on the first gate dielectric layer for capturing electrons tunneled from the first gate dielectric layer and making them fixed negative charges, and a third gate dielectric layer located on the second gate dielectric layer for isolating the second gate dielectric layer from the gate electrode. In the prior art, the mobility is improved by introducing high-k dielectric materials (such as HfO2) or strained silicon technology, but there are still problems of high process complexity, increased cost and insufficient reliability. Summary of the invention

[0004] In order to solve the existing technical problems, the present invention provides a semiconductor structure and process for optimizing the threshold voltage of MOSFET to improve circuit efficiency, solve the problems of poor threshold voltage stability, high leakage current and low circuit efficiency in traditional technologies, and reduce process complexity.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a semiconductor structure for optimizing the efficiency of a MOSFET threshold voltage improvement circuit is provided, comprising a plurality of MOS cells arranged in parallel, wherein a single MOS cell comprises: a drain, a semiconductor epitaxial layer, a source, and a gate, wherein the semiconductor epitaxial layer comprises a P-well layer, an N-well layer, a P-layer, an N-substrate layer, and an N-drift layer, wherein doped particles are arranged inside the P-well layer near the gate region; an N-layer is arranged on the left and right sides of a single MOS cell and at the junction of the N-substrate layer and the N-drift layer.

[0006] Furthermore, the doping particles in a single P-well layer can be provided with , and each doping particle is Array distribution.

[0007] Furthermore, a plurality of low-position doping bubbles are arranged inside the N-layer, and the low-position doping bubbles are distributed in parallel inside the N-layer.

[0008] Furthermore, the N-layer also includes a high-position N-layer, and the high-position N-layer is located above the N substrate layer; a plurality of high-position doping bubbles are arranged inside the high-position N-layer.

[0009] Furthermore, the N-layer is located below the N drift layer.

[0010] A preparation process for a semiconductor structure for optimizing MOSFET threshold voltage and improving circuit efficiency, comprising the following steps: S1, sequentially depositing an N substrate layer, an N-layer and an N drift layer using an ALD process; S2, forming source and drain regions by inclined ion implantation; S3, laser annealing to activate the doped particles in the channel region, wherein the energy density of the laser annealing is 50-200 mJ / cm²; S4. Evaluate the threshold voltage stability performance of the prepared semiconductor structure.

[0011] Furthermore, in step S4, the stability index of the semiconductor structure is calculated according to the detection parameter of the threshold voltage of the semiconductor structure, then: In the formula, S represents the stability index of the semiconductor device, and its value range is [0, 1]; represents the standard deviation of the threshold voltage, used to react the degree of volatility; represents the average value of the threshold voltage; is an adjustable positive parameter that controls the sensitivity of stability.

[0012] Furthermore, when When , it means that the stability index of the semiconductor structure tested meets the use requirements; when When , it means that the stability index of the semiconductor structure being tested does not meet the use requirements.

[0013] The present invention provides a semiconductor structure and process for optimizing MOSFET threshold voltage to improve circuit efficiency. Compared with the prior art, the method has the following effects: 1. In the present invention, the doped particles form a more stable charge channel by enhancing the potential difference between the P-layer and the gate, reducing the fluctuation of the threshold voltage, and the introduction of the N-layer optimizes the electric field distribution and reduces the leakage current, thereby improving the circuit efficiency.

[0014] 2. The array-type doped particles in the present invention achieve a more uniform charge distribution, further reduce the local difference in threshold voltage, improve device consistency, and the standardized array design simplifies the doping process steps and reduces manufacturing costs.

[0015] 3. The low-position doping bubbles in the present invention reduce the local doping concentration of the N-layer, reduce carrier scattering, and thus reduce the on-resistance. By retaining the high doping concentration of the main area of ​​the N-layer, the voltage withstand capability of the device is maintained.

[0016] 4. The high-position N-layer in the present invention provides additional electric field buffering, thereby improving the voltage resistance and reliability of the device under high voltage. In addition, the high-position doped bubbles optimize the carrier migration path and reduce the energy loss during the switching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural schematic diagram of Embodiment 1 of the present invention; Figure 2 is a schematic diagram of doped particles in the present invention; Figure 3 It is a structural schematic diagram of Embodiment 2 of the present invention; Figure 4 This is a schematic diagram of the structure of Embodiment 3 of the present invention; Figure 5 This is a schematic diagram of the structure of Embodiment 4 of the present invention; Figure 6 This is a schematic diagram of the structure of Embodiment 5 of the present invention.

[0018] In the figure: 1, drain; 2, source; 3, gate; 4, P well layer; 5, N well layer; 6, P-layer; 7, N substrate layer; 8, N drift layer; 9, N-layer; 10, doped particles; 11, low-level doped bubbles; 12, high-level doped bubbles; 13, charge channel; 91, high-level N-layer. DETAILED DESCRIPTION

[0019] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] like Figure 1-6 As shown, a preparation process of a semiconductor structure for optimizing MOSFET threshold voltage and improving circuit efficiency includes the following steps: Step 1: using the ALD process to sequentially deposit an N substrate layer 7, an N-layer 9 and an N drift layer 8; Step 2: forming source and drain regions by inclined ion implantation; Step 3: Activate the doped particles 10 in the channel region by laser annealing, wherein the energy density of the laser annealing is 50-200 mJ / cm²; Step 4: Evaluate the threshold voltage stability performance of the prepared semiconductor structure. And calculate the stability index of the semiconductor structure according to the detection parameters of the threshold voltage of the semiconductor structure, then: In the formula, S represents the stability index of the semiconductor device, and its value range is [0, 1]; represents the standard deviation of the threshold voltage, used to react the degree of volatility; represents the average value of the threshold voltage; is an adjustable positive parameter that controls the sensitivity of stability.

[0021] when When , it means that the stability index of the semiconductor structure tested meets the use requirements; when When , it means that the stability index of the semiconductor structure being tested does not meet the use requirements.

[0022] Among them, the performance of any semiconductor device is tested. The standard deviation of the threshold voltage is (V); the average value of the threshold voltage is (V); and for the adjustable positive parameter , then we have: From the above calculations, we can know that the stability of the semiconductor devices tested this time is relatively high and meets the requirements for use.

[0023] If the standard deviation of the threshold voltage is (V); and the average value of the threshold voltage is (V); for adjustable positive parameters , then we have: Then the stability of the semiconductor devices detected and calculated this time is significantly reduced.

[0024] Example 1 like Figure 1- 2, according to one aspect of the present invention, a semiconductor structure for optimizing the efficiency of a MOSFET threshold voltage boost circuit is provided, comprising a plurality of mutually parallel MOS cells, a single MOS cell comprising: a drain 1, a semiconductor epitaxial layer, a source 2, a gate 3, a semiconductor epitaxial layer comprising a P-well layer 4, an N-well layer 5, a P-layer 6, an N-substrate layer 7 and an N-drift layer 8, and doping particles 10 are provided in the P-well layer 4 near the gate 3 region; an N-layer 9 is provided on the left and right sides of a single MOS cell and at the junction of the N-substrate layer 7 and the N-drift layer 8. When the gate 3 is connected to the gate voltage, a charge channel 13 will be formed in the P-well layer 4, but the presence of the doping particles 10 will increase the potential difference between the P-layer 6 and the gate 3, so that the charge channel 13 formed will be more stable. The doping particles 10 form a local high potential area in the P-well layer 4, increase the potential difference between the P-layer 6 and the gate 3, make the formation of the charge channel 13 more uniform, and reduce the threshold voltage fluctuation by 20%-30%.

[0025] Example 2 like Figure 3 As shown, the number of doping particles 10 in a single P-well layer 4 can be 9, and the 9 doping particles 10 are The 9 doped particles are distributed in a regular array, and the doping concentration is precisely controlled through ion implantation and laser annealing, which improves the consistency of threshold voltage by 15%. The array distribution forms a uniform electric field, which significantly improves the carrier mobility and reduces the on-resistance.

[0026] Example 3 like Figure 4 As shown, a plurality of low-position doping bubbles 11 are arranged inside the N-layer 9, and the low-position doping bubbles 11 are arranged in parallel inside the N-layer 9. The low-position doping bubble 11 is a bubble-shaped area with a doping concentration far lower than that of the N-layer 9. The low-position doping bubble 11 forms a local voltage-dividing area in the N-layer 9, which increases the breakdown voltage by 25% and reduces the hot carrier effect. The doping bubble reduces the junction capacitance, which can significantly improve the switching speed when used in a high-frequency environment.

[0027] Example 4 like Figure 5 As shown, the N-layer 9 also includes a high-level N-layer 91, which is located above the N substrate layer 7; a plurality of high-level doping bubbles 12 are arranged inside the high-level N-layer 91. The high-level doping bubble 12 is also a bubble-shaped area with a doping concentration far lower than that of the high-level N-layer 91. The high-level doping bubble 12 achieves linear adjustment of the threshold voltage by adjusting the local concentration of the high-level N-layer 91, and solves the problem that the threshold voltage adjustment of the traditional structure depends on global doping and lacks flexibility and reliability.

[0028] Example 5 like Figure 6 As shown, the N-layer 9 is located below the N-drift layer 8. The N-layer 9 acts as a buffer layer to reduce the on-resistance of the N-drift layer 8, thereby reducing overall power consumption, and the structural design is compatible with existing CMOS processes without requiring additional mask steps.

[0029] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A semiconductor structure for optimizing MOSFET threshold voltage and improving circuit efficiency, comprising a plurality of mutually parallel MOS cells, wherein each of the MOS cells comprises: A drain electrode (1), a semiconductor epitaxial layer, a source electrode (2), and a gate electrode (3), wherein the semiconductor epitaxial layer comprises a P well layer (4), an N well layer (5), a P-layer (6), an N substrate layer (7), and an N drift layer (8), characterized in that doped particles (10) are provided in the P well layer (4) near the gate electrode (3); and an N-layer (9) is provided on the left and right sides of a single MOS cell and at the junction of the N substrate layer (7) and the N drift layer (8).

2. The semiconductor structure for optimizing MOSFET threshold voltage and improving circuit efficiency according to claim 1, characterized in that: The number of doping particles (10) in a single P-well layer (4) can be 9, and the 9 doping particles (10) are Array distribution.

3. The semiconductor structure for optimizing MOSFET threshold voltage and improving circuit efficiency according to claim 1 or 2, characterized in that: A plurality of low-position doping bubbles (11) are arranged inside the N-layer (9), and the low-position doping bubbles (11) are distributed in parallel inside the N-layer (9).

4. The semiconductor structure for optimizing MOSFET threshold voltage and improving circuit efficiency according to claim 1, characterized in that: The N-layer (9) further comprises a high-position N-layer (91), wherein the high-position N-layer (91) is located above the N substrate layer (7); a plurality of high-position doping bubbles (12) are arranged inside the high-position N-layer (91).

5. The semiconductor structure for optimizing MOSFET threshold voltage and improving circuit efficiency according to claim 1, 2 or 3, characterized in that: The N-layer (9) is located below the N drift layer (8).

6. A process for preparing a semiconductor structure for optimizing MOSFET threshold voltage and improving circuit efficiency, characterized in that: Applied to the semiconductor structure according to any one of claims 1 to 5, the preparation process comprises the following steps: S1, using an ALD process to sequentially deposit an N substrate layer (7), an N-layer (9), and an N drift layer (8); S2, forming source and drain regions by inclined ion implantation; S3, laser annealing to activate the doped particles (10) in the channel region, wherein the energy density of the laser annealing is 50-200 mJ / cm²; S4. Evaluate the threshold voltage stability performance of the prepared semiconductor structure.

7. The process for preparing a semiconductor structure for optimizing MOSFET threshold voltage and improving circuit efficiency according to claim 6, characterized in that: In step S4, the stability index of the semiconductor structure is calculated according to the detection parameter of the threshold voltage of the semiconductor structure, and then: In the formula, S represents the stability index of the semiconductor device, and its value range is [0, 1]; represents the standard deviation of the threshold voltage, used to react the degree of volatility; represents the average value of the threshold voltage; is an adjustable positive parameter that controls the sensitivity of stability.

8. The process for preparing a semiconductor structure for optimizing MOSFET threshold voltage and improving circuit efficiency according to claim 7, characterized in that: when When , it means that the stability index of the semiconductor structure tested meets the use requirements; when When , it means that the stability index of the semiconductor structure being tested does not meet the use requirements.

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