LDMOS device and forming method thereof

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a forming method thereof. The forming method comprises the following steps: forming an N-type deep trap in an upper region of a P-type substrate; ions are injected into the N-type deep trap in sequence, a P trap, an N trap and an N-type shallow injection region are formed in sequence, and the N-type shallow injection region serves as a threshold voltage adjusting injection region; the P well is approximately U-shaped, and the inner region of the U shape is the N well; the N-type shallow injection region crosses the right end part of the U shape and is located at a position close to the upper surface of the N-type deep well; the N-type deep well on the right side of the P well serves as a drift region; and forming a gate oxide layer and a gate polysilicon layer. The drift region adopts an N-type deep well, so that higher breakdown voltage is realized; the source region is arranged in the N well to improve the junction breakdown voltage of the source region, the requirement that the source region is independently connected with the potential is met, the N-type shallow injection region and the source region are adjacently connected or at least partially overlapped, the gap between the source region and the N-type shallow injection region is eliminated, P-type impurities of an actual channel of the depletion tube are correspondingly eliminated, the threshold voltage of the depletion tube is reduced, normal conduction can be achieved, and electric leakage is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to an LDMOS device and a forming method thereof. Background Art

[0002] LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistors are currently widely used in power management circuits due to their advantages such as high voltage resistance, large current driving capability, extremely low power consumption and integration with CMOS.

[0003] The source region of the isolated N-type LDMOS has a need to be connected to a separate potential (for example, to a voltage of more than ten V), so the source region is set in the N-well to improve the source region's withstand voltage. However, the N-well adopts a buried trench process, and the surface of the N-well is P-type impurities, resulting in the actual channel of the consumption tube always being P-type, so that the channel cannot be turned on normally under the consumption tube bias, and the threshold voltage V th It cannot be effectively reduced, and the current takes the path below the P-type impurities on the surface of the N-well, resulting in large power consumption and leakage. Summary of the invention

[0004] The object of the present invention is to provide an LDMOS device and a method for forming the same. The drift region of the present invention adopts an N-type deep well to achieve a higher breakdown voltage; the source region is arranged in the N-well to improve the source region junction breakdown voltage, so as to meet the requirement of the source region being connected to a potential separately; and the N-type shallow injection region is adjacent to or at least partially overlapped with the source region, so as to eliminate the gap between the source region and the N-type shallow injection region, and accordingly eliminate the P-type impurities that consume the actual channel, so as to consume the threshold voltage V th Reduced, normal conduction can be achieved, and the leakage current is reduced, thereby improving the leakage current.

[0005] The present invention provides a method for forming an LDMOS device, comprising:

[0006] Providing a P-type substrate, forming an N-type deep well in the upper region of the P-type substrate; forming a plurality of spaced field oxides in the upper surface region of the N-type deep well;

[0007] By sequentially implanting ions into the N-type deep well, a P-well, an N-well and an N-type shallow implantation region are formed successively, and the N-type shallow implantation region serves as a threshold voltage adjustment implantation region; the P-well is roughly U-shaped, and the P-well includes a U-shaped left end, a U-shaped bottom and a U-shaped right end connected in sequence; the inner area of ​​the U-shape is the N-well; the N-type shallow implantation region spans the U-shaped right end and is located near the upper surface of the N-type deep well; the N-type deep well on the right side of the P-well serves as a drift region;

[0008] forming a gate oxide layer and a gate polysilicon layer sequentially located on the P-type substrate;

[0009] Source and drain ion implantation is performed to form a source region and a drain region; the source region is located in the upper region of the N-well, and the N-type shallow implantation region is adjacent to or at least partially overlaps with the source region.

[0010] Furthermore, the ion implantation energy of the N-type shallow implantation region is smaller than the ion implantation energy of the N-well.

[0011] Furthermore, the P-well is located in the N-type deep well and extends downward from the upper surface of the N-type deep well to a certain depth in the longitudinal direction, and the depth of the P-well is less than the depth of the N-type deep well.

[0012] Furthermore, the N-well is located in the P-well and extends downward from the upper surface of the N-type deep well to a certain depth in the longitudinal direction, and the depth of the N-well is less than the depth of the P-well.

[0013] Furthermore, the source-drain ion implantation forms an N-type heavily doped region and a P-type heavily doped region, wherein the N-type heavily doped region includes the source region and the drain region; and the P-type heavily doped region is located in the upper region of the left end portion of the U-shape.

[0014] The present invention also provides an LDMOS device, comprising:

[0015] A P-type substrate, an N-type deep well is formed in the upper region of the P-type substrate; a plurality of spaced field oxides are formed in the upper surface region of the N-type deep well;

[0016] A P-well, an N-well and an N-type shallow injection region are formed in the N-type deep well, and the N-type shallow injection region serves as a threshold voltage adjustment injection region; the P-well is roughly U-shaped, and the P-well includes a U-shaped left end, a U-shaped bottom and a U-shaped right end connected in sequence; the inner area of ​​the U-shape is the N-well; the N-type shallow injection region spans the U-shaped right end and is located close to the upper surface of the N-type deep well; the N-type deep well on the right side of the P-well serves as a drift region;

[0017] A gate oxide layer and a gate polysilicon layer sequentially disposed on the P-type substrate;

[0018] A source region and a drain region; the source region is located in the upper region of the N-well, and the N-type shallow implantation region is adjacent to or at least partially overlaps with the source region.

[0019] Furthermore, a first field oxygen, a second field oxygen and a third field oxygen are formed in an upper surface region of the N-type deep well.

[0020] Furthermore, the first field oxygen is formed at the boundary region between the U-shaped left end and the N-well and close to the upper surface of the N-type deep well; and the U-shaped right end is located between the adjacent first field oxygen and second field oxygen.

[0021] Furthermore, the gate oxide layer covers part of the N-well, the right end of the U-shape and part of the N-type deep well; the right side of the gate oxide layer is adjacent to the second field oxygen; the gate polysilicon layer covers the gate oxide layer and part of the second field oxygen; the left side of the gate polysilicon layer is aligned with the left side of the gate oxide layer.

[0022] Furthermore, the right side area of ​​the N-type shallow injection region overlaps with the N-type deep well portion on the right side of the U-shaped right end, and the left side area of ​​the N-type shallow injection region overlaps with the N-well portion on the left side of the U-shaped right end.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] The invention provides an LDMOS device and a forming method thereof. The forming method comprises: providing a P-type substrate, forming an N-type deep well in an upper region of the P-type substrate; forming a plurality of spaced field oxides in an upper surface region of the N-type deep well; sequentially forming a P-well, an N-well and an N-type shallow injection region by ion implantation into the N-type deep well, wherein the N-type shallow injection region serves as a threshold voltage adjustment injection region; the P-well is roughly U-shaped, and comprises a U-shaped left end, a U-shaped bottom and a U-shaped right end connected in sequence; the inner region of the U-shape is the N-well; the N-type shallow injection region spans the U-shaped right end and is located near the upper surface of the N-type deep well; the N-type deep well on the right side of the P-well serves as a drift region; forming a gate oxide layer and a gate polysilicon layer sequentially located on the P-type substrate; performing source-drain ion implantation to form a source region and a drain region; the source region is located in an upper region of the N-well, and the N-type shallow injection region is adjacent to or at least partially overlaps with the source region. The drift region of the present invention adopts an N-type deep well to achieve a higher breakdown voltage; the source region is arranged in the N-well to improve the source region junction breakdown voltage, so as to meet the requirement of the source region being connected to a potential separately, and the N-type shallow injection region is adjacent to or at least partially overlapped with the source region, so as to eliminate the gap between the source region and the N-type shallow injection region, and correspondingly eliminate the P-type impurities that consume the actual channel, and consume the threshold voltage V th Reduced, normal conduction can be achieved, and the leakage current is reduced, thereby improving the leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The present invention is a schematic flow chart of a method for forming an LDMOS device according to an embodiment of the present invention.

[0026] Figure 2 It is a schematic diagram of the method for forming an LDMOS device according to an embodiment of the present invention after forming a field oxide.

[0027] Figure 3 It is a schematic diagram of a method for forming an LDMOS device according to an embodiment of the present invention after forming an N-type shallow implantation region.

[0028] Figure 4It is a schematic diagram of a method for forming an LDMOS device according to an embodiment of the present invention after a gate polysilicon layer is formed.

[0029] Figure 5a The first exemplary front view schematic diagram of a reasonable arrangement of an N-type shallow implantation region in an LDMOS device according to an embodiment of the present invention is shown.

[0030] Figure 5b for Figure 5a Schematic diagram of the current path corresponding to the LDMOS device.

[0031] Figure 5c The second front side schematic diagram is a schematic diagram of a reasonable arrangement of an N-type shallow implantation region in an LDMOS device according to an embodiment of the present invention.

[0032] Figure 5d The third front schematic diagram is a schematic diagram of a reasonable example of setting an N-type shallow implantation region in the LDMOS device according to an embodiment of the present invention.

[0033] Figure 6a A schematic diagram of a negative example of an unreasonable setting of the threshold voltage adjustment implantation region 006 in the LDMOS device.

[0034] Figure 6b for Figure 6a Schematic diagram of the current path corresponding to the LDMOS device.

[0035] The reference numerals are as follows:

[0036] 006-threshold voltage adjustment injection region; 101-P-type substrate; 102-N-type deep well; 102a-drift region; 103a-first field oxygen; 103b-second field oxygen; 103c-third field oxygen; 104-P well; 105-N well; 106-N-type shallow injection region; 107-gate oxide layer; 108-gate polysilicon layer; 109a-source region; 109b-drain region; 110-P-type heavily doped region; B-first region; A-second region. DETAILED DESCRIPTION

[0037] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0038] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0039] The embodiment of the present invention provides a method for forming an LDMOS device, such as Figure 1 As shown, including:

[0040] S1. Provide a P-type substrate, form an N-type deep well in the upper region of the P-type substrate; and form a plurality of spaced field oxides in the upper surface region of the N-type deep well;

[0041] S2. By sequentially implanting ions into the N-type deep well, a P-well, an N-well and an N-type shallow implantation region are formed successively, and the N-type shallow implantation region is used as a threshold voltage adjustment implantation region; the P-well is roughly U-shaped, and the P-well includes a U-shaped left end, a U-shaped bottom and a U-shaped right end connected in sequence; the inner area of ​​the U-shape is the N-well; the N-type shallow implantation region spans the U-shaped right end and is located near the upper surface of the N-type deep well; the N-type deep well on the right side of the P-well is used as a drift region;

[0042] S3, forming a gate oxide layer and a gate polysilicon layer sequentially located on the P-type substrate;

[0043] S4. Perform source-drain ion implantation to form a source region and a drain region; the source region is located in the upper region of the N-well, and the N-type shallow implantation region is adjacent to or at least partially overlaps with the source region.

[0044] Combine the following Figures 2 to 5b Each step of the method for forming an LDMOS device according to an embodiment of the present invention is described in detail.

[0045] Step S1: Figure 2As shown, an N-type deep well 102 is formed on a P-type substrate 101 by N-type ion implantation and thermal advancement. The N-type deep well 102 is located in the P-type substrate 101, and extends downward from the upper surface of the P-type substrate 101 to a certain depth in the P-type substrate 101. Active area photolithography is used to open the field oxygen region, etch the field oxygen region, and grow field oxygen 103. The field oxygen 103 is spaced and located near the upper surface of the N-type deep well 102. In the thickness direction (longitudinal direction) of the P-type substrate 101, a portion of the field oxygen 103 is deeply embedded in the N-type deep well 102, and another portion of the field oxygen 103 is deeper than the upper surface of the N-type deep well 102. The material of the P-type substrate 101 can be single crystal silicon doped with P-type impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc., and can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors.

[0046] Step S2: Figure 3 As shown, the well injection region is opened by photolithography, P-type impurity ions are injected to form a P-well 104, N-type impurity ions are injected to form an N-well 105, and N-type impurity ions are injected to form an N-type shallow injection region 106. The N-type shallow injection region 106 is used as a threshold voltage adjustment injection region for consumption. The ion injection energy of the N-type shallow injection region 106 is less than the ion injection energy of the N-well 105.

[0047] The P-well 104 is located in the N-type deep well 102 and extends longitudinally downward to a certain depth from the upper surface of the N-type deep well 102, and the depth of the P-well 104 is less than the depth of the N-type deep well 102. The N-well 105 is located in the P-well 104 and extends longitudinally downward to a certain depth from the upper surface of the N-type deep well, and the depth of the N-well 105 is less than the depth of the P-well 104.

[0048] It should be understood that the injection region of the initial P well formed by injecting P-type impurity ions is Figure 3 Then, N-type impurity ions are injected into the area where the N-well 105 is located to neutralize the original P-type impurities in the area and invert the excess N-type impurities to N-type, thus forming the N-well 105. The initial P-well area minus the N-well 105 area is the final P-well 104.

[0049] The P-well 104 is roughly U-shaped, and includes a U-shaped left end, a U-shaped right end, and a U-shaped bottom, and the U-shaped bottom connects the U-shaped left end and the U-shaped right end respectively. The U-shaped inner region of the P-well 104 is the N-well 105. The first field oxygen 103a is formed at the junction of the U-shaped left end of the P-well 104 and the N-well 105 and near the upper surface of the N-type deep well 102; the U-shaped right end of the P-well 104 is located between the adjacent first field oxygen 103a and the second field oxygen 103b.

[0050] The N-type shallow injection region 106 is located in the N-type deep well 102. The N-type shallow injection region 106 spans the U-shaped right end of the P-well 104 and is located close to the upper surface of the N-type deep well 102. The right side area of ​​the N-type shallow injection region 106 overlaps with the N-type deep well 102 portion on the right side of the U-shaped right end of the P-well 104. The left side area of ​​the N-type shallow injection region 106 overlaps with the N-well 105 portion on the left side of the U-shaped right end of the P-well 104.

[0051] Step S3: Figure 4 As shown, a gate oxide layer 107 is grown and a gate polysilicon layer 108 is deposited. The gate oxide layer 107 is located on the surface of the N-type deep well 102. The gate oxide layer 107 covers part of the N-well 106, the right end of the U-shaped structure and part of the N-type deep well 102; the right side of the gate oxide layer 107 is adjacent to the second field oxide 103b; the gate polysilicon layer 108 covers the gate oxide layer 107 and part of the second field oxide 103b; the left side of the gate polysilicon layer 108 is aligned with the left side of the gate oxide layer 107.

[0052] Figure 5a The first exemplary schematic diagram of a reasonable front surface of the N-type shallow implantation region 106 in the LDMOS device according to the embodiment of the present invention is shown. Figure 5b for Figure 5a Schematic diagram of the current path corresponding to the LDMOS device. Step S4: Figure 5a and Figure 5b As shown, source and drain ion implantation is selectively performed to form an N-type heavily doped region and a P-type heavily doped region 110, wherein the N-type heavily doped region includes a source region 109a and a drain region 109b. The source region 109a is located in the upper region of the N-well 105 between the first field oxygen 103a and the N-type shallow implantation region 106, and the source region 109a is adjacent to (adjacent to and connected to) the N-type shallow implantation region 106. The N-type deep well 102 on the right side of the P-well 104 serves as a drift region 102a (the region within the dotted line frame), and the drain region 109b is located in the N-type deep well 102 between the second field oxygen 103b and the third field oxygen 103c above the drift region 102a.

[0053] Figure 6a A schematic diagram of a negative example of an unreasonable setting of the threshold voltage adjustment implantation region 006 in the LDMOS device. Figure 6b for Figure 6aSchematic diagram of the current path corresponding to the LDMOS device. Figure 6a and Figure 6b As shown, since the source region 109a needs to be connected to a potential separately, the source region 109a needs to meet a certain withstand voltage. Placing the source region 109a in the N-well 105 can increase the junction breakdown voltage of the source region 109a. The threshold voltage adjustment injection region 006 (N-type) of the N-type LDMOS consumption even is located on the surface of the device channel, and overlaps with the N-well 105 and the drift region to a certain extent. Since the process platform is a polysilicon structure process, NMOS and PMOS have the same type of gate, and the P-type LDMOS needs to use a buried channel, that is, the surface of the N-well 105 is P-type impurities. The first region B on the surface of the N-well 105 between the threshold voltage adjustment injection region 006 and the source region 109a is P-type, resulting in the actual channel of the consumption even always being P-type, so that the channel cannot be normally turned on under the consumption even bias, and the threshold voltage V th It cannot be effectively reduced, and the current takes the path below the P-type impurities in the first region B on the surface of the N-well, resulting in large power consumption and leakage.

[0054] like Figure 5a and Figure 5b As shown, the drift region 102a of the present invention adopts an N-type deep well to achieve a higher breakdown voltage; the source region 109a is set in the N-well 105 to improve the junction breakdown voltage of the source region 109a, so as to meet the requirement of the source region 109a being connected to a potential alone, and the left end of the N-type shallow injection region 106 is adjacent to the source region 109a, and the N-type shallow injection region 106 is used as a threshold voltage adjustment injection region of the consumption path, and the gap between the source region 109a and the N-type shallow injection region 106 is eliminated, and the P-type impurities in the actual channel of the consumption path are correspondingly eliminated, that is, the second region A no longer has P-type impurities, and the threshold voltage V th Reduced, normal conduction can be achieved, and the leakage current is reduced, thereby improving the leakage current.

[0055] Figure 5c The second front side schematic diagram is a schematic diagram of a reasonable arrangement of an N-type shallow implantation region in an LDMOS device according to an embodiment of the present invention. Figure 5d The third frontal schematic diagram of a reasonable arrangement of the N-type shallow implant region in the LDMOS device of the embodiment of the present invention. In other examples of the present invention, the N-type shallow implant region 106 and the source region 109a at least partially overlap (overlap) to prevent process deviation, so that there is a gap between the left end of the N-type shallow implant region 106 and the right end of the source region 109a. Figure 5c In the second example, the left end of the N-type shallow implantation region 106 is shown to extend to the middle area of ​​the source region 109a; Figure 5dIn the third example, the left end of the N-type shallow implant region 106 extends to the leftmost end of the source region 109a and can be adjacent to the first field oxygen 103a. The N-type shallow implant region 106 and the source region 109a at least partially overlap (overlap), eliminating the gap between the source region 109a and the N-type shallow implant region 106, and correspondingly eliminating the P-type impurities that consume the actual channel, that is, the second region A no longer has P-type impurities, and the threshold voltage V th Reduced, normal conduction can be achieved, and the leakage current is reduced, thereby improving the leakage current.

[0056] The present invention also provides an LDMOS device, such as Figure 5a , Figure 5c and Figure 5d As shown, including:

[0057] A P-type substrate 101, an N-type deep well 102 is formed in the upper region of the P-type substrate 101; a plurality of spaced field oxides are formed in the upper surface region of the N-type deep well 102;

[0058] A P-well 104, an N-well 105 and an N-type shallow injection region 106 are formed in the N-type deep well 102, and the N-type shallow injection region 106 is used as a threshold voltage adjustment injection region; the P-well 104 is roughly U-shaped, and the P-well 104 includes a U-shaped left end, a U-shaped bottom and a U-shaped right end connected in sequence; the inner area of ​​the U-shape is the N-well 105; the N-type shallow injection region 106 spans the U-shaped right end and is located near the upper surface of the N-type deep well 102; the N-type deep well on the right side of the P-well 104 is used as a drift region 102a;

[0059] A gate oxide layer 107 and a gate polysilicon layer 108 are sequentially disposed on a P-type substrate 101;

[0060] The source region 109 a and the drain region 109 b , the source region 109 a is located in the upper region of the N well 105 , and the N-type shallow implantation region 106 is adjacent to or at least partially overlaps with the source region 109 a .

[0061] Specifically, the first field oxygen 103a, the second field oxygen 103b and the third field oxygen 103c are formed at intervals on the upper surface of the N-type deep well 102. The first field oxygen 103a is formed at the junction of the left end of the U-shaped portion and the N-well 105 and close to the upper surface of the N-type deep well 102; the right end of the U-shaped portion is located between the adjacent first field oxygen 103a and the second field oxygen 103b.

[0062] The gate oxide layer 107 covers part of the N-well 106 , the right end of the U-shape and part of the N-type deep well 102 ; the right side of the gate oxide layer 107 is adjacent to the second field oxygen 103 b ; the gate polysilicon layer 108 covers the gate oxide layer 107 and part of the second field oxygen 103 b ; the left side of the gate polysilicon layer 108 is aligned with the left side of the gate oxide layer 107 .

[0063] The right side of the N-type shallow implantation region 106 partially overlaps with the N-type deep well 102 on the right side of the U-shaped right end, and the left side of the N-type shallow implantation region 106 partially overlaps with the N-well 105 on the left side of the U-shaped right end.

[0064] In summary, the present invention provides an LDMOS device and a method for forming the same, the method comprising: providing a P-type substrate, forming an N-type deep well in an upper region of the P-type substrate; forming a plurality of spaced field oxides in an upper surface region of the N-type deep well; sequentially forming a P-well, an N-well and an N-type shallow injection region by ion implantation into the N-type deep well, the N-type shallow injection region serving as a threshold voltage adjustment injection region; the P-well is roughly U-shaped, the P-well comprising a U-shaped left end, a U-shaped bottom and a U-shaped right end connected in sequence; the inner region of the U-shape is the N-well; the N-type shallow injection region spans the U-shaped right end and is located near the upper surface of the N-type deep well; the N-type deep well on the right side of the P-well serves as a drift region; forming a gate oxide layer and a gate polysilicon layer sequentially located on the P-type substrate; performing source and drain ion implantation to form a source region and a drain region; the source region is located in an upper region of the N-well, and the N-type shallow injection region is adjacent to or at least partially overlaps with the source region. The drift region of the present invention adopts an N-type deep well to achieve a higher breakdown voltage; the source region is arranged in the N-well to improve the source region junction breakdown voltage, so as to meet the requirement of the source region being connected to a potential separately, and the N-type shallow injection region is adjacent to or at least partially overlapped with the source region, so as to eliminate the gap between the source region and the N-type shallow injection region, and accordingly eliminate the P-type impurities that consume the actual channel, and consume the threshold voltage V th Reduced, normal conduction can be achieved, and the leakage current is reduced, thereby improving the leakage current.

[0065] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0066] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for forming an LDMOS device, characterized in that: include: Providing a P-type substrate, forming an N-type deep well in the upper region of the P-type substrate; forming a plurality of spaced field oxides in the upper surface region of the N-type deep well; By sequentially implanting ions into the N-type deep well, a P-well, an N-well and an N-type shallow injection region are formed in sequence, and the N-type shallow injection region serves as a threshold voltage adjustment injection region; the P-well is roughly U-shaped, and the P-well includes a U-shaped left end, a U-shaped bottom and a U-shaped right end connected in sequence; the inner region of the U-shape is the N-well; the N-type shallow injection region spans the U-shaped right end and is located near the upper surface of the N-type deep well; the N-type deep well on the right side of the P-well serves as a drift region; forming a gate oxide layer and a gate polysilicon layer sequentially located on the P-type substrate; Source and drain ion implantation is performed to form a source region and a drain region; the source region is located in the upper region of the N-well, and the N-type shallow implantation region is adjacent to or at least partially overlaps with the source region.

2. The method for forming an LDMOS device according to claim 1, wherein: The ion implantation energy of the N-type shallow implantation region is smaller than the ion implantation energy of the N-well.

3. The method for forming an LDMOS device according to claim 1, wherein: The P-well is located in the N-type deep well and extends longitudinally downward to a certain depth from the upper surface of the N-type deep well. The depth of the P-well is less than the depth of the N-type deep well.

4. The method for forming an LDMOS device according to claim 1, wherein: The N-well is located in the P-well and extends longitudinally downward to a certain depth from the upper surface of the N-type deep well, and the depth of the N-well is less than the depth of the P-well.

5. The method for forming an LDMOS device according to claim 1, wherein: The source-drain ion implantation forms an N-type heavily doped region and a P-type heavily doped region, wherein the N-type heavily doped region includes the source region and the drain region; and the P-type heavily doped region is located in the upper region of the left end portion of the U-shape.

6. An LDMOS device, characterized in that: include: A P-type substrate, an N-type deep well is formed in the upper region of the P-type substrate; a plurality of spaced field oxides are formed in the upper surface region of the N-type deep well; A P-well, an N-well and an N-type shallow injection region are formed in the N-type deep well, and the N-type shallow injection region serves as a threshold voltage adjustment injection region; the P-well is roughly U-shaped, and the P-well includes a U-shaped left end, a U-shaped bottom and a U-shaped right end connected in sequence; the inner area of ​​the U-shape is the N-well; the N-type shallow injection region spans the U-shaped right end and is located close to the upper surface of the N-type deep well; the N-type deep well on the right side of the P-well serves as a drift region; A gate oxide layer and a gate polysilicon layer sequentially disposed on the P-type substrate; source region and drain region; The source region is located in an upper area of ​​the N-well, and the N-type shallow implantation region is adjacent to or at least partially overlaps with the source region.

7. The LDMOS device according to claim 6, characterized in that: A first field oxygen, a second field oxygen and a third field oxygen are formed in an upper surface region of the N-type deep well.

8. The LDMOS device according to claim 7, characterized in that: The first field oxygen is formed at the junction area between the U-shaped left end and the N-well and close to the upper surface of the N-type deep well; the U-shaped right end is located between the adjacent first field oxygen and second field oxygen.

9. The LDMOS device according to claim 7, characterized in that: The gate oxide layer covers part of the N-well, the right end of the U-shape and part of the N-type deep well; the right side of the gate oxide layer is adjacent to the second field oxygen; the gate polysilicon layer covers the gate oxide layer and part of the second field oxygen; the left side of the gate polysilicon layer is aligned with the left side of the gate oxide layer.

10. The LDMOS device according to claim 6, characterized in that: The right area of ​​the N-type shallow injection region overlaps with the N-type deep well portion on the right side of the U-shaped right end, and the left area of ​​the N-type shallow injection region overlaps with the N-well portion on the left side of the U-shaped right end.

Images